i915_gem_execbuffer.c

   1// SPDX-License-Identifier: MIT
   2/*
   3 * Copyright © 2008,2010 Intel Corporation
   4 */
   5
   6#include <linux/dma-resv.h>
   7#include <linux/highmem.h>
   8#include <linux/sync_file.h>
   9#include <linux/uaccess.h>
  10
  11#include <drm/drm_auth.h>
  12#include <drm/drm_print.h>
  13#include <drm/drm_syncobj.h>
  14
  15#include "gem/i915_gem_ioctls.h"
  16#include "gt/intel_context.h"
  17#include "gt/intel_gpu_commands.h"
  18#include "gt/intel_gt.h"
  19#include "gt/intel_gt_buffer_pool.h"
  20#include "gt/intel_gt_pm.h"
  21#include "gt/intel_ring.h"
  22
  23#include "pxp/intel_pxp.h"
  24
  25#include "i915_cmd_parser.h"
  26#include "i915_drv.h"
  27#include "i915_file_private.h"
  28#include "i915_gem_clflush.h"
  29#include "i915_gem_context.h"
  30#include "i915_gem_evict.h"
  31#include "i915_gem_ioctls.h"
  32#include "i915_reg.h"
  33#include "i915_trace.h"
  34#include "i915_user_extensions.h"
  35
  36struct eb_vma {
  37	struct i915_vma *vma;
  38	unsigned int flags;
  39
  40	/** This vma's place in the execbuf reservation list */
  41	struct drm_i915_gem_exec_object2 *exec;
  42	struct list_head bind_link;
  43	struct list_head reloc_link;
  44
  45	struct hlist_node node;
  46	u32 handle;
  47};
  48
  49enum {
  50	FORCE_CPU_RELOC = 1,
  51	FORCE_GTT_RELOC,
  52	FORCE_GPU_RELOC,
  53#define DBG_FORCE_RELOC 0 /* choose one of the above! */
  54};
  55
  56/* __EXEC_OBJECT_ flags > BIT(29) defined in i915_vma.h */
  57#define __EXEC_OBJECT_HAS_PIN		BIT(29)
  58#define __EXEC_OBJECT_HAS_FENCE		BIT(28)
  59#define __EXEC_OBJECT_USERPTR_INIT	BIT(27)
  60#define __EXEC_OBJECT_NEEDS_MAP		BIT(26)
  61#define __EXEC_OBJECT_NEEDS_BIAS	BIT(25)
  62#define __EXEC_OBJECT_INTERNAL_FLAGS	(~0u << 25) /* all of the above + */
  63#define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE)
  64
  65#define __EXEC_HAS_RELOC	BIT(31)
  66#define __EXEC_ENGINE_PINNED	BIT(30)
  67#define __EXEC_USERPTR_USED	BIT(29)
  68#define __EXEC_INTERNAL_FLAGS	(~0u << 29)
  69#define UPDATE			PIN_OFFSET_FIXED
  70
  71#define BATCH_OFFSET_BIAS (256*1024)
  72
  73#define __I915_EXEC_ILLEGAL_FLAGS \
  74	(__I915_EXEC_UNKNOWN_FLAGS | \
  75	 I915_EXEC_CONSTANTS_MASK  | \
  76	 I915_EXEC_RESOURCE_STREAMER)
  77
  78/* Catch emission of unexpected errors for CI! */
  79#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
  80#undef EINVAL
  81#define EINVAL ({ \
  82	DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
  83	22; \
  84})
  85#endif
  86
  87/**
  88 * DOC: User command execution
  89 *
  90 * Userspace submits commands to be executed on the GPU as an instruction
  91 * stream within a GEM object we call a batchbuffer. This instructions may
  92 * refer to other GEM objects containing auxiliary state such as kernels,
  93 * samplers, render targets and even secondary batchbuffers. Userspace does
  94 * not know where in the GPU memory these objects reside and so before the
  95 * batchbuffer is passed to the GPU for execution, those addresses in the
  96 * batchbuffer and auxiliary objects are updated. This is known as relocation,
  97 * or patching. To try and avoid having to relocate each object on the next
  98 * execution, userspace is told the location of those objects in this pass,
  99 * but this remains just a hint as the kernel may choose a new location for
 100 * any object in the future.
 101 *
 102 * At the level of talking to the hardware, submitting a batchbuffer for the
 103 * GPU to execute is to add content to a buffer from which the HW
 104 * command streamer is reading.
 105 *
 106 * 1. Add a command to load the HW context. For Logical Ring Contexts, i.e.
 107 *    Execlists, this command is not placed on the same buffer as the
 108 *    remaining items.
 109 *
 110 * 2. Add a command to invalidate caches to the buffer.
 111 *
 112 * 3. Add a batchbuffer start command to the buffer; the start command is
 113 *    essentially a token together with the GPU address of the batchbuffer
 114 *    to be executed.
 115 *
 116 * 4. Add a pipeline flush to the buffer.
 117 *
 118 * 5. Add a memory write command to the buffer to record when the GPU
 119 *    is done executing the batchbuffer. The memory write writes the
 120 *    global sequence number of the request, ``i915_request::global_seqno``;
 121 *    the i915 driver uses the current value in the register to determine
 122 *    if the GPU has completed the batchbuffer.
 123 *
 124 * 6. Add a user interrupt command to the buffer. This command instructs
 125 *    the GPU to issue an interrupt when the command, pipeline flush and
 126 *    memory write are completed.
 127 *
 128 * 7. Inform the hardware of the additional commands added to the buffer
 129 *    (by updating the tail pointer).
 130 *
 131 * Processing an execbuf ioctl is conceptually split up into a few phases.
 132 *
 133 * 1. Validation - Ensure all the pointers, handles and flags are valid.
 134 * 2. Reservation - Assign GPU address space for every object
 135 * 3. Relocation - Update any addresses to point to the final locations
 136 * 4. Serialisation - Order the request with respect to its dependencies
 137 * 5. Construction - Construct a request to execute the batchbuffer
 138 * 6. Submission (at some point in the future execution)
 139 *
 140 * Reserving resources for the execbuf is the most complicated phase. We
 141 * neither want to have to migrate the object in the address space, nor do
 142 * we want to have to update any relocations pointing to this object. Ideally,
 143 * we want to leave the object where it is and for all the existing relocations
 144 * to match. If the object is given a new address, or if userspace thinks the
 145 * object is elsewhere, we have to parse all the relocation entries and update
 146 * the addresses. Userspace can set the I915_EXEC_NO_RELOC flag to hint that
 147 * all the target addresses in all of its objects match the value in the
 148 * relocation entries and that they all match the presumed offsets given by the
 149 * list of execbuffer objects. Using this knowledge, we know that if we haven't
 150 * moved any buffers, all the relocation entries are valid and we can skip
 151 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
 152 * hang.) The requirement for using I915_EXEC_NO_RELOC are:
 153 *
 154 *      The addresses written in the objects must match the corresponding
 155 *      reloc.presumed_offset which in turn must match the corresponding
 156 *      execobject.offset.
 157 *
 158 *      Any render targets written to in the batch must be flagged with
 159 *      EXEC_OBJECT_WRITE.
 160 *
 161 *      To avoid stalling, execobject.offset should match the current
 162 *      address of that object within the active context.
 163 *
 164 * The reservation is done is multiple phases. First we try and keep any
 165 * object already bound in its current location - so as long as meets the
 166 * constraints imposed by the new execbuffer. Any object left unbound after the
 167 * first pass is then fitted into any available idle space. If an object does
 168 * not fit, all objects are removed from the reservation and the process rerun
 169 * after sorting the objects into a priority order (more difficult to fit
 170 * objects are tried first). Failing that, the entire VM is cleared and we try
 171 * to fit the execbuf once last time before concluding that it simply will not
 172 * fit.
 173 *
 174 * A small complication to all of this is that we allow userspace not only to
 175 * specify an alignment and a size for the object in the address space, but
 176 * we also allow userspace to specify the exact offset. This objects are
 177 * simpler to place (the location is known a priori) all we have to do is make
 178 * sure the space is available.
 179 *
 180 * Once all the objects are in place, patching up the buried pointers to point
 181 * to the final locations is a fairly simple job of walking over the relocation
 182 * entry arrays, looking up the right address and rewriting the value into
 183 * the object. Simple! ... The relocation entries are stored in user memory
 184 * and so to access them we have to copy them into a local buffer. That copy
 185 * has to avoid taking any pagefaults as they may lead back to a GEM object
 186 * requiring the vm->mutex (i.e. recursive deadlock). So once again we split
 187 * the relocation into multiple passes. First we try to do everything within an
 188 * atomic context (avoid the pagefaults) which requires that we never wait. If
 189 * we detect that we may wait, or if we need to fault, then we have to fallback
 190 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
 191 * bells yet?) Dropping the mutex means that we lose all the state we have
 192 * built up so far for the execbuf and we must reset any global data. However,
 193 * we do leave the objects pinned in their final locations - which is a
 194 * potential issue for concurrent execbufs. Once we have left the mutex, we can
 195 * allocate and copy all the relocation entries into a large array at our
 196 * leisure, reacquire the mutex, reclaim all the objects and other state and
 197 * then proceed to update any incorrect addresses with the objects.
 198 *
 199 * As we process the relocation entries, we maintain a record of whether the
 200 * object is being written to. Using NORELOC, we expect userspace to provide
 201 * this information instead. We also check whether we can skip the relocation
 202 * by comparing the expected value inside the relocation entry with the target's
 203 * final address. If they differ, we have to map the current object and rewrite
 204 * the 4 or 8 byte pointer within.
 205 *
 206 * Serialising an execbuf is quite simple according to the rules of the GEM
 207 * ABI. Execution within each context is ordered by the order of submission.
 208 * Writes to any GEM object are in order of submission and are exclusive. Reads
 209 * from a GEM object are unordered with respect to other reads, but ordered by
 210 * writes. A write submitted after a read cannot occur before the read, and
 211 * similarly any read submitted after a write cannot occur before the write.
 212 * Writes are ordered between engines such that only one write occurs at any
 213 * time (completing any reads beforehand) - using semaphores where available
 214 * and CPU serialisation otherwise. Other GEM access obey the same rules, any
 215 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
 216 * reads before starting, and any read (either using set-domain or pread) must
 217 * flush all GPU writes before starting. (Note we only employ a barrier before,
 218 * we currently rely on userspace not concurrently starting a new execution
 219 * whilst reading or writing to an object. This may be an advantage or not
 220 * depending on how much you trust userspace not to shoot themselves in the
 221 * foot.) Serialisation may just result in the request being inserted into
 222 * a DAG awaiting its turn, but most simple is to wait on the CPU until
 223 * all dependencies are resolved.
 224 *
 225 * After all of that, is just a matter of closing the request and handing it to
 226 * the hardware (well, leaving it in a queue to be executed). However, we also
 227 * offer the ability for batchbuffers to be run with elevated privileges so
 228 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
 229 * Before any batch is given extra privileges we first must check that it
 230 * contains no nefarious instructions, we check that each instruction is from
 231 * our whitelist and all registers are also from an allowed list. We first
 232 * copy the user's batchbuffer to a shadow (so that the user doesn't have
 233 * access to it, either by the CPU or GPU as we scan it) and then parse each
 234 * instruction. If everything is ok, we set a flag telling the hardware to run
 235 * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
 236 */
 237
 238struct eb_fence {
 239	struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */
 240	struct dma_fence *dma_fence;
 241	u64 value;
 242	struct dma_fence_chain *chain_fence;
 243};
 244
 245struct i915_execbuffer {
 246	struct drm_i915_private *i915; /** i915 backpointer */
 247	struct drm_file *file; /** per-file lookup tables and limits */
 248	struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */
 249	struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */
 250	struct eb_vma *vma;
 251
 252	struct intel_gt *gt; /* gt for the execbuf */
 253	struct intel_context *context; /* logical state for the request */
 254	struct i915_gem_context *gem_context; /** caller's context */
 255	intel_wakeref_t wakeref;
 256	intel_wakeref_t wakeref_gt0;
 257
 258	/** our requests to build */
 259	struct i915_request *requests[MAX_ENGINE_INSTANCE + 1];
 260	/** identity of the batch obj/vma */
 261	struct eb_vma *batches[MAX_ENGINE_INSTANCE + 1];
 262	struct i915_vma *trampoline; /** trampoline used for chaining */
 263
 264	/** used for excl fence in dma_resv objects when > 1 BB submitted */
 265	struct dma_fence *composite_fence;
 266
 267	/** actual size of execobj[] as we may extend it for the cmdparser */
 268	unsigned int buffer_count;
 269
 270	/* number of batches in execbuf IOCTL */
 271	unsigned int num_batches;
 272
 273	/** list of vma not yet bound during reservation phase */
 274	struct list_head unbound;
 275
 276	/** list of vma that have execobj.relocation_count */
 277	struct list_head relocs;
 278
 279	struct i915_gem_ww_ctx ww;
 280
 281	/**
 282	 * Track the most recently used object for relocations, as we
 283	 * frequently have to perform multiple relocations within the same
 284	 * obj/page
 285	 */
 286	struct reloc_cache {
 287		struct drm_mm_node node; /** temporary GTT binding */
 288		unsigned long vaddr; /** Current kmap address */
 289		unsigned long page; /** Currently mapped page index */
 290		unsigned int graphics_ver; /** Cached value of GRAPHICS_VER */
 291		bool use_64bit_reloc : 1;
 292		bool has_llc : 1;
 293		bool has_fence : 1;
 294		bool needs_unfenced : 1;
 295	} reloc_cache;
 296
 297	u64 invalid_flags; /** Set of execobj.flags that are invalid */
 298
 299	/** Length of batch within object */
 300	u64 batch_len[MAX_ENGINE_INSTANCE + 1];
 301	u32 batch_start_offset; /** Location within object of batch */
 302	u32 batch_flags; /** Flags composed for emit_bb_start() */
 303	struct intel_gt_buffer_pool_node *batch_pool; /** pool node for batch buffer */
 304
 305	/**
 306	 * Indicate either the size of the hashtable used to resolve
 307	 * relocation handles, or if negative that we are using a direct
 308	 * index into the execobj[].
 309	 */
 310	int lut_size;
 311	struct hlist_head *buckets; /** ht for relocation handles */
 312
 313	struct eb_fence *fences;
 314	unsigned long num_fences;
 315#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 316	struct i915_capture_list *capture_lists[MAX_ENGINE_INSTANCE + 1];
 317#endif
 318};
 319
 320static int eb_parse(struct i915_execbuffer *eb);
 321static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle);
 322static void eb_unpin_engine(struct i915_execbuffer *eb);
 323static void eb_capture_release(struct i915_execbuffer *eb);
 324
 325static bool eb_use_cmdparser(const struct i915_execbuffer *eb)
 326{
 327	return intel_engine_requires_cmd_parser(eb->context->engine) ||
 328		(intel_engine_using_cmd_parser(eb->context->engine) &&
 329		 eb->args->batch_len);
 330}
 331
 332static int eb_create(struct i915_execbuffer *eb)
 333{
 334	if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
 335		unsigned int size = 1 + ilog2(eb->buffer_count);
 336
 337		/*
 338		 * Without a 1:1 association between relocation handles and
 339		 * the execobject[] index, we instead create a hashtable.
 340		 * We size it dynamically based on available memory, starting
 341		 * first with 1:1 associative hash and scaling back until
 342		 * the allocation succeeds.
 343		 *
 344		 * Later on we use a positive lut_size to indicate we are
 345		 * using this hashtable, and a negative value to indicate a
 346		 * direct lookup.
 347		 */
 348		do {
 349			gfp_t flags;
 350
 351			/* While we can still reduce the allocation size, don't
 352			 * raise a warning and allow the allocation to fail.
 353			 * On the last pass though, we want to try as hard
 354			 * as possible to perform the allocation and warn
 355			 * if it fails.
 356			 */
 357			flags = GFP_KERNEL;
 358			if (size > 1)
 359				flags |= __GFP_NORETRY | __GFP_NOWARN;
 360
 361			eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
 362					      flags);
 363			if (eb->buckets)
 364				break;
 365		} while (--size);
 366
 367		if (unlikely(!size))
 368			return -ENOMEM;
 369
 370		eb->lut_size = size;
 371	} else {
 372		eb->lut_size = -eb->buffer_count;
 373	}
 374
 375	return 0;
 376}
 377
 378static bool
 379eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
 380		 const struct i915_vma *vma,
 381		 unsigned int flags)
 382{
 383	const u64 start = i915_vma_offset(vma);
 384	const u64 size = i915_vma_size(vma);
 385
 386	if (size < entry->pad_to_size)
 387		return true;
 388
 389	if (entry->alignment && !IS_ALIGNED(start, entry->alignment))
 390		return true;
 391
 392	if (flags & EXEC_OBJECT_PINNED &&
 393	    start != entry->offset)
 394		return true;
 395
 396	if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
 397	    start < BATCH_OFFSET_BIAS)
 398		return true;
 399
 400	if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
 401	    (start + size + 4095) >> 32)
 402		return true;
 403
 404	if (flags & __EXEC_OBJECT_NEEDS_MAP &&
 405	    !i915_vma_is_map_and_fenceable(vma))
 406		return true;
 407
 408	return false;
 409}
 410
 411static u64 eb_pin_flags(const struct drm_i915_gem_exec_object2 *entry,
 412			unsigned int exec_flags)
 413{
 414	u64 pin_flags = 0;
 415
 416	if (exec_flags & EXEC_OBJECT_NEEDS_GTT)
 417		pin_flags |= PIN_GLOBAL;
 418
 419	/*
 420	 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
 421	 * limit address to the first 4GBs for unflagged objects.
 422	 */
 423	if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
 424		pin_flags |= PIN_ZONE_4G;
 425
 426	if (exec_flags & __EXEC_OBJECT_NEEDS_MAP)
 427		pin_flags |= PIN_MAPPABLE;
 428
 429	if (exec_flags & EXEC_OBJECT_PINNED)
 430		pin_flags |= entry->offset | PIN_OFFSET_FIXED;
 431	else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS)
 432		pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
 433
 434	return pin_flags;
 435}
 436
 437static int
 438eb_pin_vma(struct i915_execbuffer *eb,
 439	   const struct drm_i915_gem_exec_object2 *entry,
 440	   struct eb_vma *ev)
 441{
 442	struct i915_vma *vma = ev->vma;
 443	u64 pin_flags;
 444	int err;
 445
 446	if (vma->node.size)
 447		pin_flags =  __i915_vma_offset(vma);
 448	else
 449		pin_flags = entry->offset & PIN_OFFSET_MASK;
 450
 451	pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED | PIN_VALIDATE;
 452	if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_GTT))
 453		pin_flags |= PIN_GLOBAL;
 454
 455	/* Attempt to reuse the current location if available */
 456	err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, pin_flags);
 457	if (err == -EDEADLK)
 458		return err;
 459
 460	if (unlikely(err)) {
 461		if (entry->flags & EXEC_OBJECT_PINNED)
 462			return err;
 463
 464		/* Failing that pick any _free_ space if suitable */
 465		err = i915_vma_pin_ww(vma, &eb->ww,
 466					     entry->pad_to_size,
 467					     entry->alignment,
 468					     eb_pin_flags(entry, ev->flags) |
 469					     PIN_USER | PIN_NOEVICT | PIN_VALIDATE);
 470		if (unlikely(err))
 471			return err;
 472	}
 473
 474	if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
 475		err = i915_vma_pin_fence(vma);
 476		if (unlikely(err))
 477			return err;
 478
 479		if (vma->fence)
 480			ev->flags |= __EXEC_OBJECT_HAS_FENCE;
 481	}
 482
 483	ev->flags |= __EXEC_OBJECT_HAS_PIN;
 484	if (eb_vma_misplaced(entry, vma, ev->flags))
 485		return -EBADSLT;
 486
 487	return 0;
 488}
 489
 490static void
 491eb_unreserve_vma(struct eb_vma *ev)
 492{
 493	if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE))
 494		__i915_vma_unpin_fence(ev->vma);
 495
 496	ev->flags &= ~__EXEC_OBJECT_RESERVED;
 497}
 498
 499static int
 500eb_validate_vma(struct i915_execbuffer *eb,
 501		struct drm_i915_gem_exec_object2 *entry,
 502		struct i915_vma *vma)
 503{
 504	/* Relocations are disallowed for all platforms after TGL-LP.  This
 505	 * also covers all platforms with local memory.
 506	 */
 507	if (entry->relocation_count &&
 508	    GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
 509		return -EINVAL;
 510
 511	if (unlikely(entry->flags & eb->invalid_flags))
 512		return -EINVAL;
 513
 514	if (unlikely(entry->alignment &&
 515		     !is_power_of_2_u64(entry->alignment)))
 516		return -EINVAL;
 517
 518	/*
 519	 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
 520	 * any non-page-aligned or non-canonical addresses.
 521	 */
 522	if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
 523		     entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
 524		return -EINVAL;
 525
 526	/* pad_to_size was once a reserved field, so sanitize it */
 527	if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
 528		if (unlikely(offset_in_page(entry->pad_to_size)))
 529			return -EINVAL;
 530	} else {
 531		entry->pad_to_size = 0;
 532	}
 533	/*
 534	 * From drm_mm perspective address space is continuous,
 535	 * so from this point we're always using non-canonical
 536	 * form internally.
 537	 */
 538	entry->offset = gen8_noncanonical_addr(entry->offset);
 539
 540	if (!eb->reloc_cache.has_fence) {
 541		entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
 542	} else {
 543		if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
 544		     eb->reloc_cache.needs_unfenced) &&
 545		    i915_gem_object_is_tiled(vma->obj))
 546			entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP;
 547	}
 548
 549	return 0;
 550}
 551
 552static bool
 553is_batch_buffer(struct i915_execbuffer *eb, unsigned int buffer_idx)
 554{
 555	return eb->args->flags & I915_EXEC_BATCH_FIRST ?
 556		buffer_idx < eb->num_batches :
 557		buffer_idx >= eb->args->buffer_count - eb->num_batches;
 558}
 559
 560static int
 561eb_add_vma(struct i915_execbuffer *eb,
 562	   unsigned int *current_batch,
 563	   unsigned int i,
 564	   struct i915_vma *vma)
 565{
 566	struct drm_i915_private *i915 = eb->i915;
 567	struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
 568	struct eb_vma *ev = &eb->vma[i];
 569
 570	ev->vma = vma;
 571	ev->exec = entry;
 572	ev->flags = entry->flags;
 573
 574	if (eb->lut_size > 0) {
 575		ev->handle = entry->handle;
 576		hlist_add_head(&ev->node,
 577			       &eb->buckets[hash_32(entry->handle,
 578						    eb->lut_size)]);
 579	}
 580
 581	if (entry->relocation_count)
 582		list_add_tail(&ev->reloc_link, &eb->relocs);
 583
 584	/*
 585	 * SNA is doing fancy tricks with compressing batch buffers, which leads
 586	 * to negative relocation deltas. Usually that works out ok since the
 587	 * relocate address is still positive, except when the batch is placed
 588	 * very low in the GTT. Ensure this doesn't happen.
 589	 *
 590	 * Note that actual hangs have only been observed on gen7, but for
 591	 * paranoia do it everywhere.
 592	 */
 593	if (is_batch_buffer(eb, i)) {
 594		if (entry->relocation_count &&
 595		    !(ev->flags & EXEC_OBJECT_PINNED))
 596			ev->flags |= __EXEC_OBJECT_NEEDS_BIAS;
 597		if (eb->reloc_cache.has_fence)
 598			ev->flags |= EXEC_OBJECT_NEEDS_FENCE;
 599
 600		eb->batches[*current_batch] = ev;
 601
 602		if (unlikely(ev->flags & EXEC_OBJECT_WRITE)) {
 603			drm_dbg(&i915->drm,
 604				"Attempting to use self-modifying batch buffer\n");
 605			return -EINVAL;
 606		}
 607
 608		if (range_overflows_t(u64,
 609				      eb->batch_start_offset,
 610				      eb->args->batch_len,
 611				      ev->vma->size)) {
 612			drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n");
 613			return -EINVAL;
 614		}
 615
 616		if (eb->args->batch_len == 0)
 617			eb->batch_len[*current_batch] = ev->vma->size -
 618				eb->batch_start_offset;
 619		else
 620			eb->batch_len[*current_batch] = eb->args->batch_len;
 621		if (unlikely(eb->batch_len[*current_batch] == 0)) { /* impossible! */
 622			drm_dbg(&i915->drm, "Invalid batch length\n");
 623			return -EINVAL;
 624		}
 625
 626		++*current_batch;
 627	}
 628
 629	return 0;
 630}
 631
 632static int use_cpu_reloc(const struct reloc_cache *cache,
 633			 const struct drm_i915_gem_object *obj)
 634{
 635	if (!i915_gem_object_has_struct_page(obj))
 636		return false;
 637
 638	if (DBG_FORCE_RELOC == FORCE_CPU_RELOC)
 639		return true;
 640
 641	if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
 642		return false;
 643
 644	/*
 645	 * For objects created by userspace through GEM_CREATE with pat_index
 646	 * set by set_pat extension, i915_gem_object_has_cache_level() always
 647	 * return true, otherwise the call would fall back to checking whether
 648	 * the object is un-cached.
 649	 */
 650	return (cache->has_llc ||
 651		obj->cache_dirty ||
 652		!i915_gem_object_has_cache_level(obj, I915_CACHE_NONE));
 653}
 654
 655static int eb_reserve_vma(struct i915_execbuffer *eb,
 656			  struct eb_vma *ev,
 657			  u64 pin_flags)
 658{
 659	struct drm_i915_gem_exec_object2 *entry = ev->exec;
 660	struct i915_vma *vma = ev->vma;
 661	int err;
 662
 663	if (drm_mm_node_allocated(&vma->node) &&
 664	    eb_vma_misplaced(entry, vma, ev->flags)) {
 665		err = i915_vma_unbind(vma);
 666		if (err)
 667			return err;
 668	}
 669
 670	err = i915_vma_pin_ww(vma, &eb->ww,
 671			   entry->pad_to_size, entry->alignment,
 672			   eb_pin_flags(entry, ev->flags) | pin_flags);
 673	if (err)
 674		return err;
 675
 676	if (entry->offset != i915_vma_offset(vma)) {
 677		entry->offset = i915_vma_offset(vma) | UPDATE;
 678		eb->args->flags |= __EXEC_HAS_RELOC;
 679	}
 680
 681	if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
 682		err = i915_vma_pin_fence(vma);
 683		if (unlikely(err))
 684			return err;
 685
 686		if (vma->fence)
 687			ev->flags |= __EXEC_OBJECT_HAS_FENCE;
 688	}
 689
 690	ev->flags |= __EXEC_OBJECT_HAS_PIN;
 691	GEM_BUG_ON(eb_vma_misplaced(entry, vma, ev->flags));
 692
 693	return 0;
 694}
 695
 696static bool eb_unbind(struct i915_execbuffer *eb, bool force)
 697{
 698	const unsigned int count = eb->buffer_count;
 699	unsigned int i;
 700	struct list_head last;
 701	bool unpinned = false;
 702
 703	/* Resort *all* the objects into priority order */
 704	INIT_LIST_HEAD(&eb->unbound);
 705	INIT_LIST_HEAD(&last);
 706
 707	for (i = 0; i < count; i++) {
 708		struct eb_vma *ev = &eb->vma[i];
 709		unsigned int flags = ev->flags;
 710
 711		if (!force && flags & EXEC_OBJECT_PINNED &&
 712		    flags & __EXEC_OBJECT_HAS_PIN)
 713			continue;
 714
 715		unpinned = true;
 716		eb_unreserve_vma(ev);
 717
 718		if (flags & EXEC_OBJECT_PINNED)
 719			/* Pinned must have their slot */
 720			list_add(&ev->bind_link, &eb->unbound);
 721		else if (flags & __EXEC_OBJECT_NEEDS_MAP)
 722			/* Map require the lowest 256MiB (aperture) */
 723			list_add_tail(&ev->bind_link, &eb->unbound);
 724		else if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
 725			/* Prioritise 4GiB region for restricted bo */
 726			list_add(&ev->bind_link, &last);
 727		else
 728			list_add_tail(&ev->bind_link, &last);
 729	}
 730
 731	list_splice_tail(&last, &eb->unbound);
 732	return unpinned;
 733}
 734
 735static int eb_reserve(struct i915_execbuffer *eb)
 736{
 737	struct eb_vma *ev;
 738	unsigned int pass;
 739	int err = 0;
 740
 741	/*
 742	 * We have one more buffers that we couldn't bind, which could be due to
 743	 * various reasons. To resolve this we have 4 passes, with every next
 744	 * level turning the screws tighter:
 745	 *
 746	 * 0. Unbind all objects that do not match the GTT constraints for the
 747	 * execbuffer (fenceable, mappable, alignment etc). Bind all new
 748	 * objects.  This avoids unnecessary unbinding of later objects in order
 749	 * to make room for the earlier objects *unless* we need to defragment.
 750	 *
 751	 * 1. Reorder the buffers, where objects with the most restrictive
 752	 * placement requirements go first (ignoring fixed location buffers for
 753	 * now).  For example, objects needing the mappable aperture (the first
 754	 * 256M of GTT), should go first vs objects that can be placed just
 755	 * about anywhere. Repeat the previous pass.
 756	 *
 757	 * 2. Consider buffers that are pinned at a fixed location. Also try to
 758	 * evict the entire VM this time, leaving only objects that we were
 759	 * unable to lock. Try again to bind the buffers. (still using the new
 760	 * buffer order).
 761	 *
 762	 * 3. We likely have object lock contention for one or more stubborn
 763	 * objects in the VM, for which we need to evict to make forward
 764	 * progress (perhaps we are fighting the shrinker?). When evicting the
 765	 * VM this time around, anything that we can't lock we now track using
 766	 * the busy_bo, using the full lock (after dropping the vm->mutex to
 767	 * prevent deadlocks), instead of trylock. We then continue to evict the
 768	 * VM, this time with the stubborn object locked, which we can now
 769	 * hopefully unbind (if still bound in the VM). Repeat until the VM is
 770	 * evicted. Finally we should be able bind everything.
 771	 */
 772	for (pass = 0; pass <= 3; pass++) {
 773		int pin_flags = PIN_USER | PIN_VALIDATE;
 774
 775		if (pass == 0)
 776			pin_flags |= PIN_NONBLOCK;
 777
 778		if (pass >= 1)
 779			eb_unbind(eb, pass >= 2);
 780
 781		if (pass == 2) {
 782			err = mutex_lock_interruptible(&eb->context->vm->mutex);
 783			if (!err) {
 784				err = i915_gem_evict_vm(eb->context->vm, &eb->ww, NULL);
 785				mutex_unlock(&eb->context->vm->mutex);
 786			}
 787			if (err)
 788				return err;
 789		}
 790
 791		if (pass == 3) {
 792retry:
 793			err = mutex_lock_interruptible(&eb->context->vm->mutex);
 794			if (!err) {
 795				struct drm_i915_gem_object *busy_bo = NULL;
 796
 797				err = i915_gem_evict_vm(eb->context->vm, &eb->ww, &busy_bo);
 798				mutex_unlock(&eb->context->vm->mutex);
 799				if (err && busy_bo) {
 800					err = i915_gem_object_lock(busy_bo, &eb->ww);
 801					i915_gem_object_put(busy_bo);
 802					if (!err)
 803						goto retry;
 804				}
 805			}
 806			if (err)
 807				return err;
 808		}
 809
 810		list_for_each_entry(ev, &eb->unbound, bind_link) {
 811			err = eb_reserve_vma(eb, ev, pin_flags);
 812			if (err)
 813				break;
 814		}
 815
 816		if (err != -ENOSPC)
 817			break;
 818	}
 819
 820	return err;
 821}
 822
 823static int eb_select_context(struct i915_execbuffer *eb)
 824{
 825	struct i915_gem_context *ctx;
 826
 827	ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1);
 828	if (IS_ERR(ctx))
 829		return PTR_ERR(ctx);
 830
 831	eb->gem_context = ctx;
 832	if (i915_gem_context_has_full_ppgtt(ctx))
 833		eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
 834
 835	return 0;
 836}
 837
 838static int __eb_add_lut(struct i915_execbuffer *eb,
 839			u32 handle, struct i915_vma *vma)
 840{
 841	struct i915_gem_context *ctx = eb->gem_context;
 842	struct i915_lut_handle *lut;
 843	int err;
 844
 845	lut = i915_lut_handle_alloc();
 846	if (unlikely(!lut))
 847		return -ENOMEM;
 848
 849	i915_vma_get(vma);
 850	if (!atomic_fetch_inc(&vma->open_count))
 851		i915_vma_reopen(vma);
 852	lut->handle = handle;
 853	lut->ctx = ctx;
 854
 855	/* Check that the context hasn't been closed in the meantime */
 856	err = -EINTR;
 857	if (!mutex_lock_interruptible(&ctx->lut_mutex)) {
 858		if (likely(!i915_gem_context_is_closed(ctx)))
 859			err = radix_tree_insert(&ctx->handles_vma, handle, vma);
 860		else
 861			err = -ENOENT;
 862		if (err == 0) { /* And nor has this handle */
 863			struct drm_i915_gem_object *obj = vma->obj;
 864
 865			spin_lock(&obj->lut_lock);
 866			if (idr_find(&eb->file->object_idr, handle) == obj) {
 867				list_add(&lut->obj_link, &obj->lut_list);
 868			} else {
 869				radix_tree_delete(&ctx->handles_vma, handle);
 870				err = -ENOENT;
 871			}
 872			spin_unlock(&obj->lut_lock);
 873		}
 874		mutex_unlock(&ctx->lut_mutex);
 875	}
 876	if (unlikely(err))
 877		goto err;
 878
 879	return 0;
 880
 881err:
 882	i915_vma_close(vma);
 883	i915_vma_put(vma);
 884	i915_lut_handle_free(lut);
 885	return err;
 886}
 887
 888static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle)
 889{
 890	struct i915_address_space *vm = eb->context->vm;
 891
 892	do {
 893		struct drm_i915_gem_object *obj;
 894		struct i915_vma *vma;
 895		int err;
 896
 897		rcu_read_lock();
 898		vma = radix_tree_lookup(&eb->gem_context->handles_vma, handle);
 899		if (likely(vma && vma->vm == vm))
 900			vma = i915_vma_tryget(vma);
 901		rcu_read_unlock();
 902		if (likely(vma))
 903			return vma;
 904
 905		obj = i915_gem_object_lookup(eb->file, handle);
 906		if (unlikely(!obj))
 907			return ERR_PTR(-ENOENT);
 908
 909		/*
 910		 * If the user has opted-in for protected-object tracking, make
 911		 * sure the object encryption can be used.
 912		 * We only need to do this when the object is first used with
 913		 * this context, because the context itself will be banned when
 914		 * the protected objects become invalid.
 915		 */
 916		if (i915_gem_context_uses_protected_content(eb->gem_context) &&
 917		    i915_gem_object_is_protected(obj)) {
 918			err = intel_pxp_key_check(intel_bo_to_drm_bo(obj), true);
 919			if (err) {
 920				i915_gem_object_put(obj);
 921				return ERR_PTR(err);
 922			}
 923		}
 924
 925		vma = i915_vma_instance(obj, vm, NULL);
 926		if (IS_ERR(vma)) {
 927			i915_gem_object_put(obj);
 928			return vma;
 929		}
 930
 931		err = __eb_add_lut(eb, handle, vma);
 932		if (likely(!err))
 933			return vma;
 934
 935		i915_gem_object_put(obj);
 936		if (err != -EEXIST)
 937			return ERR_PTR(err);
 938	} while (1);
 939}
 940
 941static int eb_lookup_vmas(struct i915_execbuffer *eb)
 942{
 943	unsigned int i, current_batch = 0;
 944	int err = 0;
 945
 946	INIT_LIST_HEAD(&eb->relocs);
 947
 948	for (i = 0; i < eb->buffer_count; i++) {
 949		struct i915_vma *vma;
 950
 951		vma = eb_lookup_vma(eb, eb->exec[i].handle);
 952		if (IS_ERR(vma)) {
 953			err = PTR_ERR(vma);
 954			return err;
 955		}
 956
 957		err = eb_validate_vma(eb, &eb->exec[i], vma);
 958		if (unlikely(err)) {
 959			i915_vma_put(vma);
 960			return err;
 961		}
 962
 963		err = eb_add_vma(eb, &current_batch, i, vma);
 964		if (err)
 965			return err;
 966
 967		if (i915_gem_object_is_userptr(vma->obj)) {
 968			err = i915_gem_object_userptr_submit_init(vma->obj);
 969			if (err)
 970				return err;
 971
 972			eb->vma[i].flags |= __EXEC_OBJECT_USERPTR_INIT;
 973			eb->args->flags |= __EXEC_USERPTR_USED;
 974		}
 975	}
 976
 977	return 0;
 978}
 979
 980static int eb_lock_vmas(struct i915_execbuffer *eb)
 981{
 982	unsigned int i;
 983	int err;
 984
 985	for (i = 0; i < eb->buffer_count; i++) {
 986		struct eb_vma *ev = &eb->vma[i];
 987		struct i915_vma *vma = ev->vma;
 988
 989		err = i915_gem_object_lock(vma->obj, &eb->ww);
 990		if (err)
 991			return err;
 992	}
 993
 994	return 0;
 995}
 996
 997static int eb_validate_vmas(struct i915_execbuffer *eb)
 998{
 999	unsigned int i;
1000	int err;
1001
1002	INIT_LIST_HEAD(&eb->unbound);
1003
1004	err = eb_lock_vmas(eb);
1005	if (err)
1006		return err;
1007
1008	for (i = 0; i < eb->buffer_count; i++) {
1009		struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
1010		struct eb_vma *ev = &eb->vma[i];
1011		struct i915_vma *vma = ev->vma;
1012
1013		err = eb_pin_vma(eb, entry, ev);
1014		if (err == -EDEADLK)
1015			return err;
1016
1017		if (!err) {
1018			if (entry->offset != i915_vma_offset(vma)) {
1019				entry->offset = i915_vma_offset(vma) | UPDATE;
1020				eb->args->flags |= __EXEC_HAS_RELOC;
1021			}
1022		} else {
1023			eb_unreserve_vma(ev);
1024
1025			list_add_tail(&ev->bind_link, &eb->unbound);
1026			if (drm_mm_node_allocated(&vma->node)) {
1027				err = i915_vma_unbind(vma);
1028				if (err)
1029					return err;
1030			}
1031		}
1032
1033		/* Reserve enough slots to accommodate composite fences */
1034		err = dma_resv_reserve_fences(vma->obj->base.resv, eb->num_batches);
1035		if (err)
1036			return err;
1037
1038		GEM_BUG_ON(drm_mm_node_allocated(&vma->node) &&
1039			   eb_vma_misplaced(&eb->exec[i], vma, ev->flags));
1040	}
1041
1042	if (!list_empty(&eb->unbound))
1043		return eb_reserve(eb);
1044
1045	return 0;
1046}
1047
1048static struct eb_vma *
1049eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle)
1050{
1051	if (eb->lut_size < 0) {
1052		if (handle >= -eb->lut_size)
1053			return NULL;
1054		return &eb->vma[handle];
1055	} else {
1056		struct hlist_head *head;
1057		struct eb_vma *ev;
1058
1059		head = &eb->buckets[hash_32(handle, eb->lut_size)];
1060		hlist_for_each_entry(ev, head, node) {
1061			if (ev->handle == handle)
1062				return ev;
1063		}
1064		return NULL;
1065	}
1066}
1067
1068static void eb_release_vmas(struct i915_execbuffer *eb, bool final)
1069{
1070	const unsigned int count = eb->buffer_count;
1071	unsigned int i;
1072
1073	for (i = 0; i < count; i++) {
1074		struct eb_vma *ev = &eb->vma[i];
1075		struct i915_vma *vma = ev->vma;
1076
1077		if (!vma)
1078			break;
1079
1080		eb_unreserve_vma(ev);
1081
1082		if (final)
1083			i915_vma_put(vma);
1084	}
1085
1086	eb_capture_release(eb);
1087	eb_unpin_engine(eb);
1088}
1089
1090static void eb_destroy(const struct i915_execbuffer *eb)
1091{
1092	if (eb->lut_size > 0)
1093		kfree(eb->buckets);
1094}
1095
1096static u64
1097relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
1098		  const struct i915_vma *target)
1099{
1100	return gen8_canonical_addr((int)reloc->delta + i915_vma_offset(target));
1101}
1102
1103static void reloc_cache_init(struct reloc_cache *cache,
1104			     struct drm_i915_private *i915)
1105{
1106	cache->page = -1;
1107	cache->vaddr = 0;
1108	/* Must be a variable in the struct to allow GCC to unroll. */
1109	cache->graphics_ver = GRAPHICS_VER(i915);
1110	cache->has_llc = HAS_LLC(i915);
1111	cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
1112	cache->has_fence = cache->graphics_ver < 4;
1113	cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
1114	cache->node.flags = 0;
1115}
1116
1117static void *unmask_page(unsigned long p)
1118{
1119	return (void *)(uintptr_t)(p & PAGE_MASK);
1120}
1121
1122static unsigned int unmask_flags(unsigned long p)
1123{
1124	return p & ~PAGE_MASK;
1125}
1126
1127#define KMAP 0x4 /* after CLFLUSH_FLAGS */
1128
1129static struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
1130{
1131	struct drm_i915_private *i915 =
1132		container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
1133	return to_gt(i915)->ggtt;
1134}
1135
1136static void reloc_cache_unmap(struct reloc_cache *cache)
1137{
1138	void *vaddr;
1139
1140	if (!cache->vaddr)
1141		return;
1142
1143	vaddr = unmask_page(cache->vaddr);
1144	if (cache->vaddr & KMAP)
1145		kunmap_local(vaddr);
1146	else
1147		io_mapping_unmap_atomic((void __iomem *)vaddr);
1148}
1149
1150static void reloc_cache_remap(struct reloc_cache *cache,
1151			      struct drm_i915_gem_object *obj)
1152{
1153	void *vaddr;
1154
1155	if (!cache->vaddr)
1156		return;
1157
1158	if (cache->vaddr & KMAP) {
1159		struct page *page = i915_gem_object_get_page(obj, cache->page);
1160
1161		vaddr = kmap_local_page(page);
1162		cache->vaddr = unmask_flags(cache->vaddr) |
1163			(unsigned long)vaddr;
1164	} else {
1165		struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1166		unsigned long offset;
1167
1168		offset = cache->node.start;
1169		if (!drm_mm_node_allocated(&cache->node))
1170			offset += cache->page << PAGE_SHIFT;
1171
1172		cache->vaddr = (unsigned long)
1173			io_mapping_map_atomic_wc(&ggtt->iomap, offset);
1174	}
1175}
1176
1177static void reloc_cache_reset(struct reloc_cache *cache, struct i915_execbuffer *eb)
1178{
1179	void *vaddr;
1180
1181	if (!cache->vaddr)
1182		return;
1183
1184	vaddr = unmask_page(cache->vaddr);
1185	if (cache->vaddr & KMAP) {
1186		struct drm_i915_gem_object *obj =
1187			(struct drm_i915_gem_object *)cache->node.mm;
1188		if (cache->vaddr & CLFLUSH_AFTER)
1189			mb();
1190
1191		kunmap_local(vaddr);
1192		i915_gem_object_finish_access(obj);
1193	} else {
1194		struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1195
1196		intel_gt_flush_ggtt_writes(ggtt->vm.gt);
1197		io_mapping_unmap_atomic((void __iomem *)vaddr);
1198
1199		if (drm_mm_node_allocated(&cache->node)) {
1200			ggtt->vm.clear_range(&ggtt->vm,
1201					     cache->node.start,
1202					     cache->node.size);
1203			mutex_lock(&ggtt->vm.mutex);
1204			drm_mm_remove_node(&cache->node);
1205			mutex_unlock(&ggtt->vm.mutex);
1206		} else {
1207			i915_vma_unpin((struct i915_vma *)cache->node.mm);
1208		}
1209	}
1210
1211	cache->vaddr = 0;
1212	cache->page = -1;
1213}
1214
1215static void *reloc_kmap(struct drm_i915_gem_object *obj,
1216			struct reloc_cache *cache,
1217			unsigned long pageno)
1218{
1219	void *vaddr;
1220	struct page *page;
1221
1222	if (cache->vaddr) {
1223		kunmap_local(unmask_page(cache->vaddr));
1224	} else {
1225		unsigned int flushes;
1226		int err;
1227
1228		err = i915_gem_object_prepare_write(obj, &flushes);
1229		if (err)
1230			return ERR_PTR(err);
1231
1232		BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
1233		BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
1234
1235		cache->vaddr = flushes | KMAP;
1236		cache->node.mm = (void *)obj;
1237		if (flushes)
1238			mb();
1239	}
1240
1241	page = i915_gem_object_get_page(obj, pageno);
1242	if (!obj->mm.dirty)
1243		set_page_dirty(page);
1244
1245	vaddr = kmap_local_page(page);
1246	cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
1247	cache->page = pageno;
1248
1249	return vaddr;
1250}
1251
1252static void *reloc_iomap(struct i915_vma *batch,
1253			 struct i915_execbuffer *eb,
1254			 unsigned long page)
1255{
1256	struct drm_i915_gem_object *obj = batch->obj;
1257	struct reloc_cache *cache = &eb->reloc_cache;
1258	struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1259	unsigned long offset;
1260	void *vaddr;
1261
1262	if (cache->vaddr) {
1263		intel_gt_flush_ggtt_writes(ggtt->vm.gt);
1264		io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
1265	} else {
1266		struct i915_vma *vma = ERR_PTR(-ENODEV);
1267		int err;
1268
1269		if (i915_gem_object_is_tiled(obj))
1270			return ERR_PTR(-EINVAL);
1271
1272		if (use_cpu_reloc(cache, obj))
1273			return NULL;
1274
1275		err = i915_gem_object_set_to_gtt_domain(obj, true);
1276		if (err)
1277			return ERR_PTR(err);
1278
1279		/*
1280		 * i915_gem_object_ggtt_pin_ww may attempt to remove the batch
1281		 * VMA from the object list because we no longer pin.
1282		 *
1283		 * Only attempt to pin the batch buffer to ggtt if the current batch
1284		 * is not inside ggtt, or the batch buffer is not misplaced.
1285		 */
1286		if (!i915_is_ggtt(batch->vm) ||
1287		    !i915_vma_misplaced(batch, 0, 0, PIN_MAPPABLE)) {
1288			vma = i915_gem_object_ggtt_pin_ww(obj, &eb->ww, NULL, 0, 0,
1289							  PIN_MAPPABLE |
1290							  PIN_NONBLOCK /* NOWARN */ |
1291							  PIN_NOEVICT);
1292		}
1293
1294		if (vma == ERR_PTR(-EDEADLK))
1295			return vma;
1296
1297		if (IS_ERR(vma)) {
1298			memset(&cache->node, 0, sizeof(cache->node));
1299			mutex_lock(&ggtt->vm.mutex);
1300			err = drm_mm_insert_node_in_range
1301				(&ggtt->vm.mm, &cache->node,
1302				 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
1303				 0, ggtt->mappable_end,
1304				 DRM_MM_INSERT_LOW);
1305			mutex_unlock(&ggtt->vm.mutex);
1306			if (err) /* no inactive aperture space, use cpu reloc */
1307				return NULL;
1308		} else {
1309			cache->node.start = i915_ggtt_offset(vma);
1310			cache->node.mm = (void *)vma;
1311		}
1312	}
1313
1314	offset = cache->node.start;
1315	if (drm_mm_node_allocated(&cache->node)) {
1316		ggtt->vm.insert_page(&ggtt->vm,
1317				     i915_gem_object_get_dma_address(obj, page),
1318				     offset,
1319				     i915_gem_get_pat_index(ggtt->vm.i915,
1320							    I915_CACHE_NONE),
1321				     0);
1322	} else {
1323		offset += page << PAGE_SHIFT;
1324	}
1325
1326	vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap,
1327							 offset);
1328	cache->page = page;
1329	cache->vaddr = (unsigned long)vaddr;
1330
1331	return vaddr;
1332}
1333
1334static void *reloc_vaddr(struct i915_vma *vma,
1335			 struct i915_execbuffer *eb,
1336			 unsigned long page)
1337{
1338	struct reloc_cache *cache = &eb->reloc_cache;
1339	void *vaddr;
1340
1341	if (cache->page == page) {
1342		vaddr = unmask_page(cache->vaddr);
1343	} else {
1344		vaddr = NULL;
1345		if ((cache->vaddr & KMAP) == 0)
1346			vaddr = reloc_iomap(vma, eb, page);
1347		if (!vaddr)
1348			vaddr = reloc_kmap(vma->obj, cache, page);
1349	}
1350
1351	return vaddr;
1352}
1353
1354static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
1355{
1356	if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
1357		if (flushes & CLFLUSH_BEFORE)
1358			drm_clflush_virt_range(addr, sizeof(*addr));
1359
1360		*addr = value;
1361
1362		/*
1363		 * Writes to the same cacheline are serialised by the CPU
1364		 * (including clflush). On the write path, we only require
1365		 * that it hits memory in an orderly fashion and place
1366		 * mb barriers at the start and end of the relocation phase
1367		 * to ensure ordering of clflush wrt to the system.
1368		 */
1369		if (flushes & CLFLUSH_AFTER)
1370			drm_clflush_virt_range(addr, sizeof(*addr));
1371	} else {
1372		*addr = value;
1373	}
1374}
1375
1376static u64
1377relocate_entry(struct i915_vma *vma,
1378	       const struct drm_i915_gem_relocation_entry *reloc,
1379	       struct i915_execbuffer *eb,
1380	       const struct i915_vma *target)
1381{
1382	u64 target_addr = relocation_target(reloc, target);
1383	u64 offset = reloc->offset;
1384	bool wide = eb->reloc_cache.use_64bit_reloc;
1385	void *vaddr;
1386
1387repeat:
1388	vaddr = reloc_vaddr(vma, eb,
1389			    offset >> PAGE_SHIFT);
1390	if (IS_ERR(vaddr))
1391		return PTR_ERR(vaddr);
1392
1393	GEM_BUG_ON(!IS_ALIGNED(offset, sizeof(u32)));
1394	clflush_write32(vaddr + offset_in_page(offset),
1395			lower_32_bits(target_addr),
1396			eb->reloc_cache.vaddr);
1397
1398	if (wide) {
1399		offset += sizeof(u32);
1400		target_addr >>= 32;
1401		wide = false;
1402		goto repeat;
1403	}
1404
1405	return target->node.start | UPDATE;
1406}
1407
1408static u64
1409eb_relocate_entry(struct i915_execbuffer *eb,
1410		  struct eb_vma *ev,
1411		  const struct drm_i915_gem_relocation_entry *reloc)
1412{
1413	struct drm_i915_private *i915 = eb->i915;
1414	struct eb_vma *target;
1415	int err;
1416
1417	/* we've already hold a reference to all valid objects */
1418	target = eb_get_vma(eb, reloc->target_handle);
1419	if (unlikely(!target))
1420		return -ENOENT;
1421
1422	/* Validate that the target is in a valid r/w GPU domain */
1423	if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
1424		drm_dbg(&i915->drm, "reloc with multiple write domains: "
1425			  "target %d offset %d "
1426			  "read %08x write %08x\n",
1427			  reloc->target_handle,
1428			  (int) reloc->offset,
1429			  reloc->read_domains,
1430			  reloc->write_domain);
1431		return -EINVAL;
1432	}
1433	if (unlikely((reloc->write_domain | reloc->read_domains)
1434		     & ~I915_GEM_GPU_DOMAINS)) {
1435		drm_dbg(&i915->drm, "reloc with read/write non-GPU domains: "
1436			  "target %d offset %d "
1437			  "read %08x write %08x\n",
1438			  reloc->target_handle,
1439			  (int) reloc->offset,
1440			  reloc->read_domains,
1441			  reloc->write_domain);
1442		return -EINVAL;
1443	}
1444
1445	if (reloc->write_domain) {
1446		target->flags |= EXEC_OBJECT_WRITE;
1447
1448		/*
1449		 * Sandybridge PPGTT errata: We need a global gtt mapping
1450		 * for MI and pipe_control writes because the gpu doesn't
1451		 * properly redirect them through the ppgtt for non_secure
1452		 * batchbuffers.
1453		 */
1454		if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1455		    GRAPHICS_VER(eb->i915) == 6 &&
1456		    !i915_vma_is_bound(target->vma, I915_VMA_GLOBAL_BIND)) {
1457			struct i915_vma *vma = target->vma;
1458
1459			reloc_cache_unmap(&eb->reloc_cache);
1460			mutex_lock(&vma->vm->mutex);
1461			err = i915_vma_bind(target->vma,
1462					    target->vma->obj->pat_index,
1463					    PIN_GLOBAL, NULL, NULL);
1464			mutex_unlock(&vma->vm->mutex);
1465			reloc_cache_remap(&eb->reloc_cache, ev->vma->obj);
1466			if (err)
1467				return err;
1468		}
1469	}
1470
1471	/*
1472	 * If the relocation already has the right value in it, no
1473	 * more work needs to be done.
1474	 */
1475	if (!DBG_FORCE_RELOC &&
1476	    gen8_canonical_addr(i915_vma_offset(target->vma)) == reloc->presumed_offset)
1477		return 0;
1478
1479	/* Check that the relocation address is valid... */
1480	if (unlikely(reloc->offset >
1481		     ev->vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) {
1482		drm_dbg(&i915->drm, "Relocation beyond object bounds: "
1483			  "target %d offset %d size %d.\n",
1484			  reloc->target_handle,
1485			  (int)reloc->offset,
1486			  (int)ev->vma->size);
1487		return -EINVAL;
1488	}
1489	if (unlikely(reloc->offset & 3)) {
1490		drm_dbg(&i915->drm, "Relocation not 4-byte aligned: "
1491			  "target %d offset %d.\n",
1492			  reloc->target_handle,
1493			  (int)reloc->offset);
1494		return -EINVAL;
1495	}
1496
1497	/*
1498	 * If we write into the object, we need to force the synchronisation
1499	 * barrier, either with an asynchronous clflush or if we executed the
1500	 * patching using the GPU (though that should be serialised by the
1501	 * timeline). To be completely sure, and since we are required to
1502	 * do relocations we are already stalling, disable the user's opt
1503	 * out of our synchronisation.
1504	 */
1505	ev->flags &= ~EXEC_OBJECT_ASYNC;
1506
1507	/* and update the user's relocation entry */
1508	return relocate_entry(ev->vma, reloc, eb, target->vma);
1509}
1510
1511static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev)
1512{
1513#define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1514	struct drm_i915_gem_relocation_entry stack[N_RELOC(512)];
1515	const struct drm_i915_gem_exec_object2 *entry = ev->exec;
1516	struct drm_i915_gem_relocation_entry __user *urelocs =
1517		u64_to_user_ptr(entry->relocs_ptr);
1518	unsigned long remain = entry->relocation_count;
1519
1520	if (unlikely(remain > N_RELOC(INT_MAX)))
1521		return -EINVAL;
1522
1523	/*
1524	 * We must check that the entire relocation array is safe
1525	 * to read. However, if the array is not writable the user loses
1526	 * the updated relocation values.
1527	 */
1528	if (unlikely(!access_ok(urelocs, remain * sizeof(*urelocs))))
1529		return -EFAULT;
1530
1531	do {
1532		struct drm_i915_gem_relocation_entry *r = stack;
1533		unsigned int count =
1534			min_t(unsigned long, remain, ARRAY_SIZE(stack));
1535		unsigned int copied;
1536
1537		/*
1538		 * This is the fast path and we cannot handle a pagefault
1539		 * whilst holding the struct mutex lest the user pass in the
1540		 * relocations contained within a mmaped bo. For in such a case
1541		 * we, the page fault handler would call i915_gem_fault() and
1542		 * we would try to acquire the struct mutex again. Obviously
1543		 * this is bad and so lockdep complains vehemently.
1544		 */
1545		pagefault_disable();
1546		copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0]));
1547		pagefault_enable();
1548		if (unlikely(copied)) {
1549			remain = -EFAULT;
1550			goto out;
1551		}
1552
1553		remain -= count;
1554		do {
1555			u64 offset = eb_relocate_entry(eb, ev, r);
1556
1557			if (likely(offset == 0))
1558				continue;
1559
1560			if ((s64)offset < 0) {
1561				remain = (int)offset;
1562				goto out;
1563			}
1564			/*
1565			 * Note that reporting an error now
1566			 * leaves everything in an inconsistent
1567			 * state as we have *already* changed
1568			 * the relocation value inside the
1569			 * object. As we have not changed the
1570			 * reloc.presumed_offset or will not
1571			 * change the execobject.offset, on the
1572			 * call we may not rewrite the value
1573			 * inside the object, leaving it
1574			 * dangling and causing a GPU hang. Unless
1575			 * userspace dynamically rebuilds the
1576			 * relocations on each execbuf rather than
1577			 * presume a static tree.
1578			 *
1579			 * We did previously check if the relocations
1580			 * were writable (access_ok), an error now
1581			 * would be a strange race with mprotect,
1582			 * having already demonstrated that we
1583			 * can read from this userspace address.
1584			 */
1585			offset = gen8_canonical_addr(offset & ~UPDATE);
1586			__put_user(offset, &urelocs[r - stack].presumed_offset);
1587		} while (r++, --count);
1588		urelocs += ARRAY_SIZE(stack);
1589	} while (remain);
1590out:
1591	reloc_cache_reset(&eb->reloc_cache, eb);
1592	return remain;
1593}
1594
1595static int
1596eb_relocate_vma_slow(struct i915_execbuffer *eb, struct eb_vma *ev)
1597{
1598	const struct drm_i915_gem_exec_object2 *entry = ev->exec;
1599	struct drm_i915_gem_relocation_entry *relocs =
1600		u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1601	unsigned int i;
1602	int err;
1603
1604	for (i = 0; i < entry->relocation_count; i++) {
1605		u64 offset = eb_relocate_entry(eb, ev, &relocs[i]);
1606
1607		if ((s64)offset < 0) {
1608			err = (int)offset;
1609			goto err;
1610		}
1611	}
1612	err = 0;
1613err:
1614	reloc_cache_reset(&eb->reloc_cache, eb);
1615	return err;
1616}
1617
1618static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
1619{
1620	const char __user *addr, *end;
1621	unsigned long size;
1622	char __maybe_unused c;
1623
1624	size = entry->relocation_count;
1625	if (size == 0)
1626		return 0;
1627
1628	if (size > N_RELOC(INT_MAX))
1629		return -EINVAL;
1630
1631	addr = u64_to_user_ptr(entry->relocs_ptr);
1632	size *= sizeof(struct drm_i915_gem_relocation_entry);
1633	if (!access_ok(addr, size))
1634		return -EFAULT;
1635
1636	end = addr + size;
1637	for (; addr < end; addr += PAGE_SIZE) {
1638		int err = __get_user(c, addr);
1639		if (err)
1640			return err;
1641	}
1642	return __get_user(c, end - 1);
1643}
1644
1645static int eb_copy_relocations(const struct i915_execbuffer *eb)
1646{
1647	struct drm_i915_gem_relocation_entry *relocs;
1648	const unsigned int count = eb->buffer_count;
1649	unsigned int i;
1650	int err;
1651
1652	for (i = 0; i < count; i++) {
1653		const unsigned int nreloc = eb->exec[i].relocation_count;
1654		struct drm_i915_gem_relocation_entry __user *urelocs;
1655		unsigned long size;
1656		unsigned long copied;
1657
1658		if (nreloc == 0)
1659			continue;
1660
1661		err = check_relocations(&eb->exec[i]);
1662		if (err)
1663			goto err;
1664
1665		urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
1666		size = nreloc * sizeof(*relocs);
1667
1668		relocs = kvmalloc_array(1, size, GFP_KERNEL);
1669		if (!relocs) {
1670			err = -ENOMEM;
1671			goto err;
1672		}
1673
1674		/* copy_from_user is limited to < 4GiB */
1675		copied = 0;
1676		do {
1677			unsigned int len =
1678				min_t(u64, BIT_ULL(31), size - copied);
1679
1680			if (__copy_from_user((char *)relocs + copied,
1681					     (char __user *)urelocs + copied,
1682					     len))
1683				goto end;
1684
1685			copied += len;
1686		} while (copied < size);
1687
1688		/*
1689		 * As we do not update the known relocation offsets after
1690		 * relocating (due to the complexities in lock handling),
1691		 * we need to mark them as invalid now so that we force the
1692		 * relocation processing next time. Just in case the target
1693		 * object is evicted and then rebound into its old
1694		 * presumed_offset before the next execbuffer - if that
1695		 * happened we would make the mistake of assuming that the
1696		 * relocations were valid.
1697		 */
1698		if (!user_access_begin(urelocs, size))
1699			goto end;
1700
1701		for (copied = 0; copied < nreloc; copied++)
1702			unsafe_put_user(-1,
1703					&urelocs[copied].presumed_offset,
1704					end_user);
1705		user_access_end();
1706
1707		eb->exec[i].relocs_ptr = (uintptr_t)relocs;
1708	}
1709
1710	return 0;
1711
1712end_user:
1713	user_access_end();
1714end:
1715	kvfree(relocs);
1716	err = -EFAULT;
1717err:
1718	while (i--) {
1719		relocs = u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr);
1720		if (eb->exec[i].relocation_count)
1721			kvfree(relocs);
1722	}
1723	return err;
1724}
1725
1726static int eb_prefault_relocations(const struct i915_execbuffer *eb)
1727{
1728	const unsigned int count = eb->buffer_count;
1729	unsigned int i;
1730
1731	for (i = 0; i < count; i++) {
1732		int err;
1733
1734		err = check_relocations(&eb->exec[i]);
1735		if (err)
1736			return err;
1737	}
1738
1739	return 0;
1740}
1741
1742static int eb_reinit_userptr(struct i915_execbuffer *eb)
1743{
1744	const unsigned int count = eb->buffer_count;
1745	unsigned int i;
1746	int ret;
1747
1748	if (likely(!(eb->args->flags & __EXEC_USERPTR_USED)))
1749		return 0;
1750
1751	for (i = 0; i < count; i++) {
1752		struct eb_vma *ev = &eb->vma[i];
1753
1754		if (!i915_gem_object_is_userptr(ev->vma->obj))
1755			continue;
1756
1757		ret = i915_gem_object_userptr_submit_init(ev->vma->obj);
1758		if (ret)
1759			return ret;
1760
1761		ev->flags |= __EXEC_OBJECT_USERPTR_INIT;
1762	}
1763
1764	return 0;
1765}
1766
1767static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb)
1768{
1769	bool have_copy = false;
1770	struct eb_vma *ev;
1771	int err = 0;
1772
1773repeat:
1774	if (signal_pending(current)) {
1775		err = -ERESTARTSYS;
1776		goto out;
1777	}
1778
1779	/* We may process another execbuffer during the unlock... */
1780	eb_release_vmas(eb, false);
1781	i915_gem_ww_ctx_fini(&eb->ww);
1782
1783	/*
1784	 * We take 3 passes through the slowpatch.
1785	 *
1786	 * 1 - we try to just prefault all the user relocation entries and
1787	 * then attempt to reuse the atomic pagefault disabled fast path again.
1788	 *
1789	 * 2 - we copy the user entries to a local buffer here outside of the
1790	 * local and allow ourselves to wait upon any rendering before
1791	 * relocations
1792	 *
1793	 * 3 - we already have a local copy of the relocation entries, but
1794	 * were interrupted (EAGAIN) whilst waiting for the objects, try again.
1795	 */
1796	if (!err) {
1797		err = eb_prefault_relocations(eb);
1798	} else if (!have_copy) {
1799		err = eb_copy_relocations(eb);
1800		have_copy = err == 0;
1801	} else {
1802		cond_resched();
1803		err = 0;
1804	}
1805
1806	if (!err)
1807		err = eb_reinit_userptr(eb);
1808
1809	i915_gem_ww_ctx_init(&eb->ww, true);
1810	if (err)
1811		goto out;
1812
1813	/* reacquire the objects */
1814repeat_validate:
1815	err = eb_pin_engine(eb, false);
1816	if (err)
1817		goto err;
1818
1819	err = eb_validate_vmas(eb);
1820	if (err)
1821		goto err;
1822
1823	GEM_BUG_ON(!eb->batches[0]);
1824
1825	list_for_each_entry(ev, &eb->relocs, reloc_link) {
1826		if (!have_copy) {
1827			err = eb_relocate_vma(eb, ev);
1828			if (err)
1829				break;
1830		} else {
1831			err = eb_relocate_vma_slow(eb, ev);
1832			if (err)
1833				break;
1834		}
1835	}
1836
1837	if (err == -EDEADLK)
1838		goto err;
1839
1840	if (err && !have_copy)
1841		goto repeat;
1842
1843	if (err)
1844		goto err;
1845
1846	/* as last step, parse the command buffer */
1847	err = eb_parse(eb);
1848	if (err)
1849		goto err;
1850
1851	/*
1852	 * Leave the user relocations as are, this is the painfully slow path,
1853	 * and we want to avoid the complication of dropping the lock whilst
1854	 * having buffers reserved in the aperture and so causing spurious
1855	 * ENOSPC for random operations.
1856	 */
1857
1858err:
1859	if (err == -EDEADLK) {
1860		eb_release_vmas(eb, false);
1861		err = i915_gem_ww_ctx_backoff(&eb->ww);
1862		if (!err)
1863			goto repeat_validate;
1864	}
1865
1866	if (err == -EAGAIN)
1867		goto repeat;
1868
1869out:
1870	if (have_copy) {
1871		const unsigned int count = eb->buffer_count;
1872		unsigned int i;
1873
1874		for (i = 0; i < count; i++) {
1875			const struct drm_i915_gem_exec_object2 *entry =
1876				&eb->exec[i];
1877			struct drm_i915_gem_relocation_entry *relocs;
1878
1879			if (!entry->relocation_count)
1880				continue;
1881
1882			relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
1883			kvfree(relocs);
1884		}
1885	}
1886
1887	return err;
1888}
1889
1890static int eb_relocate_parse(struct i915_execbuffer *eb)
1891{
1892	int err;
1893	bool throttle = true;
1894
1895retry:
1896	err = eb_pin_engine(eb, throttle);
1897	if (err) {
1898		if (err != -EDEADLK)
1899			return err;
1900
1901		goto err;
1902	}
1903
1904	/* only throttle once, even if we didn't need to throttle */
1905	throttle = false;
1906
1907	err = eb_validate_vmas(eb);
1908	if (err == -EAGAIN)
1909		goto slow;
1910	else if (err)
1911		goto err;
1912
1913	/* The objects are in their final locations, apply the relocations. */
1914	if (eb->args->flags & __EXEC_HAS_RELOC) {
1915		struct eb_vma *ev;
1916
1917		list_for_each_entry(ev, &eb->relocs, reloc_link) {
1918			err = eb_relocate_vma(eb, ev);
1919			if (err)
1920				break;
1921		}
1922
1923		if (err == -EDEADLK)
1924			goto err;
1925		else if (err)
1926			goto slow;
1927	}
1928
1929	if (!err)
1930		err = eb_parse(eb);
1931
1932err:
1933	if (err == -EDEADLK) {
1934		eb_release_vmas(eb, false);
1935		err = i915_gem_ww_ctx_backoff(&eb->ww);
1936		if (!err)
1937			goto retry;
1938	}
1939
1940	return err;
1941
1942slow:
1943	err = eb_relocate_parse_slow(eb);
1944	if (err)
1945		/*
1946		 * If the user expects the execobject.offset and
1947		 * reloc.presumed_offset to be an exact match,
1948		 * as for using NO_RELOC, then we cannot update
1949		 * the execobject.offset until we have completed
1950		 * relocation.
1951		 */
1952		eb->args->flags &= ~__EXEC_HAS_RELOC;
1953
1954	return err;
1955}
1956
1957/*
1958 * Using two helper loops for the order of which requests / batches are created
1959 * and added the to backend. Requests are created in order from the parent to
1960 * the last child. Requests are added in the reverse order, from the last child
1961 * to parent. This is done for locking reasons as the timeline lock is acquired
1962 * during request creation and released when the request is added to the
1963 * backend. To make lockdep happy (see intel_context_timeline_lock) this must be
1964 * the ordering.
1965 */
1966#define for_each_batch_create_order(_eb, _i) \
1967	for ((_i) = 0; (_i) < (_eb)->num_batches; ++(_i))
1968#define for_each_batch_add_order(_eb, _i) \
1969	BUILD_BUG_ON(!typecheck(int, _i)); \
1970	for ((_i) = (_eb)->num_batches - 1; (_i) >= 0; --(_i))
1971
1972static struct i915_request *
1973eb_find_first_request_added(struct i915_execbuffer *eb)
1974{
1975	int i;
1976
1977	for_each_batch_add_order(eb, i)
1978		if (eb->requests[i])
1979			return eb->requests[i];
1980
1981	GEM_BUG_ON("Request not found");
1982
1983	return NULL;
1984}
1985
1986#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1987
1988/* Stage with GFP_KERNEL allocations before we enter the signaling critical path */
1989static int eb_capture_stage(struct i915_execbuffer *eb)
1990{
1991	const unsigned int count = eb->buffer_count;
1992	unsigned int i = count, j;
1993
1994	while (i--) {
1995		struct eb_vma *ev = &eb->vma[i];
1996		struct i915_vma *vma = ev->vma;
1997		unsigned int flags = ev->flags;
1998
1999		if (!(flags & EXEC_OBJECT_CAPTURE))
2000			continue;
2001
2002		if (i915_gem_context_is_recoverable(eb->gem_context) &&
2003		    (IS_DGFX(eb->i915) || GRAPHICS_VER_FULL(eb->i915) > IP_VER(12, 0)))
2004			return -EINVAL;
2005
2006		for_each_batch_create_order(eb, j) {
2007			struct i915_capture_list *capture;
2008
2009			capture = kmalloc(sizeof(*capture), GFP_KERNEL);
2010			if (!capture)
2011				continue;
2012
2013			capture->next = eb->capture_lists[j];
2014			capture->vma_res = i915_vma_resource_get(vma->resource);
2015			eb->capture_lists[j] = capture;
2016		}
2017	}
2018
2019	return 0;
2020}
2021
2022/* Commit once we're in the critical path */
2023static void eb_capture_commit(struct i915_execbuffer *eb)
2024{
2025	unsigned int j;
2026
2027	for_each_batch_create_order(eb, j) {
2028		struct i915_request *rq = eb->requests[j];
2029
2030		if (!rq)
2031			break;
2032
2033		rq->capture_list = eb->capture_lists[j];
2034		eb->capture_lists[j] = NULL;
2035	}
2036}
2037
2038/*
2039 * Release anything that didn't get committed due to errors.
2040 * The capture_list will otherwise be freed at request retire.
2041 */
2042static void eb_capture_release(struct i915_execbuffer *eb)
2043{
2044	unsigned int j;
2045
2046	for_each_batch_create_order(eb, j) {
2047		if (eb->capture_lists[j]) {
2048			i915_request_free_capture_list(eb->capture_lists[j]);
2049			eb->capture_lists[j] = NULL;
2050		}
2051	}
2052}
2053
2054static void eb_capture_list_clear(struct i915_execbuffer *eb)
2055{
2056	memset(eb->capture_lists, 0, sizeof(eb->capture_lists));
2057}
2058
2059#else
2060
2061static int eb_capture_stage(struct i915_execbuffer *eb)
2062{
2063	return 0;
2064}
2065
2066static void eb_capture_commit(struct i915_execbuffer *eb)
2067{
2068}
2069
2070static void eb_capture_release(struct i915_execbuffer *eb)
2071{
2072}
2073
2074static void eb_capture_list_clear(struct i915_execbuffer *eb)
2075{
2076}
2077
2078#endif
2079
2080static int eb_move_to_gpu(struct i915_execbuffer *eb)
2081{
2082	const unsigned int count = eb->buffer_count;
2083	unsigned int i = count;
2084	int err = 0, j;
2085
2086	while (i--) {
2087		struct eb_vma *ev = &eb->vma[i];
2088		struct i915_vma *vma = ev->vma;
2089		unsigned int flags = ev->flags;
2090		struct drm_i915_gem_object *obj = vma->obj;
2091
2092		assert_vma_held(vma);
2093
2094		/*
2095		 * If the GPU is not _reading_ through the CPU cache, we need
2096		 * to make sure that any writes (both previous GPU writes from
2097		 * before a change in snooping levels and normal CPU writes)
2098		 * caught in that cache are flushed to main memory.
2099		 *
2100		 * We want to say
2101		 *   obj->cache_dirty &&
2102		 *   !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
2103		 * but gcc's optimiser doesn't handle that as well and emits
2104		 * two jumps instead of one. Maybe one day...
2105		 *
2106		 * FIXME: There is also sync flushing in set_pages(), which
2107		 * serves a different purpose(some of the time at least).
2108		 *
2109		 * We should consider:
2110		 *
2111		 *   1. Rip out the async flush code.
2112		 *
2113		 *   2. Or make the sync flushing use the async clflush path
2114		 *   using mandatory fences underneath. Currently the below
2115		 *   async flush happens after we bind the object.
2116		 */
2117		if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) {
2118			if (i915_gem_clflush_object(obj, 0))
2119				flags &= ~EXEC_OBJECT_ASYNC;
2120		}
2121
2122		/* We only need to await on the first request */
2123		if (err == 0 && !(flags & EXEC_OBJECT_ASYNC)) {
2124			err = i915_request_await_object
2125				(eb_find_first_request_added(eb), obj,
2126				 flags & EXEC_OBJECT_WRITE);
2127		}
2128
2129		for_each_batch_add_order(eb, j) {
2130			if (err)
2131				break;
2132			if (!eb->requests[j])
2133				continue;
2134
2135			err = _i915_vma_move_to_active(vma, eb->requests[j],
2136						       j ? NULL :
2137						       eb->composite_fence ?
2138						       eb->composite_fence :
2139						       &eb->requests[j]->fence,
2140						       flags | __EXEC_OBJECT_NO_RESERVE |
2141						       __EXEC_OBJECT_NO_REQUEST_AWAIT);
2142		}
2143	}
2144
2145#ifdef CONFIG_MMU_NOTIFIER
2146	if (!err && (eb->args->flags & __EXEC_USERPTR_USED)) {
2147		for (i = 0; i < count; i++) {
2148			struct eb_vma *ev = &eb->vma[i];
2149			struct drm_i915_gem_object *obj = ev->vma->obj;
2150
2151			if (!i915_gem_object_is_userptr(obj))
2152				continue;
2153
2154			err = i915_gem_object_userptr_submit_done(obj);
2155			if (err)
2156				break;
2157		}
2158	}
2159#endif
2160
2161	if (unlikely(err))
2162		goto err_skip;
2163
2164	/* Unconditionally flush any chipset caches (for streaming writes). */
2165	intel_gt_chipset_flush(eb->gt);
2166	eb_capture_commit(eb);
2167
2168	return 0;
2169
2170err_skip:
2171	for_each_batch_create_order(eb, j) {
2172		if (!eb->requests[j])
2173			break;
2174
2175		i915_request_set_error_once(eb->requests[j], err);
2176	}
2177	return err;
2178}
2179
2180static int i915_gem_check_execbuffer(struct drm_i915_private *i915,
2181				     struct drm_i915_gem_execbuffer2 *exec)
2182{
2183	if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS)
2184		return -EINVAL;
2185
2186	/* Kernel clipping was a DRI1 misfeature */
2187	if (!(exec->flags & (I915_EXEC_FENCE_ARRAY |
2188			     I915_EXEC_USE_EXTENSIONS))) {
2189		if (exec->num_cliprects || exec->cliprects_ptr)
2190			return -EINVAL;
2191	}
2192
2193	if (exec->DR4 == 0xffffffff) {
2194		drm_dbg(&i915->drm, "UXA submitting garbage DR4, fixing up\n");
2195		exec->DR4 = 0;
2196	}
2197	if (exec->DR1 || exec->DR4)
2198		return -EINVAL;
2199
2200	if ((exec->batch_start_offset | exec->batch_len) & 0x7)
2201		return -EINVAL;
2202
2203	return 0;
2204}
2205
2206static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
2207{
2208	u32 *cs;
2209	int i;
2210
2211	if (GRAPHICS_VER(rq->i915) != 7 || rq->engine->id != RCS0) {
2212		drm_dbg(&rq->i915->drm, "sol reset is gen7/rcs only\n");
2213		return -EINVAL;
2214	}
2215
2216	cs = intel_ring_begin(rq, 4 * 2 + 2);
2217	if (IS_ERR(cs))
2218		return PTR_ERR(cs);
2219
2220	*cs++ = MI_LOAD_REGISTER_IMM(4);
2221	for (i = 0; i < 4; i++) {
2222		*cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));
2223		*cs++ = 0;
2224	}
2225	*cs++ = MI_NOOP;
2226	intel_ring_advance(rq, cs);
2227
2228	return 0;
2229}
2230
2231static struct i915_vma *
2232shadow_batch_pin(struct i915_execbuffer *eb,
2233		 struct drm_i915_gem_object *obj,
2234		 struct i915_address_space *vm,
2235		 unsigned int flags)
2236{
2237	struct i915_vma *vma;
2238	int err;
2239
2240	vma = i915_vma_instance(obj, vm, NULL);
2241	if (IS_ERR(vma))
2242		return vma;
2243
2244	err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, flags | PIN_VALIDATE);
2245	if (err)
2246		return ERR_PTR(err);
2247
2248	return vma;
2249}
2250
2251static struct i915_vma *eb_dispatch_secure(struct i915_execbuffer *eb, struct i915_vma *vma)
2252{
2253	/*
2254	 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2255	 * batch" bit. Hence we need to pin secure batches into the global gtt.
2256	 * hsw should have this fixed, but bdw mucks it up again. */
2257	if (eb->batch_flags & I915_DISPATCH_SECURE)
2258		return i915_gem_object_ggtt_pin_ww(vma->obj, &eb->ww, NULL, 0, 0, PIN_VALIDATE);
2259
2260	return NULL;
2261}
2262
2263static int eb_parse(struct i915_execbuffer *eb)
2264{
2265	struct drm_i915_private *i915 = eb->i915;
2266	struct intel_gt_buffer_pool_node *pool = eb->batch_pool;
2267	struct i915_vma *shadow, *trampoline, *batch;
2268	unsigned long len;
2269	int err;
2270
2271	if (!eb_use_cmdparser(eb)) {
2272		batch = eb_dispatch_secure(eb, eb->batches[0]->vma);
2273		if (IS_ERR(batch))
2274			return PTR_ERR(batch);
2275
2276		goto secure_batch;
2277	}
2278
2279	if (intel_context_is_parallel(eb->context))
2280		return -EINVAL;
2281
2282	len = eb->batch_len[0];
2283	if (!CMDPARSER_USES_GGTT(eb->i915)) {
2284		/*
2285		 * ppGTT backed shadow buffers must be mapped RO, to prevent
2286		 * post-scan tampering
2287		 */
2288		if (!eb->context->vm->has_read_only) {
2289			drm_dbg(&i915->drm,
2290				"Cannot prevent post-scan tampering without RO capable vm\n");
2291			return -EINVAL;
2292		}
2293	} else {
2294		len += I915_CMD_PARSER_TRAMPOLINE_SIZE;
2295	}
2296	if (unlikely(len < eb->batch_len[0])) /* last paranoid check of overflow */
2297		return -EINVAL;
2298
2299	if (!pool) {
2300		pool = intel_gt_get_buffer_pool(eb->gt, len,
2301						I915_MAP_WB);
2302		if (IS_ERR(pool))
2303			return PTR_ERR(pool);
2304		eb->batch_pool = pool;
2305	}
2306
2307	err = i915_gem_object_lock(pool->obj, &eb->ww);
2308	if (err)
2309		return err;
2310
2311	shadow = shadow_batch_pin(eb, pool->obj, eb->context->vm, PIN_USER);
2312	if (IS_ERR(shadow))
2313		return PTR_ERR(shadow);
2314
2315	intel_gt_buffer_pool_mark_used(pool);
2316	i915_gem_object_set_readonly(shadow->obj);
2317	shadow->private = pool;
2318
2319	trampoline = NULL;
2320	if (CMDPARSER_USES_GGTT(eb->i915)) {
2321		trampoline = shadow;
2322
2323		shadow = shadow_batch_pin(eb, pool->obj,
2324					  &eb->gt->ggtt->vm,
2325					  PIN_GLOBAL);
2326		if (IS_ERR(shadow))
2327			return PTR_ERR(shadow);
2328
2329		shadow->private = pool;
2330
2331		eb->batch_flags |= I915_DISPATCH_SECURE;
2332	}
2333
2334	batch = eb_dispatch_secure(eb, shadow);
2335	if (IS_ERR(batch))
2336		return PTR_ERR(batch);
2337
2338	err = dma_resv_reserve_fences(shadow->obj->base.resv, 1);
2339	if (err)
2340		return err;
2341
2342	err = intel_engine_cmd_parser(eb->context->engine,
2343				      eb->batches[0]->vma,
2344				      eb->batch_start_offset,
2345				      eb->batch_len[0],
2346				      shadow, trampoline);
2347	if (err)
2348		return err;
2349
2350	eb->batches[0] = &eb->vma[eb->buffer_count++];
2351	eb->batches[0]->vma = i915_vma_get(shadow);
2352	eb->batches[0]->flags = __EXEC_OBJECT_HAS_PIN;
2353
2354	eb->trampoline = trampoline;
2355	eb->batch_start_offset = 0;
2356
2357secure_batch:
2358	if (batch) {
2359		if (intel_context_is_parallel(eb->context))
2360			return -EINVAL;
2361
2362		eb->batches[0] = &eb->vma[eb->buffer_count++];
2363		eb->batches[0]->flags = __EXEC_OBJECT_HAS_PIN;
2364		eb->batches[0]->vma = i915_vma_get(batch);
2365	}
2366	return 0;
2367}
2368
2369static int eb_request_submit(struct i915_execbuffer *eb,
2370			     struct i915_request *rq,
2371			     struct i915_vma *batch,
2372			     u64 batch_len)
2373{
2374	int err;
2375
2376	if (intel_context_nopreempt(rq->context))
2377		__set_bit(I915_FENCE_FLAG_NOPREEMPT, &rq->fence.flags);
2378
2379	if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
2380		err = i915_reset_gen7_sol_offsets(rq);
2381		if (err)
2382			return err;
2383	}
2384
2385	/*
2386	 * After we completed waiting for other engines (using HW semaphores)
2387	 * then we can signal that this request/batch is ready to run. This
2388	 * allows us to determine if the batch is still waiting on the GPU
2389	 * or actually running by checking the breadcrumb.
2390	 */
2391	if (rq->context->engine->emit_init_breadcrumb) {
2392		err = rq->context->engine->emit_init_breadcrumb(rq);
2393		if (err)
2394			return err;
2395	}
2396
2397	err = rq->context->engine->emit_bb_start(rq,
2398						 i915_vma_offset(batch) +
2399						 eb->batch_start_offset,
2400						 batch_len,
2401						 eb->batch_flags);
2402	if (err)
2403		return err;
2404
2405	if (eb->trampoline) {
2406		GEM_BUG_ON(intel_context_is_parallel(rq->context));
2407		GEM_BUG_ON(eb->batch_start_offset);
2408		err = rq->context->engine->emit_bb_start(rq,
2409							 i915_vma_offset(eb->trampoline) +
2410							 batch_len, 0, 0);
2411		if (err)
2412			return err;
2413	}
2414
2415	return 0;
2416}
2417
2418static int eb_submit(struct i915_execbuffer *eb)
2419{
2420	unsigned int i;
2421	int err;
2422
2423	err = eb_move_to_gpu(eb);
2424
2425	for_each_batch_create_order(eb, i) {
2426		if (!eb->requests[i])
2427			break;
2428
2429		trace_i915_request_queue(eb->requests[i], eb->batch_flags);
2430		if (!err)
2431			err = eb_request_submit(eb, eb->requests[i],
2432						eb->batches[i]->vma,
2433						eb->batch_len[i]);
2434	}
2435
2436	return err;
2437}
2438
2439/*
2440 * Find one BSD ring to dispatch the corresponding BSD command.
2441 * The engine index is returned.
2442 */
2443static unsigned int
2444gen8_dispatch_bsd_engine(struct drm_i915_private *i915,
2445			 struct drm_file *file)
2446{
2447	struct drm_i915_file_private *file_priv = file->driver_priv;
2448
2449	/* Check whether the file_priv has already selected one ring. */
2450	if ((int)file_priv->bsd_engine < 0)
2451		file_priv->bsd_engine =
2452			get_random_u32_below(i915->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]);
2453
2454	return file_priv->bsd_engine;
2455}
2456
2457static const enum intel_engine_id user_ring_map[] = {
2458	[I915_EXEC_DEFAULT]	= RCS0,
2459	[I915_EXEC_RENDER]	= RCS0,
2460	[I915_EXEC_BLT]		= BCS0,
2461	[I915_EXEC_BSD]		= VCS0,
2462	[I915_EXEC_VEBOX]	= VECS0
2463};
2464
2465static struct i915_request *eb_throttle(struct i915_execbuffer *eb, struct intel_context *ce)
2466{
2467	struct intel_ring *ring = ce->ring;
2468	struct intel_timeline *tl = ce->timeline;
2469	struct i915_request *rq;
2470
2471	/*
2472	 * Completely unscientific finger-in-the-air estimates for suitable
2473	 * maximum user request size (to avoid blocking) and then backoff.
2474	 */
2475	if (intel_ring_update_space(ring) >= PAGE_SIZE)
2476		return NULL;
2477
2478	/*
2479	 * Find a request that after waiting upon, there will be at least half
2480	 * the ring available. The hysteresis allows us to compete for the
2481	 * shared ring and should mean that we sleep less often prior to
2482	 * claiming our resources, but not so long that the ring completely
2483	 * drains before we can submit our next request.
2484	 */
2485	list_for_each_entry(rq, &tl->requests, link) {
2486		if (rq->ring != ring)
2487			continue;
2488
2489		if (__intel_ring_space(rq->postfix,
2490				       ring->emit, ring->size) > ring->size / 2)
2491			break;
2492	}
2493	if (&rq->link == &tl->requests)
2494		return NULL; /* weird, we will check again later for real */
2495
2496	return i915_request_get(rq);
2497}
2498
2499static int eb_pin_timeline(struct i915_execbuffer *eb, struct intel_context *ce,
2500			   bool throttle)
2501{
2502	struct intel_timeline *tl;
2503	struct i915_request *rq = NULL;
2504
2505	/*
2506	 * Take a local wakeref for preparing to dispatch the execbuf as
2507	 * we expect to access the hardware fairly frequently in the
2508	 * process, and require the engine to be kept awake between accesses.
2509	 * Upon dispatch, we acquire another prolonged wakeref that we hold
2510	 * until the timeline is idle, which in turn releases the wakeref
2511	 * taken on the engine, and the parent device.
2512	 */
2513	tl = intel_context_timeline_lock(ce);
2514	if (IS_ERR(tl))
2515		return PTR_ERR(tl);
2516
2517	intel_context_enter(ce);
2518	if (throttle)
2519		rq = eb_throttle(eb, ce);
2520	intel_context_timeline_unlock(tl);
2521
2522	if (rq) {
2523		bool nonblock = eb->file->filp->f_flags & O_NONBLOCK;
2524		long timeout = nonblock ? 0 : MAX_SCHEDULE_TIMEOUT;
2525
2526		if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
2527				      timeout) < 0) {
2528			i915_request_put(rq);
2529
2530			/*
2531			 * Error path, cannot use intel_context_timeline_lock as
2532			 * that is user interruptible and this clean up step
2533			 * must be done.
2534			 */
2535			mutex_lock(&ce->timeline->mutex);
2536			intel_context_exit(ce);
2537			mutex_unlock(&ce->timeline->mutex);
2538
2539			if (nonblock)
2540				return -EWOULDBLOCK;
2541			else
2542				return -EINTR;
2543		}
2544		i915_request_put(rq);
2545	}
2546
2547	return 0;
2548}
2549
2550static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle)
2551{
2552	struct intel_context *ce = eb->context, *child;
2553	int err;
2554	int i = 0, j = 0;
2555
2556	GEM_BUG_ON(eb->args->flags & __EXEC_ENGINE_PINNED);
2557
2558	if (unlikely(intel_context_is_banned(ce)))
2559		return -EIO;
2560
2561	/*
2562	 * Pinning the contexts may generate requests in order to acquire
2563	 * GGTT space, so do this first before we reserve a seqno for
2564	 * ourselves.
2565	 */
2566	err = intel_context_pin_ww(ce, &eb->ww);
2567	if (err)
2568		return err;
2569	for_each_child(ce, child) {
2570		err = intel_context_pin_ww(child, &eb->ww);
2571		GEM_BUG_ON(err);	/* perma-pinned should incr a counter */
2572	}
2573
2574	for_each_child(ce, child) {
2575		err = eb_pin_timeline(eb, child, throttle);
2576		if (err)
2577			goto unwind;
2578		++i;
2579	}
2580	err = eb_pin_timeline(eb, ce, throttle);
2581	if (err)
2582		goto unwind;
2583
2584	eb->args->flags |= __EXEC_ENGINE_PINNED;
2585	return 0;
2586
2587unwind:
2588	for_each_child(ce, child) {
2589		if (j++ < i) {
2590			mutex_lock(&child->timeline->mutex);
2591			intel_context_exit(child);
2592			mutex_unlock(&child->timeline->mutex);
2593		}
2594	}
2595	for_each_child(ce, child)
2596		intel_context_unpin(child);
2597	intel_context_unpin(ce);
2598	return err;
2599}
2600
2601static void eb_unpin_engine(struct i915_execbuffer *eb)
2602{
2603	struct intel_context *ce = eb->context, *child;
2604
2605	if (!(eb->args->flags & __EXEC_ENGINE_PINNED))
2606		return;
2607
2608	eb->args->flags &= ~__EXEC_ENGINE_PINNED;
2609
2610	for_each_child(ce, child) {
2611		mutex_lock(&child->timeline->mutex);
2612		intel_context_exit(child);
2613		mutex_unlock(&child->timeline->mutex);
2614
2615		intel_context_unpin(child);
2616	}
2617
2618	mutex_lock(&ce->timeline->mutex);
2619	intel_context_exit(ce);
2620	mutex_unlock(&ce->timeline->mutex);
2621
2622	intel_context_unpin(ce);
2623}
2624
2625static unsigned int
2626eb_select_legacy_ring(struct i915_execbuffer *eb)
2627{
2628	struct drm_i915_private *i915 = eb->i915;
2629	struct drm_i915_gem_execbuffer2 *args = eb->args;
2630	unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
2631
2632	if (user_ring_id != I915_EXEC_BSD &&
2633	    (args->flags & I915_EXEC_BSD_MASK)) {
2634		drm_dbg(&i915->drm,
2635			"execbuf with non bsd ring but with invalid "
2636			"bsd dispatch flags: %d\n", (int)(args->flags));
2637		return -1;
2638	}
2639
2640	if (user_ring_id == I915_EXEC_BSD &&
2641	    i915->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO] > 1) {
2642		unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
2643
2644		if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
2645			bsd_idx = gen8_dispatch_bsd_engine(i915, eb->file);
2646		} else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
2647			   bsd_idx <= I915_EXEC_BSD_RING2) {
2648			bsd_idx >>= I915_EXEC_BSD_SHIFT;
2649			bsd_idx--;
2650		} else {
2651			drm_dbg(&i915->drm,
2652				"execbuf with unknown bsd ring: %u\n",
2653				bsd_idx);
2654			return -1;
2655		}
2656
2657		return _VCS(bsd_idx);
2658	}
2659
2660	if (user_ring_id >= ARRAY_SIZE(user_ring_map)) {
2661		drm_dbg(&i915->drm, "execbuf with unknown ring: %u\n",
2662			user_ring_id);
2663		return -1;
2664	}
2665
2666	return user_ring_map[user_ring_id];
2667}
2668
2669static int
2670eb_select_engine(struct i915_execbuffer *eb)
2671{
2672	struct intel_context *ce, *child;
2673	struct intel_gt *gt;
2674	unsigned int idx;
2675	int err;
2676
2677	if (i915_gem_context_user_engines(eb->gem_context))
2678		idx = eb->args->flags & I915_EXEC_RING_MASK;
2679	else
2680		idx = eb_select_legacy_ring(eb);
2681
2682	ce = i915_gem_context_get_engine(eb->gem_context, idx);
2683	if (IS_ERR(ce))
2684		return PTR_ERR(ce);
2685
2686	if (intel_context_is_parallel(ce)) {
2687		if (eb->buffer_count < ce->parallel.number_children + 1) {
2688			intel_context_put(ce);
2689			return -EINVAL;
2690		}
2691		if (eb->batch_start_offset || eb->args->batch_len) {
2692			intel_context_put(ce);
2693			return -EINVAL;
2694		}
2695	}
2696	eb->num_batches = ce->parallel.number_children + 1;
2697	gt = ce->engine->gt;
2698
2699	for_each_child(ce, child)
2700		intel_context_get(child);
2701	eb->wakeref = intel_gt_pm_get(ce->engine->gt);
2702	/*
2703	 * Keep GT0 active on MTL so that i915_vma_parked() doesn't
2704	 * free VMAs while execbuf ioctl is validating VMAs.
2705	 */
2706	if (gt->info.id)
2707		eb->wakeref_gt0 = intel_gt_pm_get(to_gt(gt->i915));
2708
2709	if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
2710		err = intel_context_alloc_state(ce);
2711		if (err)
2712			goto err;
2713	}
2714	for_each_child(ce, child) {
2715		if (!test_bit(CONTEXT_ALLOC_BIT, &child->flags)) {
2716			err = intel_context_alloc_state(child);
2717			if (err)
2718				goto err;
2719		}
2720	}
2721
2722	/*
2723	 * ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2724	 * EIO if the GPU is already wedged.
2725	 */
2726	err = intel_gt_terminally_wedged(ce->engine->gt);
2727	if (err)
2728		goto err;
2729
2730	if (!i915_vm_tryget(ce->vm)) {
2731		err = -ENOENT;
2732		goto err;
2733	}
2734
2735	eb->context = ce;
2736	eb->gt = ce->engine->gt;
2737
2738	/*
2739	 * Make sure engine pool stays alive even if we call intel_context_put
2740	 * during ww handling. The pool is destroyed when last pm reference
2741	 * is dropped, which breaks our -EDEADLK handling.
2742	 */
2743	return err;
2744
2745err:
2746	if (gt->info.id)
2747		intel_gt_pm_put(to_gt(gt->i915), eb->wakeref_gt0);
2748
2749	intel_gt_pm_put(ce->engine->gt, eb->wakeref);
2750	for_each_child(ce, child)
2751		intel_context_put(child);
2752	intel_context_put(ce);
2753	return err;
2754}
2755
2756static void
2757eb_put_engine(struct i915_execbuffer *eb)
2758{
2759	struct intel_context *child;
2760
2761	i915_vm_put(eb->context->vm);
2762	/*
2763	 * This works in conjunction with eb_select_engine() to prevent
2764	 * i915_vma_parked() from interfering while execbuf validates vmas.
2765	 */
2766	if (eb->gt->info.id)
2767		intel_gt_pm_put(to_gt(eb->gt->i915), eb->wakeref_gt0);
2768	intel_gt_pm_put(eb->context->engine->gt, eb->wakeref);
2769	for_each_child(eb->context, child)
2770		intel_context_put(child);
2771	intel_context_put(eb->context);
2772}
2773
2774static void
2775__free_fence_array(struct eb_fence *fences, unsigned int n)
2776{
2777	while (n--) {
2778		drm_syncobj_put(ptr_mask_bits(fences[n].syncobj, 2));
2779		dma_fence_put(fences[n].dma_fence);
2780		dma_fence_chain_free(fences[n].chain_fence);
2781	}
2782	kvfree(fences);
2783}
2784
2785static int
2786add_timeline_fence_array(struct i915_execbuffer *eb,
2787			 const struct drm_i915_gem_execbuffer_ext_timeline_fences *timeline_fences)
2788{
2789	struct drm_i915_gem_exec_fence __user *user_fences;
2790	u64 __user *user_values;
2791	struct eb_fence *f;
2792	u64 nfences;
2793	int err = 0;
2794
2795	nfences = timeline_fences->fence_count;
2796	if (!nfences)
2797		return 0;
2798
2799	/* Check multiplication overflow for access_ok() and kvmalloc_array() */
2800	BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2801	if (nfences > min_t(unsigned long,
2802			    ULONG_MAX / sizeof(*user_fences),
2803			    SIZE_MAX / sizeof(*f)) - eb->num_fences)
2804		return -EINVAL;
2805
2806	user_fences = u64_to_user_ptr(timeline_fences->handles_ptr);
2807	if (!access_ok(user_fences, nfences * sizeof(*user_fences)))
2808		return -EFAULT;
2809
2810	user_values = u64_to_user_ptr(timeline_fences->values_ptr);
2811	if (!access_ok(user_values, nfences * sizeof(*user_values)))
2812		return -EFAULT;
2813
2814	f = krealloc(eb->fences,
2815		     (eb->num_fences + nfences) * sizeof(*f),
2816		     __GFP_NOWARN | GFP_KERNEL);
2817	if (!f)
2818		return -ENOMEM;
2819
2820	eb->fences = f;
2821	f += eb->num_fences;
2822
2823	BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
2824		     ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
2825
2826	while (nfences--) {
2827		struct drm_i915_gem_exec_fence user_fence;
2828		struct drm_syncobj *syncobj;
2829		struct dma_fence *fence = NULL;
2830		u64 point;
2831
2832		if (__copy_from_user(&user_fence,
2833				     user_fences++,
2834				     sizeof(user_fence)))
2835			return -EFAULT;
2836
2837		if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS)
2838			return -EINVAL;
2839
2840		if (__get_user(point, user_values++))
2841			return -EFAULT;
2842
2843		syncobj = drm_syncobj_find(eb->file, user_fence.handle);
2844		if (!syncobj) {
2845			drm_dbg(&eb->i915->drm,
2846				"Invalid syncobj handle provided\n");
2847			return -ENOENT;
2848		}
2849
2850		fence = drm_syncobj_fence_get(syncobj);
2851
2852		if (!fence && user_fence.flags &&
2853		    !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2854			drm_dbg(&eb->i915->drm,
2855				"Syncobj handle has no fence\n");
2856			drm_syncobj_put(syncobj);
2857			return -EINVAL;
2858		}
2859
2860		if (fence)
2861			err = dma_fence_chain_find_seqno(&fence, point);
2862
2863		if (err && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2864			drm_dbg(&eb->i915->drm,
2865				"Syncobj handle missing requested point %llu\n",
2866				point);
2867			dma_fence_put(fence);
2868			drm_syncobj_put(syncobj);
2869			return err;
2870		}
2871
2872		/*
2873		 * A point might have been signaled already and
2874		 * garbage collected from the timeline. In this case
2875		 * just ignore the point and carry on.
2876		 */
2877		if (!fence && !(user_fence.flags & I915_EXEC_FENCE_SIGNAL)) {
2878			drm_syncobj_put(syncobj);
2879			continue;
2880		}
2881
2882		/*
2883		 * For timeline syncobjs we need to preallocate chains for
2884		 * later signaling.
2885		 */
2886		if (point != 0 && user_fence.flags & I915_EXEC_FENCE_SIGNAL) {
2887			/*
2888			 * Waiting and signaling the same point (when point !=
2889			 * 0) would break the timeline.
2890			 */
2891			if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
2892				drm_dbg(&eb->i915->drm,
2893					"Trying to wait & signal the same timeline point.\n");
2894				dma_fence_put(fence);
2895				drm_syncobj_put(syncobj);
2896				return -EINVAL;
2897			}
2898
2899			f->chain_fence = dma_fence_chain_alloc();
2900			if (!f->chain_fence) {
2901				drm_syncobj_put(syncobj);
2902				dma_fence_put(fence);
2903				return -ENOMEM;
2904			}
2905		} else {
2906			f->chain_fence = NULL;
2907		}
2908
2909		f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
2910		f->dma_fence = fence;
2911		f->value = point;
2912		f++;
2913		eb->num_fences++;
2914	}
2915
2916	return 0;
2917}
2918
2919static int add_fence_array(struct i915_execbuffer *eb)
2920{
2921	struct drm_i915_gem_execbuffer2 *args = eb->args;
2922	struct drm_i915_gem_exec_fence __user *user;
2923	unsigned long num_fences = args->num_cliprects;
2924	struct eb_fence *f;
2925
2926	if (!(args->flags & I915_EXEC_FENCE_ARRAY))
2927		return 0;
2928
2929	if (!num_fences)
2930		return 0;
2931
2932	/* Check multiplication overflow for access_ok() and kvmalloc_array() */
2933	BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2934	if (num_fences > min_t(unsigned long,
2935			       ULONG_MAX / sizeof(*user),
2936			       SIZE_MAX / sizeof(*f) - eb->num_fences))
2937		return -EINVAL;
2938
2939	user = u64_to_user_ptr(args->cliprects_ptr);
2940	if (!access_ok(user, num_fences * sizeof(*user)))
2941		return -EFAULT;
2942
2943	f = krealloc(eb->fences,
2944		     (eb->num_fences + num_fences) * sizeof(*f),
2945		     __GFP_NOWARN | GFP_KERNEL);
2946	if (!f)
2947		return -ENOMEM;
2948
2949	eb->fences = f;
2950	f += eb->num_fences;
2951	while (num_fences--) {
2952		struct drm_i915_gem_exec_fence user_fence;
2953		struct drm_syncobj *syncobj;
2954		struct dma_fence *fence = NULL;
2955
2956		if (__copy_from_user(&user_fence, user++, sizeof(user_fence)))
2957			return -EFAULT;
2958
2959		if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS)
2960			return -EINVAL;
2961
2962		syncobj = drm_syncobj_find(eb->file, user_fence.handle);
2963		if (!syncobj) {
2964			drm_dbg(&eb->i915->drm,
2965				"Invalid syncobj handle provided\n");
2966			return -ENOENT;
2967		}
2968
2969		if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
2970			fence = drm_syncobj_fence_get(syncobj);
2971			if (!fence) {
2972				drm_dbg(&eb->i915->drm,
2973					"Syncobj handle has no fence\n");
2974				drm_syncobj_put(syncobj);
2975				return -EINVAL;
2976			}
2977		}
2978
2979		BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
2980			     ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
2981
2982		f->syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
2983		f->dma_fence = fence;
2984		f->value = 0;
2985		f->chain_fence = NULL;
2986		f++;
2987		eb->num_fences++;
2988	}
2989
2990	return 0;
2991}
2992
2993static void put_fence_array(struct eb_fence *fences, int num_fences)
2994{
2995	if (fences)
2996		__free_fence_array(fences, num_fences);
2997}
2998
2999static int
3000await_fence_array(struct i915_execbuffer *eb,
3001		  struct i915_request *rq)
3002{
3003	unsigned int n;
3004	int err;
3005
3006	for (n = 0; n < eb->num_fences; n++) {
3007		if (!eb->fences[n].dma_fence)
3008			continue;
3009
3010		err = i915_request_await_dma_fence(rq, eb->fences[n].dma_fence);
3011		if (err < 0)
3012			return err;
3013	}
3014
3015	return 0;
3016}
3017
3018static void signal_fence_array(const struct i915_execbuffer *eb,
3019			       struct dma_fence * const fence)
3020{
3021	unsigned int n;
3022
3023	for (n = 0; n < eb->num_fences; n++) {
3024		struct drm_syncobj *syncobj;
3025		unsigned int flags;
3026
3027		syncobj = ptr_unpack_bits(eb->fences[n].syncobj, &flags, 2);
3028		if (!(flags & I915_EXEC_FENCE_SIGNAL))
3029			continue;
3030
3031		if (eb->fences[n].chain_fence) {
3032			drm_syncobj_add_point(syncobj,
3033					      eb->fences[n].chain_fence,
3034					      fence,
3035					      eb->fences[n].value);
3036			/*
3037			 * The chain's ownership is transferred to the
3038			 * timeline.
3039			 */
3040			eb->fences[n].chain_fence = NULL;
3041		} else {
3042			drm_syncobj_replace_fence(syncobj, fence);
3043		}
3044	}
3045}
3046
3047static int
3048parse_timeline_fences(struct i915_user_extension __user *ext, void *data)
3049{
3050	struct i915_execbuffer *eb = data;
3051	struct drm_i915_gem_execbuffer_ext_timeline_fences timeline_fences;
3052
3053	if (copy_from_user(&timeline_fences, ext, sizeof(timeline_fences)))
3054		return -EFAULT;
3055
3056	return add_timeline_fence_array(eb, &timeline_fences);
3057}
3058
3059static void retire_requests(struct intel_timeline *tl, struct i915_request *end)
3060{
3061	struct i915_request *rq, *rn;
3062
3063	list_for_each_entry_safe(rq, rn, &tl->requests, link)
3064		if (rq == end || !i915_request_retire(rq))
3065			break;
3066}
3067
3068static int eb_request_add(struct i915_execbuffer *eb, struct i915_request *rq,
3069			  int err, bool last_parallel)
3070{
3071	struct intel_timeline * const tl = i915_request_timeline(rq);
3072	struct i915_sched_attr attr = {};
3073	struct i915_request *prev;
3074
3075	lockdep_assert_held(&tl->mutex);
3076	lockdep_unpin_lock(&tl->mutex, rq->cookie);
3077
3078	trace_i915_request_add(rq);
3079
3080	prev = __i915_request_commit(rq);
3081
3082	/* Check that the context wasn't destroyed before submission */
3083	if (likely(!intel_context_is_closed(eb->context))) {
3084		attr = eb->gem_context->sched;
3085	} else {
3086		/* Serialise with context_close via the add_to_timeline */
3087		i915_request_set_error_once(rq, -ENOENT);
3088		__i915_request_skip(rq);
3089		err = -ENOENT; /* override any transient errors */
3090	}
3091
3092	if (intel_context_is_parallel(eb->context)) {
3093		if (err) {
3094			__i915_request_skip(rq);
3095			set_bit(I915_FENCE_FLAG_SKIP_PARALLEL,
3096				&rq->fence.flags);
3097		}
3098		if (last_parallel)
3099			set_bit(I915_FENCE_FLAG_SUBMIT_PARALLEL,
3100				&rq->fence.flags);
3101	}
3102
3103	__i915_request_queue(rq, &attr);
3104
3105	/* Try to clean up the client's timeline after submitting the request */
3106	if (prev)
3107		retire_requests(tl, prev);
3108
3109	mutex_unlock(&tl->mutex);
3110
3111	return err;
3112}
3113
3114static int eb_requests_add(struct i915_execbuffer *eb, int err)
3115{
3116	int i;
3117
3118	/*
3119	 * We iterate in reverse order of creation to release timeline mutexes in
3120	 * same order.
3121	 */
3122	for_each_batch_add_order(eb, i) {
3123		struct i915_request *rq = eb->requests[i];
3124
3125		if (!rq)
3126			continue;
3127		err |= eb_request_add(eb, rq, err, i == 0);
3128	}
3129
3130	return err;
3131}
3132
3133static const i915_user_extension_fn execbuf_extensions[] = {
3134	[DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES] = parse_timeline_fences,
3135};
3136
3137static int
3138parse_execbuf2_extensions(struct drm_i915_gem_execbuffer2 *args,
3139			  struct i915_execbuffer *eb)
3140{
3141	if (!(args->flags & I915_EXEC_USE_EXTENSIONS))
3142		return 0;
3143
3144	/* The execbuf2 extension mechanism reuses cliprects_ptr. So we cannot
3145	 * have another flag also using it at the same time.
3146	 */
3147	if (eb->args->flags & I915_EXEC_FENCE_ARRAY)
3148		return -EINVAL;
3149
3150	if (args->num_cliprects != 0)
3151		return -EINVAL;
3152
3153	return i915_user_extensions(u64_to_user_ptr(args->cliprects_ptr),
3154				    execbuf_extensions,
3155				    ARRAY_SIZE(execbuf_extensions),
3156				    eb);
3157}
3158
3159static void eb_requests_get(struct i915_execbuffer *eb)
3160{
3161	unsigned int i;
3162
3163	for_each_batch_create_order(eb, i) {
3164		if (!eb->requests[i])
3165			break;
3166
3167		i915_request_get(eb->requests[i]);
3168	}
3169}
3170
3171static void eb_requests_put(struct i915_execbuffer *eb)
3172{
3173	unsigned int i;
3174
3175	for_each_batch_create_order(eb, i) {
3176		if (!eb->requests[i])
3177			break;
3178
3179		i915_request_put(eb->requests[i]);
3180	}
3181}
3182
3183static struct sync_file *
3184eb_composite_fence_create(struct i915_execbuffer *eb, int out_fence_fd)
3185{
3186	struct sync_file *out_fence = NULL;
3187	struct dma_fence_array *fence_array;
3188	struct dma_fence **fences;
3189	unsigned int i;
3190
3191	GEM_BUG_ON(!intel_context_is_parent(eb->context));
3192
3193	fences = kmalloc_array(eb->num_batches, sizeof(*fences), GFP_KERNEL);
3194	if (!fences)
3195		return ERR_PTR(-ENOMEM);
3196
3197	for_each_batch_create_order(eb, i) {
3198		fences[i] = &eb->requests[i]->fence;
3199		__set_bit(I915_FENCE_FLAG_COMPOSITE,
3200			  &eb->requests[i]->fence.flags);
3201	}
3202
3203	fence_array = dma_fence_array_create(eb->num_batches,
3204					     fences,
3205					     eb->context->parallel.fence_context,
3206					     eb->context->parallel.seqno++,
3207					     false);
3208	if (!fence_array) {
3209		kfree(fences);
3210		return ERR_PTR(-ENOMEM);
3211	}
3212
3213	/* Move ownership to the dma_fence_array created above */
3214	for_each_batch_create_order(eb, i)
3215		dma_fence_get(fences[i]);
3216
3217	if (out_fence_fd != -1) {
3218		out_fence = sync_file_create(&fence_array->base);
3219		/* sync_file now owns fence_arry, drop creation ref */
3220		dma_fence_put(&fence_array->base);
3221		if (!out_fence)
3222			return ERR_PTR(-ENOMEM);
3223	}
3224
3225	eb->composite_fence = &fence_array->base;
3226
3227	return out_fence;
3228}
3229
3230static struct sync_file *
3231eb_fences_add(struct i915_execbuffer *eb, struct i915_request *rq,
3232	      struct dma_fence *in_fence, int out_fence_fd)
3233{
3234	struct sync_file *out_fence = NULL;
3235	int err;
3236
3237	if (unlikely(eb->gem_context->syncobj)) {
3238		struct dma_fence *fence;
3239
3240		fence = drm_syncobj_fence_get(eb->gem_context->syncobj);
3241		err = i915_request_await_dma_fence(rq, fence);
3242		dma_fence_put(fence);
3243		if (err)
3244			return ERR_PTR(err);
3245	}
3246
3247	if (in_fence) {
3248		if (eb->args->flags & I915_EXEC_FENCE_SUBMIT)
3249			err = i915_request_await_execution(rq, in_fence);
3250		else
3251			err = i915_request_await_dma_fence(rq, in_fence);
3252		if (err < 0)
3253			return ERR_PTR(err);
3254	}
3255
3256	if (eb->fences) {
3257		err = await_fence_array(eb, rq);
3258		if (err)
3259			return ERR_PTR(err);
3260	}
3261
3262	if (intel_context_is_parallel(eb->context)) {
3263		out_fence = eb_composite_fence_create(eb, out_fence_fd);
3264		if (IS_ERR(out_fence))
3265			return ERR_PTR(-ENOMEM);
3266	} else if (out_fence_fd != -1) {
3267		out_fence = sync_file_create(&rq->fence);
3268		if (!out_fence)
3269			return ERR_PTR(-ENOMEM);
3270	}
3271
3272	return out_fence;
3273}
3274
3275static struct intel_context *
3276eb_find_context(struct i915_execbuffer *eb, unsigned int context_number)
3277{
3278	struct intel_context *child;
3279
3280	if (likely(context_number == 0))
3281		return eb->context;
3282
3283	for_each_child(eb->context, child)
3284		if (!--context_number)
3285			return child;
3286
3287	GEM_BUG_ON("Context not found");
3288
3289	return NULL;
3290}
3291
3292static struct sync_file *
3293eb_requests_create(struct i915_execbuffer *eb, struct dma_fence *in_fence,
3294		   int out_fence_fd)
3295{
3296	struct sync_file *out_fence = NULL;
3297	unsigned int i;
3298
3299	for_each_batch_create_order(eb, i) {
3300		/* Allocate a request for this batch buffer nice and early. */
3301		eb->requests[i] = i915_request_create(eb_find_context(eb, i));
3302		if (IS_ERR(eb->requests[i])) {
3303			out_fence = ERR_CAST(eb->requests[i]);
3304			eb->requests[i] = NULL;
3305			return out_fence;
3306		}
3307
3308		/*
3309		 * Only the first request added (committed to backend) has to
3310		 * take the in fences into account as all subsequent requests
3311		 * will have fences inserted inbetween them.
3312		 */
3313		if (i + 1 == eb->num_batches) {
3314			out_fence = eb_fences_add(eb, eb->requests[i],
3315						  in_fence, out_fence_fd);
3316			if (IS_ERR(out_fence))
3317				return out_fence;
3318		}
3319
3320		/*
3321		 * Not really on stack, but we don't want to call
3322		 * kfree on the batch_snapshot when we put it, so use the
3323		 * _onstack interface.
3324		 */
3325		if (eb->batches[i]->vma)
3326			eb->requests[i]->batch_res =
3327				i915_vma_resource_get(eb->batches[i]->vma->resource);
3328		if (eb->batch_pool) {
3329			GEM_BUG_ON(intel_context_is_parallel(eb->context));
3330			intel_gt_buffer_pool_mark_active(eb->batch_pool,
3331							 eb->requests[i]);
3332		}
3333	}
3334
3335	return out_fence;
3336}
3337
3338static int
3339i915_gem_do_execbuffer(struct drm_device *dev,
3340		       struct drm_file *file,
3341		       struct drm_i915_gem_execbuffer2 *args,
3342		       struct drm_i915_gem_exec_object2 *exec)
3343{
3344	struct drm_i915_private *i915 = to_i915(dev);
3345	struct i915_execbuffer eb;
3346	struct dma_fence *in_fence = NULL;
3347	struct sync_file *out_fence = NULL;
3348	int out_fence_fd = -1;
3349	int err;
3350
3351	BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
3352	BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
3353		     ~__EXEC_OBJECT_UNKNOWN_FLAGS);
3354
3355	eb.i915 = i915;
3356	eb.file = file;
3357	eb.args = args;
3358	if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC))
3359		args->flags |= __EXEC_HAS_RELOC;
3360
3361	eb.exec = exec;
3362	eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1);
3363	memset(eb.vma, 0, (args->buffer_count + 1) * sizeof(struct eb_vma));
3364
3365	eb.batch_pool = NULL;
3366
3367	eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
3368	reloc_cache_init(&eb.reloc_cache, eb.i915);
3369
3370	eb.buffer_count = args->buffer_count;
3371	eb.batch_start_offset = args->batch_start_offset;
3372	eb.trampoline = NULL;
3373
3374	eb.fences = NULL;
3375	eb.num_fences = 0;
3376
3377	eb_capture_list_clear(&eb);
3378
3379	memset(eb.requests, 0, sizeof(struct i915_request *) *
3380	       ARRAY_SIZE(eb.requests));
3381	eb.composite_fence = NULL;
3382
3383	eb.batch_flags = 0;
3384	if (args->flags & I915_EXEC_SECURE) {
3385		if (GRAPHICS_VER(i915) >= 11)
3386			return -ENODEV;
3387
3388		/* Return -EPERM to trigger fallback code on old binaries. */
3389		if (!HAS_SECURE_BATCHES(i915))
3390			return -EPERM;
3391
3392		if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
3393			return -EPERM;
3394
3395		eb.batch_flags |= I915_DISPATCH_SECURE;
3396	}
3397	if (args->flags & I915_EXEC_IS_PINNED)
3398		eb.batch_flags |= I915_DISPATCH_PINNED;
3399
3400	err = parse_execbuf2_extensions(args, &eb);
3401	if (err)
3402		goto err_ext;
3403
3404	err = add_fence_array(&eb);
3405	if (err)
3406		goto err_ext;
3407
3408#define IN_FENCES (I915_EXEC_FENCE_IN | I915_EXEC_FENCE_SUBMIT)
3409	if (args->flags & IN_FENCES) {
3410		if ((args->flags & IN_FENCES) == IN_FENCES)
3411			return -EINVAL;
3412
3413		in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
3414		if (!in_fence) {
3415			err = -EINVAL;
3416			goto err_ext;
3417		}
3418	}
3419#undef IN_FENCES
3420
3421	if (args->flags & I915_EXEC_FENCE_OUT) {
3422		out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
3423		if (out_fence_fd < 0) {
3424			err = out_fence_fd;
3425			goto err_in_fence;
3426		}
3427	}
3428
3429	err = eb_create(&eb);
3430	if (err)
3431		goto err_out_fence;
3432
3433	GEM_BUG_ON(!eb.lut_size);
3434
3435	err = eb_select_context(&eb);
3436	if (unlikely(err))
3437		goto err_destroy;
3438
3439	err = eb_select_engine(&eb);
3440	if (unlikely(err))
3441		goto err_context;
3442
3443	err = eb_lookup_vmas(&eb);
3444	if (err) {
3445		eb_release_vmas(&eb, true);
3446		goto err_engine;
3447	}
3448
3449	i915_gem_ww_ctx_init(&eb.ww, true);
3450
3451	err = eb_relocate_parse(&eb);
3452	if (err) {
3453		/*
3454		 * If the user expects the execobject.offset and
3455		 * reloc.presumed_offset to be an exact match,
3456		 * as for using NO_RELOC, then we cannot update
3457		 * the execobject.offset until we have completed
3458		 * relocation.
3459		 */
3460		args->flags &= ~__EXEC_HAS_RELOC;
3461		goto err_vma;
3462	}
3463
3464	ww_acquire_done(&eb.ww.ctx);
3465	err = eb_capture_stage(&eb);
3466	if (err)
3467		goto err_vma;
3468
3469	out_fence = eb_requests_create(&eb, in_fence, out_fence_fd);
3470	if (IS_ERR(out_fence)) {
3471		err = PTR_ERR(out_fence);
3472		out_fence = NULL;
3473		if (eb.requests[0])
3474			goto err_request;
3475		else
3476			goto err_vma;
3477	}
3478
3479	err = eb_submit(&eb);
3480
3481err_request:
3482	eb_requests_get(&eb);
3483	err = eb_requests_add(&eb, err);
3484
3485	if (eb.fences)
3486		signal_fence_array(&eb, eb.composite_fence ?
3487				   eb.composite_fence :
3488				   &eb.requests[0]->fence);
3489
3490	if (unlikely(eb.gem_context->syncobj)) {
3491		drm_syncobj_replace_fence(eb.gem_context->syncobj,
3492					  eb.composite_fence ?
3493					  eb.composite_fence :
3494					  &eb.requests[0]->fence);
3495	}
3496
3497	if (out_fence) {
3498		if (err == 0) {
3499			fd_install(out_fence_fd, out_fence->file);
3500			args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */
3501			args->rsvd2 |= (u64)out_fence_fd << 32;
3502			out_fence_fd = -1;
3503		} else {
3504			fput(out_fence->file);
3505		}
3506	}
3507
3508	if (!out_fence && eb.composite_fence)
3509		dma_fence_put(eb.composite_fence);
3510
3511	eb_requests_put(&eb);
3512
3513err_vma:
3514	eb_release_vmas(&eb, true);
3515	WARN_ON(err == -EDEADLK);
3516	i915_gem_ww_ctx_fini(&eb.ww);
3517
3518	if (eb.batch_pool)
3519		intel_gt_buffer_pool_put(eb.batch_pool);
3520err_engine:
3521	eb_put_engine(&eb);
3522err_context:
3523	i915_gem_context_put(eb.gem_context);
3524err_destroy:
3525	eb_destroy(&eb);
3526err_out_fence:
3527	if (out_fence_fd != -1)
3528		put_unused_fd(out_fence_fd);
3529err_in_fence:
3530	dma_fence_put(in_fence);
3531err_ext:
3532	put_fence_array(eb.fences, eb.num_fences);
3533	return err;
3534}
3535
3536static size_t eb_element_size(void)
3537{
3538	return sizeof(struct drm_i915_gem_exec_object2) + sizeof(struct eb_vma);
3539}
3540
3541static bool check_buffer_count(size_t count)
3542{
3543	const size_t sz = eb_element_size();
3544
3545	/*
3546	 * When using LUT_HANDLE, we impose a limit of INT_MAX for the lookup
3547	 * array size (see eb_create()). Otherwise, we can accept an array as
3548	 * large as can be addressed (though use large arrays at your peril)!
3549	 */
3550
3551	return !(count < 1 || count > INT_MAX || count > SIZE_MAX / sz - 1);
3552}
3553
3554int
3555i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
3556			   struct drm_file *file)
3557{
3558	struct drm_i915_private *i915 = to_i915(dev);
3559	struct drm_i915_gem_execbuffer2 *args = data;
3560	struct drm_i915_gem_exec_object2 *exec2_list;
3561	const size_t count = args->buffer_count;
3562	int err;
3563
3564	if (!check_buffer_count(count)) {
3565		drm_dbg(&i915->drm, "execbuf2 with %zd buffers\n", count);
3566		return -EINVAL;
3567	}
3568
3569	err = i915_gem_check_execbuffer(i915, args);
3570	if (err)
3571		return err;
3572
3573	/*
3574	 * Allocate extra slots for use by the command parser.
3575	 *
3576	 * Note that this allocation handles two different arrays (the
3577	 * exec2_list array, and the eventual eb.vma array introduced in
3578	 * i915_gem_do_execbuffer()), that reside in virtually contiguous
3579	 * memory. Also note that the allocation intentionally doesn't fill the
3580	 * area with zeros, because the exec2_list part doesn't need to be, as
3581	 * it's immediately overwritten by user data a few lines below.
3582	 * However, the eb.vma part is explicitly zeroed later in
3583	 * i915_gem_do_execbuffer().
3584	 */
3585	exec2_list = kvmalloc_array(count + 2, eb_element_size(),
3586				    __GFP_NOWARN | GFP_KERNEL);
3587	if (exec2_list == NULL) {
3588		drm_dbg(&i915->drm, "Failed to allocate exec list for %zd buffers\n",
3589			count);
3590		return -ENOMEM;
3591	}
3592	if (copy_from_user(exec2_list,
3593			   u64_to_user_ptr(args->buffers_ptr),
3594			   sizeof(*exec2_list) * count)) {
3595		drm_dbg(&i915->drm, "copy %zd exec entries failed\n", count);
3596		kvfree(exec2_list);
3597		return -EFAULT;
3598	}
3599
3600	err = i915_gem_do_execbuffer(dev, file, args, exec2_list);
3601
3602	/*
3603	 * Now that we have begun execution of the batchbuffer, we ignore
3604	 * any new error after this point. Also given that we have already
3605	 * updated the associated relocations, we try to write out the current
3606	 * object locations irrespective of any error.
3607	 */
3608	if (args->flags & __EXEC_HAS_RELOC) {
3609		struct drm_i915_gem_exec_object2 __user *user_exec_list =
3610			u64_to_user_ptr(args->buffers_ptr);
3611		unsigned int i;
3612
3613		/* Copy the new buffer offsets back to the user's exec list. */
3614		/*
3615		 * Note: count * sizeof(*user_exec_list) does not overflow,
3616		 * because we checked 'count' in check_buffer_count().
3617		 *
3618		 * And this range already got effectively checked earlier
3619		 * when we did the "copy_from_user()" above.
3620		 */
3621		if (!user_write_access_begin(user_exec_list,
3622					     count * sizeof(*user_exec_list)))
3623			goto end;
3624
3625		for (i = 0; i < args->buffer_count; i++) {
3626			if (!(exec2_list[i].offset & UPDATE))
3627				continue;
3628
3629			exec2_list[i].offset =
3630				gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
3631			unsafe_put_user(exec2_list[i].offset,
3632					&user_exec_list[i].offset,
3633					end_user);
3634		}
3635end_user:
3636		user_write_access_end();
3637end:;
3638	}
3639
3640	args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;
3641	kvfree(exec2_list);
3642	return err;
3643}