vlv_sideband.c

 1// SPDX-License-Identifier: MIT
 2/* Copyright © 2025 Intel Corporation */
 3
 4#include <drm/drm_print.h>
 5
 6#include "intel_display_core.h"
 7#include "intel_display_types.h"
 8#include "intel_dpio_phy.h"
 9#include "vlv_sideband.h"
10
11static enum vlv_iosf_sb_unit vlv_dpio_phy_to_unit(struct intel_display *display,
12						  enum dpio_phy phy)
13{
14	/*
15	 * IOSF_PORT_DPIO: VLV x2 PHY (DP/HDMI B and C), CHV x1 PHY (DP/HDMI D)
16	 * IOSF_PORT_DPIO_2: CHV x2 PHY (DP/HDMI B and C)
17	 */
18	if (display->platform.cherryview)
19		return phy == DPIO_PHY0 ? VLV_IOSF_SB_DPIO_2 : VLV_IOSF_SB_DPIO;
20	else
21		return VLV_IOSF_SB_DPIO;
22}
23
24u32 vlv_dpio_read(struct drm_device *drm, enum dpio_phy phy, int reg)
25{
26	struct intel_display *display = to_intel_display(drm);
27	enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(display, phy);
28	u32 val;
29
30	val = vlv_iosf_sb_read(drm, unit, reg);
31
32	/*
33	 * FIXME: There might be some registers where all 1's is a valid value,
34	 * so ideally we should check the register offset instead...
35	 */
36	drm_WARN(display->drm, val == 0xffffffff,
37		 "DPIO PHY%d read reg 0x%x == 0x%x\n",
38		 phy, reg, val);
39
40	return val;
41}
42
43void vlv_dpio_write(struct drm_device *drm,
44		    enum dpio_phy phy, int reg, u32 val)
45{
46	struct intel_display *display = to_intel_display(drm);
47	enum vlv_iosf_sb_unit unit = vlv_dpio_phy_to_unit(display, phy);
48
49	vlv_iosf_sb_write(drm, unit, reg, val);
50}