vlv_dsi_regs.h

  1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2022 Intel Corporation
  4 */
  5
  6#ifndef __VLV_DSI_REGS_H__
  7#define __VLV_DSI_REGS_H__
  8
  9#include "intel_display_reg_defs.h"
 10
 11#define VLV_MIPI_BASE			VLV_DISPLAY_BASE
 12#define BXT_MIPI_BASE			0x60000
 13
 14#define _MIPI_MMIO_BASE(display)	((display)->dsi.mmio_base)
 15
 16#define _MIPI_PORT(port, a, c)	(((port) == PORT_A) ? a : c)	/* ports A and C only */
 17#define _MMIO_MIPI(base, port, a, c)	_MMIO((base) + _MIPI_PORT(port, a, c))
 18
 19/* BXT MIPI mode configure */
 20#define  _BXT_MIPIA_TRANS_HACTIVE		0xb0f8
 21#define  _BXT_MIPIC_TRANS_HACTIVE		0xb8f8
 22#define  BXT_MIPI_TRANS_HACTIVE(tc)		_MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
 23
 24#define  _BXT_MIPIA_TRANS_VACTIVE		0xb0fc
 25#define  _BXT_MIPIC_TRANS_VACTIVE		0xb8fc
 26#define  BXT_MIPI_TRANS_VACTIVE(tc)		_MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
 27
 28#define  _BXT_MIPIA_TRANS_VTOTAL		0xb100
 29#define  _BXT_MIPIC_TRANS_VTOTAL		0xb900
 30#define  BXT_MIPI_TRANS_VTOTAL(tc)		_MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
 31
 32#define BXT_P_DSI_REGULATOR_CFG			_MMIO(0x160020)
 33#define  STAP_SELECT					(1 << 0)
 34
 35#define BXT_P_DSI_REGULATOR_TX_CTRL		_MMIO(0x160054)
 36#define  HS_IO_CTRL_SELECT				(1 << 0)
 37
 38#define _MIPIA_PORT_CTRL			0x61190
 39#define _MIPIC_PORT_CTRL			0x61700
 40#define VLV_MIPI_PORT_CTRL(port)		_MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
 41
 42 /* BXT port control */
 43#define _BXT_MIPIA_PORT_CTRL			0xb0c0
 44#define _BXT_MIPIC_PORT_CTRL			0xb8c0
 45#define BXT_MIPI_PORT_CTRL(tc)			_MMIO_MIPI(BXT_MIPI_BASE, tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
 46
 47#define  DPI_ENABLE					(1 << 31) /* A + C */
 48#define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
 49#define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
 50#define  DUAL_LINK_MODE_SHIFT				26
 51#define  DUAL_LINK_MODE_MASK				(1 << 26)
 52#define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
 53#define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE		(1 << 26)
 54#define  DITHERING_ENABLE				(1 << 25) /* A + C */
 55#define  FLOPPED_HSTX					(1 << 23)
 56#define  DE_INVERT					(1 << 19) /* XXX */
 57#define  MIPIA_FLISDSI_DELAY_COUNT_SHIFT		18
 58#define  MIPIA_FLISDSI_DELAY_COUNT_MASK			(0xf << 18)
 59#define  AFE_LATCHOUT					(1 << 17)
 60#define  LP_OUTPUT_HOLD					(1 << 16)
 61#define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT		15
 62#define  MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK		(1 << 15)
 63#define  MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT		11
 64#define  MIPIC_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 11)
 65#define  CSB_SHIFT					9
 66#define  CSB_MASK					(3 << 9)
 67#define  CSB_20MHZ					(0 << 9)
 68#define  CSB_10MHZ					(1 << 9)
 69#define  CSB_40MHZ					(2 << 9)
 70#define  BANDGAP_MASK					(1 << 8)
 71#define  BANDGAP_PNW_CIRCUIT				(0 << 8)
 72#define  BANDGAP_LNC_CIRCUIT				(1 << 8)
 73#define  MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT		5
 74#define  MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK		(7 << 5)
 75#define  TEARING_EFFECT_DELAY				(1 << 4) /* A + C */
 76#define  TEARING_EFFECT_SHIFT				2 /* A + C */
 77#define  TEARING_EFFECT_MASK				(3 << 2)
 78#define  TEARING_EFFECT_OFF				(0 << 2)
 79#define  TEARING_EFFECT_DSI				(1 << 2)
 80#define  TEARING_EFFECT_GPIO				(2 << 2)
 81#define  LANE_CONFIGURATION_SHIFT			0
 82#define  LANE_CONFIGURATION_MASK			(3 << 0)
 83#define  LANE_CONFIGURATION_4LANE			(0 << 0)
 84#define  LANE_CONFIGURATION_DUAL_LINK_A			(1 << 0)
 85#define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)
 86
 87#define _MIPIA_TEARING_CTRL			0x61194
 88#define _MIPIC_TEARING_CTRL			0x61704
 89#define VLV_MIPI_TEARING_CTRL(port)			_MMIO_MIPI(VLV_MIPI_BASE, port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
 90#define  TEARING_EFFECT_DELAY_SHIFT			0
 91#define  TEARING_EFFECT_DELAY_MASK			(0xffff << 0)
 92
 93/* MIPI DSI Controller and D-PHY registers */
 94
 95#define _MIPIA_DEVICE_READY			0xb000
 96#define _MIPIC_DEVICE_READY			0xb800
 97#define MIPI_DEVICE_READY(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
 98#define  BUS_POSSESSION					(1 << 3) /* set to give bus to receiver */
 99#define  ULPS_STATE_MASK				(3 << 1)
100#define  ULPS_STATE_ENTER				(2 << 1)
101#define  ULPS_STATE_EXIT				(1 << 1)
102#define  ULPS_STATE_NORMAL_OPERATION			(0 << 1)
103#define  DEVICE_READY					(1 << 0)
104
105#define _MIPIA_INTR_STAT			0xb004
106#define _MIPIC_INTR_STAT			0xb804
107#define MIPI_INTR_STAT(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
108#define _MIPIA_INTR_EN				0xb008
109#define _MIPIC_INTR_EN				0xb808
110#define MIPI_INTR_EN(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
111#define  TEARING_EFFECT					(1 << 31)
112#define  SPL_PKT_SENT_INTERRUPT				(1 << 30)
113#define  GEN_READ_DATA_AVAIL				(1 << 29)
114#define  LP_GENERIC_WR_FIFO_FULL			(1 << 28)
115#define  HS_GENERIC_WR_FIFO_FULL			(1 << 27)
116#define  RX_PROT_VIOLATION				(1 << 26)
117#define  RX_INVALID_TX_LENGTH				(1 << 25)
118#define  ACK_WITH_NO_ERROR				(1 << 24)
119#define  TURN_AROUND_ACK_TIMEOUT			(1 << 23)
120#define  LP_RX_TIMEOUT					(1 << 22)
121#define  HS_TX_TIMEOUT					(1 << 21)
122#define  DPI_FIFO_UNDERRUN				(1 << 20)
123#define  LOW_CONTENTION					(1 << 19)
124#define  HIGH_CONTENTION				(1 << 18)
125#define  TXDSI_VC_ID_INVALID				(1 << 17)
126#define  TXDSI_DATA_TYPE_NOT_RECOGNISED			(1 << 16)
127#define  TXCHECKSUM_ERROR				(1 << 15)
128#define  TXECC_MULTIBIT_ERROR				(1 << 14)
129#define  TXECC_SINGLE_BIT_ERROR				(1 << 13)
130#define  TXFALSE_CONTROL_ERROR				(1 << 12)
131#define  RXDSI_VC_ID_INVALID				(1 << 11)
132#define  RXDSI_DATA_TYPE_NOT_REGOGNISED			(1 << 10)
133#define  RXCHECKSUM_ERROR				(1 << 9)
134#define  RXECC_MULTIBIT_ERROR				(1 << 8)
135#define  RXECC_SINGLE_BIT_ERROR				(1 << 7)
136#define  RXFALSE_CONTROL_ERROR				(1 << 6)
137#define  RXHS_RECEIVE_TIMEOUT_ERROR			(1 << 5)
138#define  RX_LP_TX_SYNC_ERROR				(1 << 4)
139#define  RXEXCAPE_MODE_ENTRY_ERROR			(1 << 3)
140#define  RXEOT_SYNC_ERROR				(1 << 2)
141#define  RXSOT_SYNC_ERROR				(1 << 1)
142#define  RXSOT_ERROR					(1 << 0)
143
144#define _MIPIA_DSI_FUNC_PRG			0xb00c
145#define _MIPIC_DSI_FUNC_PRG			0xb80c
146#define MIPI_DSI_FUNC_PRG(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
147#define  CMD_MODE_DATA_WIDTH_MASK			(7 << 13)
148#define  CMD_MODE_NOT_SUPPORTED				(0 << 13)
149#define  CMD_MODE_DATA_WIDTH_16_BIT			(1 << 13)
150#define  CMD_MODE_DATA_WIDTH_9_BIT			(2 << 13)
151#define  CMD_MODE_DATA_WIDTH_8_BIT			(3 << 13)
152#define  CMD_MODE_DATA_WIDTH_OPTION1			(4 << 13)
153#define  CMD_MODE_DATA_WIDTH_OPTION2			(5 << 13)
154#define  VID_MODE_FORMAT_MASK				(0xf << 7)
155#define  VID_MODE_NOT_SUPPORTED				(0 << 7)
156#define  VID_MODE_FORMAT_RGB565				(1 << 7)
157#define  VID_MODE_FORMAT_RGB666_PACKED			(2 << 7)
158#define  VID_MODE_FORMAT_RGB666				(3 << 7)
159#define  VID_MODE_FORMAT_RGB888				(4 << 7)
160#define  CMD_MODE_CHANNEL_NUMBER_SHIFT			5
161#define  CMD_MODE_CHANNEL_NUMBER_MASK			(3 << 5)
162#define  VID_MODE_CHANNEL_NUMBER_SHIFT			3
163#define  VID_MODE_CHANNEL_NUMBER_MASK			(3 << 3)
164#define  DATA_LANES_PRG_REG_SHIFT			0
165#define  DATA_LANES_PRG_REG_MASK			(7 << 0)
166
167#define _MIPIA_HS_TX_TIMEOUT			0xb010
168#define _MIPIC_HS_TX_TIMEOUT			0xb810
169#define MIPI_HS_TX_TIMEOUT(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
170#define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK		0xffffff
171
172#define _MIPIA_LP_RX_TIMEOUT			0xb014
173#define _MIPIC_LP_RX_TIMEOUT			0xb814
174#define MIPI_LP_RX_TIMEOUT(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
175#define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK		0xffffff
176
177#define _MIPIA_TURN_AROUND_TIMEOUT		0xb018
178#define _MIPIC_TURN_AROUND_TIMEOUT		0xb818
179#define MIPI_TURN_AROUND_TIMEOUT(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
180#define  TURN_AROUND_TIMEOUT_MASK			0x3f
181
182#define _MIPIA_DEVICE_RESET_TIMER		0xb01c
183#define _MIPIC_DEVICE_RESET_TIMER		0xb81c
184#define MIPI_DEVICE_RESET_TIMER(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
185#define  DEVICE_RESET_TIMER_MASK			0xffff
186
187#define _MIPIA_DPI_RESOLUTION			0xb020
188#define _MIPIC_DPI_RESOLUTION			0xb820
189#define MIPI_DPI_RESOLUTION(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
190#define  VERTICAL_ADDRESS_SHIFT				16
191#define  VERTICAL_ADDRESS_MASK				(0xffff << 16)
192#define  HORIZONTAL_ADDRESS_SHIFT			0
193#define  HORIZONTAL_ADDRESS_MASK			0xffff
194
195#define _MIPIA_DBI_FIFO_THROTTLE		0xb024
196#define _MIPIC_DBI_FIFO_THROTTLE		0xb824
197#define MIPI_DBI_FIFO_THROTTLE(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
198#define  DBI_FIFO_EMPTY_HALF				(0 << 0)
199#define  DBI_FIFO_EMPTY_QUARTER				(1 << 0)
200#define  DBI_FIFO_EMPTY_7_LOCATIONS			(2 << 0)
201
202/* regs below are bits 15:0 */
203#define _MIPIA_HSYNC_PADDING_COUNT		0xb028
204#define _MIPIC_HSYNC_PADDING_COUNT		0xb828
205#define MIPI_HSYNC_PADDING_COUNT(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
206
207#define _MIPIA_HBP_COUNT			0xb02c
208#define _MIPIC_HBP_COUNT			0xb82c
209#define MIPI_HBP_COUNT(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
210
211#define _MIPIA_HFP_COUNT			0xb030
212#define _MIPIC_HFP_COUNT			0xb830
213#define MIPI_HFP_COUNT(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
214
215#define _MIPIA_HACTIVE_AREA_COUNT		0xb034
216#define _MIPIC_HACTIVE_AREA_COUNT		0xb834
217#define MIPI_HACTIVE_AREA_COUNT(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
218
219#define _MIPIA_VSYNC_PADDING_COUNT		0xb038
220#define _MIPIC_VSYNC_PADDING_COUNT		0xb838
221#define MIPI_VSYNC_PADDING_COUNT(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
222
223#define _MIPIA_VBP_COUNT			0xb03c
224#define _MIPIC_VBP_COUNT			0xb83c
225#define MIPI_VBP_COUNT(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
226
227#define _MIPIA_VFP_COUNT			0xb040
228#define _MIPIC_VFP_COUNT			0xb840
229#define MIPI_VFP_COUNT(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
230
231#define _MIPIA_HIGH_LOW_SWITCH_COUNT		0xb044
232#define _MIPIC_HIGH_LOW_SWITCH_COUNT		0xb844
233#define MIPI_HIGH_LOW_SWITCH_COUNT(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port,	_MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
234
235#define _MIPIA_DPI_CONTROL			0xb048
236#define _MIPIC_DPI_CONTROL			0xb848
237#define MIPI_DPI_CONTROL(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
238#define  DPI_LP_MODE					(1 << 6)
239#define  BACKLIGHT_OFF					(1 << 5)
240#define  BACKLIGHT_ON					(1 << 4)
241#define  COLOR_MODE_OFF					(1 << 3)
242#define  COLOR_MODE_ON					(1 << 2)
243#define  TURN_ON					(1 << 1)
244#define  SHUTDOWN					(1 << 0)
245
246#define _MIPIA_DPI_DATA				0xb04c
247#define _MIPIC_DPI_DATA				0xb84c
248#define MIPI_DPI_DATA(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
249#define  COMMAND_BYTE_SHIFT				0
250#define  COMMAND_BYTE_MASK				(0x3f << 0)
251
252#define _MIPIA_INIT_COUNT			0xb050
253#define _MIPIC_INIT_COUNT			0xb850
254#define MIPI_INIT_COUNT(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
255#define  MASTER_INIT_TIMER_SHIFT			0
256#define  MASTER_INIT_TIMER_MASK				(0xffff << 0)
257
258#define _MIPIA_MAX_RETURN_PKT_SIZE		0xb054
259#define _MIPIC_MAX_RETURN_PKT_SIZE		0xb854
260#define MIPI_MAX_RETURN_PKT_SIZE(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
261#define  MAX_RETURN_PKT_SIZE_SHIFT			0
262#define  MAX_RETURN_PKT_SIZE_MASK			(0x3ff << 0)
263
264#define _MIPIA_VIDEO_MODE_FORMAT		0xb058
265#define _MIPIC_VIDEO_MODE_FORMAT		0xb858
266#define MIPI_VIDEO_MODE_FORMAT(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
267#define  RANDOM_DPI_DISPLAY_RESOLUTION			(1 << 4)
268#define  DISABLE_VIDEO_BTA				(1 << 3)
269#define  IP_TG_CONFIG					(1 << 2)
270#define  VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE		(1 << 0)
271#define  VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS		(2 << 0)
272#define  VIDEO_MODE_BURST				(3 << 0)
273
274#define _MIPIA_EOT_DISABLE			0xb05c
275#define _MIPIC_EOT_DISABLE			0xb85c
276#define MIPI_EOT_DISABLE(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
277#define  BXT_DEFEATURE_DPI_FIFO_CTR			(1 << 9)
278#define  BXT_DPHY_DEFEATURE_EN				(1 << 8)
279#define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 7)
280#define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 6)
281#define  LOW_CONTENTION_RECOVERY_DISABLE		(1 << 5)
282#define  HIGH_CONTENTION_RECOVERY_DISABLE		(1 << 4)
283#define  TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
284#define  TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE		(1 << 2)
285#define  CLOCKSTOP					(1 << 1)
286#define  EOT_DISABLE					(1 << 0)
287
288#define _MIPIA_LP_BYTECLK			0xb060
289#define _MIPIC_LP_BYTECLK			0xb860
290#define MIPI_LP_BYTECLK(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
291#define  LP_BYTECLK_SHIFT				0
292#define  LP_BYTECLK_MASK				(0xffff << 0)
293
294#define _MIPIA_TLPX_TIME_COUNT			0xb0a4
295#define _MIPIC_TLPX_TIME_COUNT			0xb8a4
296#define MIPI_TLPX_TIME_COUNT(display, port)	 _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
297
298#define _MIPIA_CLK_LANE_TIMING			0xb098
299#define _MIPIC_CLK_LANE_TIMING			0xb898
300#define MIPI_CLK_LANE_TIMING(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
301
302/* bits 31:0 */
303#define _MIPIA_LP_GEN_DATA			0xb064
304#define _MIPIC_LP_GEN_DATA			0xb864
305#define MIPI_LP_GEN_DATA(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
306
307/* bits 31:0 */
308#define _MIPIA_HS_GEN_DATA			0xb068
309#define _MIPIC_HS_GEN_DATA			0xb868
310#define MIPI_HS_GEN_DATA(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
311
312#define _MIPIA_LP_GEN_CTRL			0xb06c
313#define _MIPIC_LP_GEN_CTRL			0xb86c
314#define MIPI_LP_GEN_CTRL(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
315#define _MIPIA_HS_GEN_CTRL			0xb070
316#define _MIPIC_HS_GEN_CTRL			0xb870
317#define MIPI_HS_GEN_CTRL(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
318#define  LONG_PACKET_WORD_COUNT_SHIFT			8
319#define  LONG_PACKET_WORD_COUNT_MASK			(0xffff << 8)
320#define  SHORT_PACKET_PARAM_SHIFT			8
321#define  SHORT_PACKET_PARAM_MASK			(0xffff << 8)
322#define  VIRTUAL_CHANNEL_SHIFT				6
323#define  VIRTUAL_CHANNEL_MASK				(3 << 6)
324#define  DATA_TYPE_SHIFT				0
325#define  DATA_TYPE_MASK					(0x3f << 0)
326/* data type values, see include/video/mipi_display.h */
327
328#define _MIPIA_GEN_FIFO_STAT			0xb074
329#define _MIPIC_GEN_FIFO_STAT			0xb874
330#define MIPI_GEN_FIFO_STAT(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
331#define  DPI_FIFO_EMPTY					(1 << 28)
332#define  DBI_FIFO_EMPTY					(1 << 27)
333#define  LP_CTRL_FIFO_EMPTY				(1 << 26)
334#define  LP_CTRL_FIFO_HALF_EMPTY			(1 << 25)
335#define  LP_CTRL_FIFO_FULL				(1 << 24)
336#define  HS_CTRL_FIFO_EMPTY				(1 << 18)
337#define  HS_CTRL_FIFO_HALF_EMPTY			(1 << 17)
338#define  HS_CTRL_FIFO_FULL				(1 << 16)
339#define  LP_DATA_FIFO_EMPTY				(1 << 10)
340#define  LP_DATA_FIFO_HALF_EMPTY			(1 << 9)
341#define  LP_DATA_FIFO_FULL				(1 << 8)
342#define  HS_DATA_FIFO_EMPTY				(1 << 2)
343#define  HS_DATA_FIFO_HALF_EMPTY			(1 << 1)
344#define  HS_DATA_FIFO_FULL				(1 << 0)
345
346#define _MIPIA_HS_LS_DBI_ENABLE			0xb078
347#define _MIPIC_HS_LS_DBI_ENABLE			0xb878
348#define MIPI_HS_LP_DBI_ENABLE(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
349#define  DBI_HS_LP_MODE_MASK				(1 << 0)
350#define  DBI_LP_MODE					(1 << 0)
351#define  DBI_HS_MODE					(0 << 0)
352
353#define _MIPIA_DPHY_PARAM			0xb080
354#define _MIPIC_DPHY_PARAM			0xb880
355#define MIPI_DPHY_PARAM(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
356#define  EXIT_ZERO_COUNT_SHIFT				24
357#define  EXIT_ZERO_COUNT_MASK				(0x3f << 24)
358#define  TRAIL_COUNT_SHIFT				16
359#define  TRAIL_COUNT_MASK				(0x1f << 16)
360#define  CLK_ZERO_COUNT_SHIFT				8
361#define  CLK_ZERO_COUNT_MASK				(0xff << 8)
362#define  PREPARE_COUNT_SHIFT				0
363#define  PREPARE_COUNT_MASK				(0x3f << 0)
364
365#define _MIPIA_DBI_BW_CTRL			0xb084
366#define _MIPIC_DBI_BW_CTRL			0xb884
367#define MIPI_DBI_BW_CTRL(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
368
369#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		0xb088
370#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		0xb888
371#define MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
372#define  LP_HS_SSW_CNT_SHIFT				16
373#define  LP_HS_SSW_CNT_MASK				(0xffff << 16)
374#define  HS_LP_PWR_SW_CNT_SHIFT				0
375#define  HS_LP_PWR_SW_CNT_MASK				(0xffff << 0)
376
377#define _MIPIA_STOP_STATE_STALL			0xb08c
378#define _MIPIC_STOP_STATE_STALL			0xb88c
379#define MIPI_STOP_STATE_STALL(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
380#define  STOP_STATE_STALL_COUNTER_SHIFT			0
381#define  STOP_STATE_STALL_COUNTER_MASK			(0xff << 0)
382
383#define _MIPIA_INTR_STAT_REG_1			0xb090
384#define _MIPIC_INTR_STAT_REG_1			0xb890
385#define MIPI_INTR_STAT_REG_1(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
386#define _MIPIA_INTR_EN_REG_1			0xb094
387#define _MIPIC_INTR_EN_REG_1			0xb894
388#define MIPI_INTR_EN_REG_1(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
389#define  RX_CONTENTION_DETECTED				(1 << 0)
390
391/* XXX: only pipe A ?!? */
392#define MIPIA_DBI_TYPEC_CTRL(display)		(_MIPI_MMIO_BASE(display) + 0xb100)
393#define  DBI_TYPEC_ENABLE				(1 << 31)
394#define  DBI_TYPEC_WIP					(1 << 30)
395#define  DBI_TYPEC_OPTION_SHIFT				28
396#define  DBI_TYPEC_OPTION_MASK				(3 << 28)
397#define  DBI_TYPEC_FREQ_SHIFT				24
398#define  DBI_TYPEC_FREQ_MASK				(0xf << 24)
399#define  DBI_TYPEC_OVERRIDE				(1 << 8)
400#define  DBI_TYPEC_OVERRIDE_COUNTER_SHIFT		0
401#define  DBI_TYPEC_OVERRIDE_COUNTER_MASK		(0xff << 0)
402
403/* MIPI adapter registers */
404
405#define _MIPIA_CTRL				0xb104
406#define _MIPIC_CTRL				0xb904
407#define MIPI_CTRL(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_CTRL, _MIPIC_CTRL)
408#define  ESCAPE_CLOCK_DIVIDER_SHIFT			5 /* A only */
409#define  ESCAPE_CLOCK_DIVIDER_MASK			(3 << 5)
410#define  ESCAPE_CLOCK_DIVIDER_1				(0 << 5)
411#define  ESCAPE_CLOCK_DIVIDER_2				(1 << 5)
412#define  ESCAPE_CLOCK_DIVIDER_4				(2 << 5)
413#define  READ_REQUEST_PRIORITY_SHIFT			3
414#define  READ_REQUEST_PRIORITY_MASK			(3 << 3)
415#define  READ_REQUEST_PRIORITY_LOW			(0 << 3)
416#define  READ_REQUEST_PRIORITY_HIGH			(3 << 3)
417#define  RGB_FLIP_TO_BGR				(1 << 2)
418
419#define  BXT_PIPE_SELECT_SHIFT				7
420#define  BXT_PIPE_SELECT_MASK				(7 << 7)
421#define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
422#define  GLK_PHY_STATUS_PORT_READY			(1 << 31) /* RO */
423#define  GLK_ULPS_NOT_ACTIVE				(1 << 30) /* RO */
424#define  GLK_MIPIIO_RESET_RELEASED			(1 << 28)
425#define  GLK_CLOCK_LANE_STOP_STATE			(1 << 27) /* RO */
426#define  GLK_DATA_LANE_STOP_STATE			(1 << 26) /* RO */
427#define  GLK_LP_WAKE					(1 << 22)
428#define  GLK_LP11_LOW_PWR_MODE				(1 << 21)
429#define  GLK_LP00_LOW_PWR_MODE				(1 << 20)
430#define  GLK_FIREWALL_ENABLE				(1 << 16)
431#define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
432#define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10
433#define  BXT_DSC_ENABLE					(1 << 3)
434#define  BXT_RGB_FLIP					(1 << 2)
435#define  GLK_MIPIIO_PORT_POWERED			(1 << 1) /* RO */
436#define  GLK_MIPIIO_ENABLE				(1 << 0)
437
438#define _MIPIA_DATA_ADDRESS			0xb108
439#define _MIPIC_DATA_ADDRESS			0xb908
440#define MIPI_DATA_ADDRESS(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
441#define  DATA_MEM_ADDRESS_SHIFT				5
442#define  DATA_MEM_ADDRESS_MASK				(0x7ffffff << 5)
443#define  DATA_VALID					(1 << 0)
444
445#define _MIPIA_DATA_LENGTH			0xb10c
446#define _MIPIC_DATA_LENGTH			0xb90c
447#define MIPI_DATA_LENGTH(display, port)		_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
448#define  DATA_LENGTH_SHIFT				0
449#define  DATA_LENGTH_MASK				(0xfffff << 0)
450
451#define _MIPIA_COMMAND_ADDRESS			0xb110
452#define _MIPIC_COMMAND_ADDRESS			0xb910
453#define MIPI_COMMAND_ADDRESS(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
454#define  COMMAND_MEM_ADDRESS_SHIFT			5
455#define  COMMAND_MEM_ADDRESS_MASK			(0x7ffffff << 5)
456#define  AUTO_PWG_ENABLE				(1 << 2)
457#define  MEMORY_WRITE_DATA_FROM_PIPE_RENDERING		(1 << 1)
458#define  COMMAND_VALID					(1 << 0)
459
460#define _MIPIA_COMMAND_LENGTH			0xb114
461#define _MIPIC_COMMAND_LENGTH			0xb914
462#define MIPI_COMMAND_LENGTH(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
463#define  COMMAND_LENGTH_SHIFT(n)			(8 * (n)) /* n: 0...3 */
464#define  COMMAND_LENGTH_MASK(n)				(0xff << (8 * (n)))
465
466#define _MIPIA_READ_DATA_RETURN0		0xb118
467#define _MIPIC_READ_DATA_RETURN0		0xb918
468#define MIPI_READ_DATA_RETURN(display, port, n)	_MMIO_MIPI(_MIPI_MMIO_BASE(display) + 4 * (n), port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) /* n: 0...7 */
469
470#define _MIPIA_READ_DATA_VALID			0xb138
471#define _MIPIC_READ_DATA_VALID			0xb938
472#define MIPI_READ_DATA_VALID(display, port)	_MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
473#define  READ_DATA_VALID(n)				(1 << (n))
474
475#endif /* __VLV_DSI_REGS_H__ */