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vlv_dsi.c
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linux-6.19.14/drivers/gpu/drm/i915/display/vlv_dsi.c
1/* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Jani Nikula <jani.nikula@intel.com> 24 */ 25 26#include <linux/dmi.h> 27#include <linux/slab.h> 28 29#include <drm/drm_atomic_helper.h> 30#include <drm/drm_crtc.h> 31#include <drm/drm_edid.h> 32#include <drm/drm_mipi_dsi.h> 33#include <drm/drm_print.h> 34#include <drm/drm_probe_helper.h> 35 36#include "i915_reg.h" 37#include "intel_atomic.h" 38#include "intel_backlight.h" 39#include "intel_connector.h" 40#include "intel_crtc.h" 41#include "intel_de.h" 42#include "intel_display_regs.h" 43#include "intel_display_types.h" 44#include "intel_display_utils.h" 45#include "intel_dsi.h" 46#include "intel_dsi_vbt.h" 47#include "intel_fifo_underrun.h" 48#include "intel_panel.h" 49#include "intel_pfit.h" 50#include "skl_scaler.h" 51#include "vlv_dsi.h" 52#include "vlv_dsi_pll.h" 53#include "vlv_dsi_regs.h" 54#include "vlv_sideband.h" 55 56/* return pixels in terms of txbyteclkhs */ 57static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, 58 u16 burst_mode_ratio) 59{ 60 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, 61 8 * 100), lane_count); 62} 63 64/* return pixels equivalent to txbyteclkhs */ 65static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, 66 u16 burst_mode_ratio) 67{ 68 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), 69 (bpp * burst_mode_ratio)); 70} 71 72static enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 73{ 74 switch (fmt) { 75 case VID_MODE_FORMAT_RGB888: 76 return MIPI_DSI_FMT_RGB888; 77 case VID_MODE_FORMAT_RGB666: 78 return MIPI_DSI_FMT_RGB666; 79 case VID_MODE_FORMAT_RGB666_PACKED: 80 return MIPI_DSI_FMT_RGB666_PACKED; 81 case VID_MODE_FORMAT_RGB565: 82 return MIPI_DSI_FMT_RGB565; 83 default: 84 MISSING_CASE(fmt); 85 return MIPI_DSI_FMT_RGB666; 86 } 87} 88 89void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) 90{ 91 struct intel_display *display = to_intel_display(&intel_dsi->base); 92 u32 mask; 93 94 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | 95 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; 96 97 if (intel_de_wait_for_set_ms(display, MIPI_GEN_FIFO_STAT(display, port), 98 mask, 100)) 99 drm_err(display->drm, "DPI FIFOs are not empty\n"); 100} 101 102static void write_data(struct intel_display *display, 103 i915_reg_t reg, 104 const u8 *data, u32 len) 105{ 106 u32 i, j; 107 108 for (i = 0; i < len; i += 4) { 109 u32 val = 0; 110 111 for (j = 0; j < min_t(u32, len - i, 4); j++) 112 val |= *data++ << 8 * j; 113 114 intel_de_write(display, reg, val); 115 } 116} 117 118static void read_data(struct intel_display *display, 119 i915_reg_t reg, 120 u8 *data, u32 len) 121{ 122 u32 i, j; 123 124 for (i = 0; i < len; i += 4) { 125 u32 val = intel_de_read(display, reg); 126 127 for (j = 0; j < min_t(u32, len - i, 4); j++) 128 *data++ = val >> 8 * j; 129 } 130} 131 132static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, 133 const struct mipi_dsi_msg *msg) 134{ 135 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 136 struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi; 137 struct intel_display *display = to_intel_display(&intel_dsi->base); 138 enum port port = intel_dsi_host->port; 139 struct mipi_dsi_packet packet; 140 ssize_t ret; 141 const u8 *header; 142 i915_reg_t data_reg, ctrl_reg; 143 u32 data_mask, ctrl_mask; 144 145 ret = mipi_dsi_create_packet(&packet, msg); 146 if (ret < 0) 147 return ret; 148 149 header = packet.header; 150 151 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { 152 data_reg = MIPI_LP_GEN_DATA(display, port); 153 data_mask = LP_DATA_FIFO_FULL; 154 ctrl_reg = MIPI_LP_GEN_CTRL(display, port); 155 ctrl_mask = LP_CTRL_FIFO_FULL; 156 } else { 157 data_reg = MIPI_HS_GEN_DATA(display, port); 158 data_mask = HS_DATA_FIFO_FULL; 159 ctrl_reg = MIPI_HS_GEN_CTRL(display, port); 160 ctrl_mask = HS_CTRL_FIFO_FULL; 161 } 162 163 /* note: this is never true for reads */ 164 if (packet.payload_length) { 165 if (intel_de_wait_for_clear_ms(display, MIPI_GEN_FIFO_STAT(display, port), 166 data_mask, 50)) 167 drm_err(display->drm, 168 "Timeout waiting for HS/LP DATA FIFO !full\n"); 169 170 write_data(display, data_reg, packet.payload, 171 packet.payload_length); 172 } 173 174 if (msg->rx_len) { 175 intel_de_write(display, MIPI_INTR_STAT(display, port), 176 GEN_READ_DATA_AVAIL); 177 } 178 179 if (intel_de_wait_for_clear_ms(display, MIPI_GEN_FIFO_STAT(display, port), 180 ctrl_mask, 50)) { 181 drm_err(display->drm, 182 "Timeout waiting for HS/LP CTRL FIFO !full\n"); 183 } 184 185 intel_de_write(display, ctrl_reg, 186 header[2] << 16 | header[1] << 8 | header[0]); 187 188 /* ->rx_len is set only for reads */ 189 if (msg->rx_len) { 190 data_mask = GEN_READ_DATA_AVAIL; 191 if (intel_de_wait_for_set_ms(display, MIPI_INTR_STAT(display, port), 192 data_mask, 50)) 193 drm_err(display->drm, 194 "Timeout waiting for read data.\n"); 195 196 read_data(display, data_reg, msg->rx_buf, msg->rx_len); 197 } 198 199 /* XXX: fix for reads and writes */ 200 return 4 + packet.payload_length; 201} 202 203static int intel_dsi_host_attach(struct mipi_dsi_host *host, 204 struct mipi_dsi_device *dsi) 205{ 206 return 0; 207} 208 209static int intel_dsi_host_detach(struct mipi_dsi_host *host, 210 struct mipi_dsi_device *dsi) 211{ 212 return 0; 213} 214 215static const struct mipi_dsi_host_ops intel_dsi_host_ops = { 216 .attach = intel_dsi_host_attach, 217 .detach = intel_dsi_host_detach, 218 .transfer = intel_dsi_host_transfer, 219}; 220 221/* 222 * send a video mode command 223 * 224 * XXX: commands with data in MIPI_DPI_DATA? 225 */ 226static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, 227 enum port port) 228{ 229 struct intel_display *display = to_intel_display(&intel_dsi->base); 230 u32 mask; 231 232 /* XXX: pipe, hs */ 233 if (hs) 234 cmd &= ~DPI_LP_MODE; 235 else 236 cmd |= DPI_LP_MODE; 237 238 /* clear bit */ 239 intel_de_write(display, MIPI_INTR_STAT(display, port), SPL_PKT_SENT_INTERRUPT); 240 241 /* XXX: old code skips write if control unchanged */ 242 if (cmd == intel_de_read(display, MIPI_DPI_CONTROL(display, port))) 243 drm_dbg_kms(display->drm, 244 "Same special packet %02x twice in a row.\n", cmd); 245 246 intel_de_write(display, MIPI_DPI_CONTROL(display, port), cmd); 247 248 mask = SPL_PKT_SENT_INTERRUPT; 249 if (intel_de_wait_for_set_ms(display, MIPI_INTR_STAT(display, port), mask, 100)) 250 drm_err(display->drm, 251 "Video mode command 0x%08x send failed.\n", cmd); 252 253 return 0; 254} 255 256static void band_gap_reset(struct intel_display *display) 257{ 258 vlv_flisdsi_get(display->drm); 259 260 vlv_flisdsi_write(display->drm, 0x08, 0x0001); 261 vlv_flisdsi_write(display->drm, 0x0F, 0x0005); 262 vlv_flisdsi_write(display->drm, 0x0F, 0x0025); 263 udelay(150); 264 vlv_flisdsi_write(display->drm, 0x0F, 0x0000); 265 vlv_flisdsi_write(display->drm, 0x08, 0x0000); 266 267 vlv_flisdsi_put(display->drm); 268} 269 270static int intel_dsi_compute_config(struct intel_encoder *encoder, 271 struct intel_crtc_state *pipe_config, 272 struct drm_connector_state *conn_state) 273{ 274 struct intel_display *display = to_intel_display(encoder); 275 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 276 struct intel_connector *intel_connector = intel_dsi->attached_connector; 277 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 278 int ret; 279 280 drm_dbg_kms(display->drm, "\n"); 281 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 282 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 283 284 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 285 if (ret) 286 return ret; 287 288 ret = intel_pfit_compute_config(pipe_config, conn_state); 289 if (ret) 290 return ret; 291 292 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 293 return -EINVAL; 294 295 /* DSI uses short packets for sync events, so clear mode flags for DSI */ 296 adjusted_mode->flags = 0; 297 298 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 299 pipe_config->pipe_bpp = 24; 300 else 301 pipe_config->pipe_bpp = 18; 302 303 if (display->platform.geminilake || display->platform.broxton) { 304 /* Enable Frame time stamp based scanline reporting */ 305 pipe_config->mode_flags |= 306 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 307 308 /* Dual link goes to DSI transcoder A. */ 309 if (intel_dsi->ports == BIT(PORT_C)) 310 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; 311 else 312 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; 313 314 ret = bxt_dsi_pll_compute(encoder, pipe_config); 315 if (ret) 316 return -EINVAL; 317 } else { 318 ret = vlv_dsi_pll_compute(encoder, pipe_config); 319 if (ret) 320 return -EINVAL; 321 } 322 323 pipe_config->clock_set = true; 324 325 return 0; 326} 327 328static bool glk_dsi_enable_io(struct intel_encoder *encoder) 329{ 330 struct intel_display *display = to_intel_display(encoder); 331 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 332 enum port port; 333 bool cold_boot = false; 334 335 /* Set the MIPI mode 336 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting. 337 * Power ON MIPI IO first and then write into IO reset and LP wake bits 338 */ 339 for_each_dsi_port(port, intel_dsi->ports) 340 intel_de_rmw(display, MIPI_CTRL(display, port), 0, GLK_MIPIIO_ENABLE); 341 342 /* Put the IO into reset */ 343 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); 344 345 /* Program LP Wake */ 346 for_each_dsi_port(port, intel_dsi->ports) { 347 u32 tmp = intel_de_read(display, MIPI_DEVICE_READY(display, port)); 348 349 intel_de_rmw(display, MIPI_CTRL(display, port), 350 GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0); 351 } 352 353 /* Wait for Pwr ACK */ 354 for_each_dsi_port(port, intel_dsi->ports) { 355 if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port), 356 GLK_MIPIIO_PORT_POWERED, 20)) 357 drm_err(display->drm, "MIPIO port is powergated\n"); 358 } 359 360 /* Check for cold boot scenario */ 361 for_each_dsi_port(port, intel_dsi->ports) { 362 cold_boot |= 363 !(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY); 364 } 365 366 return cold_boot; 367} 368 369static void glk_dsi_device_ready(struct intel_encoder *encoder) 370{ 371 struct intel_display *display = to_intel_display(encoder); 372 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 373 enum port port; 374 375 /* Wait for MIPI PHY status bit to set */ 376 for_each_dsi_port(port, intel_dsi->ports) { 377 if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port), 378 GLK_PHY_STATUS_PORT_READY, 20)) 379 drm_err(display->drm, "PHY is not ON\n"); 380 } 381 382 /* Get IO out of reset */ 383 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); 384 385 /* Get IO out of Low power state*/ 386 for_each_dsi_port(port, intel_dsi->ports) { 387 if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) { 388 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), 389 ULPS_STATE_MASK, DEVICE_READY); 390 usleep_range(10, 15); 391 } else { 392 /* Enter ULPS */ 393 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), 394 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); 395 396 /* Wait for ULPS active */ 397 if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port), 398 GLK_ULPS_NOT_ACTIVE, 20)) 399 drm_err(display->drm, "ULPS not active\n"); 400 401 /* Exit ULPS */ 402 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), 403 ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY); 404 405 /* Enter Normal Mode */ 406 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), 407 ULPS_STATE_MASK, 408 ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); 409 410 intel_de_rmw(display, MIPI_CTRL(display, port), GLK_LP_WAKE, 0); 411 } 412 } 413 414 /* Wait for Stop state */ 415 for_each_dsi_port(port, intel_dsi->ports) { 416 if (intel_de_wait_for_set_ms(display, MIPI_CTRL(display, port), 417 GLK_DATA_LANE_STOP_STATE, 20)) 418 drm_err(display->drm, 419 "Date lane not in STOP state\n"); 420 } 421 422 /* Wait for AFE LATCH */ 423 for_each_dsi_port(port, intel_dsi->ports) { 424 if (intel_de_wait_for_set_ms(display, BXT_MIPI_PORT_CTRL(port), 425 AFE_LATCHOUT, 20)) 426 drm_err(display->drm, 427 "D-PHY not entering LP-11 state\n"); 428 } 429} 430 431static void bxt_dsi_device_ready(struct intel_encoder *encoder) 432{ 433 struct intel_display *display = to_intel_display(encoder); 434 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 435 enum port port; 436 u32 val; 437 438 drm_dbg_kms(display->drm, "\n"); 439 440 /* Enable MIPI PHY transparent latch */ 441 for_each_dsi_port(port, intel_dsi->ports) { 442 intel_de_rmw(display, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); 443 usleep_range(2000, 2500); 444 } 445 446 /* Clear ULPS and set device ready */ 447 for_each_dsi_port(port, intel_dsi->ports) { 448 val = intel_de_read(display, MIPI_DEVICE_READY(display, port)); 449 val &= ~ULPS_STATE_MASK; 450 intel_de_write(display, MIPI_DEVICE_READY(display, port), val); 451 usleep_range(2000, 2500); 452 val |= DEVICE_READY; 453 intel_de_write(display, MIPI_DEVICE_READY(display, port), val); 454 } 455} 456 457static void vlv_dsi_device_ready(struct intel_encoder *encoder) 458{ 459 struct intel_display *display = to_intel_display(encoder); 460 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 461 enum port port; 462 463 drm_dbg_kms(display->drm, "\n"); 464 465 vlv_flisdsi_get(display->drm); 466 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms 467 * needed everytime after power gate */ 468 vlv_flisdsi_write(display->drm, 0x04, 0x0004); 469 vlv_flisdsi_put(display->drm); 470 471 /* bandgap reset is needed after everytime we do power gate */ 472 band_gap_reset(display); 473 474 for_each_dsi_port(port, intel_dsi->ports) { 475 476 intel_de_write(display, MIPI_DEVICE_READY(display, port), 477 ULPS_STATE_ENTER); 478 usleep_range(2500, 3000); 479 480 /* Enable MIPI PHY transparent latch 481 * Common bit for both MIPI Port A & MIPI Port C 482 * No similar bit in MIPI Port C reg 483 */ 484 intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); 485 usleep_range(1000, 1500); 486 487 intel_de_write(display, MIPI_DEVICE_READY(display, port), 488 ULPS_STATE_EXIT); 489 usleep_range(2500, 3000); 490 491 intel_de_write(display, MIPI_DEVICE_READY(display, port), 492 DEVICE_READY); 493 usleep_range(2500, 3000); 494 } 495} 496 497static void intel_dsi_device_ready(struct intel_encoder *encoder) 498{ 499 struct intel_display *display = to_intel_display(encoder); 500 501 if (display->platform.geminilake) 502 glk_dsi_device_ready(encoder); 503 else if (display->platform.geminilake || display->platform.broxton) 504 bxt_dsi_device_ready(encoder); 505 else 506 vlv_dsi_device_ready(encoder); 507} 508 509static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) 510{ 511 struct intel_display *display = to_intel_display(encoder); 512 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 513 enum port port; 514 515 /* Enter ULPS */ 516 for_each_dsi_port(port, intel_dsi->ports) 517 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), 518 ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY); 519 520 /* Wait for MIPI PHY status bit to unset */ 521 for_each_dsi_port(port, intel_dsi->ports) { 522 if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port), 523 GLK_PHY_STATUS_PORT_READY, 20)) 524 drm_err(display->drm, "PHY is not turning OFF\n"); 525 } 526 527 /* Wait for Pwr ACK bit to unset */ 528 for_each_dsi_port(port, intel_dsi->ports) { 529 if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port), 530 GLK_MIPIIO_PORT_POWERED, 20)) 531 drm_err(display->drm, 532 "MIPI IO Port is not powergated\n"); 533 } 534} 535 536static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) 537{ 538 struct intel_display *display = to_intel_display(encoder); 539 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 540 enum port port; 541 542 /* Put the IO into reset */ 543 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); 544 545 /* Wait for MIPI PHY status bit to unset */ 546 for_each_dsi_port(port, intel_dsi->ports) { 547 if (intel_de_wait_for_clear_ms(display, MIPI_CTRL(display, port), 548 GLK_PHY_STATUS_PORT_READY, 20)) 549 drm_err(display->drm, "PHY is not turning OFF\n"); 550 } 551 552 /* Clear MIPI mode */ 553 for_each_dsi_port(port, intel_dsi->ports) 554 intel_de_rmw(display, MIPI_CTRL(display, port), GLK_MIPIIO_ENABLE, 0); 555} 556 557static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) 558{ 559 glk_dsi_enter_low_power_mode(encoder); 560 glk_dsi_disable_mipi_io(encoder); 561} 562 563static i915_reg_t port_ctrl_reg(struct intel_display *display, enum port port) 564{ 565 return display->platform.geminilake || display->platform.broxton ? 566 BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(port); 567} 568 569static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) 570{ 571 struct intel_display *display = to_intel_display(encoder); 572 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 573 enum port port; 574 575 drm_dbg_kms(display->drm, "\n"); 576 for_each_dsi_port(port, intel_dsi->ports) { 577 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ 578 i915_reg_t port_ctrl = display->platform.broxton ? 579 BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A); 580 581 intel_de_write(display, MIPI_DEVICE_READY(display, port), 582 DEVICE_READY | ULPS_STATE_ENTER); 583 usleep_range(2000, 2500); 584 585 intel_de_write(display, MIPI_DEVICE_READY(display, port), 586 DEVICE_READY | ULPS_STATE_EXIT); 587 usleep_range(2000, 2500); 588 589 intel_de_write(display, MIPI_DEVICE_READY(display, port), 590 DEVICE_READY | ULPS_STATE_ENTER); 591 usleep_range(2000, 2500); 592 593 /* 594 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI 595 * Port A only. MIPI Port C has no similar bit for checking. 596 */ 597 if ((display->platform.broxton || port == PORT_A) && 598 intel_de_wait_for_clear_ms(display, port_ctrl, 599 AFE_LATCHOUT, 30)) 600 drm_err(display->drm, "DSI LP not going Low\n"); 601 602 /* Disable MIPI PHY transparent latch */ 603 intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0); 604 usleep_range(1000, 1500); 605 606 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x00); 607 usleep_range(2000, 2500); 608 } 609} 610 611static void intel_dsi_port_enable(struct intel_encoder *encoder, 612 const struct intel_crtc_state *crtc_state) 613{ 614 struct intel_display *display = to_intel_display(encoder); 615 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 616 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 617 enum port port; 618 619 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 620 u32 temp = intel_dsi->pixel_overlap; 621 622 if (display->platform.geminilake || display->platform.broxton) { 623 for_each_dsi_port(port, intel_dsi->ports) 624 intel_de_rmw(display, MIPI_CTRL(display, port), 625 BXT_PIXEL_OVERLAP_CNT_MASK, 626 temp << BXT_PIXEL_OVERLAP_CNT_SHIFT); 627 } else { 628 intel_de_rmw(display, VLV_CHICKEN_3, 629 PIXEL_OVERLAP_CNT_MASK, 630 temp << PIXEL_OVERLAP_CNT_SHIFT); 631 } 632 } 633 634 for_each_dsi_port(port, intel_dsi->ports) { 635 i915_reg_t port_ctrl = port_ctrl_reg(display, port); 636 u32 temp; 637 638 temp = intel_de_read(display, port_ctrl); 639 640 temp &= ~LANE_CONFIGURATION_MASK; 641 temp &= ~DUAL_LINK_MODE_MASK; 642 643 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { 644 temp |= (intel_dsi->dual_link - 1) 645 << DUAL_LINK_MODE_SHIFT; 646 if (display->platform.broxton) 647 temp |= LANE_CONFIGURATION_DUAL_LINK_A; 648 else 649 temp |= crtc->pipe ? 650 LANE_CONFIGURATION_DUAL_LINK_B : 651 LANE_CONFIGURATION_DUAL_LINK_A; 652 } 653 654 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) 655 temp |= DITHERING_ENABLE; 656 657 /* assert ip_tg_enable signal */ 658 intel_de_write(display, port_ctrl, temp | DPI_ENABLE); 659 intel_de_posting_read(display, port_ctrl); 660 } 661} 662 663static void intel_dsi_port_disable(struct intel_encoder *encoder) 664{ 665 struct intel_display *display = to_intel_display(encoder); 666 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 667 enum port port; 668 669 for_each_dsi_port(port, intel_dsi->ports) { 670 i915_reg_t port_ctrl = port_ctrl_reg(display, port); 671 672 /* de-assert ip_tg_enable signal */ 673 intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0); 674 intel_de_posting_read(display, port_ctrl); 675 } 676} 677 678static void intel_dsi_prepare(struct intel_encoder *encoder, 679 const struct intel_crtc_state *pipe_config); 680static void intel_dsi_unprepare(struct intel_encoder *encoder); 681 682/* 683 * Panel enable/disable sequences from the VBT spec. 684 * 685 * Note the spec has AssertReset / DeassertReset swapped from their 686 * usual naming. We use the normal names to avoid confusion (so below 687 * they are swapped compared to the spec). 688 * 689 * Steps starting with MIPI refer to VBT sequences, note that for v2 690 * VBTs several steps which have a VBT in v2 are expected to be handled 691 * directly by the driver, by directly driving gpios for example. 692 * 693 * v2 video mode seq v3 video mode seq command mode seq 694 * - power on - MIPIPanelPowerOn - power on 695 * - wait t1+t2 - wait t1+t2 696 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin 697 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11 698 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds 699 * - MIPITearOn 700 * - MIPIDisplayOn 701 * - turn on DPI - turn on DPI - set pipe to dsr mode 702 * - MIPIDisplayOn - MIPIDisplayOn 703 * - wait t5 - wait t5 704 * - backlight on - MIPIBacklightOn - backlight on 705 * ... ... ... issue mem cmds ... 706 * - backlight off - MIPIBacklightOff - backlight off 707 * - wait t6 - wait t6 708 * - MIPIDisplayOff 709 * - turn off DPI - turn off DPI - disable pipe dsr mode 710 * - MIPITearOff 711 * - MIPIDisplayOff - MIPIDisplayOff 712 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00 713 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin 714 * - wait t3 - wait t3 715 * - power off - MIPIPanelPowerOff - power off 716 * - wait t4 - wait t4 717 */ 718 719/* 720 * DSI port enable has to be done before pipe and plane enable, so we do it in 721 * the pre_enable hook instead of the enable hook. 722 */ 723static void intel_dsi_pre_enable(struct intel_atomic_state *state, 724 struct intel_encoder *encoder, 725 const struct intel_crtc_state *pipe_config, 726 const struct drm_connector_state *conn_state) 727{ 728 struct intel_display *display = to_intel_display(encoder); 729 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 730 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 731 enum pipe pipe = crtc->pipe; 732 enum port port; 733 bool glk_cold_boot = false; 734 735 drm_dbg_kms(display->drm, "\n"); 736 737 intel_dsi_wait_panel_power_cycle(intel_dsi); 738 739 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 740 741 /* 742 * The BIOS may leave the PLL in a wonky state where it doesn't 743 * lock. It needs to be fully powered down to fix it. 744 */ 745 if (display->platform.geminilake || display->platform.broxton) { 746 bxt_dsi_pll_disable(encoder); 747 bxt_dsi_pll_enable(encoder, pipe_config); 748 } else { 749 vlv_dsi_pll_disable(encoder); 750 vlv_dsi_pll_enable(encoder, pipe_config); 751 } 752 753 if (display->platform.broxton) { 754 /* Add MIPI IO reset programming for modeset */ 755 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL); 756 757 /* Power up DSI regulator */ 758 intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 759 intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 0); 760 } 761 762 if (display->platform.valleyview || display->platform.cherryview) { 763 /* Disable DPOunit clock gating, can stall pipe */ 764 intel_de_rmw(display, VLV_DSPCLK_GATE_D, 765 0, DPOUNIT_CLOCK_GATE_DISABLE); 766 } 767 768 if (!display->platform.geminilake) 769 intel_dsi_prepare(encoder, pipe_config); 770 771 /* Give the panel time to power-on and then deassert its reset */ 772 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 773 msleep(intel_dsi->panel_on_delay); 774 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 775 776 if (display->platform.geminilake) { 777 glk_cold_boot = glk_dsi_enable_io(encoder); 778 779 /* Prepare port in cold boot(s3/s4) scenario */ 780 if (glk_cold_boot) 781 intel_dsi_prepare(encoder, pipe_config); 782 } 783 784 /* Put device in ready state (LP-11) */ 785 intel_dsi_device_ready(encoder); 786 787 /* Prepare port in normal boot scenario */ 788 if (display->platform.geminilake && !glk_cold_boot) 789 intel_dsi_prepare(encoder, pipe_config); 790 791 /* Send initialization commands in LP mode */ 792 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 793 794 /* 795 * Enable port in pre-enable phase itself because as per hw team 796 * recommendation, port should be enabled before plane & pipe 797 */ 798 if (is_cmd_mode(intel_dsi)) { 799 for_each_dsi_port(port, intel_dsi->ports) 800 intel_de_write(display, 801 MIPI_MAX_RETURN_PKT_SIZE(display, port), 8 * 4); 802 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); 803 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 804 } else { 805 msleep(20); /* XXX */ 806 for_each_dsi_port(port, intel_dsi->ports) 807 dpi_send_cmd(intel_dsi, TURN_ON, false, port); 808 msleep(100); 809 810 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 811 812 intel_dsi_port_enable(encoder, pipe_config); 813 } 814 815 intel_backlight_enable(pipe_config, conn_state); 816 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 817} 818 819static void bxt_dsi_enable(struct intel_atomic_state *state, 820 struct intel_encoder *encoder, 821 const struct intel_crtc_state *crtc_state, 822 const struct drm_connector_state *conn_state) 823{ 824 intel_crtc_vblank_on(crtc_state); 825} 826 827/* 828 * DSI port disable has to be done after pipe and plane disable, so we do it in 829 * the post_disable hook. 830 */ 831static void intel_dsi_disable(struct intel_atomic_state *state, 832 struct intel_encoder *encoder, 833 const struct intel_crtc_state *old_crtc_state, 834 const struct drm_connector_state *old_conn_state) 835{ 836 struct intel_display *display = to_intel_display(encoder); 837 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 838 enum port port; 839 840 drm_dbg_kms(display->drm, "\n"); 841 842 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 843 intel_backlight_disable(old_conn_state); 844 845 /* 846 * According to the spec we should send SHUTDOWN before 847 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing 848 * has shown that the v3 sequence works for v2 VBTs too 849 */ 850 if (is_vid_mode(intel_dsi)) { 851 /* Send Shutdown command to the panel in LP mode */ 852 for_each_dsi_port(port, intel_dsi->ports) 853 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); 854 msleep(10); 855 } 856} 857 858static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 859{ 860 struct intel_display *display = to_intel_display(encoder); 861 862 if (display->platform.geminilake) 863 glk_dsi_clear_device_ready(encoder); 864 else 865 vlv_dsi_clear_device_ready(encoder); 866} 867 868static void intel_dsi_post_disable(struct intel_atomic_state *state, 869 struct intel_encoder *encoder, 870 const struct intel_crtc_state *old_crtc_state, 871 const struct drm_connector_state *old_conn_state) 872{ 873 struct intel_display *display = to_intel_display(encoder); 874 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 875 enum port port; 876 877 drm_dbg_kms(display->drm, "\n"); 878 879 if (display->platform.geminilake || display->platform.broxton) { 880 intel_crtc_vblank_off(old_crtc_state); 881 882 skl_scaler_disable(old_crtc_state); 883 } 884 885 if (is_vid_mode(intel_dsi)) { 886 for_each_dsi_port(port, intel_dsi->ports) 887 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 888 889 intel_dsi_port_disable(encoder); 890 usleep_range(2000, 5000); 891 } 892 893 intel_dsi_unprepare(encoder); 894 895 /* 896 * if disable packets are sent before sending shutdown packet then in 897 * some next enable sequence send turn on packet error is observed 898 */ 899 if (is_cmd_mode(intel_dsi)) 900 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF); 901 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 902 903 /* Transition to LP-00 */ 904 intel_dsi_clear_device_ready(encoder); 905 906 if (display->platform.broxton) { 907 /* Power down DSI regulator to save power */ 908 intel_de_write(display, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); 909 intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, 910 HS_IO_CTRL_SELECT); 911 912 /* Add MIPI IO reset programming for modeset */ 913 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0); 914 } 915 916 if (display->platform.geminilake || display->platform.broxton) { 917 bxt_dsi_pll_disable(encoder); 918 } else { 919 vlv_dsi_pll_disable(encoder); 920 921 intel_de_rmw(display, VLV_DSPCLK_GATE_D, 922 DPOUNIT_CLOCK_GATE_DISABLE, 0); 923 } 924 925 /* Assert reset */ 926 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 927 928 msleep(intel_dsi->panel_off_delay); 929 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 930 931 intel_dsi->panel_power_off_time = ktime_get_boottime(); 932} 933 934static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 935 enum pipe *pipe) 936{ 937 struct intel_display *display = to_intel_display(encoder); 938 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 939 intel_wakeref_t wakeref; 940 enum port port; 941 bool active = false; 942 943 drm_dbg_kms(display->drm, "\n"); 944 945 wakeref = intel_display_power_get_if_enabled(display, 946 encoder->power_domain); 947 if (!wakeref) 948 return false; 949 950 /* 951 * On Broxton the PLL needs to be enabled with a valid divider 952 * configuration, otherwise accessing DSI registers will hang the 953 * machine. See BSpec North Display Engine registers/MIPI[BXT]. 954 */ 955 if ((display->platform.geminilake || display->platform.broxton) && 956 !bxt_dsi_pll_is_enabled(display)) 957 goto out_put_power; 958 959 /* XXX: this only works for one DSI output */ 960 for_each_dsi_port(port, intel_dsi->ports) { 961 i915_reg_t port_ctrl = port_ctrl_reg(display, port); 962 bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE; 963 964 /* 965 * Due to some hardware limitations on VLV/CHV, the DPI enable 966 * bit in port C control register does not get set. As a 967 * workaround, check pipe B conf instead. 968 */ 969 if ((display->platform.valleyview || display->platform.cherryview) && 970 port == PORT_C) 971 enabled = intel_de_read(display, 972 TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE; 973 974 /* Try command mode if video mode not enabled */ 975 if (!enabled) { 976 u32 tmp = intel_de_read(display, 977 MIPI_DSI_FUNC_PRG(display, port)); 978 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; 979 } 980 981 if (!enabled) 982 continue; 983 984 if (!(intel_de_read(display, MIPI_DEVICE_READY(display, port)) & DEVICE_READY)) 985 continue; 986 987 if (display->platform.geminilake || display->platform.broxton) { 988 u32 tmp = intel_de_read(display, MIPI_CTRL(display, port)); 989 tmp &= BXT_PIPE_SELECT_MASK; 990 tmp >>= BXT_PIPE_SELECT_SHIFT; 991 992 if (drm_WARN_ON(display->drm, tmp > PIPE_C)) 993 continue; 994 995 *pipe = tmp; 996 } else { 997 *pipe = port == PORT_A ? PIPE_A : PIPE_B; 998 } 999 1000 active = true; 1001 break; 1002 } 1003 1004out_put_power: 1005 intel_display_power_put(display, encoder->power_domain, wakeref); 1006 1007 return active; 1008} 1009 1010static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, 1011 struct intel_crtc_state *pipe_config) 1012{ 1013 struct intel_display *display = to_intel_display(encoder); 1014 struct drm_display_mode *adjusted_mode = 1015 &pipe_config->hw.adjusted_mode; 1016 struct drm_display_mode *adjusted_mode_sw; 1017 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1018 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1019 unsigned int lane_count = intel_dsi->lane_count; 1020 unsigned int bpp, fmt; 1021 enum port port; 1022 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1023 u16 hfp_sw, hsync_sw, hbp_sw; 1024 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, 1025 crtc_hblank_start_sw, crtc_hblank_end_sw; 1026 1027 /* FIXME: hw readout should not depend on SW state */ 1028 adjusted_mode_sw = &crtc->config->hw.adjusted_mode; 1029 1030 /* 1031 * Atleast one port is active as encoder->get_config called only if 1032 * encoder->get_hw_state() returns true. 1033 */ 1034 for_each_dsi_port(port, intel_dsi->ports) { 1035 if (intel_de_read(display, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) 1036 break; 1037 } 1038 1039 fmt = intel_de_read(display, MIPI_DSI_FUNC_PRG(display, port)) & VID_MODE_FORMAT_MASK; 1040 bpp = mipi_dsi_pixel_format_to_bpp( 1041 pixel_format_from_register_bits(fmt)); 1042 1043 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); 1044 1045 /* Enable Frame time stamo based scanline reporting */ 1046 pipe_config->mode_flags |= 1047 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; 1048 1049 /* In terms of pixels */ 1050 adjusted_mode->crtc_hdisplay = 1051 intel_de_read(display, 1052 BXT_MIPI_TRANS_HACTIVE(port)); 1053 adjusted_mode->crtc_vdisplay = 1054 intel_de_read(display, 1055 BXT_MIPI_TRANS_VACTIVE(port)); 1056 adjusted_mode->crtc_vtotal = 1057 intel_de_read(display, 1058 BXT_MIPI_TRANS_VTOTAL(port)) + 1; 1059 1060 hactive = adjusted_mode->crtc_hdisplay; 1061 hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port)); 1062 1063 /* 1064 * Meaningful for video mode non-burst sync pulse mode only, 1065 * can be zero for non-burst sync events and burst modes 1066 */ 1067 hsync = intel_de_read(display, MIPI_HSYNC_PADDING_COUNT(display, port)); 1068 hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port)); 1069 1070 /* horizontal values are in terms of high speed byte clock */ 1071 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, 1072 intel_dsi->burst_mode_ratio); 1073 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, 1074 intel_dsi->burst_mode_ratio); 1075 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, 1076 intel_dsi->burst_mode_ratio); 1077 1078 if (intel_dsi->dual_link) { 1079 hfp *= 2; 1080 hsync *= 2; 1081 hbp *= 2; 1082 } 1083 1084 /* vertical values are in terms of lines */ 1085 vfp = intel_de_read(display, MIPI_VFP_COUNT(display, port)); 1086 vbp = intel_de_read(display, MIPI_VBP_COUNT(display, port)); 1087 vsync = intel_de_read(display, MIPI_VSYNC_PADDING_COUNT(display, port)); 1088 1089 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; 1090 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; 1091 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; 1092 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1093 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1094 1095 drm_WARN_ON(display->drm, adjusted_mode->crtc_vdisplay + 1096 vfp + vsync + vbp != adjusted_mode->crtc_vtotal); 1097 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; 1098 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; 1099 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1100 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1101 1102 /* 1103 * In BXT DSI there is no regs programmed with few horizontal timings 1104 * in Pixels but txbyteclkhs.. So retrieval process adds some 1105 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. 1106 * Actually here for the given adjusted_mode, we are calculating the 1107 * value programmed to the port and then back to the horizontal timing 1108 * param in pixels. This is the expected value, including roundup errors 1109 * And if that is same as retrieved value from port, then 1110 * (HW state) adjusted_mode's horizontal timings are corrected to 1111 * match with SW state to nullify the errors. 1112 */ 1113 /* Calculating the value programmed to the Port register */ 1114 hfp_sw = adjusted_mode_sw->crtc_hsync_start - 1115 adjusted_mode_sw->crtc_hdisplay; 1116 hsync_sw = adjusted_mode_sw->crtc_hsync_end - 1117 adjusted_mode_sw->crtc_hsync_start; 1118 hbp_sw = adjusted_mode_sw->crtc_htotal - 1119 adjusted_mode_sw->crtc_hsync_end; 1120 1121 if (intel_dsi->dual_link) { 1122 hfp_sw /= 2; 1123 hsync_sw /= 2; 1124 hbp_sw /= 2; 1125 } 1126 1127 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, 1128 intel_dsi->burst_mode_ratio); 1129 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, 1130 intel_dsi->burst_mode_ratio); 1131 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, 1132 intel_dsi->burst_mode_ratio); 1133 1134 /* Reverse calculating the adjusted mode parameters from port reg vals*/ 1135 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, 1136 intel_dsi->burst_mode_ratio); 1137 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, 1138 intel_dsi->burst_mode_ratio); 1139 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, 1140 intel_dsi->burst_mode_ratio); 1141 1142 if (intel_dsi->dual_link) { 1143 hfp_sw *= 2; 1144 hsync_sw *= 2; 1145 hbp_sw *= 2; 1146 } 1147 1148 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + 1149 hsync_sw + hbp_sw; 1150 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; 1151 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; 1152 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; 1153 crtc_hblank_end_sw = crtc_htotal_sw; 1154 1155 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) 1156 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; 1157 1158 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) 1159 adjusted_mode->crtc_hsync_start = 1160 adjusted_mode_sw->crtc_hsync_start; 1161 1162 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) 1163 adjusted_mode->crtc_hsync_end = 1164 adjusted_mode_sw->crtc_hsync_end; 1165 1166 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) 1167 adjusted_mode->crtc_hblank_start = 1168 adjusted_mode_sw->crtc_hblank_start; 1169 1170 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) 1171 adjusted_mode->crtc_hblank_end = 1172 adjusted_mode_sw->crtc_hblank_end; 1173} 1174 1175static void intel_dsi_get_config(struct intel_encoder *encoder, 1176 struct intel_crtc_state *pipe_config) 1177{ 1178 struct intel_display *display = to_intel_display(encoder); 1179 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1180 u32 pclk; 1181 1182 drm_dbg_kms(display->drm, "\n"); 1183 1184 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1185 1186 if (display->platform.geminilake || display->platform.broxton) { 1187 bxt_dsi_get_pipe_config(encoder, pipe_config); 1188 pclk = bxt_dsi_get_pclk(encoder, pipe_config); 1189 } else { 1190 pclk = vlv_dsi_get_pclk(encoder, pipe_config); 1191 } 1192 1193 pipe_config->port_clock = pclk; 1194 1195 /* FIXME definitely not right for burst/cmd mode/pixel overlap */ 1196 pipe_config->hw.adjusted_mode.crtc_clock = pclk; 1197 if (intel_dsi->dual_link) 1198 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1199} 1200 1201/* return txclkesc cycles in terms of divider and duration in us */ 1202static u16 txclkesc(u32 divider, unsigned int us) 1203{ 1204 switch (divider) { 1205 case ESCAPE_CLOCK_DIVIDER_1: 1206 default: 1207 return 20 * us; 1208 case ESCAPE_CLOCK_DIVIDER_2: 1209 return 10 * us; 1210 case ESCAPE_CLOCK_DIVIDER_4: 1211 return 5 * us; 1212 } 1213} 1214 1215static void set_dsi_timings(struct intel_encoder *encoder, 1216 const struct drm_display_mode *adjusted_mode) 1217{ 1218 struct intel_display *display = to_intel_display(encoder); 1219 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1220 enum port port; 1221 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1222 unsigned int lane_count = intel_dsi->lane_count; 1223 1224 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 1225 1226 hactive = adjusted_mode->crtc_hdisplay; 1227 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; 1228 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; 1229 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; 1230 1231 if (intel_dsi->dual_link) { 1232 hactive /= 2; 1233 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1234 hactive += intel_dsi->pixel_overlap; 1235 hfp /= 2; 1236 hsync /= 2; 1237 hbp /= 2; 1238 } 1239 1240 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; 1241 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; 1242 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; 1243 1244 /* horizontal values are in terms of high speed byte clock */ 1245 hactive = txbyteclkhs(hactive, bpp, lane_count, 1246 intel_dsi->burst_mode_ratio); 1247 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1248 hsync = txbyteclkhs(hsync, bpp, lane_count, 1249 intel_dsi->burst_mode_ratio); 1250 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); 1251 1252 for_each_dsi_port(port, intel_dsi->ports) { 1253 if (display->platform.geminilake || display->platform.broxton) { 1254 /* 1255 * Program hdisplay and vdisplay on MIPI transcoder. 1256 * This is different from calculated hactive and 1257 * vactive, as they are calculated per channel basis, 1258 * whereas these values should be based on resolution. 1259 */ 1260 intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port), 1261 adjusted_mode->crtc_hdisplay); 1262 intel_de_write(display, BXT_MIPI_TRANS_VACTIVE(port), 1263 adjusted_mode->crtc_vdisplay); 1264 intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port), 1265 adjusted_mode->crtc_vtotal - 1); 1266 } 1267 1268 intel_de_write(display, MIPI_HACTIVE_AREA_COUNT(display, port), 1269 hactive); 1270 intel_de_write(display, MIPI_HFP_COUNT(display, port), hfp); 1271 1272 /* meaningful for video mode non-burst sync pulse mode only, 1273 * can be zero for non-burst sync events and burst modes */ 1274 intel_de_write(display, MIPI_HSYNC_PADDING_COUNT(display, port), 1275 hsync); 1276 intel_de_write(display, MIPI_HBP_COUNT(display, port), hbp); 1277 1278 /* vertical values are in terms of lines */ 1279 intel_de_write(display, MIPI_VFP_COUNT(display, port), vfp); 1280 intel_de_write(display, MIPI_VSYNC_PADDING_COUNT(display, port), 1281 vsync); 1282 intel_de_write(display, MIPI_VBP_COUNT(display, port), vbp); 1283 } 1284} 1285 1286static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) 1287{ 1288 switch (fmt) { 1289 case MIPI_DSI_FMT_RGB888: 1290 return VID_MODE_FORMAT_RGB888; 1291 case MIPI_DSI_FMT_RGB666: 1292 return VID_MODE_FORMAT_RGB666; 1293 case MIPI_DSI_FMT_RGB666_PACKED: 1294 return VID_MODE_FORMAT_RGB666_PACKED; 1295 case MIPI_DSI_FMT_RGB565: 1296 return VID_MODE_FORMAT_RGB565; 1297 default: 1298 MISSING_CASE(fmt); 1299 return VID_MODE_FORMAT_RGB666; 1300 } 1301} 1302 1303static void intel_dsi_prepare(struct intel_encoder *encoder, 1304 const struct intel_crtc_state *pipe_config) 1305{ 1306 struct intel_display *display = to_intel_display(encoder); 1307 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1308 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1309 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1310 enum port port; 1311 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1312 u32 val, tmp; 1313 u16 mode_hdisplay; 1314 1315 drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(crtc->pipe)); 1316 1317 mode_hdisplay = adjusted_mode->crtc_hdisplay; 1318 1319 if (intel_dsi->dual_link) { 1320 mode_hdisplay /= 2; 1321 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1322 mode_hdisplay += intel_dsi->pixel_overlap; 1323 } 1324 1325 for_each_dsi_port(port, intel_dsi->ports) { 1326 if (display->platform.valleyview || display->platform.cherryview) { 1327 /* 1328 * escape clock divider, 20MHz, shared for A and C. 1329 * device ready must be off when doing this! txclkesc? 1330 */ 1331 tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A)); 1332 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 1333 intel_de_write(display, MIPI_CTRL(display, PORT_A), 1334 tmp | ESCAPE_CLOCK_DIVIDER_1); 1335 1336 /* read request priority is per pipe */ 1337 tmp = intel_de_read(display, MIPI_CTRL(display, port)); 1338 tmp &= ~READ_REQUEST_PRIORITY_MASK; 1339 intel_de_write(display, MIPI_CTRL(display, port), 1340 tmp | READ_REQUEST_PRIORITY_HIGH); 1341 } else if (display->platform.geminilake || display->platform.broxton) { 1342 enum pipe pipe = crtc->pipe; 1343 1344 intel_de_rmw(display, MIPI_CTRL(display, port), 1345 BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe)); 1346 } 1347 1348 /* XXX: why here, why like this? handling in irq handler?! */ 1349 intel_de_write(display, MIPI_INTR_STAT(display, port), 0xffffffff); 1350 intel_de_write(display, MIPI_INTR_EN(display, port), 0xffffffff); 1351 1352 intel_de_write(display, MIPI_DPHY_PARAM(display, port), 1353 intel_dsi->dphy_reg); 1354 1355 intel_de_write(display, MIPI_DPI_RESOLUTION(display, port), 1356 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); 1357 } 1358 1359 set_dsi_timings(encoder, adjusted_mode); 1360 1361 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; 1362 if (is_cmd_mode(intel_dsi)) { 1363 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; 1364 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ 1365 } else { 1366 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; 1367 val |= pixel_format_to_reg(intel_dsi->pixel_format); 1368 } 1369 1370 tmp = 0; 1371 if (intel_dsi->eotp_pkt == 0) 1372 tmp |= EOT_DISABLE; 1373 if (intel_dsi->clock_stop) 1374 tmp |= CLOCKSTOP; 1375 1376 if (display->platform.geminilake || display->platform.broxton) { 1377 tmp |= BXT_DPHY_DEFEATURE_EN; 1378 if (!is_cmd_mode(intel_dsi)) 1379 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; 1380 } 1381 1382 for_each_dsi_port(port, intel_dsi->ports) { 1383 intel_de_write(display, MIPI_DSI_FUNC_PRG(display, port), val); 1384 1385 /* timeouts for recovery. one frame IIUC. if counter expires, 1386 * EOT and stop state. */ 1387 1388 /* 1389 * In burst mode, value greater than one DPI line Time in byte 1390 * clock (txbyteclkhs) To timeout this timer 1+ of the above 1391 * said value is recommended. 1392 * 1393 * In non-burst mode, Value greater than one DPI frame time in 1394 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1395 * said value is recommended. 1396 * 1397 * In DBI only mode, value greater than one DBI frame time in 1398 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above 1399 * said value is recommended. 1400 */ 1401 1402 if (is_vid_mode(intel_dsi) && 1403 intel_dsi->video_mode == BURST_MODE) { 1404 intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port), 1405 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1406 } else { 1407 intel_de_write(display, MIPI_HS_TX_TIMEOUT(display, port), 1408 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); 1409 } 1410 intel_de_write(display, MIPI_LP_RX_TIMEOUT(display, port), 1411 intel_dsi->lp_rx_timeout); 1412 intel_de_write(display, MIPI_TURN_AROUND_TIMEOUT(display, port), 1413 intel_dsi->turn_arnd_val); 1414 intel_de_write(display, MIPI_DEVICE_RESET_TIMER(display, port), 1415 intel_dsi->rst_timer_val); 1416 1417 /* dphy stuff */ 1418 1419 /* in terms of low power clock */ 1420 intel_de_write(display, MIPI_INIT_COUNT(display, port), 1421 txclkesc(intel_dsi->escape_clk_div, 100)); 1422 1423 if ((display->platform.geminilake || display->platform.broxton) && 1424 !intel_dsi->dual_link) { 1425 /* 1426 * BXT spec says write MIPI_INIT_COUNT for 1427 * both the ports, even if only one is 1428 * getting used. So write the other port 1429 * if not in dual link mode. 1430 */ 1431 intel_de_write(display, 1432 MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A), 1433 intel_dsi->init_count); 1434 } 1435 1436 /* recovery disables */ 1437 intel_de_write(display, MIPI_EOT_DISABLE(display, port), tmp); 1438 1439 /* in terms of low power clock */ 1440 intel_de_write(display, MIPI_INIT_COUNT(display, port), 1441 intel_dsi->init_count); 1442 1443 /* in terms of txbyteclkhs. actual high to low switch + 1444 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. 1445 * 1446 * XXX: write MIPI_STOP_STATE_STALL? 1447 */ 1448 intel_de_write(display, MIPI_HIGH_LOW_SWITCH_COUNT(display, port), 1449 intel_dsi->hs_to_lp_count); 1450 1451 /* XXX: low power clock equivalence in terms of byte clock. 1452 * the number of byte clocks occupied in one low power clock. 1453 * based on txbyteclkhs and txclkesc. 1454 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL 1455 * ) / 105.??? 1456 */ 1457 intel_de_write(display, MIPI_LP_BYTECLK(display, port), 1458 intel_dsi->lp_byte_clk); 1459 1460 if (display->platform.geminilake) { 1461 intel_de_write(display, MIPI_TLPX_TIME_COUNT(display, port), 1462 intel_dsi->lp_byte_clk); 1463 /* Shadow of DPHY reg */ 1464 intel_de_write(display, MIPI_CLK_LANE_TIMING(display, port), 1465 intel_dsi->dphy_reg); 1466 } 1467 1468 /* the bw essential for transmitting 16 long packets containing 1469 * 252 bytes meant for dcs write memory command is programmed in 1470 * this register in terms of byte clocks. based on dsi transfer 1471 * rate and the number of lanes configured the time taken to 1472 * transmit 16 long packets in a dsi stream varies. */ 1473 intel_de_write(display, MIPI_DBI_BW_CTRL(display, port), 1474 intel_dsi->bw_timer); 1475 1476 intel_de_write(display, MIPI_CLK_LANE_SWITCH_TIME_CNT(display, port), 1477 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); 1478 1479 if (is_vid_mode(intel_dsi)) { 1480 u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG; 1481 1482 /* 1483 * Some panels might have resolution which is not a 1484 * multiple of 64 like 1366 x 768. Enable RANDOM 1485 * resolution support for such panels by default. 1486 */ 1487 fmt |= RANDOM_DPI_DISPLAY_RESOLUTION; 1488 1489 switch (intel_dsi->video_mode) { 1490 default: 1491 MISSING_CASE(intel_dsi->video_mode); 1492 fallthrough; 1493 case NON_BURST_SYNC_EVENTS: 1494 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS; 1495 break; 1496 case NON_BURST_SYNC_PULSE: 1497 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE; 1498 break; 1499 case BURST_MODE: 1500 fmt |= VIDEO_MODE_BURST; 1501 break; 1502 } 1503 1504 intel_de_write(display, MIPI_VIDEO_MODE_FORMAT(display, port), fmt); 1505 } 1506 } 1507} 1508 1509static void intel_dsi_unprepare(struct intel_encoder *encoder) 1510{ 1511 struct intel_display *display = to_intel_display(encoder); 1512 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1513 enum port port; 1514 1515 if (display->platform.geminilake) 1516 return; 1517 1518 for_each_dsi_port(port, intel_dsi->ports) { 1519 /* Panel commands can be sent when clock is in LP11 */ 1520 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x0); 1521 1522 if (display->platform.geminilake || display->platform.broxton) 1523 bxt_dsi_reset_clocks(encoder, port); 1524 else 1525 vlv_dsi_reset_clocks(encoder, port); 1526 intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP); 1527 1528 intel_de_rmw(display, MIPI_DSI_FUNC_PRG(display, port), VID_MODE_FORMAT_MASK, 0); 1529 1530 intel_de_write(display, MIPI_DEVICE_READY(display, port), 0x1); 1531 } 1532} 1533 1534static const struct drm_encoder_funcs intel_dsi_funcs = { 1535 .destroy = intel_encoder_destroy, 1536}; 1537 1538static enum drm_mode_status vlv_dsi_mode_valid(struct drm_connector *connector, 1539 const struct drm_display_mode *mode) 1540{ 1541 struct intel_display *display = to_intel_display(connector->dev); 1542 1543 if (display->platform.valleyview || display->platform.cherryview) { 1544 enum drm_mode_status status; 1545 1546 status = intel_cpu_transcoder_mode_valid(display, mode); 1547 if (status != MODE_OK) 1548 return status; 1549 } 1550 1551 return intel_dsi_mode_valid(connector, mode); 1552} 1553 1554static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 1555 .get_modes = intel_dsi_get_modes, 1556 .mode_valid = vlv_dsi_mode_valid, 1557 .atomic_check = intel_digital_connector_atomic_check, 1558}; 1559 1560static const struct drm_connector_funcs intel_dsi_connector_funcs = { 1561 .detect = intel_panel_detect, 1562 .late_register = intel_connector_register, 1563 .early_unregister = intel_connector_unregister, 1564 .destroy = intel_connector_destroy, 1565 .fill_modes = drm_helper_probe_single_connector_modes, 1566 .atomic_get_property = intel_digital_connector_atomic_get_property, 1567 .atomic_set_property = intel_digital_connector_atomic_set_property, 1568 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1569 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1570}; 1571 1572static void vlv_dsi_add_properties(struct intel_connector *connector) 1573{ 1574 const struct drm_display_mode *fixed_mode = 1575 intel_panel_preferred_fixed_mode(connector); 1576 1577 intel_attach_scaling_mode_property(&connector->base); 1578 1579 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1580 intel_dsi_get_panel_orientation(connector), 1581 fixed_mode->hdisplay, 1582 fixed_mode->vdisplay); 1583} 1584 1585#define NS_KHZ_RATIO 1000000 1586 1587#define PREPARE_CNT_MAX 0x3F 1588#define EXIT_ZERO_CNT_MAX 0x3F 1589#define CLK_ZERO_CNT_MAX 0xFF 1590#define TRAIL_CNT_MAX 0x1F 1591 1592static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) 1593{ 1594 struct intel_display *display = to_intel_display(&intel_dsi->base); 1595 struct intel_connector *connector = intel_dsi->attached_connector; 1596 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1597 u32 tlpx_ns, extra_byte_count, tlpx_ui; 1598 u32 ui_num, ui_den; 1599 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1600 u32 ths_prepare_ns, tclk_trail_ns; 1601 u32 tclk_prepare_clkzero, ths_prepare_hszero; 1602 u32 lp_to_hs_switch, hs_to_lp_switch; 1603 u32 mul; 1604 1605 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1606 1607 switch (intel_dsi->lane_count) { 1608 case 1: 1609 case 2: 1610 extra_byte_count = 2; 1611 break; 1612 case 3: 1613 extra_byte_count = 4; 1614 break; 1615 case 4: 1616 default: 1617 extra_byte_count = 3; 1618 break; 1619 } 1620 1621 /* in Kbps */ 1622 ui_num = NS_KHZ_RATIO; 1623 ui_den = intel_dsi_bitrate(intel_dsi); 1624 1625 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; 1626 ths_prepare_hszero = mipi_config->ths_prepare_hszero; 1627 1628 /* 1629 * B060 1630 * LP byte clock = TLPX/ (8UI) 1631 */ 1632 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); 1633 1634 /* DDR clock period = 2 * UI 1635 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ) 1636 * UI(nsec) = 10^6 / bitrate 1637 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate 1638 * DDR clock count = ns_value / DDR clock period 1639 * 1640 * For GEMINILAKE dphy_param_reg will be programmed in terms of 1641 * HS byte clock count for other platform in HS ddr clock count 1642 */ 1643 mul = display->platform.geminilake ? 8 : 2; 1644 ths_prepare_ns = max(mipi_config->ths_prepare, 1645 mipi_config->tclk_prepare); 1646 1647 /* prepare count */ 1648 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul); 1649 1650 if (prepare_cnt > PREPARE_CNT_MAX) { 1651 drm_dbg_kms(display->drm, "prepare count too high %u\n", 1652 prepare_cnt); 1653 prepare_cnt = PREPARE_CNT_MAX; 1654 } 1655 1656 /* exit zero count */ 1657 exit_zero_cnt = DIV_ROUND_UP( 1658 (ths_prepare_hszero - ths_prepare_ns) * ui_den, 1659 ui_num * mul 1660 ); 1661 1662 /* 1663 * Exit zero is unified val ths_zero and ths_exit 1664 * minimum value for ths_exit = 110ns 1665 * min (exit_zero_cnt * 2) = 110/UI 1666 * exit_zero_cnt = 55/UI 1667 */ 1668 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num) 1669 exit_zero_cnt += 1; 1670 1671 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) { 1672 drm_dbg_kms(display->drm, "exit zero count too high %u\n", 1673 exit_zero_cnt); 1674 exit_zero_cnt = EXIT_ZERO_CNT_MAX; 1675 } 1676 1677 /* clk zero count */ 1678 clk_zero_cnt = DIV_ROUND_UP( 1679 (tclk_prepare_clkzero - ths_prepare_ns) 1680 * ui_den, ui_num * mul); 1681 1682 if (clk_zero_cnt > CLK_ZERO_CNT_MAX) { 1683 drm_dbg_kms(display->drm, "clock zero count too high %u\n", 1684 clk_zero_cnt); 1685 clk_zero_cnt = CLK_ZERO_CNT_MAX; 1686 } 1687 1688 /* trail count */ 1689 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1690 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul); 1691 1692 if (trail_cnt > TRAIL_CNT_MAX) { 1693 drm_dbg_kms(display->drm, "trail count too high %u\n", 1694 trail_cnt); 1695 trail_cnt = TRAIL_CNT_MAX; 1696 } 1697 1698 /* B080 */ 1699 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | 1700 clk_zero_cnt << 8 | prepare_cnt; 1701 1702 /* 1703 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT * 1704 * mul + 10UI + Extra Byte Count 1705 * 1706 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count 1707 * Extra Byte Count is calculated according to number of lanes. 1708 * High Low Switch Count is the Max of LP to HS and 1709 * HS to LP switch count 1710 * 1711 */ 1712 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); 1713 1714 /* B044 */ 1715 /* FIXME: 1716 * The comment above does not match with the code */ 1717 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul + 1718 exit_zero_cnt * mul + 10, 8); 1719 1720 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); 1721 1722 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); 1723 intel_dsi->hs_to_lp_count += extra_byte_count; 1724 1725 /* B088 */ 1726 /* LP -> HS for clock lanes 1727 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + 1728 * extra byte count 1729 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * 1730 * 2(in UI) + extra byte count 1731 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / 1732 * 8 + extra byte count 1733 */ 1734 intel_dsi->clk_lp_to_hs_count = 1735 DIV_ROUND_UP( 1736 4 * tlpx_ui + prepare_cnt * 2 + 1737 clk_zero_cnt * 2, 1738 8); 1739 1740 intel_dsi->clk_lp_to_hs_count += extra_byte_count; 1741 1742 /* HS->LP for Clock Lanes 1743 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + 1744 * Extra byte count 1745 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count 1746 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + 1747 * Extra byte count 1748 */ 1749 intel_dsi->clk_hs_to_lp_count = 1750 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, 1751 8); 1752 intel_dsi->clk_hs_to_lp_count += extra_byte_count; 1753 1754 intel_dsi_log_params(intel_dsi); 1755} 1756 1757int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state) 1758{ 1759 struct intel_display *display = to_intel_display(crtc_state); 1760 1761 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1762 return 0; 1763 1764 /* 1765 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 1766 * than 320000KHz. 1767 */ 1768 if (display->platform.valleyview) 1769 return 320000; 1770 1771 /* 1772 * On Geminilake once the CDCLK gets as low as 79200 1773 * picture gets unstable, despite that values are 1774 * correct for DSI PLL and DE PLL. 1775 */ 1776 if (display->platform.geminilake) 1777 return 158400; 1778 1779 return 0; 1780} 1781 1782typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi); 1783 1784/* 1785 * Vtotal is wrong on the Asus TF103C leading to the last line of the display 1786 * being shown as the first line. The factory installed Android has a hardcoded 1787 * modeline, causing it to not suffer from this BIOS bug. 1788 * 1789 * Original mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 820 0x8 0xa 1790 * Fixed mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 816 0x8 0xa 1791 * 1792 * https://gitlab.freedesktop.org/drm/intel/-/issues/9381 1793 */ 1794static void vlv_dsi_asus_tf103c_mode_fixup(struct intel_dsi *intel_dsi) 1795{ 1796 /* Cast away the const as we want to fixup the mode */ 1797 struct drm_display_mode *fixed_mode = (struct drm_display_mode *) 1798 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector); 1799 1800 if (fixed_mode->vtotal == 820) 1801 fixed_mode->vtotal -= 4; 1802} 1803 1804/* 1805 * On the Lenovo Yoga Tablet 2 830 / 1050 there are 2 problems: 1806 * 1. The I2C MIPI sequence elements reference bus 3. ACPI has I2C1 - I2C7 1807 * which under Linux become bus 0 - 6. And the MIPI sequence reference 1808 * to bus 3 is indented for I2C3 which is bus 2 under Linux. 1809 * 1810 * Note mipi_exec_i2c() cannot just subtract 1 from the bus 1811 * given in the I2C MIPI sequence element. Since on other 1812 * devices the I2C bus-numbers used in the MIPI sequences do 1813 * actually start at 0. 1814 * 1815 * 2. width_/height_mm contain a bogus 192mm x 120mm size. This is 1816 * especially a problem on the 8" 830 version which uses a 10:16 1817 * portrait screen where as the bogus size is 16:10. 1818 * 1819 * https://gitlab.freedesktop.org/drm/intel/-/issues/9379 1820 */ 1821static void vlv_dsi_lenovo_yoga_tab2_size_fixup(struct intel_dsi *intel_dsi) 1822{ 1823 const struct drm_display_mode *fixed_mode = 1824 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector); 1825 struct drm_display_info *info = &intel_dsi->attached_connector->base.display_info; 1826 1827 intel_dsi->i2c_bus_num = 2; 1828 1829 /* 1830 * The 10" 1050 uses a 1920x1200 landscape screen, where as the 8" 830 1831 * uses a 1200x1920 portrait screen. 1832 */ 1833 if (fixed_mode->hdisplay == 1920) { 1834 info->width_mm = 216; 1835 info->height_mm = 135; 1836 } else { 1837 info->width_mm = 107; 1838 info->height_mm = 171; 1839 } 1840} 1841 1842/* 1843 * On the Lenovo Yoga Tab 3 Pro YT3-X90F there are 2 problems: 1844 * 1. i2c_acpi_find_adapter() picks the wrong adapter causing mipi_exec_i2c() 1845 * to not work. Fix this by setting i2c_bus_num. 1846 * 2. There is no backlight off MIPI sequence, causing the backlight to stay on. 1847 * Add a backlight off sequence mirroring the existing backlight on sequence. 1848 * 1849 * https://gitlab.freedesktop.org/drm/intel/-/issues/9380 1850 */ 1851static void vlv_dsi_lenovo_yoga_tab3_backlight_fixup(struct intel_dsi *intel_dsi) 1852{ 1853 static const u8 backlight_off_sequence[16] = { 1854 /* Header Seq-id 7, length after header 11 bytes */ 1855 0x07, 0x0b, 0x00, 0x00, 0x00, 1856 /* MIPI_SEQ_ELEM_I2C bus 0 addr 0x2c reg 0x00 data-len 1 data 0x00 */ 1857 0x04, 0x08, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x01, 0x00, 1858 /* MIPI_SEQ_ELEM_END */ 1859 0x00 1860 }; 1861 struct intel_connector *connector = intel_dsi->attached_connector; 1862 1863 intel_dsi->i2c_bus_num = 0; 1864 connector->panel.vbt.dsi.sequence[MIPI_SEQ_BACKLIGHT_OFF] = backlight_off_sequence; 1865} 1866 1867static const struct dmi_system_id vlv_dsi_dmi_quirk_table[] = { 1868 { 1869 /* Asus Transformer Pad TF103C */ 1870 .matches = { 1871 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."), 1872 DMI_MATCH(DMI_PRODUCT_NAME, "TF103C"), 1873 }, 1874 .driver_data = (void *)vlv_dsi_asus_tf103c_mode_fixup, 1875 }, 1876 { 1877 /* 1878 * Lenovo Yoga Tablet 2 830F/L or 1050F/L (The 8" and 10" 1879 * Lenovo Yoga Tablet 2 use the same mainboard) 1880 */ 1881 .matches = { 1882 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp."), 1883 DMI_MATCH(DMI_PRODUCT_NAME, "VALLEYVIEW C0 PLATFORM"), 1884 DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"), 1885 /* Partial match on beginning of BIOS version */ 1886 DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21"), 1887 }, 1888 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab2_size_fixup, 1889 }, 1890 { 1891 /* Lenovo Yoga Tab 3 Pro YT3-X90F */ 1892 .matches = { 1893 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"), 1894 DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"), 1895 }, 1896 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab3_backlight_fixup, 1897 }, 1898 { } 1899}; 1900 1901void vlv_dsi_init(struct intel_display *display) 1902{ 1903 struct intel_dsi *intel_dsi; 1904 struct intel_encoder *encoder; 1905 struct intel_connector *connector; 1906 struct drm_display_mode *current_mode; 1907 const struct dmi_system_id *dmi_id; 1908 enum port port; 1909 enum pipe pipe; 1910 1911 drm_dbg_kms(display->drm, "\n"); 1912 1913 /* There is no detection method for MIPI so rely on VBT */ 1914 if (!intel_bios_is_dsi_present(display, &port)) 1915 return; 1916 1917 if (display->platform.geminilake || display->platform.broxton) 1918 display->dsi.mmio_base = BXT_MIPI_BASE; 1919 else 1920 display->dsi.mmio_base = VLV_MIPI_BASE; 1921 1922 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1923 if (!intel_dsi) 1924 return; 1925 1926 connector = intel_connector_alloc(); 1927 if (!connector) { 1928 kfree(intel_dsi); 1929 return; 1930 } 1931 1932 encoder = &intel_dsi->base; 1933 intel_dsi->attached_connector = connector; 1934 1935 drm_encoder_init(display->drm, &encoder->base, &intel_dsi_funcs, 1936 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 1937 1938 encoder->compute_config = intel_dsi_compute_config; 1939 encoder->pre_enable = intel_dsi_pre_enable; 1940 if (display->platform.geminilake || display->platform.broxton) 1941 encoder->enable = bxt_dsi_enable; 1942 encoder->disable = intel_dsi_disable; 1943 encoder->post_disable = intel_dsi_post_disable; 1944 encoder->get_hw_state = intel_dsi_get_hw_state; 1945 encoder->get_config = intel_dsi_get_config; 1946 encoder->update_pipe = intel_backlight_update; 1947 encoder->shutdown = intel_dsi_shutdown; 1948 1949 connector->get_hw_state = intel_connector_get_hw_state; 1950 1951 encoder->port = port; 1952 encoder->type = INTEL_OUTPUT_DSI; 1953 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1954 encoder->cloneable = 0; 1955 1956 /* 1957 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI 1958 * port C. BXT isn't limited like this. 1959 */ 1960 if (display->platform.geminilake || display->platform.broxton) 1961 encoder->pipe_mask = ~0; 1962 else if (port == PORT_A) 1963 encoder->pipe_mask = BIT(PIPE_A); 1964 else 1965 encoder->pipe_mask = BIT(PIPE_B); 1966 1967 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1968 1969 intel_bios_init_panel_late(display, &connector->panel, NULL, NULL); 1970 1971 if (connector->panel.vbt.dsi.config->dual_link) 1972 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); 1973 else 1974 intel_dsi->ports = BIT(port); 1975 1976 if (drm_WARN_ON(display->drm, connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 1977 connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 1978 1979 if (drm_WARN_ON(display->drm, connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 1980 connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 1981 1982 /* Create a DSI host (and a device) for each port. */ 1983 for_each_dsi_port(port, intel_dsi->ports) { 1984 struct intel_dsi_host *host; 1985 1986 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops, 1987 port); 1988 if (!host) 1989 goto err; 1990 1991 intel_dsi->dsi_hosts[port] = host; 1992 } 1993 1994 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1995 drm_dbg_kms(display->drm, "no device found\n"); 1996 goto err; 1997 } 1998 1999 /* Use clock read-back from current hw-state for fastboot */ 2000 current_mode = intel_encoder_current_mode(encoder); 2001 if (current_mode) { 2002 drm_dbg_kms(display->drm, "Calculated pclk %d GOP %d\n", 2003 intel_dsi->pclk, current_mode->clock); 2004 if (intel_fuzzy_clock_check(intel_dsi->pclk, 2005 current_mode->clock)) { 2006 drm_dbg_kms(display->drm, "Using GOP pclk\n"); 2007 intel_dsi->pclk = current_mode->clock; 2008 } 2009 2010 kfree(current_mode); 2011 } 2012 2013 vlv_dphy_param_init(intel_dsi); 2014 2015 intel_dsi_vbt_gpio_init(intel_dsi, 2016 intel_dsi_get_hw_state(encoder, &pipe)); 2017 2018 drm_connector_init(display->drm, &connector->base, &intel_dsi_connector_funcs, 2019 DRM_MODE_CONNECTOR_DSI); 2020 2021 drm_connector_helper_add(&connector->base, &intel_dsi_connector_helper_funcs); 2022 2023 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ 2024 2025 intel_connector_attach_encoder(connector, encoder); 2026 2027 mutex_lock(&display->drm->mode_config.mutex); 2028 intel_panel_add_vbt_lfp_fixed_mode(connector); 2029 mutex_unlock(&display->drm->mode_config.mutex); 2030 2031 if (!intel_panel_preferred_fixed_mode(connector)) { 2032 drm_dbg_kms(display->drm, "no fixed mode\n"); 2033 goto err_cleanup_connector; 2034 } 2035 2036 dmi_id = dmi_first_match(vlv_dsi_dmi_quirk_table); 2037 if (dmi_id) { 2038 vlv_dsi_dmi_quirk_func quirk_func = 2039 (vlv_dsi_dmi_quirk_func)dmi_id->driver_data; 2040 2041 quirk_func(intel_dsi); 2042 } 2043 2044 intel_panel_init(connector, NULL); 2045 2046 intel_backlight_setup(connector, INVALID_PIPE); 2047 2048 vlv_dsi_add_properties(connector); 2049 2050 return; 2051 2052err_cleanup_connector: 2053 drm_connector_cleanup(&connector->base); 2054err: 2055 drm_encoder_cleanup(&encoder->base); 2056 kfree(intel_dsi); 2057 kfree(connector); 2058}
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