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intel_vbt_defs.h
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linux-6.19.14/drivers/gpu/drm/i915/display/intel_vbt_defs.h
1/* 2 * Copyright © 2006-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28/* 29 * This information is private to VBT parsing in intel_bios.c. 30 * 31 * Please do NOT include anywhere else. 32 */ 33#ifndef _INTEL_BIOS_PRIVATE 34#error "intel_vbt_defs.h is private to intel_bios.c" 35#endif 36 37#ifndef _INTEL_VBT_DEFS_H_ 38#define _INTEL_VBT_DEFS_H_ 39 40#include "intel_dsi_vbt_defs.h" 41 42/* EDID derived structures */ 43struct bdb_edid_pnp_id { 44 u16 mfg_name; 45 u16 product_code; 46 u32 serial; 47 u8 mfg_week; 48 u8 mfg_year; 49} __packed; 50 51struct bdb_edid_product_name { 52 char name[13]; 53} __packed; 54 55struct bdb_edid_dtd { 56 u16 clock; /**< In 10khz */ 57 u8 hactive_lo; 58 u8 hblank_lo; 59 u8 hblank_hi:4; 60 u8 hactive_hi:4; 61 u8 vactive_lo; 62 u8 vblank_lo; 63 u8 vblank_hi:4; 64 u8 vactive_hi:4; 65 u8 hsync_off_lo; 66 u8 hsync_pulse_width_lo; 67 u8 vsync_pulse_width_lo:4; 68 u8 vsync_off_lo:4; 69 u8 vsync_pulse_width_hi:2; 70 u8 vsync_off_hi:2; 71 u8 hsync_pulse_width_hi:2; 72 u8 hsync_off_hi:2; 73 u8 himage_lo; 74 u8 vimage_lo; 75 u8 vimage_hi:4; 76 u8 himage_hi:4; 77 u8 h_border; 78 u8 v_border; 79 u8 rsvd1:3; 80 u8 digital:2; 81 u8 vsync_positive:1; 82 u8 hsync_positive:1; 83 u8 non_interlaced:1; 84} __packed; 85 86/** 87 * struct vbt_header - VBT Header structure 88 * @signature: VBT signature, always starts with "$VBT" 89 * @version: Version of this structure 90 * @header_size: Size of this structure 91 * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks) 92 * @vbt_checksum: Checksum 93 * @reserved0: Reserved 94 * @bdb_offset: Offset of &struct bdb_header from beginning of VBT 95 * @aim_offset: Offsets of add-in data blocks from beginning of VBT 96 */ 97struct vbt_header { 98 u8 signature[20]; 99 u16 version; 100 u16 header_size; 101 u16 vbt_size; 102 u8 vbt_checksum; 103 u8 reserved0; 104 u32 bdb_offset; 105 u32 aim_offset[4]; 106} __packed; 107 108/** 109 * struct bdb_header - BDB Header structure 110 * @signature: BDB signature "BIOS_DATA_BLOCK" 111 * @version: Version of the data block definitions 112 * @header_size: Size of this structure 113 * @bdb_size: Size of BDB (BDB Header and data blocks) 114 */ 115struct bdb_header { 116 u8 signature[16]; 117 u16 version; 118 u16 header_size; 119 u16 bdb_size; 120} __packed; 121 122/* 123 * BDB version number dependencies are documented as: 124 * 125 * <start>+ 126 * indicates the field was introduced in version <start> 127 * and is still valid 128 * 129 * <start>-<end> 130 * indicates the field was introduced in version <start> 131 * and obsoleted in version <end>+1. 132 * 133 * ??? indicates the specific version number is unknown 134 */ 135 136/* 137 * There are several types of BIOS data blocks (BDBs), each block has 138 * an ID and size in the first 3 bytes (ID in first, size in next 2). 139 * Known types are listed below. 140 */ 141enum bdb_block_id { 142 BDB_GENERAL_FEATURES = 1, 143 BDB_GENERAL_DEFINITIONS = 2, 144 BDB_DISPLAY_TOGGLE = 3, 145 BDB_MODE_SUPPORT_LIST = 4, 146 BDB_GENERIC_MODE_TABLE = 5, 147 BDB_EXT_MMIO_REGS = 6, /* VBIOS only */ 148 BDB_SWF_IO = 7, /* VBIOS only */ 149 BDB_SWF_MMIO = 8, /* VBIOS only */ 150 BDB_DOT_CLOCK_OVERRIDE_ALM = 9, 151 BDB_PSR = 9, /* 165+ */ 152 BDB_MODE_REMOVAL_TABLE = 10, 153 BDB_CHILD_DEVICE_TABLE = 11, 154 BDB_DRIVER_FEATURES = 12, 155 BDB_DRIVER_PERSISTENCE = 13, 156 BDB_EXT_TABLE_PTRS = 14, /* VBIOS only */ 157 BDB_DOT_CLOCK_OVERRIDE = 15, 158 BDB_DISPLAY_SELECT_OLD = 16, 159 BDB_SV_TEST_FUNCTIONS = 17, 160 BDB_DRIVER_ROTATION = 18, 161 BDB_DISPLAY_REMOVE_OLD = 19, 162 BDB_OEM_CUSTOM = 20, 163 BDB_EFP_LIST = 21, /* workarounds for VGA hsync/vsync */ 164 BDB_SDVO_LVDS_OPTIONS = 22, 165 BDB_SDVO_LVDS_DTD = 23, 166 BDB_SDVO_LVDS_PNP_ID = 24, 167 BDB_SDVO_LVDS_PPS = 25, 168 BDB_TV_OPTIONS = 26, 169 BDB_EDP = 27, 170 BDB_EFP_DTD = 28, /* 161+ */ 171 BDB_DISPLAY_SELECT_IVB = 29, /* 164+ */ 172 BDB_DISPLAY_REMOVE_IVB = 30, /* 164+ */ 173 BDB_DISPLAY_SELECT_HSW = 31, /* 166+ */ 174 BDB_DISPLAY_REMOVE_HSW = 32, /* 166+ */ 175 BDB_LFP_OPTIONS = 40, 176 BDB_LFP_DATA_PTRS = 41, 177 BDB_LFP_DATA = 42, 178 BDB_LFP_BACKLIGHT = 43, 179 BDB_LFP_POWER = 44, 180 BDB_EDP_BFI = 45, /* 160+ */ 181 BDB_CHROMATICITY = 46, /* 169+ */ 182 BDB_MIPI = 50, /* 170-172 */ 183 BDB_FIXED_SET_MODE = 51, /* 172+ */ 184 BDB_MIPI_CONFIG = 52, /* 175+ */ 185 BDB_MIPI_SEQUENCE = 53, /* 177+ */ 186 BDB_RGB_PALETTE = 54, /* 180+ */ 187 BDB_COMPRESSION_PARAMETERS_OLD = 55, /* 198-212 */ 188 BDB_COMPRESSION_PARAMETERS = 56, /* 213+ */ 189 BDB_VSWING_PREEMPH = 57, /* 218+ */ 190 BDB_GENERIC_DTD = 58, /* 229+ */ 191 BDB_INT15_HOOK = 252, /* VBIOS only */ 192 BDB_PRD_TABLE = 253, 193 BDB_SKIP = 254, /* VBIOS only */ 194}; 195 196/* 197 * Block 1 - General Bit Definitions 198 */ 199 200struct bdb_general_features { 201 /* bits 1 */ 202 u8 panel_fitting:2; 203 u8 flexaim:1; 204 u8 msg_enable:1; 205 u8 clear_screen:3; 206 u8 color_flip:1; 207 208 /* bits 2 */ 209 u8 download_ext_vbt:1; 210 u8 enable_ssc:1; 211 u8 ssc_freq:1; 212 u8 enable_lfp_on_override:1; 213 u8 disable_ssc_ddt:1; 214 u8 underscan_vga_timings:1; 215 u8 display_clock_mode:1; 216 u8 vbios_hotplug_support:1; 217 218 /* bits 3 */ 219 u8 disable_smooth_vision:1; 220 u8 single_dvi:1; 221 u8 rotate_180:1; /* 181+ */ 222 u8 fdi_rx_polarity_inverted:1; 223 u8 vbios_extended_mode:1; /* 160+ */ 224 u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160+ */ 225 u8 panel_best_fit_timing:1; /* 160+ */ 226 u8 ignore_strap_state:1; /* 160+ */ 227 228 /* bits 4 */ 229 u8 legacy_monitor_detect; 230 231 /* bits 5 */ 232 u8 int_crt_support:1; 233 u8 int_tv_support:1; 234 u8 int_efp_support:1; 235 u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */ 236 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ 237 u8 dp_ssc_dongle_supported:1; 238 u8 rsvd11:2; /* finish byte */ 239 240 /* bits 6 */ 241 u8 tc_hpd_retry_timeout:7; /* 242+ */ 242 u8 rsvd12:1; 243 244 /* bits 7 */ 245 u8 afc_startup_config:2; /* 249+ */ 246 u8 rsvd13:6; 247} __packed; 248 249/* 250 * Block 2 - General Bytes Definition 251 */ 252 253/* pre-915 */ 254#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ 255#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ 256#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ 257#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ 258 259/* Device handle */ 260#define DEVICE_HANDLE_CRT 0x0001 261#define DEVICE_HANDLE_TV 0x0002 /* ???-214 */ 262#define DEVICE_HANDLE_EFP1 0x0004 263#define DEVICE_HANDLE_EFP2 0x0040 264#define DEVICE_HANDLE_EFP3 0x0020 265#define DEVICE_HANDLE_EFP4 0x0010 266#define DEVICE_HANDLE_EFP5 0x0002 /* 215+ */ 267#define DEVICE_HANDLE_EFP6 0x0001 /* 217+ */ 268#define DEVICE_HANDLE_EFP7 0x0100 /* 217+ */ 269#define DEVICE_HANDLE_EFP8 0x0200 /* 217+ */ 270#define DEVICE_HANDLE_LFP1 0x0008 271#define DEVICE_HANDLE_LFP2 0x0080 272 273/* Pre 915 */ 274#define DEVICE_TYPE_NONE 0x00 275#define DEVICE_TYPE_CRT 0x01 276#define DEVICE_TYPE_TV 0x09 277#define DEVICE_TYPE_EFP 0x12 278#define DEVICE_TYPE_LFP 0x22 279/* On 915+ */ 280#define DEVICE_TYPE_CRT_DPMS 0x6001 281#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 282#define DEVICE_TYPE_TV_COMPOSITE 0x0209 283#define DEVICE_TYPE_TV_MACROVISION 0x0289 284#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c 285#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 286#define DEVICE_TYPE_TV_SCART 0x0209 287#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 288#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 289#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 290#define DEVICE_TYPE_EFP_DVI_I 0x6053 291#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 292#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 293#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 294#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 295#define DEVICE_TYPE_LFP_PANELLINK 0x5012 296#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 297#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 298#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 299#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 300 301/* Add the device class for LFP, TV, HDMI */ 302#define DEVICE_TYPE_INT_LFP 0x1022 303#define DEVICE_TYPE_INT_TV 0x1009 304#define DEVICE_TYPE_HDMI 0x60D2 305#define DEVICE_TYPE_DP 0x68C6 306#define DEVICE_TYPE_DP_DUAL_MODE 0x60D6 307#define DEVICE_TYPE_eDP 0x78C6 308 309#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) 310#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) 311#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) 312#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) 313#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) 314#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) 315#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) 316#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) 317#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) 318#define DEVICE_TYPE_LVDS_SIGNALING (1 << 5) 319#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) 320#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) 321#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) 322#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) 323#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) 324 325#define DEVICE_CFG_NONE 0x00 326#define DEVICE_CFG_12BIT_DVOB 0x01 327#define DEVICE_CFG_12BIT_DVOC 0x02 328#define DEVICE_CFG_24BIT_DVOBC 0x09 329#define DEVICE_CFG_24BIT_DVOCB 0x0a 330#define DEVICE_CFG_DUAL_DVOB 0x11 331#define DEVICE_CFG_DUAL_DVOC 0x12 332#define DEVICE_CFG_DUAL_DVOBC 0x13 333#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 334#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a 335 336#define DEVICE_WIRE_NONE 0x00 337#define DEVICE_WIRE_DVOB 0x01 338#define DEVICE_WIRE_DVOC 0x02 339#define DEVICE_WIRE_DVOBC 0x03 340#define DEVICE_WIRE_DVOBB 0x05 341#define DEVICE_WIRE_DVOCC 0x06 342#define DEVICE_WIRE_DVOB_MASTER 0x0d 343#define DEVICE_WIRE_DVOC_MASTER 0x0e 344 345/* dvo_port pre BDB 155 */ 346#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ 347#define DEVICE_PORT_DVOB 0x01 348#define DEVICE_PORT_DVOC 0x02 349 350/* dvo_port BDB 155+ */ 351#define DVO_PORT_HDMIA 0 352#define DVO_PORT_HDMIB 1 353#define DVO_PORT_HDMIC 2 354#define DVO_PORT_HDMID 3 355#define DVO_PORT_LVDS 4 356#define DVO_PORT_TV 5 357#define DVO_PORT_CRT 6 358#define DVO_PORT_DPB 7 359#define DVO_PORT_DPC 8 360#define DVO_PORT_DPD 9 361#define DVO_PORT_DPA 10 362#define DVO_PORT_DPE 11 /* 193+ */ 363#define DVO_PORT_HDMIE 12 /* 193+ */ 364#define DVO_PORT_DPF 13 /* N/A */ 365#define DVO_PORT_HDMIF 14 /* N/A */ 366#define DVO_PORT_DPG 15 /* 217+ */ 367#define DVO_PORT_HDMIG 16 /* 217+ */ 368#define DVO_PORT_DPH 17 /* 217+ */ 369#define DVO_PORT_HDMIH 18 /* 217+ */ 370#define DVO_PORT_DPI 19 /* 217+ */ 371#define DVO_PORT_HDMII 20 /* 217+ */ 372#define DVO_PORT_MIPIA 21 /* 171+ */ 373#define DVO_PORT_MIPIB 22 /* 171+ */ 374#define DVO_PORT_MIPIC 23 /* 171+ */ 375#define DVO_PORT_MIPID 24 /* 171+ */ 376 377#define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204+ */ 378#define HDMI_MAX_DATA_RATE_297 1 /* 204+ */ 379#define HDMI_MAX_DATA_RATE_165 2 /* 204+ */ 380#define HDMI_MAX_DATA_RATE_594 3 /* 249+ */ 381#define HDMI_MAX_DATA_RATE_340 4 /* 249+ */ 382#define HDMI_MAX_DATA_RATE_300 5 /* 249+ */ 383 384#define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33 385 386/* DDC Bus DDI Type 155+ */ 387enum vbt_gmbus_ddi { 388 DDC_BUS_DDI_B = 0x1, 389 DDC_BUS_DDI_C, 390 DDC_BUS_DDI_D, 391 DDC_BUS_DDI_F, 392 ICL_DDC_BUS_DDI_A = 0x1, 393 ICL_DDC_BUS_DDI_B, 394 TGL_DDC_BUS_DDI_C, 395 RKL_DDC_BUS_DDI_D = 0x3, 396 RKL_DDC_BUS_DDI_E, 397 ICL_DDC_BUS_PORT_1 = 0x4, 398 ICL_DDC_BUS_PORT_2, 399 ICL_DDC_BUS_PORT_3, 400 ICL_DDC_BUS_PORT_4, 401 TGL_DDC_BUS_PORT_5, 402 TGL_DDC_BUS_PORT_6, 403 ADLS_DDC_BUS_PORT_TC1 = 0x2, 404 ADLS_DDC_BUS_PORT_TC2, 405 ADLS_DDC_BUS_PORT_TC3, 406 ADLS_DDC_BUS_PORT_TC4, 407 ADLP_DDC_BUS_PORT_TC1 = 0x3, 408 ADLP_DDC_BUS_PORT_TC2, 409 ADLP_DDC_BUS_PORT_TC3, 410 ADLP_DDC_BUS_PORT_TC4 411 412}; 413 414#define DP_AUX_A 0x40 415#define DP_AUX_B 0x10 416#define DP_AUX_C 0x20 417#define DP_AUX_D 0x30 418#define DP_AUX_E 0x50 419#define DP_AUX_F 0x60 420#define DP_AUX_G 0x70 421#define DP_AUX_H 0x80 422#define DP_AUX_I 0x90 423 424/* DP max link rate 216+ */ 425#define BDB_216_VBT_DP_MAX_LINK_RATE_HBR3 0 426#define BDB_216_VBT_DP_MAX_LINK_RATE_HBR2 1 427#define BDB_216_VBT_DP_MAX_LINK_RATE_HBR 2 428#define BDB_216_VBT_DP_MAX_LINK_RATE_LBR 3 429 430/* DP max link rate 230+ */ 431#define BDB_230_VBT_DP_MAX_LINK_RATE_DEF 0 432#define BDB_230_VBT_DP_MAX_LINK_RATE_LBR 1 433#define BDB_230_VBT_DP_MAX_LINK_RATE_HBR 2 434#define BDB_230_VBT_DP_MAX_LINK_RATE_HBR2 3 435#define BDB_230_VBT_DP_MAX_LINK_RATE_HBR3 4 436#define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR10 5 437#define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR13P5 6 438#define BDB_230_VBT_DP_MAX_LINK_RATE_UHBR20 7 439 440/* EDP link rate 263+ */ 441#define BDB_263_VBT_EDP_LINK_RATE_1_62 BIT_U32(0) 442#define BDB_263_VBT_EDP_LINK_RATE_2_16 BIT_U32(1) 443#define BDB_263_VBT_EDP_LINK_RATE_2_43 BIT_U32(2) 444#define BDB_263_VBT_EDP_LINK_RATE_2_7 BIT_U32(3) 445#define BDB_263_VBT_EDP_LINK_RATE_3_24 BIT_U32(4) 446#define BDB_263_VBT_EDP_LINK_RATE_4_32 BIT_U32(5) 447#define BDB_263_VBT_EDP_LINK_RATE_5_4 BIT_U32(6) 448#define BDB_263_VBT_EDP_LINK_RATE_6_75 BIT_U32(7) 449#define BDB_263_VBT_EDP_LINK_RATE_8_1 BIT_U32(8) 450#define BDB_263_VBT_EDP_LINK_RATE_10 BIT_U32(9) 451#define BDB_263_VBT_EDP_LINK_RATE_13_5 BIT_U32(10) 452#define BDB_263_VBT_EDP_LINK_RATE_20 BIT_U32(11) 453#define BDB_263_VBT_EDP_NUM_RATES 12 454#define BDB_263_VBT_EDP_RATES_MASK GENMASK(BDB_263_VBT_EDP_NUM_RATES - 1, 0) 455 456/* 457 * The child device config, aka the display device data structure, provides a 458 * description of a port and its configuration on the platform. 459 * 460 * The child device config size has been increased, and fields have been added 461 * and their meaning has changed over time. Care must be taken when accessing 462 * basically any of the fields to ensure the correct interpretation for the BDB 463 * version in question. 464 * 465 * When we copy the child device configs to display->vbt.child_dev, we 466 * reserve space for the full structure below, and initialize the tail not 467 * actually present in VBT to zeros. Accessing those fields is fine, as long as 468 * the default zero is taken into account, again according to the BDB version. 469 * 470 * BDB versions 155 and below are considered legacy, and version 155 seems to be 471 * a baseline for some of the VBT documentation. When adding new fields, please 472 * include the BDB version when the field was added, if it's above that. 473 */ 474struct child_device_config { 475 u16 handle; 476 u16 device_type; /* See DEVICE_TYPE_* above */ 477 478 union { 479 u8 device_id[10]; /* ascii string */ 480 struct { 481 u8 i2c_speed; 482 u8 dp_onboard_redriver_preemph:3; /* 158+ */ 483 u8 dp_onboard_redriver_vswing:3; /* 158+ */ 484 u8 dp_onboard_redriver_present:1; /* 158+ */ 485 u8 reserved0:1; 486 u8 dp_ondock_redriver_preemph:3; /* 158+ */ 487 u8 dp_ondock_redriver_vswing:3; /* 158+ */ 488 u8 dp_ondock_redriver_present:1; /* 158+ */ 489 u8 reserved1:1; 490 u8 hdmi_level_shifter_value:5; /* 158+ */ 491 u8 hdmi_max_data_rate:3; /* 204+ */ 492 u16 dtd_buf_ptr; /* 161+ */ 493 u8 edidless_efp:1; /* 161+ */ 494 u8 compression_enable:1; /* 198+ */ 495 u8 compression_method_cps:1; /* 198+ */ 496 u8 ganged_edp:1; /* 202+ */ 497 u8 lttpr_non_transparent:1; /* 235+ */ 498 u8 disable_compression_for_ext_disp:1; /* 251+ */ 499 u8 reserved2:2; 500 u8 compression_structure_index:4; /* 198+ */ 501 u8 reserved3:4; 502 u8 hdmi_max_frl_rate:4; /* 237+ */ 503 u8 hdmi_max_frl_rate_valid:1; /* 237+ */ 504 u8 reserved4:3; /* 237+ */ 505 u8 reserved5; 506 } __packed; 507 } __packed; 508 509 u16 addin_offset; 510 u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */ 511 u8 i2c_pin; 512 u8 target_addr; 513 u8 ddc_pin; 514 u16 edid_ptr; 515 u8 dvo_cfg; /* See DEVICE_CFG_* above */ 516 517 union { 518 struct { 519 u8 dvo2_port; 520 u8 i2c2_pin; 521 u8 target2_addr; 522 u8 ddc2_pin; 523 } __packed; 524 struct { 525 u8 efp_routed:1; /* 158+ */ 526 u8 lane_reversal:1; /* 184+ */ 527 u8 lspcon:1; /* 192+ */ 528 u8 iboost:1; /* 196+ */ 529 u8 hpd_invert:1; /* 196+ */ 530 u8 use_vbt_vswing:1; /* 218+ */ 531 u8 dp_max_lane_count:2; /* 244+ */ 532 u8 hdmi_support:1; /* 158+ */ 533 u8 dp_support:1; /* 158+ */ 534 u8 tmds_support:1; /* 158+ */ 535 u8 support_reserved:5; 536 u8 aux_channel; 537 u8 dongle_detect; 538 } __packed; 539 } __packed; 540 541 u8 pipe_cap:2; 542 u8 sdvo_stall:1; /* 158+ */ 543 u8 hpd_status:2; 544 u8 integrated_encoder:1; 545 u8 capabilities_reserved:2; 546 u8 dvo_wiring; /* See DEVICE_WIRE_* above */ 547 548 union { 549 u8 dvo2_wiring; 550 u8 mipi_bridge_type; /* 171+ */ 551 } __packed; 552 553 u16 extended_type; 554 u8 dvo_function; 555 u8 dp_usb_type_c:1; /* 195+ */ 556 u8 tbt:1; /* 209+ */ 557 u8 flags2_reserved:2; /* 195+ */ 558 u8 dp_port_trace_length:4; /* 209+ */ 559 u8 dp_gpio_index; /* 195+ */ 560 u16 dp_gpio_pin_num; /* 195+ */ 561 u8 dp_iboost_level:4; /* 196+ */ 562 u8 hdmi_iboost_level:4; /* 196+ */ 563 u8 dp_max_link_rate:3; /* 216+ */ 564 u8 dp_max_link_rate_reserved:5; /* 216+ */ 565 u8 efp_index; /* 256+ */ 566 u32 edp_data_rate_override:12; /* 263+ */ 567 u32 edp_data_rate_override_reserved:20; /* 263+ */ 568} __packed; 569 570struct bdb_general_definitions { 571 /* DDC GPIO */ 572 u8 crt_ddc_gmbus_pin; 573 574 /* DPMS bits */ 575 u8 dpms_non_acpi:1; 576 u8 skip_boot_crt_detect:1; 577 u8 dpms_aim:1; 578 u8 rsvd1:5; /* finish byte */ 579 580 /* boot device bits */ 581 u8 boot_display[2]; 582 u8 child_dev_size; 583 584 /* 585 * Device info: 586 * If TV is present, it'll be at devices[0]. 587 * LVDS will be next, either devices[0] or [1], if present. 588 * On some platforms the number of device is 6. But could be as few as 589 * 4 if both TV and LVDS are missing. 590 * And the device num is related with the size of general definition 591 * block. It is obtained by using the following formula: 592 * number = (block_size - sizeof(bdb_general_definitions))/ 593 * defs->child_dev_size; 594 */ 595 u8 devices[]; 596} __packed; 597 598/* 599 * Block 3 - Display Toggle Option Block 600 */ 601 602struct bdb_display_toggle { 603 u8 feature_bits; 604 u16 num_entries; /* ALM only */ 605 u16 list[]; /* ALM only */ 606} __packed; 607 608/* 609 * Block 4 - Mode Support List 610 */ 611 612struct bdb_mode_support_list { 613 u8 intel_mode_number[0]; 614 u16 mode_list_length; 615} __packed; 616 617/* 618 * Block 5 - Generic Mode Table 619 */ 620 621struct generic_mode_table { 622 u16 x_res; 623 u16 y_res; 624 u8 color_depths; 625 u8 refresh_rate[3]; 626 u8 reserved; 627 u8 text_cols; 628 u8 text_rows; 629 u8 font_height; 630 u16 page_size; 631 u8 misc; 632} __packed; 633 634struct generic_mode_timings { 635 u32 dotclock_khz; 636 u16 hdisplay; 637 u16 htotal; 638 u16 hblank_start; 639 u16 hblank_end; 640 u16 hsync_start; 641 u16 hsync_end; 642 u16 vdisplay; 643 u16 vtotal; 644 u16 vblank_start; 645 u16 vblank_end; 646 u16 vsync_start; 647 u16 vsync_end; 648} __packed; 649 650struct generic_mode_timings_alm { 651 struct generic_mode_timings timings; 652 u8 wm_8bpp; 653 u8 burst_8bpp; 654 u8 wm_16bpp; 655 u8 burst_16bpp; 656 u8 wm_32bpp; 657 u8 burst_32bpp; 658} __packed; 659 660struct bdb_generic_mode_table_alm { 661 struct generic_mode_table table; 662 struct generic_mode_timings_alm timings[3]; 663} __packed; 664 665struct bdb_generic_mode_table_mgm { 666 u16 mode_flag; 667 struct generic_mode_table table; 668 struct generic_mode_timings timings[3]; 669} __packed; 670 671/* 672 * Block 6 - Extended MMIO Register Table, VBIOS only 673 * Block 7 - IO Software Flag Table, VBIOS only 674 * Block 8 - MMIO SWF Register Table, VBIOS only 675 */ 676struct bdb_reg_table { 677 u16 table_id; 678 u8 data_access_size; 679 /* 680 * offset,value tuples: 681 * data_access_size==0xce -> u8,u8 682 * data_access_size==0x02 -> u32,u32 683 */ 684 /* u16 table_end_marker; */ 685} __packed; 686 687/* 688 * Block 9 - Undocumented table (ALM only) 689 */ 690 691struct dot_clock_override_entry_gen2 { 692 u32 dotclock; 693 u8 n; 694 u8 m1; 695 u8 m2; 696 u8 p1:5; 697 u8 p1_div_by_2:1; 698 u8 reserved:1; 699 u8 p2_div_by_4:1; 700} __packed; 701 702struct bdb_dot_clock_override_alm { 703 struct dot_clock_override_entry_gen2 t[0]; 704} __packed; 705 706/* 707 * Block 9 - SRD Feature Block 708 */ 709 710struct psr_table { 711 /* Feature bits */ 712 u8 full_link:1; /* 165+ */ 713 u8 require_aux_to_wakeup:1; /* 165+ */ 714 u8 feature_bits_rsvd:6; 715 716 /* Wait times */ 717 u8 idle_frames:4; /* 165+ */ 718 u8 lines_to_wait:3; /* 165+ */ 719 u8 wait_times_rsvd:1; 720 721 /* TP wake up time in multiple of 100 */ 722 u16 tp1_wakeup_time; /* 165+ */ 723 u16 tp2_tp3_wakeup_time; /* 165+ */ 724} __packed; 725 726struct bdb_psr { 727 struct psr_table psr_table[16]; 728 729 /* PSR2 TP2/TP3 wakeup time for 16 panels */ 730 u32 psr2_tp2_tp3_wakeup_time; /* 226+ */ 731} __packed; 732 733/* 734 * Block 10 - Mode Removal Table 735 */ 736 737struct mode_removal_table { 738 u16 x_res; 739 u16 y_res; 740 u8 bpp; 741 u16 refresh_rate; 742 u8 removal_flags; 743 u16 panel_flags; 744} __packed; 745 746struct bdb_mode_removal { 747 u8 row_size; /* 8 or 10 bytes */ 748 /* 749 * VBT spec says this is always 20 entries, 750 * but ALM seems to have only 15 entries. 751 */ 752 struct mode_removal_table modes[]; 753 /* u16 terminator; 0x0000 */ 754} __packed; 755 756/* 757 * Block 12 - Driver Features Data Block 758 */ 759 760#define BDB_DRIVER_FEATURE_NO_LVDS 0 761#define BDB_DRIVER_FEATURE_INT_LVDS 1 762#define BDB_DRIVER_FEATURE_SDVO_LVDS 2 763#define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3 764 765struct bdb_driver_features { 766 /* Driver bits */ 767 u8 boot_dev_algorithm:1; 768 u8 allow_display_switch_dvd:1; 769 u8 allow_display_switch_dos:1; 770 u8 hotplug_dvo:1; 771 u8 dual_view_zoom:1; 772 u8 int15h_hook:1; 773 u8 sprite_in_clone:1; 774 u8 primary_lfp_id:1; 775 776 u16 boot_mode_x; 777 u16 boot_mode_y; 778 u8 boot_mode_bpp; 779 u8 boot_mode_refresh; 780 781 /* Extended Driver Bits 1 */ 782 u16 enable_lfp_primary:1; 783 u16 selective_mode_pruning:1; 784 u16 dual_frequency:1; 785 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ 786 u16 nt_clone_support:1; 787 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ 788 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ 789 u16 cui_aspect_scaling:1; 790 u16 preserve_aspect_ratio:1; 791 u16 sdvo_device_power_down:1; 792 u16 crt_hotplug:1; 793 u16 lvds_config:2; 794 u16 tv_hotplug:1; 795 u16 hdmi_config:2; 796 797 /* Driver Flags 1 */ 798 u8 static_display:1; /* 163+ */ 799 u8 embedded_platform:1; /* 163+ */ 800 u8 display_subsystem_enable:1; /* 163+ */ 801 u8 reserved0:5; 802 803 u16 legacy_crt_max_x; 804 u16 legacy_crt_max_y; 805 u8 legacy_crt_max_refresh; 806 807 /* Extended Driver Bits 2 */ 808 u8 hdmi_termination:1; 809 u8 cea861d_hdmi_support:1; 810 u8 self_refresh_enable:1; 811 u8 reserved1:5; 812 813 u8 custom_vbt_version; /* 155+ */ 814 815 /* Driver Feature Flags */ 816 u16 rmpm_enabled:1; /* 159+ */ 817 u16 s2ddt_enabled:1; /* 159+ */ 818 u16 dpst_enabled:1; /* 159-227 */ 819 u16 bltclt_enabled:1; /* 159+ */ 820 u16 adb_enabled:1; /* 159-227 */ 821 u16 drrs_enabled:1; /* 159-227 */ 822 u16 grs_enabled:1; /* 159+ */ 823 u16 gpmt_enabled:1; /* 159+ */ 824 u16 tbt_enabled:1; /* 159+ */ 825 u16 psr_enabled:1; /* 165-227 */ 826 u16 ips_enabled:1; /* 165+ */ 827 u16 dfps_enabled:1; /* 165+ */ 828 u16 dmrrs_enabled:1; /* 174-227 */ 829 u16 adt_enabled:1; /* ???-228 */ 830 u16 hpd_wake:1; /* 201-240 */ 831 u16 pc_feature_valid:1; /* 159+ */ 832} __packed; 833 834/* 835 * Block 13 - Driver Persistent Algorithm 836 */ 837 838struct bdb_driver_persistence { 839 u16 hotkey_persistent_algorithm:1; 840 u16 lid_switch_persistent_algorithm:1; 841 u16 power_management_persistent_algorithm:1; 842 u16 hotkey_persistent_on_mds_twin:1; 843 u16 hotkey_persistent_on_refresh_rate:1; 844 u16 hotkey_persistent_on_restore_pipe:1; 845 u16 hotkey_persistent_on_mode:1; 846 u16 edid_persistent_on_mode:1; 847 u16 dvo_hotplug_persistent_on_mode:1; 848 u16 docking_persistent_algorithm:1; 849 u16 rsvd:6; 850 u8 persistent_max_config; 851} __packed; 852 853/* 854 * Block 15 - Dot Clock Override Table 855 */ 856 857struct dot_clock_override_entry_gen3 { 858 u32 dotclock; 859 u8 n; 860 u8 m1; 861 u8 m2; 862 u8 p1; 863 u8 p2; 864} __packed; 865 866struct bdb_dot_clock_override { 867 u8 row_size; /* 8 == gen2, 9 == gen3+ */ 868 u8 num_rows; 869 struct dot_clock_override_entry_gen3 table[]; /* or _gen2 */ 870} __packed; 871 872/* 873 * Block 16 - Toggle List Block (pre-HSW) 874 */ 875 876struct toggle_list_entry_old { 877 u8 display_select_pipe_a; 878 u8 display_select_pipe_b; 879 u8 caps; 880} __packed; 881 882struct toggle_list_table_old { 883 u16 num_entries; 884 u8 entry_size; 885 struct toggle_list_entry_old list[]; 886} __packed; 887 888struct bdb_display_select_old { 889 /* each table has variable size! */ 890 struct toggle_list_table_old tables[4]; 891} __packed; 892 893/* 894 * Block 17 - SV Test Functions 895 */ 896 897struct bdb_sv_test_functions { 898 u8 sv_bits[8]; 899} __packed; 900 901/* 902 * Block 18 - Driver Rotation 903 */ 904 905struct bdb_driver_rotation { 906 u8 rotation_enable; 907 u8 rotation_flags_1; 908 u16 rotation_flags_2; 909 u32 rotation_flags_3; 910 u32 rotation_flags_4; 911} __packed; 912 913/* 914 * Block 19 - Display Configuration Removal Table (pre-IVB) 915 */ 916 917struct display_remove_entry_old { 918 u8 display_select_pipe_a; 919 u8 display_select_pipe_b; 920} __packed; 921 922struct bdb_display_remove_old { 923 u8 num_entries; 924 u8 entry_size; 925 struct display_remove_entry_old table[]; 926} __packed; 927 928/* 929 * Block 20 - OEM Customizable Modes 930 */ 931 932struct oem_mode { 933 u8 enable_in_vbios:1; 934 u8 enable_in_os:1; 935 u8 enable_in_gop:1; /* 207+ */ 936 u8 reserved:5; 937 u8 display_flags; /* ???-216 */ 938 u16 x_res; 939 u16 y_res; 940 u8 color_depth; 941 u8 refresh_rate; 942 struct bdb_edid_dtd dtd; 943 u16 display_flags_2; /* 217+ */ 944} __packed; 945 946struct bdb_oem_custom { 947 u8 num_entries; 948 u8 entry_size; 949 struct oem_mode modes[]; 950} __packed; 951 952/* 953 * Block 21 - EFP List 954 */ 955 956struct efp_entry { 957 u16 mfg_name; 958 u16 product_code; 959} __packed; 960 961struct bdb_efp_list { 962 u8 num_entries; 963 u8 entry_size; 964 struct efp_entry efp[]; 965} __packed; 966 967/* 968 * Block 22 - SDVO LVDS General Options 969 */ 970 971struct bdb_sdvo_lvds_options { 972 u8 panel_backlight; 973 u8 h40_set_panel_type; 974 u8 panel_type; 975 u8 ssc_clk_freq; 976 u16 als_low_trip; 977 u16 als_high_trip; 978 u8 sclalarcoeff_tab_row_num; 979 u8 sclalarcoeff_tab_row_size; 980 u8 coefficient[8]; 981 u8 panel_misc_bits_1; 982 u8 panel_misc_bits_2; 983 u8 panel_misc_bits_3; 984 u8 panel_misc_bits_4; 985} __packed; 986 987/* 988 * Block 23 - SDVO LVDS DTD 989 */ 990 991struct bdb_sdvo_lvds_dtd { 992 struct bdb_edid_dtd dtd[4]; 993} __packed; 994 995/* 996 * Block 24 - SDVO LVDS PnP ID 997 */ 998 999struct bdb_sdvo_lvds_pnp_id { 1000 struct bdb_edid_pnp_id pnp_id[4]; 1001} __packed; 1002 1003/* 1004 * Block 25 - SDVO LVDS PPS 1005 */ 1006 1007struct sdvo_lvds_pps { 1008 u16 t0; /* power on */ 1009 u16 t1; /* backlight on */ 1010 u16 t2; /* backlight off */ 1011 u16 t3; /* power off */ 1012 u16 t4; /* power cycle */ 1013} __packed; 1014 1015struct bdb_sdvo_lvds_pps { 1016 struct sdvo_lvds_pps pps[4]; 1017} __packed; 1018 1019/* 1020 * Block 26 - TV Options Block 1021 */ 1022 1023struct bdb_tv_options { 1024 u16 underscan_overscan_hdtv_component:2; 1025 u16 rsvd1:10; 1026 u16 underscan_overscan_hdtv_dvi:2; 1027 u16 add_modes_to_avoid_overscan_issue:1; 1028 u16 d_connector_support:1; 1029} __packed; 1030 1031/* 1032 * Block 27 - eDP VBT Block 1033 */ 1034 1035struct edp_power_seq { 1036 u16 t1_t3; 1037 u16 t8; 1038 u16 t9; 1039 u16 t10; 1040 u16 t11_t12; 1041} __packed; 1042 1043#define EDP_18BPP 0 1044#define EDP_24BPP 1 1045#define EDP_30BPP 2 1046#define EDP_RATE_1_62 0 1047#define EDP_RATE_2_7 1 1048#define EDP_RATE_5_4 2 1049#define EDP_LANE_1 0 1050#define EDP_LANE_2 1 1051#define EDP_LANE_4 3 1052#define EDP_PREEMPHASIS_NONE 0 1053#define EDP_PREEMPHASIS_3_5dB 1 1054#define EDP_PREEMPHASIS_6dB 2 1055#define EDP_PREEMPHASIS_9_5dB 3 1056#define EDP_VSWING_0_4V 0 1057#define EDP_VSWING_0_6V 1 1058#define EDP_VSWING_0_8V 2 1059#define EDP_VSWING_1_2V 3 1060 1061 1062struct edp_fast_link_params { 1063 u8 rate:4; /* ???-223 */ 1064 u8 lanes:4; 1065 u8 preemphasis:4; 1066 u8 vswing:4; 1067} __packed; 1068 1069struct edp_pwm_delays { 1070 u16 pwm_on_to_backlight_enable; 1071 u16 backlight_disable_to_pwm_off; 1072} __packed; 1073 1074struct edp_full_link_params { 1075 u8 preemphasis:4; 1076 u8 vswing:4; 1077} __packed; 1078 1079struct edp_apical_params { 1080 u32 panel_oui; 1081 u32 dpcd_base_address; 1082 u32 dpcd_idridix_control_0; 1083 u32 dpcd_option_select; 1084 u32 dpcd_backlight; 1085 u32 ambient_light; 1086 u32 backlight_scale; 1087} __packed; 1088 1089struct bdb_edp { 1090 struct edp_power_seq power_seqs[16]; 1091 u32 color_depth; 1092 struct edp_fast_link_params fast_link_params[16]; 1093 u32 sdrrs_msa_timing_delay; 1094 1095 /* ith bit indicates enabled/disabled for (i+1)th panel */ 1096 u16 edp_s3d_feature; /* 162+ */ 1097 u16 edp_t3_optimization; /* 165+ */ 1098 u64 edp_vswing_preemph; /* 173+ */ 1099 u16 fast_link_training; /* 182+ */ 1100 u16 dpcd_600h_write_required; /* 185+ */ 1101 struct edp_pwm_delays pwm_delays[16]; /* 186+ */ 1102 u16 full_link_params_provided; /* 199+ */ 1103 struct edp_full_link_params full_link_params[16]; /* 199+ */ 1104 u16 apical_enable; /* 203+ */ 1105 struct edp_apical_params apical_params[16]; /* 203+ */ 1106 u16 edp_fast_link_training_rate[16]; /* 224+ */ 1107 u16 edp_max_port_link_rate[16]; /* 244+ */ 1108 u16 edp_dsc_disable; /* 251+ */ 1109 u16 t6_delay_support; /* 260+ */ 1110 u16 link_idle_time[16]; /* 260+ */ 1111} __packed; 1112 1113/* 1114 * Block 28 - EFP DTD Block 1115 */ 1116 1117struct bdb_efp_dtd { 1118 struct bdb_edid_dtd dtd[3]; 1119} __packed; 1120 1121/* 1122 * Block 29 - Toggle List Block (IVB) 1123 */ 1124 1125struct toggle_list_entry_ivb { 1126 u8 display_select; 1127} __packed; 1128 1129struct toggle_list_table_ivb { 1130 u16 num_entries; 1131 u8 entry_size; 1132 struct toggle_list_entry_ivb list[]; 1133} __packed; 1134 1135struct bdb_display_select_ivb { 1136 /* each table has variable size! */ 1137 struct toggle_list_table_ivb tables[4]; 1138} __packed; 1139 1140/* 1141 * Block 30 - Display Configuration Removal Table (IVB) 1142 */ 1143 1144struct display_remove_entry_ivb { 1145 u8 display_select; 1146} __packed; 1147 1148struct bdb_display_remove_ivb { 1149 u8 num_entries; 1150 u8 entry_size; 1151 struct display_remove_entry_ivb table[]; 1152} __packed; 1153 1154/* 1155 * Block 31 - Toggle List Block (HSW+) 1156 */ 1157 1158struct toggle_list_entry_hsw { 1159 u16 display_select; 1160} __packed; 1161 1162struct toggle_list_table_hsw { 1163 u16 num_entries; 1164 u8 entry_size; 1165 struct toggle_list_entry_hsw list[]; 1166} __packed; 1167 1168struct bdb_display_select_hsw { 1169 /* each table has variable size! */ 1170 struct toggle_list_table_hsw tables[4]; 1171} __packed; 1172 1173/* 1174 * Block 32 - Display Configuration Removal Table (HSW+) 1175 */ 1176 1177struct display_remove_entry_hsw { 1178 u16 display_select; 1179} __packed; 1180 1181struct bdb_display_remove_hsw { 1182 u8 num_entries; 1183 u8 entry_size; 1184 struct display_remove_entry_hsw table[]; 1185} __packed; 1186 1187/* 1188 * Block 40 - LFP Data Block 1189 */ 1190 1191struct bdb_lfp_options { 1192 u8 panel_type; 1193 u8 panel_type2; /* 212+ */ 1194 /* LVDS capabilities, stored in a dword */ 1195 u8 pfit_mode:2; 1196 u8 pfit_text_mode_enhanced:1; 1197 u8 pfit_gfx_mode_enhanced:1; 1198 u8 pfit_ratio_auto:1; 1199 u8 pixel_dither:1; 1200 u8 lvds_edid:1; /* ???-240 */ 1201 u8 rsvd2:1; 1202 u8 rsvd4; 1203 /* LVDS Panel channel bits stored here */ 1204 u32 lvds_panel_channel_bits; 1205 /* LVDS SSC (Spread Spectrum Clock) bits stored here. */ 1206 u16 ssc_bits; 1207 u16 ssc_freq; 1208 u16 ssc_ddt; 1209 /* Panel color depth defined here */ 1210 u16 panel_color_depth; 1211 /* LVDS panel type bits stored here */ 1212 u32 dps_panel_type_bits; 1213 /* LVDS backlight control type bits stored here */ 1214 u32 blt_control_type_bits; /* ???-240 */ 1215 1216 u16 lcdvcc_s0_enable; /* 200+ */ 1217 u32 rotation; /* 228+ */ 1218 u32 position; /* 240+ */ 1219} __packed; 1220 1221/* 1222 * Block 41 - LFP Data Table Pointers 1223 */ 1224struct lfp_data_ptr_table { 1225 u16 offset; /* offsets are from start of bdb */ 1226 u8 table_size; 1227} __packed; 1228 1229/* LFP pointer table contains entries to the struct below */ 1230struct lfp_data_ptr { 1231 struct lfp_data_ptr_table fp_timing; 1232 struct lfp_data_ptr_table dvo_timing; 1233 struct lfp_data_ptr_table panel_pnp_id; 1234} __packed; 1235 1236struct bdb_lfp_data_ptrs { 1237 u8 num_entries; 1238 struct lfp_data_ptr ptr[16]; 1239 struct lfp_data_ptr_table panel_name; /* (156-163?)+ */ 1240} __packed; 1241 1242/* 1243 * Block 42 - LFP Data Tables 1244 */ 1245 1246/* LFP data has 3 blocks per entry */ 1247struct fp_timing { 1248 u16 x_res; 1249 u16 y_res; 1250 u32 lvds_reg; 1251 u32 lvds_reg_val; 1252 u32 pp_on_reg; 1253 u32 pp_on_reg_val; 1254 u32 pp_off_reg; 1255 u32 pp_off_reg_val; 1256 u32 pp_cycle_reg; 1257 u32 pp_cycle_reg_val; 1258 u32 pfit_reg; 1259 u32 pfit_reg_val; 1260 u16 terminator; 1261} __packed; 1262 1263/* 1264 * For reference only. fp_timing has variable size so 1265 * the data must be accessed using the data table pointers. 1266 * Do not use this directly! 1267 */ 1268struct lfp_data_entry { 1269 struct fp_timing fp_timing; 1270 struct bdb_edid_dtd dvo_timing; 1271 struct bdb_edid_pnp_id pnp_id; 1272} __packed; 1273 1274struct bdb_lfp_data { 1275 struct lfp_data_entry data[16]; 1276} __packed; 1277 1278struct lfp_black_border { 1279 u8 top; /* 227+ */ 1280 u8 bottom; /* 227+ */ 1281 u8 left; /* 238+ */ 1282 u8 right; /* 238+ */ 1283} __packed; 1284 1285struct bdb_lfp_data_tail { 1286 struct bdb_edid_product_name panel_name[16]; /* (156-163?)+ */ 1287 u16 scaling_enable; /* 187+ */ 1288 u8 seamless_drrs_min_refresh_rate[16]; /* 188+ */ 1289 u8 pixel_overlap_count[16]; /* 208+ */ 1290 struct lfp_black_border black_border[16]; /* 227+ */ 1291 u16 dual_lfp_port_sync_enable; /* 231+ */ 1292 u16 gpu_dithering_for_banding_artifacts; /* 245+ */ 1293} __packed; 1294 1295/* 1296 * Block 43 - LFP Backlight Control Data Block 1297 */ 1298 1299#define BDB_BACKLIGHT_TYPE_NONE 0 1300#define BDB_BACKLIGHT_TYPE_PWM 2 1301 1302struct lfp_backlight_data_entry { 1303 u8 type:2; 1304 u8 active_low_pwm:1; 1305 u8 i2c_pin:3; /* obsolete since ? */ 1306 u8 i2c_speed:2; /* obsolete since ? */ 1307 u16 pwm_freq_hz; 1308 u8 min_brightness; /* ???-233 */ 1309 u8 i2c_address; /* obsolete since ? */ 1310 u8 i2c_command; /* obsolete since ? */ 1311} __packed; 1312 1313struct lfp_backlight_control_method { 1314 u8 type:4; 1315 u8 controller:4; 1316} __packed; 1317 1318struct lfp_brightness_level { 1319 u16 level; 1320 u16 reserved; 1321} __packed; 1322 1323struct bdb_lfp_backlight { 1324 u8 entry_size; 1325 struct lfp_backlight_data_entry data[16]; 1326 u8 level[16]; /* 162-233 */ 1327 struct lfp_backlight_control_method backlight_control[16]; /* 191+ */ 1328 struct lfp_brightness_level brightness_level[16]; /* 234+ */ 1329 struct lfp_brightness_level brightness_min_level[16]; /* 234+ */ 1330 u8 brightness_precision_bits[16]; /* 236+ */ 1331 u16 hdr_dpcd_refresh_timeout[16]; /* 239+ */ 1332} __packed; 1333 1334/* 1335 * Block 44 - LFP Power Conservation Features Block 1336 */ 1337struct lfp_power_features { 1338 u8 dpst_support:1; /* ???-159 */ 1339 u8 power_conservation_pref:3; 1340 u8 reserved2:1; 1341 u8 lace_enabled_status:1; /* 210+ */ 1342 u8 lace_support:1; /* 210+ */ 1343 u8 als_enable:1; 1344} __packed; 1345 1346struct als_data_entry { 1347 u16 backlight_adjust; 1348 u16 lux; 1349} __packed; 1350 1351struct aggressiveness_profile_entry { 1352 u8 dpst_aggressiveness : 4; /* (228/252)-256 */ 1353 u8 lace_aggressiveness : 4; 1354} __packed; 1355 1356struct aggressiveness_profile2_entry { 1357 u8 opst_aggressiveness : 4; 1358 u8 elp_aggressiveness : 4; 1359} __packed; 1360 1361struct aggressiveness_profile3_entry { 1362 u8 apd_aggressiveness:4; 1363 u8 pixoptix_aggressiveness:4; 1364} __packed; 1365 1366struct aggressiveness_profile4_entry { 1367 u8 xpst_aggressiveness:4; 1368 u8 tcon_aggressiveness:4; 1369} __packed; 1370 1371struct panel_identification { 1372 u8 panel_technology:4; 1373 u8 reserved:4; 1374} __packed; 1375 1376struct bdb_lfp_power { 1377 struct lfp_power_features features; /* ???-227 */ 1378 struct als_data_entry als[5]; 1379 u8 lace_aggressiveness_profile:3; /* 210-227 */ 1380 u8 reserved1:5; 1381 u16 dpst; /* 228-256 */ 1382 u16 psr; /* 228+ */ 1383 u16 drrs; /* 228+ */ 1384 u16 lace_support; /* 228+ */ 1385 u16 adt; /* 228+ */ 1386 u16 dmrrs; /* 228+ */ 1387 u16 adb; /* 228+ */ 1388 u16 lace_enabled_status; /* 228+ */ 1389 struct aggressiveness_profile_entry aggressiveness[16]; 1390 u16 hobl; /* 232+ */ 1391 u16 vrr_feature_enabled; /* 233+ */ 1392 u16 elp; /* 247-256 */ 1393 u16 opst; /* 247-256 */ 1394 struct aggressiveness_profile2_entry aggressiveness2[16]; /* 247-256 */ 1395 u16 apd; /* 253-256 */ 1396 u16 pixoptix; /* 253-256 */ 1397 struct aggressiveness_profile3_entry aggressiveness3[16]; /* 253-256 */ 1398 struct panel_identification panel_identification[16]; /* 257+ */ 1399 u16 xpst_support; /* 257+ */ 1400 u16 tcon_based_backlight_optimization; /* 257+ */ 1401 struct aggressiveness_profile4_entry aggressiveness4[16]; /* 257+ */ 1402 u16 tcon_backlight_xpst_coexistence; /* 257+ */ 1403} __packed; 1404 1405/* 1406 * Block 45 - eDP BFI Block 1407 */ 1408 1409struct edp_bfi { 1410 u8 enable_bfi_in_driver:1; 1411 u8 enable_brightness_control_in_cui:1; 1412 u8 reserved:6; 1413 u8 brightness_percentage_when_bfi_disabled; 1414} __packed; 1415 1416struct bdb_edp_bfi { 1417 u8 bfi_structure_size; 1418 struct edp_bfi bfi[16]; 1419} __packed; 1420 1421/* 1422 * Block 46 - Chromaticity For Narrow Gamut Panel Configuration Block 1423 */ 1424 1425struct chromaticity { 1426 u8 chromaticity_enable:1; 1427 u8 chromaticity_from_edid_base_block:1; 1428 u8 rsvd:6; 1429 1430 u8 green_y_lo:2; 1431 u8 green_x_lo:2; 1432 u8 red_y_lo:2; 1433 u8 red_x_lo:2; 1434 u8 white_y_lo:2; 1435 u8 white_x_lo:2; 1436 u8 blue_y_lo:2; 1437 u8 blue_x_lo:2; 1438 1439 u8 red_x_hi; 1440 u8 red_y_hi; 1441 u8 green_x_hi; 1442 u8 green_y_hi; 1443 u8 blue_x_hi; 1444 u8 blue_y_hi; 1445 u8 white_x_hi; 1446 u8 white_y_hi; 1447} __packed; 1448 1449struct luminance_and_gamma { 1450 u8 luminance_enable:1; /* 211+ */ 1451 u8 gamma_enable:1; /* 211+ */ 1452 u8 rsvd:6; 1453 1454 u16 min_luminance; /* 211+ */ 1455 u16 max_luminance; /* 211+ */ 1456 u16 one_percent_max_luminance; /* 211+ */ 1457 u8 gamma; /* 211+ */ 1458} __packed; 1459 1460struct bdb_chromaticity { 1461 struct chromaticity chromaticity[16]; 1462 struct luminance_and_gamma luminance_and_gamma[16]; /* 211+ */ 1463} __packed; 1464 1465/* 1466 * Block 50 - MIPI Block 1467 */ 1468 1469struct mipi_data { 1470 u16 panel_identifier; 1471 u16 bridge_revision; 1472 1473 u32 dithering:1; 1474 u32 pixel_format_18bpp:1; 1475 u32 reserved1:1; 1476 u32 dphy_params_valid:1; 1477 u32 reserved2:28; 1478 1479 u16 port_info; 1480 1481 u16 reserved3:2; 1482 u16 num_lanes:2; 1483 u16 reserved4:12; 1484 1485 u16 virtual_channel_num:2; 1486 u16 video_transfer_mode:2; 1487 u16 reserved5:12; 1488 1489 u32 dsi_ddr_clock; 1490 u32 renesas_bridge_ref_clock; 1491 u16 power_conservation; 1492 1493 u32 prepare_count:5; 1494 u32 reserved6:3; 1495 u32 clk_zero_count:8; 1496 u32 trail_count:5; 1497 u32 reserved7:3; 1498 u32 exit_zero_count:6; 1499 u32 reserved8:2; 1500 1501 u32 high_low_switch_count; 1502 u32 lp_byte_clock; 1503 u32 clock_lane_switch_time_counter; 1504 u32 panel_color_depth; 1505} __packed; 1506 1507struct bdb_mipi { 1508 struct mipi_data mipi[16]; 1509} __packed; 1510 1511/* 1512 * Block 51 - Fixed Set Mode Table 1513 */ 1514 1515struct bdb_fixed_set_mode { 1516 u8 enable; 1517 u32 x_res; 1518 u32 y_res; 1519} __packed; 1520 1521/* 1522 * Block 52 - MIPI Configuration Block 1523 */ 1524 1525#define MAX_MIPI_CONFIGURATIONS 6 1526 1527struct bdb_mipi_config { 1528 struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; /* 175+ */ 1529 struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; /* 177+ */ 1530 struct edp_pwm_delays pwm_delays[MAX_MIPI_CONFIGURATIONS]; /* 186+ */ 1531 u8 pmic_i2c_bus_number[MAX_MIPI_CONFIGURATIONS]; /* 190+ */ 1532} __packed; 1533 1534/* 1535 * Block 53 - MIPI Sequence Block 1536 */ 1537 1538struct bdb_mipi_sequence { 1539 u8 version; 1540 u8 data[]; /* up to 6 variable length blocks */ 1541} __packed; 1542 1543/* 1544 * Block 55 - RGB Palette Table 1545 */ 1546 1547struct bdb_rgb_palette { 1548 u8 is_enabled; 1549 u8 red[256]; 1550 u8 blue[256]; 1551 u8 green[256]; 1552} __packed; 1553 1554/* 1555 * Block 56 - Compression Parameters 1556 */ 1557 1558#define VBT_RC_BUFFER_BLOCK_SIZE_1KB 0 1559#define VBT_RC_BUFFER_BLOCK_SIZE_4KB 1 1560#define VBT_RC_BUFFER_BLOCK_SIZE_16KB 2 1561#define VBT_RC_BUFFER_BLOCK_SIZE_64KB 3 1562 1563#define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value) ((vbt_value) + 8) /* bits */ 1564#define VBT_DSC_MAX_BPP(vbt_value) (6 + (vbt_value) * 2) 1565 1566struct dsc_compression_parameters_entry { 1567 u8 version_major:4; 1568 u8 version_minor:4; 1569 1570 u8 rc_buffer_block_size:2; 1571 u8 reserved1:6; 1572 1573 /* 1574 * Buffer size in bytes: 1575 * 1576 * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes 1577 */ 1578 u8 rc_buffer_size; 1579 u32 slices_per_line; 1580 1581 u8 line_buffer_depth:4; 1582 u8 reserved2:4; 1583 1584 /* Flag Bits 1 */ 1585 u8 block_prediction_enable:1; 1586 u8 reserved3:7; 1587 1588 u8 max_bpp; /* mapping */ 1589 1590 /* Color depth capabilities */ 1591 u8 reserved4:1; 1592 u8 support_8bpc:1; 1593 u8 support_10bpc:1; 1594 u8 support_12bpc:1; 1595 u8 reserved5:4; 1596 1597 u16 slice_height; 1598} __packed; 1599 1600struct bdb_compression_parameters { 1601 u16 entry_size; 1602 struct dsc_compression_parameters_entry data[16]; 1603} __packed; 1604 1605/* 1606 * Block 57 - Vswing PreEmphasis Table 1607 */ 1608 1609struct bdb_vswing_preemph { 1610 u8 num_tables; 1611 u8 num_columns; 1612 u32 tables[]; 1613} __packed; 1614 1615/* 1616 * Block 58 - Generic DTD Block 1617 */ 1618 1619struct generic_dtd_entry { 1620 u32 pixel_clock; 1621 u16 hactive; 1622 u16 hblank; 1623 u16 hfront_porch; 1624 u16 hsync; 1625 u16 vactive; 1626 u16 vblank; 1627 u16 vfront_porch; 1628 u16 vsync; 1629 u16 width_mm; 1630 u16 height_mm; 1631 1632 /* Flags */ 1633 u8 rsvd_flags:6; 1634 u8 vsync_positive_polarity:1; 1635 u8 hsync_positive_polarity:1; 1636 1637 u8 rsvd[3]; 1638} __packed; 1639 1640struct bdb_generic_dtd { 1641 u16 gdtd_size; 1642 struct generic_dtd_entry dtd[]; /* up to 24 DTD's */ 1643} __packed; 1644 1645/* 1646 * Block 253 - PRD Table 1647 */ 1648 1649struct prd_entry_old { 1650 u8 displays_attached; 1651 u8 display_in_pipe_a; 1652 u8 display_in_pipe_b; 1653} __packed; 1654 1655struct bdb_prd_table_old { 1656 struct prd_entry_old list[0]; /* ???-216 */ 1657 u16 num_entries; /* ???-216 */ 1658} __packed; 1659 1660struct prd_entry_new { 1661 u16 primary_display; 1662 u16 secondary_display; 1663} __packed; 1664 1665struct bdb_prd_table_new { 1666 u16 num_entries; /* 217+ */ 1667 struct prd_entry_new list[]; /* 217+ */ 1668} __packed; 1669 1670#endif /* _INTEL_VBT_DEFS_H_ */
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