intel_vblank.c

  1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright © 2022-2023 Intel Corporation
  4 */
  5
  6#include <linux/iopoll.h>
  7
  8#include <drm/drm_print.h>
  9#include <drm/drm_vblank.h>
 10
 11#include "i915_drv.h"
 12#include "intel_color.h"
 13#include "intel_crtc.h"
 14#include "intel_de.h"
 15#include "intel_display_jiffies.h"
 16#include "intel_display_regs.h"
 17#include "intel_display_types.h"
 18#include "intel_display_utils.h"
 19#include "intel_vblank.h"
 20#include "intel_vrr.h"
 21
 22/*
 23 * This timing diagram depicts the video signal in and
 24 * around the vertical blanking period.
 25 *
 26 * Assumptions about the fictitious mode used in this example:
 27 *  vblank_start >= 3
 28 *  vsync_start = vblank_start + 1
 29 *  vsync_end = vblank_start + 2
 30 *  vtotal = vblank_start + 3
 31 *
 32 *           start of vblank:
 33 *           latch double buffered registers
 34 *           increment frame counter (ctg+)
 35 *           generate start of vblank interrupt (gen4+)
 36 *           |
 37 *           |          frame start:
 38 *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 39 *           |          may be shifted forward 1-3 extra lines via TRANSCONF
 40 *           |          |
 41 *           |          |  start of vsync:
 42 *           |          |  generate vsync interrupt
 43 *           |          |  |
 44 * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 45 *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 46 * ----va---> <-----------------vb--------------------> <--------va-------------
 47 *       |          |       <----vs----->                     |
 48 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 49 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 50 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 51 *       |          |                                         |
 52 *       last visible pixel                                   first visible pixel
 53 *                  |                                         increment frame counter (gen3/4)
 54 *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 55 *
 56 * x  = horizontal active
 57 * _  = horizontal blanking
 58 * hs = horizontal sync
 59 * va = vertical active
 60 * vb = vertical blanking
 61 * vs = vertical sync
 62 * vbs = vblank_start (number)
 63 *
 64 * Summary:
 65 * - most events happen at the start of horizontal sync
 66 * - frame start happens at the start of horizontal blank, 1-4 lines
 67 *   (depending on TRANSCONF settings) after the start of vblank
 68 * - gen3/4 pixel and frame counter are synchronized with the start
 69 *   of horizontal active on the first line of vertical active
 70 */
 71
 72/*
 73 * Called from drm generic code, passed a 'crtc', which we use as a pipe index.
 74 */
 75u32 i915_get_vblank_counter(struct drm_crtc *crtc)
 76{
 77	struct intel_display *display = to_intel_display(crtc->dev);
 78	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
 79	const struct drm_display_mode *mode = &vblank->hwmode;
 80	enum pipe pipe = to_intel_crtc(crtc)->pipe;
 81	u32 pixel, vbl_start, hsync_start, htotal;
 82	u64 frame;
 83
 84	/*
 85	 * On i965gm TV output the frame counter only works up to
 86	 * the point when we enable the TV encoder. After that the
 87	 * frame counter ceases to work and reads zero. We need a
 88	 * vblank wait before enabling the TV encoder and so we
 89	 * have to enable vblank interrupts while the frame counter
 90	 * is still in a working state. However the core vblank code
 91	 * does not like us returning non-zero frame counter values
 92	 * when we've told it that we don't have a working frame
 93	 * counter. Thus we must stop non-zero values leaking out.
 94	 */
 95	if (!vblank->max_vblank_count)
 96		return 0;
 97
 98	htotal = mode->crtc_htotal;
 99	hsync_start = mode->crtc_hsync_start;
100	vbl_start = intel_mode_vblank_start(mode);
101
102	/* Convert to pixel count */
103	vbl_start *= htotal;
104
105	/* Start of vblank event occurs at start of hsync */
106	vbl_start -= htotal - hsync_start;
107
108	/*
109	 * High & low register fields aren't synchronized, so make sure
110	 * we get a low value that's stable across two reads of the high
111	 * register.
112	 */
113	frame = intel_de_read64_2x32(display, PIPEFRAMEPIXEL(display, pipe),
114				     PIPEFRAME(display, pipe));
115
116	pixel = frame & PIPE_PIXEL_MASK;
117	frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff;
118
119	/*
120	 * The frame counter increments at beginning of active.
121	 * Cook up a vblank counter by also checking the pixel
122	 * counter against vblank start.
123	 */
124	return (frame + (pixel >= vbl_start)) & 0xffffff;
125}
126
127u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
128{
129	struct intel_display *display = to_intel_display(crtc->dev);
130	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
131	enum pipe pipe = to_intel_crtc(crtc)->pipe;
132
133	if (!vblank->max_vblank_count)
134		return 0;
135
136	return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));
137}
138
139static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
140{
141	struct intel_display *display = to_intel_display(crtc);
142	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
143	const struct drm_display_mode *mode = &vblank->hwmode;
144	u32 htotal = mode->crtc_htotal;
145	u32 clock = mode->crtc_clock;
146	u32 scan_prev_time, scan_curr_time, scan_post_time;
147
148	/*
149	 * To avoid the race condition where we might cross into the
150	 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
151	 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
152	 * during the same frame.
153	 */
154	do {
155		/*
156		 * This field provides read back of the display
157		 * pipe frame time stamp. The time stamp value
158		 * is sampled at every start of vertical blank.
159		 */
160		scan_prev_time = intel_de_read_fw(display,
161						  PIPE_FRMTMSTMP(crtc->pipe));
162
163		/*
164		 * The TIMESTAMP_CTR register has the current
165		 * time stamp value.
166		 */
167		scan_curr_time = intel_de_read_fw(display, IVB_TIMESTAMP_CTR);
168
169		scan_post_time = intel_de_read_fw(display,
170						  PIPE_FRMTMSTMP(crtc->pipe));
171	} while (scan_post_time != scan_prev_time);
172
173	return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
174				   clock), 1000 * htotal);
175}
176
177/*
178 * On certain encoders on certain platforms, pipe
179 * scanline register will not work to get the scanline,
180 * since the timings are driven from the PORT or issues
181 * with scanline register updates.
182 * This function will use Framestamp and current
183 * timestamp registers to calculate the scanline.
184 */
185static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
186{
187	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
188	const struct drm_display_mode *mode = &vblank->hwmode;
189	u32 vblank_start = mode->crtc_vblank_start;
190	u32 vtotal = mode->crtc_vtotal;
191	u32 scanline;
192
193	scanline = intel_crtc_scanlines_since_frame_timestamp(crtc);
194	scanline = min(scanline, vtotal - 1);
195	scanline = (scanline + vblank_start) % vtotal;
196
197	return scanline;
198}
199
200int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
201{
202	struct intel_display *display = to_intel_display(crtc_state);
203
204	/*
205	 * The scanline counter increments at the leading edge of hsync.
206	 *
207	 * On most platforms it starts counting from vtotal-1 on the
208	 * first active line. That means the scanline counter value is
209	 * always one less than what we would expect. Ie. just after
210	 * start of vblank, which also occurs at start of hsync (on the
211	 * last active line), the scanline counter will read vblank_start-1.
212	 *
213	 * On gen2 the scanline counter starts counting from 1 instead
214	 * of vtotal-1, so we have to subtract one.
215	 *
216	 * On HSW+ the behaviour of the scanline counter depends on the output
217	 * type. For DP ports it behaves like most other platforms, but on HDMI
218	 * there's an extra 1 line difference. So we need to add two instead of
219	 * one to the value.
220	 *
221	 * On VLV/CHV DSI the scanline counter would appear to increment
222	 * approx. 1/3 of a scanline before start of vblank. Unfortunately
223	 * that means we can't tell whether we're in vblank or not while
224	 * we're on that particular line. We must still set scanline_offset
225	 * to 1 so that the vblank timestamps come out correct when we query
226	 * the scanline counter from within the vblank interrupt handler.
227	 * However if queried just before the start of vblank we'll get an
228	 * answer that's slightly in the future.
229	 */
230	if (DISPLAY_VER(display) >= 20 || display->platform.battlemage)
231		return 1;
232	else if (DISPLAY_VER(display) >= 9 ||
233		 display->platform.broadwell || display->platform.haswell)
234		return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ? 2 : 1;
235	else if (DISPLAY_VER(display) >= 3)
236		return 1;
237	else
238		return -1;
239}
240
241/*
242 * intel_de_read_fw(), only for fast reads of display block, no need for
243 * forcewake etc.
244 */
245static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
246{
247	struct intel_display *display = to_intel_display(crtc);
248	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
249	const struct drm_display_mode *mode = &vblank->hwmode;
250	enum pipe pipe = crtc->pipe;
251	int position, vtotal;
252
253	if (!crtc->active)
254		return 0;
255
256	if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
257		return __intel_get_crtc_scanline_from_timestamp(crtc);
258
259	vtotal = intel_mode_vtotal(mode);
260
261	position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
262
263	/*
264	 * On HSW, the DSL reg (0x70000) appears to return 0 if we
265	 * read it just before the start of vblank.  So try it again
266	 * so we don't accidentally end up spanning a vblank frame
267	 * increment, causing the pipe_update_end() code to squak at us.
268	 *
269	 * The nature of this problem means we can't simply check the ISR
270	 * bit and return the vblank start value; nor can we use the scanline
271	 * debug register in the transcoder as it appears to have the same
272	 * problem.  We may need to extend this to include other platforms,
273	 * but so far testing only shows the problem on HSW.
274	 */
275	if (HAS_DDI(display) && !position) {
276		int i, temp;
277
278		for (i = 0; i < 100; i++) {
279			udelay(1);
280			temp = intel_de_read_fw(display,
281						PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK;
282			if (temp != position) {
283				position = temp;
284				break;
285			}
286		}
287	}
288
289	/*
290	 * See update_scanline_offset() for the details on the
291	 * scanline_offset adjustment.
292	 */
293	return (position + vtotal + crtc->scanline_offset) % vtotal;
294}
295
296/*
297 * The uncore version of the spin lock functions is used to decide
298 * whether we need to lock the uncore lock or not.  This is only
299 * needed in i915, not in Xe.
300 *
301 * This lock in i915 is needed because some old platforms (at least
302 * IVB and possibly HSW as well), which are not supported in Xe, need
303 * all register accesses to the same cacheline to be serialized,
304 * otherwise they may hang.
305 */
306#ifdef I915
307static void intel_vblank_section_enter(struct intel_display *display)
308	__acquires(i915->uncore.lock)
309{
310	struct drm_i915_private *i915 = to_i915(display->drm);
311	spin_lock(&i915->uncore.lock);
312}
313
314static void intel_vblank_section_exit(struct intel_display *display)
315	__releases(i915->uncore.lock)
316{
317	struct drm_i915_private *i915 = to_i915(display->drm);
318	spin_unlock(&i915->uncore.lock);
319}
320#else
321static void intel_vblank_section_enter(struct intel_display *display)
322{
323}
324
325static void intel_vblank_section_exit(struct intel_display *display)
326{
327}
328#endif
329
330static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
331				     bool in_vblank_irq,
332				     int *vpos, int *hpos,
333				     ktime_t *stime, ktime_t *etime,
334				     const struct drm_display_mode *mode)
335{
336	struct intel_display *display = to_intel_display(_crtc->dev);
337	struct intel_crtc *crtc = to_intel_crtc(_crtc);
338	enum pipe pipe = crtc->pipe;
339	int position;
340	int vbl_start, vbl_end, hsync_start, htotal, vtotal;
341	unsigned long irqflags;
342	bool use_scanline_counter = DISPLAY_VER(display) >= 5 ||
343		display->platform.g4x || DISPLAY_VER(display) == 2 ||
344		crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
345
346	if (drm_WARN_ON(display->drm, !mode->crtc_clock)) {
347		drm_dbg(display->drm,
348			"trying to get scanoutpos for disabled pipe %c\n",
349			pipe_name(pipe));
350		return false;
351	}
352
353	htotal = mode->crtc_htotal;
354	hsync_start = mode->crtc_hsync_start;
355	vtotal = intel_mode_vtotal(mode);
356	vbl_start = intel_mode_vblank_start(mode);
357	vbl_end = intel_mode_vblank_end(mode);
358
359	/*
360	 * Enter vblank critical section, as we will do multiple
361	 * timing critical raw register reads, potentially with
362	 * preemption disabled, so the following code must not block.
363	 */
364	local_irq_save(irqflags);
365	intel_vblank_section_enter(display);
366
367	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
368
369	/* Get optional system timestamp before query. */
370	if (stime)
371		*stime = ktime_get();
372
373	if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
374		int scanlines = intel_crtc_scanlines_since_frame_timestamp(crtc);
375
376		position = __intel_get_crtc_scanline(crtc);
377
378		/*
379		 * Already exiting vblank? If so, shift our position
380		 * so it looks like we're already approaching the full
381		 * vblank end. This should make the generated timestamp
382		 * more or less match when the active portion will start.
383		 */
384		if (position >= vbl_start && scanlines < position)
385			position = min(crtc->vmax_vblank_start + scanlines, vtotal - 1);
386	} else if (use_scanline_counter) {
387		/* No obvious pixelcount register. Only query vertical
388		 * scanout position from Display scan line register.
389		 */
390		position = __intel_get_crtc_scanline(crtc);
391	} else {
392		/*
393		 * Have access to pixelcount since start of frame.
394		 * We can split this into vertical and horizontal
395		 * scanout position.
396		 */
397		position = (intel_de_read_fw(display, PIPEFRAMEPIXEL(display, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
398
399		/* convert to pixel counts */
400		vbl_start *= htotal;
401		vbl_end *= htotal;
402		vtotal *= htotal;
403
404		/*
405		 * In interlaced modes, the pixel counter counts all pixels,
406		 * so one field will have htotal more pixels. In order to avoid
407		 * the reported position from jumping backwards when the pixel
408		 * counter is beyond the length of the shorter field, just
409		 * clamp the position the length of the shorter field. This
410		 * matches how the scanline counter based position works since
411		 * the scanline counter doesn't count the two half lines.
412		 */
413		position = min(position, vtotal - 1);
414
415		/*
416		 * Start of vblank interrupt is triggered at start of hsync,
417		 * just prior to the first active line of vblank. However we
418		 * consider lines to start at the leading edge of horizontal
419		 * active. So, should we get here before we've crossed into
420		 * the horizontal active of the first line in vblank, we would
421		 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
422		 * always add htotal-hsync_start to the current pixel position.
423		 */
424		position = (position + htotal - hsync_start) % vtotal;
425	}
426
427	/* Get optional system timestamp after query. */
428	if (etime)
429		*etime = ktime_get();
430
431	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
432
433	intel_vblank_section_exit(display);
434	local_irq_restore(irqflags);
435
436	/*
437	 * While in vblank, position will be negative
438	 * counting up towards 0 at vbl_end. And outside
439	 * vblank, position will be positive counting
440	 * up since vbl_end.
441	 */
442	if (position >= vbl_start)
443		position -= vbl_end;
444	else
445		position += vtotal - vbl_end;
446
447	if (use_scanline_counter) {
448		*vpos = position;
449		*hpos = 0;
450	} else {
451		*vpos = position / htotal;
452		*hpos = position - (*vpos * htotal);
453	}
454
455	return true;
456}
457
458bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
459				     ktime_t *vblank_time, bool in_vblank_irq)
460{
461	return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
462		crtc, max_error, vblank_time, in_vblank_irq,
463		i915_get_crtc_scanoutpos);
464}
465
466int intel_get_crtc_scanline(struct intel_crtc *crtc)
467{
468	struct intel_display *display = to_intel_display(crtc);
469	unsigned long irqflags;
470	int position;
471
472	local_irq_save(irqflags);
473	intel_vblank_section_enter(display);
474
475	position = __intel_get_crtc_scanline(crtc);
476
477	intel_vblank_section_exit(display);
478	local_irq_restore(irqflags);
479
480	return position;
481}
482
483static bool pipe_scanline_is_moving(struct intel_display *display,
484				    enum pipe pipe)
485{
486	i915_reg_t reg = PIPEDSL(display, pipe);
487	u32 line1, line2;
488
489	line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
490	msleep(5);
491	line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK;
492
493	return line1 != line2;
494}
495
496static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state)
497{
498	struct intel_display *display = to_intel_display(crtc);
499	enum pipe pipe = crtc->pipe;
500	bool is_moving;
501	int ret;
502
503	/* Wait for the display line to settle/start moving */
504	ret = poll_timeout_us(is_moving = pipe_scanline_is_moving(display, pipe),
505			      is_moving == state,
506			      500, 100 * 1000, false);
507	if (ret)
508		drm_err(display->drm,
509			"pipe %c scanline %s wait timed out\n",
510			pipe_name(pipe), str_on_off(state));
511}
512
513void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
514{
515	wait_for_pipe_scanline_moving(crtc, false);
516}
517
518void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
519{
520	wait_for_pipe_scanline_moving(crtc, true);
521}
522
523static void intel_crtc_active_timings(struct drm_display_mode *mode,
524				      int *vmax_vblank_start,
525				      const struct intel_crtc_state *crtc_state,
526				      bool vrr_enable)
527{
528	drm_mode_init(mode, &crtc_state->hw.adjusted_mode);
529	*vmax_vblank_start = 0;
530
531	if (!vrr_enable)
532		return;
533
534	mode->crtc_vtotal = intel_vrr_vmax_vtotal(crtc_state);
535	mode->crtc_vblank_end = intel_vrr_vmax_vtotal(crtc_state);
536	mode->crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
537	*vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
538}
539
540void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
541				      bool vrr_enable)
542{
543	struct intel_display *display = to_intel_display(crtc_state);
544	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
545	u8 mode_flags = crtc_state->mode_flags;
546	struct drm_display_mode adjusted_mode;
547	int vmax_vblank_start = 0;
548	unsigned long irqflags;
549
550	intel_crtc_active_timings(&adjusted_mode, &vmax_vblank_start,
551				  crtc_state, vrr_enable);
552
553	if (vrr_enable)
554		drm_WARN_ON(display->drm, (mode_flags & I915_MODE_FLAG_VRR) == 0);
555	else
556		mode_flags &= ~I915_MODE_FLAG_VRR;
557
558	/*
559	 * Belts and suspenders locking to guarantee everyone sees 100%
560	 * consistent state during fastset seamless refresh rate changes.
561	 *
562	 * vblank_time_lock takes care of all drm_vblank.c stuff, and
563	 * uncore.lock takes care of __intel_get_crtc_scanline() which
564	 * may get called elsewhere as well.
565	 *
566	 * TODO maybe just protect everything (including
567	 * __intel_get_crtc_scanline()) with vblank_time_lock?
568	 * Need to audit everything to make sure it's safe.
569	 */
570	spin_lock_irqsave(&display->drm->vblank_time_lock, irqflags);
571	intel_vblank_section_enter(display);
572
573	drm_calc_timestamping_constants(&crtc->base, &adjusted_mode);
574
575	crtc->vmax_vblank_start = vmax_vblank_start;
576
577	crtc->mode_flags = mode_flags;
578
579	crtc->scanline_offset = intel_crtc_scanline_offset(crtc_state);
580	intel_vblank_section_exit(display);
581	spin_unlock_irqrestore(&display->drm->vblank_time_lock, irqflags);
582}
583
584int intel_mode_vdisplay(const struct drm_display_mode *mode)
585{
586	int vdisplay = mode->crtc_vdisplay;
587
588	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
589		vdisplay = DIV_ROUND_UP(vdisplay, 2);
590
591	return vdisplay;
592}
593
594int intel_mode_vblank_start(const struct drm_display_mode *mode)
595{
596	int vblank_start = mode->crtc_vblank_start;
597
598	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
599		vblank_start = DIV_ROUND_UP(vblank_start, 2);
600
601	return vblank_start;
602}
603
604int intel_mode_vblank_end(const struct drm_display_mode *mode)
605{
606	int vblank_end = mode->crtc_vblank_end;
607
608	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
609		vblank_end /= 2;
610
611	return vblank_end;
612}
613
614int intel_mode_vtotal(const struct drm_display_mode *mode)
615{
616	int vtotal = mode->crtc_vtotal;
617
618	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
619		vtotal /= 2;
620
621	return vtotal;
622}
623
624int intel_mode_vblank_delay(const struct drm_display_mode *mode)
625{
626	return intel_mode_vblank_start(mode) - intel_mode_vdisplay(mode);
627}
628
629static const struct intel_crtc_state *
630pre_commit_crtc_state(const struct intel_crtc_state *old_crtc_state,
631		      const struct intel_crtc_state *new_crtc_state)
632{
633	/*
634	 * During fastsets/etc. the transcoder is still
635	 * running with the old timings at this point.
636	 */
637	if (intel_crtc_needs_modeset(new_crtc_state))
638		return new_crtc_state;
639	else
640		return old_crtc_state;
641}
642
643const struct intel_crtc_state *
644intel_pre_commit_crtc_state(struct intel_atomic_state *state,
645			    struct intel_crtc *crtc)
646{
647	const struct intel_crtc_state *old_crtc_state =
648		intel_atomic_get_old_crtc_state(state, crtc);
649	const struct intel_crtc_state *new_crtc_state =
650		intel_atomic_get_new_crtc_state(state, crtc);
651
652	return pre_commit_crtc_state(old_crtc_state, new_crtc_state);
653}
654
655void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
656			     const struct intel_crtc_state *new_crtc_state,
657			     struct intel_vblank_evade_ctx *evade)
658{
659	struct intel_display *display = to_intel_display(new_crtc_state);
660	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
661	const struct intel_crtc_state *crtc_state;
662	const struct drm_display_mode *adjusted_mode;
663	int vblank_delay;
664
665	evade->crtc = crtc;
666
667	evade->need_vlv_dsi_wa = (display->platform.valleyview ||
668				  display->platform.cherryview) &&
669		intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
670
671	/* TODO: maybe just use the active timings here? */
672	crtc_state = pre_commit_crtc_state(old_crtc_state, new_crtc_state);
673
674	adjusted_mode = &crtc_state->hw.adjusted_mode;
675
676	if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
677		/* timing changes should happen with VRR disabled */
678		drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
679			    new_crtc_state->update_m_n || new_crtc_state->update_lrr);
680
681		if (intel_vrr_is_push_sent(crtc_state))
682			evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
683		else
684			evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
685
686		vblank_delay = crtc_state->set_context_latency;
687	} else {
688		evade->vblank_start = intel_mode_vblank_start(adjusted_mode);
689
690		vblank_delay = intel_mode_vblank_delay(adjusted_mode);
691	}
692
693	/* FIXME needs to be calibrated sensibly */
694	evade->min = evade->vblank_start - intel_usecs_to_scanlines(adjusted_mode,
695								    VBLANK_EVASION_TIME_US);
696	evade->max = evade->vblank_start - 1;
697
698	/*
699	 * M/N and TRANS_VTOTAL are double buffered on the transcoder's
700	 * undelayed vblank, so with seamless M/N and LRR we must evade
701	 * both vblanks.
702	 *
703	 * DSB execution waits for the transcoder's undelayed vblank,
704	 * hence we must kick off the commit before that.
705	 */
706	if (intel_color_uses_dsb(new_crtc_state) ||
707	    new_crtc_state->update_m_n || new_crtc_state->update_lrr)
708		evade->min -= vblank_delay;
709}
710
711/* must be called with vblank interrupt already enabled! */
712int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
713{
714	struct intel_crtc *crtc = evade->crtc;
715	struct intel_display *display = to_intel_display(crtc);
716	long timeout = msecs_to_jiffies_timeout(1);
717	wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
718	DEFINE_WAIT(wait);
719	int scanline;
720
721	if (evade->min <= 0 || evade->max <= 0)
722		return 0;
723
724	for (;;) {
725		/*
726		 * prepare_to_wait() has a memory barrier, which guarantees
727		 * other CPUs can see the task state update by the time we
728		 * read the scanline.
729		 */
730		prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
731
732		scanline = intel_get_crtc_scanline(crtc);
733		if (scanline < evade->min || scanline > evade->max)
734			break;
735
736		if (!timeout) {
737			drm_dbg_kms(display->drm,
738				    "Potential atomic update failure on pipe %c\n",
739				    pipe_name(crtc->pipe));
740			break;
741		}
742
743		local_irq_enable();
744
745		timeout = schedule_timeout(timeout);
746
747		local_irq_disable();
748	}
749
750	finish_wait(wq, &wait);
751
752	/*
753	 * On VLV/CHV DSI the scanline counter would appear to
754	 * increment approx. 1/3 of a scanline before start of vblank.
755	 * The registers still get latched at start of vblank however.
756	 * This means we must not write any registers on the first
757	 * line of vblank (since not the whole line is actually in
758	 * vblank). And unfortunately we can't use the interrupt to
759	 * wait here since it will fire too soon. We could use the
760	 * frame start interrupt instead since it will fire after the
761	 * critical scanline, but that would require more changes
762	 * in the interrupt code. So for now we'll just do the nasty
763	 * thing and poll for the bad scanline to pass us by.
764	 *
765	 * FIXME figure out if BXT+ DSI suffers from this as well
766	 */
767	while (evade->need_vlv_dsi_wa && scanline == evade->vblank_start)
768		scanline = intel_get_crtc_scanline(crtc);
769
770	return scanline;
771}
772
773int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state)
774{
775	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
776
777	if (crtc_state->vrr.enable)
778		return crtc_state->vrr.guardband;
779	else
780		return adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
781}