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intel_sprite_regs.h

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linux-6.19.14/drivers/gpu/drm/i915/display/intel_sprite_regs.h C 
  1/* SPDX-License-Identifier: MIT */
  2/* Copyright © 2024 Intel Corporation */
  3
  4#ifndef __INTEL_SPRITE_REGS__
  5#define __INTEL_SPRITE_REGS__
  6
  7#include "intel_display_reg_defs.h"
  8
  9/* g4x/ilk/snb video sprite */
 10#define _DVSACNTR		0x72180
 11#define _DVSBCNTR		0x73180
 12#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
 13#define   DVS_ENABLE			REG_BIT(31)
 14#define   DVS_PIPE_GAMMA_ENABLE		REG_BIT(30)
 15#define   DVS_YUV_RANGE_CORRECTION_DISABLE	REG_BIT(27)
 16#define   DVS_FORMAT_MASK		REG_GENMASK(26, 25)
 17#define   DVS_FORMAT_YUV422		REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
 18#define   DVS_FORMAT_RGBX101010		REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
 19#define   DVS_FORMAT_RGBX888		REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
 20#define   DVS_FORMAT_RGBX161616		REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
 21#define   DVS_PIPE_CSC_ENABLE		REG_BIT(24)
 22#define   DVS_SOURCE_KEY		REG_BIT(22)
 23#define   DVS_RGB_ORDER_XBGR		REG_BIT(20)
 24#define   DVS_YUV_FORMAT_BT709		REG_BIT(18)
 25#define   DVS_YUV_ORDER_MASK		REG_GENMASK(17, 16)
 26#define   DVS_YUV_ORDER_YUYV		REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
 27#define   DVS_YUV_ORDER_UYVY		REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
 28#define   DVS_YUV_ORDER_YVYU		REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
 29#define   DVS_YUV_ORDER_VYUY		REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
 30#define   DVS_ROTATE_180		REG_BIT(15)
 31#define   DVS_TRICKLE_FEED_DISABLE	REG_BIT(14)
 32#define   DVS_TILED			REG_BIT(10)
 33#define   DVS_DEST_KEY			REG_BIT(2)
 34
 35#define _DVSALINOFF		0x72184
 36#define _DVSBLINOFF		0x73184
 37#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
 38
 39#define _DVSASTRIDE		0x72188
 40#define _DVSBSTRIDE		0x73188
 41#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
 42
 43#define _DVSAPOS		0x7218c
 44#define _DVSBPOS		0x7318c
 45#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
 46#define   DVS_POS_Y_MASK		REG_GENMASK(31, 16)
 47#define   DVS_POS_Y(y)			REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
 48#define   DVS_POS_X_MASK		REG_GENMASK(15, 0)
 49#define   DVS_POS_X(x)			REG_FIELD_PREP(DVS_POS_X_MASK, (x))
 50
 51#define _DVSASIZE		0x72190
 52#define _DVSBSIZE		0x73190
 53#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
 54#define   DVS_HEIGHT_MASK		REG_GENMASK(31, 16)
 55#define   DVS_HEIGHT(h)			REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
 56#define   DVS_WIDTH_MASK		REG_GENMASK(15, 0)
 57#define   DVS_WIDTH(w)			REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
 58
 59#define _DVSAKEYVAL		0x72194
 60#define _DVSBKEYVAL		0x73194
 61#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
 62
 63#define _DVSAKEYMSK		0x72198
 64#define _DVSBKEYMSK		0x73198
 65#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
 66
 67#define _DVSASURF		0x7219c
 68#define _DVSBSURF		0x7319c
 69#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
 70#define   DVS_ADDR_MASK			REG_GENMASK(31, 12)
 71
 72#define _DVSAKEYMAXVAL		0x721a0
 73#define _DVSBKEYMAXVAL		0x731a0
 74#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
 75
 76#define _DVSATILEOFF		0x721a4
 77#define _DVSBTILEOFF		0x731a4
 78#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
 79#define   DVS_OFFSET_Y_MASK		REG_GENMASK(31, 16)
 80#define   DVS_OFFSET_Y(y)		REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
 81#define   DVS_OFFSET_X_MASK		REG_GENMASK(15, 0)
 82#define   DVS_OFFSET_X(x)		REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
 83
 84#define _DVSASURFLIVE		0x721ac
 85#define _DVSBSURFLIVE		0x731ac
 86#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
 87
 88#define _DVSAGAMC_G4X		0x721e0 /* g4x */
 89#define _DVSBGAMC_G4X		0x731e0 /* g4x */
 90#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
 91
 92#define _DVSASCALE		0x72204
 93#define _DVSBSCALE		0x73204
 94#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
 95#define   DVS_SCALE_ENABLE		REG_BIT(31)
 96#define   DVS_FILTER_MASK		REG_GENMASK(30, 29)
 97#define   DVS_FILTER_MEDIUM		REG_FIELD_PREP(DVS_FILTER_MASK, 0)
 98#define   DVS_FILTER_ENHANCING		REG_FIELD_PREP(DVS_FILTER_MASK, 1)
 99#define   DVS_FILTER_SOFTENING		REG_FIELD_PREP(DVS_FILTER_MASK, 2)
100#define   DVS_VERTICAL_OFFSET_HALF	REG_BIT(28) /* must be enabled below */
101#define   DVS_VERTICAL_OFFSET_ENABLE	REG_BIT(27)
102#define   DVS_SRC_WIDTH_MASK		REG_GENMASK(26, 16)
103#define   DVS_SRC_WIDTH(w)		REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
104#define   DVS_SRC_HEIGHT_MASK		REG_GENMASK(10, 0)
105#define   DVS_SRC_HEIGHT(h)		REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
106
107#define _DVSAGAMC_ILK		0x72300 /* ilk/snb */
108#define _DVSBGAMC_ILK		0x73300 /* ilk/snb */
109#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
110
111#define _DVSAGAMCMAX_ILK	0x72340 /* ilk/snb */
112#define _DVSBGAMCMAX_ILK	0x73340 /* ilk/snb */
113#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
114
115/* ivb/hsw/bdw sprite */
116#define _SPRA_CTL		0x70280
117#define _SPRB_CTL		0x71280
118#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
119#define   SPRITE_ENABLE				REG_BIT(31)
120#define   SPRITE_PIPE_GAMMA_ENABLE		REG_BIT(30)
121#define   SPRITE_YUV_RANGE_CORRECTION_DISABLE	REG_BIT(28)
122#define   SPRITE_FORMAT_MASK			REG_GENMASK(27, 25)
123#define   SPRITE_FORMAT_YUV422			REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
124#define   SPRITE_FORMAT_RGBX101010		REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
125#define   SPRITE_FORMAT_RGBX888			REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
126#define   SPRITE_FORMAT_RGBX161616		REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
127#define   SPRITE_FORMAT_YUV444			REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
128#define   SPRITE_FORMAT_XR_BGR101010		REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
129#define   SPRITE_PIPE_CSC_ENABLE		REG_BIT(24)
130#define   SPRITE_SOURCE_KEY			REG_BIT(22)
131#define   SPRITE_RGB_ORDER_RGBX			REG_BIT(20) /* only for 888 and 161616 */
132#define   SPRITE_YUV_TO_RGB_CSC_DISABLE		REG_BIT(19)
133#define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709	REG_BIT(18) /* 0 is BT601 */
134#define   SPRITE_YUV_ORDER_MASK			REG_GENMASK(17, 16)
135#define   SPRITE_YUV_ORDER_YUYV			REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
136#define   SPRITE_YUV_ORDER_UYVY			REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
137#define   SPRITE_YUV_ORDER_YVYU			REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
138#define   SPRITE_YUV_ORDER_VYUY			REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
139#define   SPRITE_ROTATE_180			REG_BIT(15)
140#define   SPRITE_TRICKLE_FEED_DISABLE		REG_BIT(14)
141#define   SPRITE_PLANE_GAMMA_DISABLE		REG_BIT(13)
142#define   SPRITE_TILED				REG_BIT(10)
143#define   SPRITE_DEST_KEY			REG_BIT(2)
144
145#define _SPRA_LINOFF		0x70284 /* ivb */
146#define _SPRB_LINOFF		0x71284 /* ivb */
147#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
148
149#define _SPRA_STRIDE		0x70288
150#define _SPRB_STRIDE		0x71288
151#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
152
153#define _SPRA_POS		0x7028c
154#define _SPRB_POS		0x7128c
155#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
156#define   SPRITE_POS_Y_MASK	REG_GENMASK(31, 16)
157#define   SPRITE_POS_Y(y)	REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
158#define   SPRITE_POS_X_MASK	REG_GENMASK(15, 0)
159#define   SPRITE_POS_X(x)	REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
160
161#define _SPRA_SIZE		0x70290
162#define _SPRB_SIZE		0x71290
163#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
164#define   SPRITE_HEIGHT_MASK	REG_GENMASK(31, 16)
165#define   SPRITE_HEIGHT(h)	REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
166#define   SPRITE_WIDTH_MASK	REG_GENMASK(15, 0)
167#define   SPRITE_WIDTH(w)	REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
168
169#define _SPRA_KEYVAL		0x70294
170#define _SPRB_KEYVAL		0x71294
171#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
172
173#define _SPRA_KEYMSK		0x70298
174#define _SPRB_KEYMSK		0x71298
175#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
176
177#define _SPRA_SURF		0x7029c
178#define _SPRB_SURF		0x7129c
179#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
180#define   SPRITE_ADDR_MASK	REG_GENMASK(31, 12)
181
182#define _SPRA_KEYMAX		0x702a0
183#define _SPRB_KEYMAX		0x712a0
184#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
185
186#define _SPRA_TILEOFF		0x702a4 /* ivb */
187#define _SPRB_TILEOFF		0x712a4 /* ivb */
188#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
189#define   SPRITE_OFFSET_Y_MASK	REG_GENMASK(31, 16)
190#define   SPRITE_OFFSET_Y(y)	REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
191#define   SPRITE_OFFSET_X_MASK	REG_GENMASK(15, 0)
192#define   SPRITE_OFFSET_X(x)	REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
193
194#define _SPRA_OFFSET		0x702a4 /* hsw/bdw */
195#define _SPRB_OFFSET		0x712a4 /* hsw/bdw */
196#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
197
198#define _SPRA_SURFLIVE		0x702ac
199#define _SPRB_SURFLIVE		0x712ac
200#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
201
202#define _SPRA_SCALE		0x70304 /* ivb */
203#define _SPRB_SCALE		0x71304 /* ivb */
204#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
205#define   SPRITE_SCALE_ENABLE			REG_BIT(31)
206#define   SPRITE_FILTER_MASK			REG_GENMASK(30, 29)
207#define   SPRITE_FILTER_MEDIUM			REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
208#define   SPRITE_FILTER_ENHANCING		REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
209#define   SPRITE_FILTER_SOFTENING		REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
210#define   SPRITE_VERTICAL_OFFSET_HALF		REG_BIT(28) /* must be enabled below */
211#define   SPRITE_VERTICAL_OFFSET_ENABLE		REG_BIT(27)
212#define   SPRITE_SRC_WIDTH_MASK			REG_GENMASK(26, 16)
213#define   SPRITE_SRC_WIDTH(w)			REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
214#define   SPRITE_SRC_HEIGHT_MASK		REG_GENMASK(10, 0)
215#define   SPRITE_SRC_HEIGHT(h)			REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
216
217#define _SPRA_GAMC		0x70400
218#define _SPRB_GAMC		0x71400
219#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
220
221#define _SPRA_GAMC16		0x70440
222#define _SPRB_GAMC16		0x71440
223#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
224
225#define _SPRA_GAMC17		0x7044c
226#define _SPRB_GAMC17		0x7144c
227#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
228
229/* vlv/chv sprite */
230#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
231	_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
232#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
233	_MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
234
235#define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
236#define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
237#define SPCNTR(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
238#define   SP_ENABLE			REG_BIT(31)
239#define   SP_PIPE_GAMMA_ENABLE		REG_BIT(30)
240#define   SP_FORMAT_MASK		REG_GENMASK(29, 26)
241#define   SP_FORMAT_YUV422		REG_FIELD_PREP(SP_FORMAT_MASK, 0)
242#define   SP_FORMAT_8BPP		REG_FIELD_PREP(SP_FORMAT_MASK, 2)
243#define   SP_FORMAT_BGR565		REG_FIELD_PREP(SP_FORMAT_MASK, 5)
244#define   SP_FORMAT_BGRX8888		REG_FIELD_PREP(SP_FORMAT_MASK, 6)
245#define   SP_FORMAT_BGRA8888		REG_FIELD_PREP(SP_FORMAT_MASK, 7)
246#define   SP_FORMAT_RGBX1010102		REG_FIELD_PREP(SP_FORMAT_MASK, 8)
247#define   SP_FORMAT_RGBA1010102		REG_FIELD_PREP(SP_FORMAT_MASK, 9)
248#define   SP_FORMAT_BGRX1010102		REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
249#define   SP_FORMAT_BGRA1010102		REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
250#define   SP_FORMAT_RGBX8888		REG_FIELD_PREP(SP_FORMAT_MASK, 14)
251#define   SP_FORMAT_RGBA8888		REG_FIELD_PREP(SP_FORMAT_MASK, 15)
252#define   SP_ALPHA_PREMULTIPLY		REG_BIT(23) /* CHV pipe B */
253#define   SP_SOURCE_KEY			REG_BIT(22)
254#define   SP_YUV_FORMAT_BT709		REG_BIT(18)
255#define   SP_YUV_ORDER_MASK		REG_GENMASK(17, 16)
256#define   SP_YUV_ORDER_YUYV		REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
257#define   SP_YUV_ORDER_UYVY		REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
258#define   SP_YUV_ORDER_YVYU		REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
259#define   SP_YUV_ORDER_VYUY		REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
260#define   SP_ROTATE_180			REG_BIT(15)
261#define   SP_TILED			REG_BIT(10)
262#define   SP_MIRROR			REG_BIT(8) /* CHV pipe B */
263
264#define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
265#define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
266#define SPLINOFF(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
267
268#define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
269#define _SPBSTRIDE		(VLV_DISPLAY_BASE + 0x72288)
270#define SPSTRIDE(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
271
272#define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
273#define _SPBPOS			(VLV_DISPLAY_BASE + 0x7228c)
274#define SPPOS(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
275#define   SP_POS_Y_MASK			REG_GENMASK(31, 16)
276#define   SP_POS_Y(y)			REG_FIELD_PREP(SP_POS_Y_MASK, (y))
277#define   SP_POS_X_MASK			REG_GENMASK(15, 0)
278#define   SP_POS_X(x)			REG_FIELD_PREP(SP_POS_X_MASK, (x))
279
280#define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
281#define _SPBSIZE		(VLV_DISPLAY_BASE + 0x72290)
282#define SPSIZE(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
283#define   SP_HEIGHT_MASK		REG_GENMASK(31, 16)
284#define   SP_HEIGHT(h)			REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
285#define   SP_WIDTH_MASK			REG_GENMASK(15, 0)
286#define   SP_WIDTH(w)			REG_FIELD_PREP(SP_WIDTH_MASK, (w))
287
288#define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
289#define _SPBKEYMINVAL		(VLV_DISPLAY_BASE + 0x72294)
290#define SPKEYMINVAL(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
291
292#define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
293#define _SPBKEYMSK		(VLV_DISPLAY_BASE + 0x72298)
294#define SPKEYMSK(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
295
296#define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
297#define _SPBSURF		(VLV_DISPLAY_BASE + 0x7229c)
298#define SPSURF(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
299#define   SP_ADDR_MASK			REG_GENMASK(31, 12)
300
301#define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
302#define _SPBKEYMAXVAL		(VLV_DISPLAY_BASE + 0x722a0)
303#define SPKEYMAXVAL(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
304
305#define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
306#define _SPBTILEOFF		(VLV_DISPLAY_BASE + 0x722a4)
307#define SPTILEOFF(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
308#define   SP_OFFSET_Y_MASK		REG_GENMASK(31, 16)
309#define   SP_OFFSET_Y(y)		REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
310#define   SP_OFFSET_X_MASK		REG_GENMASK(15, 0)
311#define   SP_OFFSET_X(x)		REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
312
313#define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
314#define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
315#define SPCONSTALPHA(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
316#define   SP_CONST_ALPHA_ENABLE		REG_BIT(31)
317#define   SP_CONST_ALPHA_MASK		REG_GENMASK(7, 0)
318#define   SP_CONST_ALPHA(alpha)		REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
319
320#define _SPASURFLIVE		(VLV_DISPLAY_BASE + 0x721ac)
321#define _SPBSURFLIVE		(VLV_DISPLAY_BASE + 0x722ac)
322#define SPSURFLIVE(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
323
324#define _SPACLRC0		(VLV_DISPLAY_BASE + 0x721d0)
325#define _SPBCLRC0		(VLV_DISPLAY_BASE + 0x722d0)
326#define SPCLRC0(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
327#define   SP_CONTRAST_MASK		REG_GENMASK(26, 18)
328#define   SP_CONTRAST(x)		REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
329#define   SP_BRIGHTNESS_MASK		REG_GENMASK(7, 0)
330#define   SP_BRIGHTNESS(x)		REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
331
332#define _SPACLRC1		(VLV_DISPLAY_BASE + 0x721d4)
333#define _SPBCLRC1		(VLV_DISPLAY_BASE + 0x722d4)
334#define SPCLRC1(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
335#define   SP_SH_SIN_MASK		REG_GENMASK(26, 16)
336#define   SP_SH_SIN(x)			REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
337#define   SP_SH_COS_MASK		REG_GENMASK(9, 0)
338#define   SP_SH_COS(x)			REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
339
340#define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721e0)
341#define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722e0)
342#define SPGAMC(pipe, plane_id, i)	_MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
343
344/*
345 * CHV pipe B sprite CSC
346 *
347 * |cr|   |c0 c1 c2|   |cr + cr_ioff|   |cr_ooff|
348 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
349 * |cb|   |c6 c7 c8|   |cb + cr_ioff|   |cb_ooff|
350 */
351#define _MMIO_CHV_SPCSC(plane_id, reg) \
352	_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
353
354#define SPCSCYGOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d900)
355#define SPCSCCBOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d904)
356#define SPCSCCROFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d908)
357#define  SPCSC_OOFF_MASK	REG_GENMASK(26, 16)
358#define  SPCSC_OOFF(x)		REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
359#define  SPCSC_IOFF_MASK	REG_GENMASK(10, 0)
360#define  SPCSC_IOFF(x)		REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
361
362#define SPCSCC01(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d90c)
363#define SPCSCC23(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d910)
364#define SPCSCC45(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d914)
365#define SPCSCC67(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d918)
366#define SPCSCC8(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d91c)
367#define  SPCSC_C1_MASK		REG_GENMASK(30, 16)
368#define  SPCSC_C1(x)		REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
369#define  SPCSC_C0_MASK		REG_GENMASK(14, 0)
370#define  SPCSC_C0(x)		REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
371
372#define SPCSCYGICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d920)
373#define SPCSCCBICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d924)
374#define SPCSCCRICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d928)
375#define  SPCSC_IMAX_MASK	REG_GENMASK(26, 16)
376#define  SPCSC_IMAX(x)		REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
377#define  SPCSC_IMIN_MASK	REG_GENMASK(10, 0)
378#define  SPCSC_IMIN(x)		REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
379
380#define SPCSCYGOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d92c)
381#define SPCSCCBOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d930)
382#define SPCSCCROCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d934)
383#define  SPCSC_OMAX_MASK	REG_GENMASK(25, 16)
384#define  SPCSC_OMAX(x)		REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
385#define  SPCSC_OMIN_MASK	REG_GENMASK(9, 0)
386#define  SPCSC_OMIN(x)		REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
387
388#endif /* __INTEL_SPRITE_REGS__ */
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