intel_snps_phy.c

   1// SPDX-License-Identifier: MIT
   2/*
   3 * Copyright © 2019 Intel Corporation
   4 */
   5
   6#include <linux/math.h>
   7
   8#include <drm/drm_print.h>
   9
  10#include "intel_ddi.h"
  11#include "intel_ddi_buf_trans.h"
  12#include "intel_de.h"
  13#include "intel_display_regs.h"
  14#include "intel_display_types.h"
  15#include "intel_display_utils.h"
  16#include "intel_snps_hdmi_pll.h"
  17#include "intel_snps_phy.h"
  18#include "intel_snps_phy_regs.h"
  19
  20/**
  21 * DOC: Synopsis PHY support
  22 *
  23 * Synopsis PHYs are primarily programmed by looking up magic register values
  24 * in tables rather than calculating the necessary values at runtime.
  25 *
  26 * Of special note is that the SNPS PHYs include a dedicated port PLL, known as
  27 * an "MPLLB."  The MPLLB replaces the shared DPLL functionality used on other
  28 * platforms and must be programming directly during the modeset sequence
  29 * since it is not handled by the shared DPLL framework as on other platforms.
  30 */
  31
  32void intel_snps_phy_wait_for_calibration(struct intel_display *display)
  33{
  34	enum phy phy;
  35
  36	for_each_phy_masked(phy, ~0) {
  37		if (!intel_phy_is_snps(display, phy))
  38			continue;
  39
  40		/*
  41		 * If calibration does not complete successfully, we'll remember
  42		 * which phy was affected and skip setup of the corresponding
  43		 * output later.
  44		 */
  45		if (intel_de_wait_for_clear_ms(display, DG2_PHY_MISC(phy),
  46					       DG2_PHY_DP_TX_ACK_MASK, 25))
  47			display->snps.phy_failed_calibration |= BIT(phy);
  48	}
  49}
  50
  51void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder,
  52					   bool enable)
  53{
  54	struct intel_display *display = to_intel_display(encoder);
  55	enum phy phy = intel_encoder_to_phy(encoder);
  56	u32 val;
  57
  58	if (!intel_encoder_is_snps(encoder))
  59		return;
  60
  61	val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR,
  62			     enable ? 2 : 3);
  63	intel_de_rmw(display, SNPS_PHY_TX_REQ(phy),
  64		     SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val);
  65}
  66
  67void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
  68				      const struct intel_crtc_state *crtc_state)
  69{
  70	struct intel_display *display = to_intel_display(encoder);
  71	const struct intel_ddi_buf_trans *trans;
  72	enum phy phy = intel_encoder_to_phy(encoder);
  73	int n_entries, ln;
  74
  75	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
  76	if (drm_WARN_ON_ONCE(display->drm, !trans))
  77		return;
  78
  79	for (ln = 0; ln < 4; ln++) {
  80		int level = intel_ddi_level(encoder, crtc_state, ln);
  81		u32 val = 0;
  82
  83		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing);
  84		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor);
  85		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor);
  86
  87		intel_de_write(display, SNPS_PHY_TX_EQ(ln, phy), val);
  88	}
  89}
  90
  91/*
  92 * Basic DP link rates with 100 MHz reference clock.
  93 */
  94
  95static const struct intel_mpllb_state dg2_dp_rbr_100 = {
  96	.clock = 162000,
  97	.ref_control =
  98		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
  99	.mpllb_cp =
 100		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
 101		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
 102		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
 103		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
 104	.mpllb_div =
 105		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 106		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
 107		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 108		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 109		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
 110	.mpllb_div2 =
 111		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
 112		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),
 113	.mpllb_fracn1 =
 114		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 115		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 116		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
 117	.mpllb_fracn2 =
 118		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
 119		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),
 120};
 121
 122static const struct intel_mpllb_state dg2_dp_hbr1_100 = {
 123	.clock = 270000,
 124	.ref_control =
 125		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 126	.mpllb_cp =
 127		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
 128		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
 129		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
 130		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
 131	.mpllb_div =
 132		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 133		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
 134		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 135		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
 136	.mpllb_div2 =
 137		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
 138		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),
 139	.mpllb_fracn1 =
 140		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 141		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
 142};
 143
 144static const struct intel_mpllb_state dg2_dp_hbr2_100 = {
 145	.clock = 540000,
 146	.ref_control =
 147		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 148	.mpllb_cp =
 149		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
 150		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
 151		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
 152		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
 153	.mpllb_div =
 154		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 155		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 156		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
 157	.mpllb_div2 =
 158		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
 159		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),
 160	.mpllb_fracn1 =
 161		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 162		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
 163};
 164
 165static const struct intel_mpllb_state dg2_dp_hbr3_100 = {
 166	.clock = 810000,
 167	.ref_control =
 168		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 169	.mpllb_cp =
 170		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
 171		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
 172		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
 173		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
 174	.mpllb_div =
 175		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 176		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
 177	.mpllb_div2 =
 178		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
 179		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 292),
 180	.mpllb_fracn1 =
 181		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 182		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
 183};
 184
 185static const struct intel_mpllb_state dg2_dp_uhbr10_100 = {
 186	.clock = 1000000,
 187	.ref_control =
 188		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 189	.mpllb_cp =
 190		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
 191		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 21) |
 192		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
 193		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
 194	.mpllb_div =
 195		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 196		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
 197		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
 198		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 199		REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
 200		REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
 201		REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) |
 202		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
 203	.mpllb_div2 =
 204		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
 205		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 368),
 206	.mpllb_fracn1 =
 207		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 208		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
 209
 210	/*
 211	 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
 212	 */
 213	.mpllb_sscen =
 214		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
 215		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 58982),
 216	.mpllb_sscstep =
 217		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101),
 218};
 219
 220static const struct intel_mpllb_state dg2_dp_uhbr13_100 = {
 221	.clock = 1350000,
 222	.ref_control =
 223		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 224	.mpllb_cp =
 225		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
 226		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) |
 227		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
 228		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
 229	.mpllb_div =
 230		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 231		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
 232		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
 233		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 234		REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
 235		REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
 236		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
 237	.mpllb_div2 =
 238		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
 239		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508),
 240	.mpllb_fracn1 =
 241		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 242		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
 243
 244	/*
 245	 * SSC will be enabled, DP UHBR has a minimum SSC requirement.
 246	 */
 247	.mpllb_sscen =
 248		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
 249		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626),
 250	.mpllb_sscstep =
 251		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737),
 252};
 253
 254static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {
 255	&dg2_dp_rbr_100,
 256	&dg2_dp_hbr1_100,
 257	&dg2_dp_hbr2_100,
 258	&dg2_dp_hbr3_100,
 259	&dg2_dp_uhbr10_100,
 260	&dg2_dp_uhbr13_100,
 261	NULL,
 262};
 263
 264/*
 265 * eDP link rates with 100 MHz reference clock.
 266 */
 267
 268static const struct intel_mpllb_state dg2_edp_r216 = {
 269	.clock = 216000,
 270	.ref_control =
 271		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 272	.mpllb_cp =
 273		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
 274		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
 275		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
 276		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
 277	.mpllb_div =
 278		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 279		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
 280		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 281		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
 282	.mpllb_div2 =
 283		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
 284		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),
 285	.mpllb_fracn1 =
 286		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 287		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 288		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
 289	.mpllb_fracn2 =
 290		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
 291		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),
 292	.mpllb_sscen =
 293		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
 294		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),
 295	.mpllb_sscstep =
 296		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),
 297};
 298
 299static const struct intel_mpllb_state dg2_edp_r243 = {
 300	.clock = 243000,
 301	.ref_control =
 302		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 303	.mpllb_cp =
 304		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
 305		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
 306		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
 307		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
 308	.mpllb_div =
 309		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 310		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
 311		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 312		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
 313	.mpllb_div2 =
 314		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
 315		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 356),
 316	.mpllb_fracn1 =
 317		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 318		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 319		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
 320	.mpllb_fracn2 =
 321		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
 322		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
 323	.mpllb_sscen =
 324		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
 325		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 57331),
 326	.mpllb_sscstep =
 327		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 73971),
 328};
 329
 330static const struct intel_mpllb_state dg2_edp_r324 = {
 331	.clock = 324000,
 332	.ref_control =
 333		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 334	.mpllb_cp =
 335		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
 336		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
 337		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
 338		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
 339	.mpllb_div =
 340		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 341		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
 342		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 343		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 344		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
 345	.mpllb_div2 =
 346		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
 347		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),
 348	.mpllb_fracn1 =
 349		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 350		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 351		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
 352	.mpllb_fracn2 =
 353		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
 354		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),
 355	.mpllb_sscen =
 356		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
 357		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 38221),
 358	.mpllb_sscstep =
 359		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 49314),
 360};
 361
 362static const struct intel_mpllb_state dg2_edp_r432 = {
 363	.clock = 432000,
 364	.ref_control =
 365		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 366	.mpllb_cp =
 367		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
 368		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
 369		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
 370		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
 371	.mpllb_div =
 372		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 373		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
 374		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 375		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
 376	.mpllb_div2 =
 377		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
 378		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),
 379	.mpllb_fracn1 =
 380		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 381		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 382		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
 383	.mpllb_fracn2 =
 384		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
 385		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),
 386	.mpllb_sscen =
 387		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
 388		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),
 389	.mpllb_sscstep =
 390		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),
 391};
 392
 393static const struct intel_mpllb_state * const dg2_edp_tables[] = {
 394	&dg2_dp_rbr_100,
 395	&dg2_edp_r216,
 396	&dg2_edp_r243,
 397	&dg2_dp_hbr1_100,
 398	&dg2_edp_r324,
 399	&dg2_edp_r432,
 400	&dg2_dp_hbr2_100,
 401	&dg2_dp_hbr3_100,
 402	NULL,
 403};
 404
 405/*
 406 * HDMI link rates with 100 MHz reference clock.
 407 */
 408
 409static const struct intel_mpllb_state dg2_hdmi_25_175 = {
 410	.clock = 25175,
 411	.ref_control =
 412		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 413	.mpllb_cp =
 414		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
 415		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
 416		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 417		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 418	.mpllb_div =
 419		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 420		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
 421		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 422		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
 423	.mpllb_div2 =
 424		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 425		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
 426		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 427	.mpllb_fracn1 =
 428		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 429		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 430		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 143),
 431	.mpllb_fracn2 =
 432		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36663) |
 433		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 71),
 434	.mpllb_sscen =
 435		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 436};
 437
 438static const struct intel_mpllb_state dg2_hdmi_27_0 = {
 439	.clock = 27000,
 440	.ref_control =
 441		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 442	.mpllb_cp =
 443		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
 444		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
 445		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 446		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 447	.mpllb_div =
 448		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 449		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
 450		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 451		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
 452	.mpllb_div2 =
 453		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 454		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
 455		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 456	.mpllb_fracn1 =
 457		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 458		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 459		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
 460	.mpllb_fracn2 =
 461		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
 462		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
 463	.mpllb_sscen =
 464		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 465};
 466
 467static const struct intel_mpllb_state dg2_hdmi_74_25 = {
 468	.clock = 74250,
 469	.ref_control =
 470		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 471	.mpllb_cp =
 472		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
 473		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
 474		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 475		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 476	.mpllb_div =
 477		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 478		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
 479		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 480		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 481		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
 482	.mpllb_div2 =
 483		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 484		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
 485		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 486	.mpllb_fracn1 =
 487		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 488		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 489		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
 490	.mpllb_fracn2 =
 491		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
 492		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
 493	.mpllb_sscen =
 494		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 495};
 496
 497static const struct intel_mpllb_state dg2_hdmi_148_5 = {
 498	.clock = 148500,
 499	.ref_control =
 500		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 501	.mpllb_cp =
 502		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
 503		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
 504		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 505		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 506	.mpllb_div =
 507		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 508		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
 509		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 510		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 511		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
 512	.mpllb_div2 =
 513		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 514		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
 515		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 516	.mpllb_fracn1 =
 517		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 518		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 519		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
 520	.mpllb_fracn2 =
 521		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
 522		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
 523	.mpllb_sscen =
 524		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 525};
 526
 527/* values in the below table are calculated using the algo */
 528static const struct intel_mpllb_state dg2_hdmi_25200 = {
 529	.clock = 25200,
 530	.ref_control =
 531		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 532	.mpllb_cp =
 533		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
 534		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 535		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 536		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 537	.mpllb_div =
 538		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 539		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
 540		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 541		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 542		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
 543	.mpllb_div2 =
 544		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 545		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
 546		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 547	.mpllb_fracn1 =
 548		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 549		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 550		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
 551	.mpllb_fracn2 =
 552		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 41943) |
 553		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2621),
 554	.mpllb_sscen =
 555		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 556};
 557
 558static const struct intel_mpllb_state dg2_hdmi_27027 = {
 559	.clock = 27027,
 560	.ref_control =
 561		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 562	.mpllb_cp =
 563		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
 564		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 565		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 566		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 567	.mpllb_div =
 568		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 569		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
 570		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 571		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 572		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
 573	.mpllb_div2 =
 574		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 575		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
 576		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 577	.mpllb_fracn1 =
 578		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 579		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 580		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
 581	.mpllb_fracn2 =
 582		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 31876) |
 583		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 46555),
 584	.mpllb_sscen =
 585		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 586};
 587
 588static const struct intel_mpllb_state dg2_hdmi_28320 = {
 589	.clock = 28320,
 590	.ref_control =
 591		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 592	.mpllb_cp =
 593		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
 594		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 595		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 596		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 597	.mpllb_div =
 598		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 599		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
 600		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 601		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 602		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
 603	.mpllb_div2 =
 604		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 605		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 148) |
 606		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 607	.mpllb_fracn1 =
 608		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 609		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 610		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
 611	.mpllb_fracn2 =
 612		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40894) |
 613		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 30408),
 614	.mpllb_sscen =
 615		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 616};
 617
 618static const struct intel_mpllb_state dg2_hdmi_30240 = {
 619	.clock = 30240,
 620	.ref_control =
 621		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 622	.mpllb_cp =
 623		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
 624		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 625		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 626		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 627	.mpllb_div =
 628		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 629		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
 630		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 631		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 632		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
 633	.mpllb_div2 =
 634		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 635		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) |
 636		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 637	.mpllb_fracn1 =
 638		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 639		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 640		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
 641	.mpllb_fracn2 =
 642		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 50331) |
 643		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 42466),
 644	.mpllb_sscen =
 645		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 646};
 647
 648static const struct intel_mpllb_state dg2_hdmi_31500 = {
 649	.clock = 31500,
 650	.ref_control =
 651		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 652	.mpllb_cp =
 653		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
 654		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 655		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 656		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 657	.mpllb_div =
 658		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 659		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
 660		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 661		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 662		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
 663	.mpllb_div2 =
 664		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 665		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 68) |
 666		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 667	.mpllb_fracn1 =
 668		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 669		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 670		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
 671	.mpllb_fracn2 =
 672		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
 673		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
 674	.mpllb_sscen =
 675		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 676};
 677
 678static const struct intel_mpllb_state dg2_hdmi_36000 = {
 679	.clock = 36000,
 680	.ref_control =
 681		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 682	.mpllb_cp =
 683		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
 684		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 685		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 686		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 687	.mpllb_div =
 688		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 689		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
 690		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 691		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 692		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
 693	.mpllb_div2 =
 694		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 695		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 82) |
 696		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 697	.mpllb_fracn1 =
 698		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 699		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 700		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
 701	.mpllb_fracn2 =
 702		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
 703		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),
 704	.mpllb_sscen =
 705		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 706};
 707
 708static const struct intel_mpllb_state dg2_hdmi_40000 = {
 709	.clock = 40000,
 710	.ref_control =
 711		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 712	.mpllb_cp =
 713		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
 714		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 715		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 716		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 717	.mpllb_div =
 718		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 719		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
 720		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
 721		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 722		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
 723	.mpllb_div2 =
 724		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 725		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) |
 726		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 727	.mpllb_fracn1 =
 728		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 729		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
 730		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
 731	.mpllb_fracn2 =
 732		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
 733		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
 734	.mpllb_sscen =
 735		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 736};
 737
 738static const struct intel_mpllb_state dg2_hdmi_49500 = {
 739	.clock = 49500,
 740	.ref_control =
 741		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 742	.mpllb_cp =
 743		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
 744		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 745		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 746		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 747	.mpllb_div =
 748		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 749		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
 750		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 751		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 752		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),
 753	.mpllb_div2 =
 754		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 755		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 126) |
 756		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 757	.mpllb_fracn1 =
 758		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 759		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 760		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
 761	.mpllb_fracn2 =
 762		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
 763		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
 764	.mpllb_sscen =
 765		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 766};
 767
 768static const struct intel_mpllb_state dg2_hdmi_50000 = {
 769	.clock = 50000,
 770	.ref_control =
 771		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 772	.mpllb_cp =
 773		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
 774		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 775		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 776		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 777	.mpllb_div =
 778		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 779		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
 780		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
 781		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 782		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),
 783	.mpllb_div2 =
 784		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 785		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
 786		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 787	.mpllb_fracn1 =
 788		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 789		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
 790		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
 791	.mpllb_fracn2 =
 792		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
 793		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
 794	.mpllb_sscen =
 795		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 796};
 797
 798static const struct intel_mpllb_state dg2_hdmi_57284 = {
 799	.clock = 57284,
 800	.ref_control =
 801		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 802	.mpllb_cp =
 803		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
 804		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 805		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 806		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 807	.mpllb_div =
 808		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 809		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
 810		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 811		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 812		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
 813	.mpllb_div2 =
 814		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 815		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 150) |
 816		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 817	.mpllb_fracn1 =
 818		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 819		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 820		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
 821	.mpllb_fracn2 =
 822		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 42886) |
 823		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 49701),
 824	.mpllb_sscen =
 825		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 826};
 827
 828static const struct intel_mpllb_state dg2_hdmi_58000 = {
 829	.clock = 58000,
 830	.ref_control =
 831		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 832	.mpllb_cp =
 833		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
 834		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 835		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 836		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 837	.mpllb_div =
 838		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 839		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
 840		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 841		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 842		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
 843	.mpllb_div2 =
 844		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 845		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) |
 846		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 847	.mpllb_fracn1 =
 848		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 849		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 850		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
 851	.mpllb_fracn2 =
 852		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
 853		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
 854	.mpllb_sscen =
 855		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 856};
 857
 858static const struct intel_mpllb_state dg2_hdmi_65000 = {
 859	.clock = 65000,
 860	.ref_control =
 861		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 862	.mpllb_cp =
 863		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
 864		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 865		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 866		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 867	.mpllb_div =
 868		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 869		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
 870		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
 871		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 872		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
 873	.mpllb_div2 =
 874		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 875		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) |
 876		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 877	.mpllb_fracn1 =
 878		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 879		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
 880		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
 881	.mpllb_fracn2 =
 882		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
 883		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
 884	.mpllb_sscen =
 885		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 886};
 887
 888static const struct intel_mpllb_state dg2_hdmi_71000 = {
 889	.clock = 71000,
 890	.ref_control =
 891		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 892	.mpllb_cp =
 893		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
 894		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 895		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 896		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 897	.mpllb_div =
 898		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 899		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
 900		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 901		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 902		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
 903	.mpllb_div2 =
 904		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 905		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 80) |
 906		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 907	.mpllb_fracn1 =
 908		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 909		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 910		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
 911	.mpllb_fracn2 =
 912		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
 913		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
 914	.mpllb_sscen =
 915		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 916};
 917
 918static const struct intel_mpllb_state dg2_hdmi_74176 = {
 919	.clock = 74176,
 920	.ref_control =
 921		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 922	.mpllb_cp =
 923		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
 924		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 925		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 926		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 927	.mpllb_div =
 928		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 929		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
 930		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
 931		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 932		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
 933	.mpllb_div2 =
 934		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 935		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
 936		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 937	.mpllb_fracn1 =
 938		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 939		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
 940		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
 941	.mpllb_fracn2 =
 942		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) |
 943		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829),
 944	.mpllb_sscen =
 945		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 946};
 947
 948static const struct intel_mpllb_state dg2_hdmi_75000 = {
 949	.clock = 75000,
 950	.ref_control =
 951		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 952	.mpllb_cp =
 953		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
 954		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 955		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 956		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 957	.mpllb_div =
 958		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 959		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
 960		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
 961		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 962		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
 963	.mpllb_div2 =
 964		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 965		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 88) |
 966		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 967	.mpllb_fracn1 =
 968		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 969		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
 970		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
 971	.mpllb_fracn2 =
 972		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
 973		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
 974	.mpllb_sscen =
 975		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
 976};
 977
 978static const struct intel_mpllb_state dg2_hdmi_78750 = {
 979	.clock = 78750,
 980	.ref_control =
 981		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
 982	.mpllb_cp =
 983		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
 984		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
 985		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
 986		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
 987	.mpllb_div =
 988		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
 989		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
 990		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
 991		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
 992		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
 993	.mpllb_div2 =
 994		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
 995		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) |
 996		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
 997	.mpllb_fracn1 =
 998		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
 999		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
1000		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1001	.mpllb_fracn2 =
1002		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
1003		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
1004	.mpllb_sscen =
1005		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1006};
1007
1008static const struct intel_mpllb_state dg2_hdmi_85500 = {
1009	.clock = 85500,
1010	.ref_control =
1011		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1012	.mpllb_cp =
1013		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1014		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1015		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1016		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1017	.mpllb_div =
1018		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1019		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1020		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1021		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1022		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
1023	.mpllb_div2 =
1024		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1025		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 104) |
1026		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1027	.mpllb_fracn1 =
1028		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1029		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1030		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1031	.mpllb_fracn2 =
1032		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1033		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
1034	.mpllb_sscen =
1035		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1036};
1037
1038static const struct intel_mpllb_state dg2_hdmi_88750 = {
1039	.clock = 88750,
1040	.ref_control =
1041		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1042	.mpllb_cp =
1043		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1044		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
1045		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1046		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1047	.mpllb_div =
1048		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1049		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1050		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
1051		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1052		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),
1053	.mpllb_div2 =
1054		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1055		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 110) |
1056		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1057	.mpllb_fracn1 =
1058		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1059		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
1060		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1061	.mpllb_fracn2 =
1062		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
1063		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
1064	.mpllb_sscen =
1065		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1066};
1067
1068static const struct intel_mpllb_state dg2_hdmi_106500 = {
1069	.clock = 106500,
1070	.ref_control =
1071		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1072	.mpllb_cp =
1073		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1074		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1075		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1076		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1077	.mpllb_div =
1078		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1079		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1080		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1081		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1082		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1083	.mpllb_div2 =
1084		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1085		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 138) |
1086		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1087	.mpllb_fracn1 =
1088		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1089		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1090		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1091	.mpllb_fracn2 =
1092		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
1093		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
1094	.mpllb_sscen =
1095		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1096};
1097
1098static const struct intel_mpllb_state dg2_hdmi_108000 = {
1099	.clock = 108000,
1100	.ref_control =
1101		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1102	.mpllb_cp =
1103		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1104		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1105		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1106		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1107	.mpllb_div =
1108		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1109		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1110		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1111		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1112		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1113	.mpllb_div2 =
1114		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1115		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
1116		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1117	.mpllb_fracn1 =
1118		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1119		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1120		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1121	.mpllb_fracn2 =
1122		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1123		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
1124	.mpllb_sscen =
1125		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1126};
1127
1128static const struct intel_mpllb_state dg2_hdmi_115500 = {
1129	.clock = 115500,
1130	.ref_control =
1131		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1132	.mpllb_cp =
1133		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1134		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1135		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1136		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1137	.mpllb_div =
1138		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1139		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1140		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1141		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1142		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1143	.mpllb_div2 =
1144		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1145		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) |
1146		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1147	.mpllb_fracn1 =
1148		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1149		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1150		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1151	.mpllb_fracn2 =
1152		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1153		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
1154	.mpllb_sscen =
1155		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1156};
1157
1158static const struct intel_mpllb_state dg2_hdmi_119000 = {
1159	.clock = 119000,
1160	.ref_control =
1161		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1162	.mpllb_cp =
1163		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1164		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1165		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1166		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1167	.mpllb_div =
1168		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1169		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
1170		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1171		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1172		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1173	.mpllb_div2 =
1174		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1175		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 158) |
1176		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1177	.mpllb_fracn1 =
1178		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1179		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1180		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1181	.mpllb_fracn2 =
1182		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
1183		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
1184	.mpllb_sscen =
1185		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1186};
1187
1188static const struct intel_mpllb_state dg2_hdmi_135000 = {
1189	.clock = 135000,
1190	.ref_control =
1191		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1192	.mpllb_cp =
1193		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1194		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
1195		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1196		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1197	.mpllb_div =
1198		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1199		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1200		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
1201		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1202		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1203	.mpllb_div2 =
1204		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1205		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 76) |
1206		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1207	.mpllb_fracn1 =
1208		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1209		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
1210		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1211	.mpllb_fracn2 =
1212		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
1213		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
1214	.mpllb_sscen =
1215		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1216};
1217
1218static const struct intel_mpllb_state dg2_hdmi_138500 = {
1219	.clock = 138500,
1220	.ref_control =
1221		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1222	.mpllb_cp =
1223		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1224		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1225		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1226		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1227	.mpllb_div =
1228		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1229		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1230		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1231		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1232		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1233	.mpllb_div2 =
1234		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1235		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 78) |
1236		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1237	.mpllb_fracn1 =
1238		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1239		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1240		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1241	.mpllb_fracn2 =
1242		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1243		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
1244	.mpllb_sscen =
1245		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1246};
1247
1248static const struct intel_mpllb_state dg2_hdmi_147160 = {
1249	.clock = 147160,
1250	.ref_control =
1251		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1252	.mpllb_cp =
1253		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1254		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1255		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1256		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1257	.mpllb_div =
1258		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1259		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1260		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1261		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1262		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1263	.mpllb_div2 =
1264		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1265		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 84) |
1266		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1267	.mpllb_fracn1 =
1268		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1269		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1270		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1271	.mpllb_fracn2 =
1272		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 56623) |
1273		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 6815),
1274	.mpllb_sscen =
1275		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1276};
1277
1278static const struct intel_mpllb_state dg2_hdmi_148352 = {
1279	.clock = 148352,
1280	.ref_control =
1281		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1282	.mpllb_cp =
1283		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1284		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1285		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1286		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1287	.mpllb_div =
1288		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1289		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1290		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1291		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1292		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1293	.mpllb_div2 =
1294		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1295		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1296		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1297	.mpllb_fracn1 =
1298		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1299		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1300		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1301	.mpllb_fracn2 =
1302		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) |
1303		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829),
1304	.mpllb_sscen =
1305		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1306};
1307
1308static const struct intel_mpllb_state dg2_hdmi_154000 = {
1309	.clock = 154000,
1310	.ref_control =
1311		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1312	.mpllb_cp =
1313		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1314		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 13) |
1315		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1316		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1317	.mpllb_div =
1318		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1319		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1320		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1321		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1322		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
1323	.mpllb_div2 =
1324		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1325		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 90) |
1326		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1327	.mpllb_fracn1 =
1328		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1329		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1330		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1331	.mpllb_fracn2 =
1332		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
1333		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),
1334	.mpllb_sscen =
1335		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1336};
1337
1338static const struct intel_mpllb_state dg2_hdmi_162000 = {
1339	.clock = 162000,
1340	.ref_control =
1341		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1342	.mpllb_cp =
1343		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1344		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1345		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1346		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1347	.mpllb_div =
1348		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1349		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1350		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1351		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1352		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
1353	.mpllb_div2 =
1354		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1355		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) |
1356		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1357	.mpllb_fracn1 =
1358		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1359		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1360		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1361	.mpllb_fracn2 =
1362		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
1363		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
1364	.mpllb_sscen =
1365		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1366};
1367
1368static const struct intel_mpllb_state dg2_hdmi_209800 = {
1369	.clock = 209800,
1370	.ref_control =
1371		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1372	.mpllb_cp =
1373		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1374		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1375		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1376		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1377	.mpllb_div =
1378		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1379		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1380		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1381		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1382		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1383	.mpllb_div2 =
1384		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1385		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 134) |
1386		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1387	.mpllb_fracn1 =
1388		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1389		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1390		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1391	.mpllb_fracn2 =
1392		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 60293) |
1393		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7864),
1394	.mpllb_sscen =
1395		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1396};
1397
1398static const struct intel_mpllb_state dg2_hdmi_262750 = {
1399	.clock = 262750,
1400	.ref_control =
1401		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1402	.mpllb_cp =
1403		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1404		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1405		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1406		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1407	.mpllb_div =
1408		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1409		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1410		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1411		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1412		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1413	.mpllb_div2 =
1414		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1415		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) |
1416		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1417	.mpllb_fracn1 =
1418		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1419		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1420		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1421	.mpllb_fracn2 =
1422		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) |
1423		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
1424	.mpllb_sscen =
1425		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1426};
1427
1428static const struct intel_mpllb_state dg2_hdmi_267300 = {
1429	.clock = 267300,
1430	.ref_control =
1431		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1432	.mpllb_cp =
1433		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1434		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1435		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1436		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1437	.mpllb_div =
1438		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1439		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1440		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1441		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1442		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1443	.mpllb_div2 =
1444		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1445		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) |
1446		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1447	.mpllb_fracn1 =
1448		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1449		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1450		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1451	.mpllb_fracn2 =
1452		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 30146) |
1453		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36699),
1454	.mpllb_sscen =
1455		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1456};
1457
1458static const struct intel_mpllb_state dg2_hdmi_268500 = {
1459	.clock = 268500,
1460	.ref_control =
1461		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1462	.mpllb_cp =
1463		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
1464		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1465		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1466		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1467	.mpllb_div =
1468		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1469		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1470		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1471		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1472		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1473	.mpllb_div2 =
1474		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1475		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) |
1476		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1477	.mpllb_fracn1 =
1478		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1479		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1480		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1481	.mpllb_fracn2 =
1482		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 45875) |
1483		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
1484	.mpllb_sscen =
1485		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1486};
1487
1488static const struct intel_mpllb_state dg2_hdmi_296703 = {
1489	.clock = 296703,
1490	.ref_control =
1491		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1492	.mpllb_cp =
1493		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1494		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1495		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1496		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1497	.mpllb_div =
1498		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1499		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1500		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1501		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1502		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1503	.mpllb_div2 =
1504		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1505		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1506		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1507	.mpllb_fracn1 =
1508		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1509		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1510		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1511	.mpllb_fracn2 =
1512		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22321) |
1513		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36804),
1514	.mpllb_sscen =
1515		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1516};
1517
1518static const struct intel_mpllb_state dg2_hdmi_241500 = {
1519	.clock = 241500,
1520	.ref_control =
1521		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1522	.mpllb_cp =
1523		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1524		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1525		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1526		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1527	.mpllb_div =
1528		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1529		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
1530		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1531		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1532		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1533	.mpllb_div2 =
1534		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1535		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) |
1536		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1537	.mpllb_fracn1 =
1538		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1539		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1540		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1541	.mpllb_fracn2 =
1542		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
1543		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),
1544	.mpllb_sscen =
1545		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1546};
1547
1548static const struct intel_mpllb_state dg2_hdmi_319890 = {
1549	.clock = 319890,
1550	.ref_control =
1551		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1552	.mpllb_cp =
1553		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1554		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1555		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1556		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1557	.mpllb_div =
1558		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1559		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1560		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1561		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1562		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
1563	.mpllb_div2 =
1564		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1565		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) |
1566		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1567	.mpllb_fracn1 =
1568		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1569		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1570		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1571	.mpllb_fracn2 =
1572		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 64094) |
1573		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13631),
1574	.mpllb_sscen =
1575		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1576};
1577
1578static const struct intel_mpllb_state dg2_hdmi_497750 = {
1579	.clock = 497750,
1580	.ref_control =
1581		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1582	.mpllb_cp =
1583		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1584		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
1585		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1586		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1587	.mpllb_div =
1588		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1589		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1590		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1591		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1592		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
1593	.mpllb_div2 =
1594		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1595		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 166) |
1596		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1597	.mpllb_fracn1 =
1598		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1599		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1600		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1601	.mpllb_fracn2 =
1602		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) |
1603		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
1604	.mpllb_sscen =
1605		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1606};
1607
1608static const struct intel_mpllb_state dg2_hdmi_592000 = {
1609	.clock = 592000,
1610	.ref_control =
1611		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1612	.mpllb_cp =
1613		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1614		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1615		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1616		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1617	.mpllb_div =
1618		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1619		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) |
1620		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1621		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1622		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1623	.mpllb_div2 =
1624		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1625		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1626		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1627	.mpllb_fracn1 =
1628		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1629		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1630		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1631	.mpllb_fracn2 =
1632		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
1633		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
1634	.mpllb_sscen =
1635		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1636};
1637
1638static const struct intel_mpllb_state dg2_hdmi_593407 = {
1639	.clock = 593407,
1640	.ref_control =
1641		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1642	.mpllb_cp =
1643		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1644		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1645		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1646		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1647	.mpllb_div =
1648		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1649		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) |
1650		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1651		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1652		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1653	.mpllb_div2 =
1654		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1655		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1656		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1657	.mpllb_fracn1 =
1658		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1659		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1660		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1661	.mpllb_fracn2 =
1662		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22328) |
1663		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7549),
1664	.mpllb_sscen =
1665		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1666};
1667
1668static const struct intel_mpllb_state dg2_hdmi_297 = {
1669	.clock = 297000,
1670	.ref_control =
1671		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1672	.mpllb_cp =
1673		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
1674		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
1675		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1676		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1677	.mpllb_div =
1678		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1679		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
1680		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1681		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1682		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1683	.mpllb_div2 =
1684		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1685		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1686		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1687	.mpllb_fracn1 =
1688		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1689		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1690		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
1691	.mpllb_fracn2 =
1692		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1693		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
1694	.mpllb_sscen =
1695		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1696};
1697
1698static const struct intel_mpllb_state dg2_hdmi_594 = {
1699	.clock = 594000,
1700	.ref_control =
1701		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
1702	.mpllb_cp =
1703		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
1704		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
1705		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
1706		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
1707	.mpllb_div =
1708		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
1709		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
1710		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
1711		REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
1712	.mpllb_div2 =
1713		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
1714		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
1715		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
1716	.mpllb_fracn1 =
1717		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
1718		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
1719		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
1720	.mpllb_fracn2 =
1721		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
1722		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
1723	.mpllb_sscen =
1724		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
1725};
1726
1727static const struct intel_mpllb_state * const dg2_hdmi_tables[] = {
1728	&dg2_hdmi_25_175,
1729	&dg2_hdmi_27_0,
1730	&dg2_hdmi_74_25,
1731	&dg2_hdmi_148_5,
1732	&dg2_hdmi_297,
1733	&dg2_hdmi_594,
1734	&dg2_hdmi_25200,
1735	&dg2_hdmi_27027,
1736	&dg2_hdmi_28320,
1737	&dg2_hdmi_30240,
1738	&dg2_hdmi_31500,
1739	&dg2_hdmi_36000,
1740	&dg2_hdmi_40000,
1741	&dg2_hdmi_49500,
1742	&dg2_hdmi_50000,
1743	&dg2_hdmi_57284,
1744	&dg2_hdmi_58000,
1745	&dg2_hdmi_65000,
1746	&dg2_hdmi_71000,
1747	&dg2_hdmi_74176,
1748	&dg2_hdmi_75000,
1749	&dg2_hdmi_78750,
1750	&dg2_hdmi_85500,
1751	&dg2_hdmi_88750,
1752	&dg2_hdmi_106500,
1753	&dg2_hdmi_108000,
1754	&dg2_hdmi_115500,
1755	&dg2_hdmi_119000,
1756	&dg2_hdmi_135000,
1757	&dg2_hdmi_138500,
1758	&dg2_hdmi_147160,
1759	&dg2_hdmi_148352,
1760	&dg2_hdmi_154000,
1761	&dg2_hdmi_162000,
1762	&dg2_hdmi_209800,
1763	&dg2_hdmi_241500,
1764	&dg2_hdmi_262750,
1765	&dg2_hdmi_267300,
1766	&dg2_hdmi_268500,
1767	&dg2_hdmi_296703,
1768	&dg2_hdmi_319890,
1769	&dg2_hdmi_497750,
1770	&dg2_hdmi_592000,
1771	&dg2_hdmi_593407,
1772	NULL,
1773};
1774
1775static const struct intel_mpllb_state * const *
1776intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
1777		       struct intel_encoder *encoder)
1778{
1779	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1780		return dg2_edp_tables;
1781	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
1782		return dg2_dp_100_tables;
1783	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1784		return dg2_hdmi_tables;
1785	}
1786
1787	MISSING_CASE(encoder->type);
1788	return NULL;
1789}
1790
1791int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
1792			   struct intel_encoder *encoder)
1793{
1794	const struct intel_mpllb_state * const *tables;
1795	int i;
1796
1797	tables = intel_mpllb_tables_get(crtc_state, encoder);
1798	if (!tables)
1799		return -EINVAL;
1800
1801	for (i = 0; tables[i]; i++) {
1802		if (crtc_state->port_clock == tables[i]->clock) {
1803			crtc_state->dpll_hw_state.mpllb = *tables[i];
1804			return 0;
1805		}
1806	}
1807
1808	/* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed tables */
1809	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1810		intel_snps_hdmi_pll_compute_mpllb(&crtc_state->dpll_hw_state.mpllb,
1811						  crtc_state->port_clock);
1812
1813		return 0;
1814	}
1815
1816	return -EINVAL;
1817}
1818
1819void intel_mpllb_enable(struct intel_encoder *encoder,
1820			const struct intel_crtc_state *crtc_state)
1821{
1822	struct intel_display *display = to_intel_display(encoder);
1823	const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb;
1824	enum phy phy = intel_encoder_to_phy(encoder);
1825	i915_reg_t enable_reg = (phy <= PHY_D ?
1826				 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
1827
1828	/*
1829	 * 3. Software programs the following PLL registers for the desired
1830	 * frequency.
1831	 */
1832	intel_de_write(display, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp);
1833	intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div);
1834	intel_de_write(display, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2);
1835	intel_de_write(display, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen);
1836	intel_de_write(display, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep);
1837	intel_de_write(display, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1);
1838	intel_de_write(display, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2);
1839
1840	/*
1841	 * 4. If the frequency will result in a change to the voltage
1842	 * requirement, follow the Display Voltage Frequency Switching -
1843	 * Sequence Before Frequency Change.
1844	 *
1845	 * We handle this step in bxt_set_cdclk().
1846	 */
1847
1848	/* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */
1849	intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
1850
1851	/*
1852	 * 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This
1853	 * will keep the PLL running during the DDI lane programming and any
1854	 * typeC DP cable disconnect. Do not set the force before enabling the
1855	 * PLL because that will start the PLL before it has sampled the
1856	 * divider values.
1857	 */
1858	intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy),
1859		       pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN);
1860
1861	/*
1862	 * 10. Software polls on register DPLL_ENABLE [PLL Lock] to confirm PLL
1863	 * is locked at new settings. This register bit is sampling PHY
1864	 * dp_mpllb_state interface signal.
1865	 */
1866	if (intel_de_wait_for_set_ms(display, enable_reg, PLL_LOCK, 5))
1867		drm_dbg_kms(display->drm, "Port %c PLL not locked\n", phy_name(phy));
1868
1869	/*
1870	 * 11. If the frequency will result in a change to the voltage
1871	 * requirement, follow the Display Voltage Frequency Switching -
1872	 * Sequence After Frequency Change.
1873	 *
1874	 * We handle this step in bxt_set_cdclk().
1875	 */
1876}
1877
1878void intel_mpllb_disable(struct intel_encoder *encoder)
1879{
1880	struct intel_display *display = to_intel_display(encoder);
1881	enum phy phy = intel_encoder_to_phy(encoder);
1882	i915_reg_t enable_reg = (phy <= PHY_D ?
1883				 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
1884
1885	/*
1886	 * 1. If the frequency will result in a change to the voltage
1887	 * requirement, follow the Display Voltage Frequency Switching -
1888	 * Sequence Before Frequency Change.
1889	 *
1890	 * We handle this step in bxt_set_cdclk().
1891	 */
1892
1893	/* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */
1894	intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);
1895
1896	/*
1897	 * 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0".
1898	 * This will allow the PLL to stop running.
1899	 */
1900	intel_de_rmw(display, SNPS_PHY_MPLLB_DIV(phy), SNPS_PHY_MPLLB_FORCE_EN, 0);
1901
1902	/*
1903	 * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment
1904	 * (dp_txX_ack) that the new transmitter setting request is completed.
1905	 */
1906	if (intel_de_wait_for_clear_ms(display, enable_reg, PLL_LOCK, 5))
1907		drm_err(display->drm, "Port %c PLL not locked\n", phy_name(phy));
1908
1909	/*
1910	 * 6. If the frequency will result in a change to the voltage
1911	 * requirement, follow the Display Voltage Frequency Switching -
1912	 * Sequence After Frequency Change.
1913	 *
1914	 * We handle this step in bxt_set_cdclk().
1915	 */
1916}
1917
1918int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
1919				const struct intel_mpllb_state *pll_state)
1920{
1921	unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
1922	unsigned int multiplier, tx_clk_div, refclk;
1923	bool frac_en;
1924
1925	if (0)
1926		refclk = 38400;
1927	else
1928		refclk = 100000;
1929
1930	refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1;
1931
1932	frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1);
1933
1934	if (frac_en) {
1935		frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2);
1936		frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2);
1937		frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1);
1938	}
1939
1940	multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16;
1941
1942	tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div);
1943
1944	return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
1945				     DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
1946				     10 << (tx_clk_div + 16));
1947}
1948
1949void intel_mpllb_readout_hw_state(struct intel_encoder *encoder,
1950				  struct intel_mpllb_state *pll_state)
1951{
1952	struct intel_display *display = to_intel_display(encoder);
1953	enum phy phy = intel_encoder_to_phy(encoder);
1954
1955	pll_state->mpllb_cp = intel_de_read(display, SNPS_PHY_MPLLB_CP(phy));
1956	pll_state->mpllb_div = intel_de_read(display, SNPS_PHY_MPLLB_DIV(phy));
1957	pll_state->mpllb_div2 = intel_de_read(display, SNPS_PHY_MPLLB_DIV2(phy));
1958	pll_state->mpllb_sscen = intel_de_read(display, SNPS_PHY_MPLLB_SSCEN(phy));
1959	pll_state->mpllb_sscstep = intel_de_read(display, SNPS_PHY_MPLLB_SSCSTEP(phy));
1960	pll_state->mpllb_fracn1 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN1(phy));
1961	pll_state->mpllb_fracn2 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN2(phy));
1962
1963	/*
1964	 * REF_CONTROL is under firmware control and never programmed by the
1965	 * driver; we read it only for sanity checking purposes.  The bspec
1966	 * only tells us the expected value for one field in this register,
1967	 * so we'll only read out those specific bits here.
1968	 */
1969	pll_state->ref_control = intel_de_read(display, SNPS_PHY_REF_CONTROL(phy)) &
1970		SNPS_PHY_REF_CONTROL_REF_RANGE;
1971
1972	/*
1973	 * MPLLB_DIV is programmed twice, once with the software-computed
1974	 * state, then again with the MPLLB_FORCE_EN bit added.  Drop that
1975	 * extra bit during readout so that we return the actual expected
1976	 * software state.
1977	 */
1978	pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN;
1979}
1980
1981void intel_mpllb_state_verify(struct intel_atomic_state *state,
1982			      struct intel_crtc *crtc)
1983{
1984	struct intel_display *display = to_intel_display(state);
1985	const struct intel_crtc_state *new_crtc_state =
1986		intel_atomic_get_new_crtc_state(state, crtc);
1987	struct intel_mpllb_state mpllb_hw_state = {};
1988	const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->dpll_hw_state.mpllb;
1989	struct intel_encoder *encoder;
1990
1991	if (!display->platform.dg2)
1992		return;
1993
1994	if (!new_crtc_state->hw.active)
1995		return;
1996
1997	/* intel_get_crtc_new_encoder() only works for modeset/fastset commits */
1998	if (!intel_crtc_needs_modeset(new_crtc_state) &&
1999	    !intel_crtc_needs_fastset(new_crtc_state))
2000		return;
2001
2002	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
2003	intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);
2004
2005#define MPLLB_CHECK(__name)						\
2006	INTEL_DISPLAY_STATE_WARN(display, mpllb_sw_state->__name != mpllb_hw_state.__name, \
2007				 "[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
2008				 crtc->base.base.id, crtc->base.name,	\
2009				 __stringify(__name),			\
2010				 mpllb_sw_state->__name, mpllb_hw_state.__name)
2011
2012	MPLLB_CHECK(mpllb_cp);
2013	MPLLB_CHECK(mpllb_div);
2014	MPLLB_CHECK(mpllb_div2);
2015	MPLLB_CHECK(mpllb_fracn1);
2016	MPLLB_CHECK(mpllb_fracn2);
2017	MPLLB_CHECK(mpllb_sscen);
2018	MPLLB_CHECK(mpllb_sscstep);
2019
2020	/*
2021	 * ref_control is handled by the hardware/firemware and never
2022	 * programmed by the software, but the proper values are supplied
2023	 * in the bspec for verification purposes.
2024	 */
2025	MPLLB_CHECK(ref_control);
2026
2027#undef MPLLB_CHECK
2028}