intel_sbi_regs.h

 1/* SPDX-License-Identifier: MIT */
 2/* Copyright © 2025 Intel Corporation */
 3
 4#ifndef __INTEL_SBI_REGS_H__
 5#define __INTEL_SBI_REGS_H__
 6
 7#include "intel_display_reg_defs.h"
 8
 9/*
10 * Sideband Interface (SBI) is programmed indirectly, via SBI_ADDR, which
11 * contains the register offset; and SBI_DATA, which contains the payload.
12 */
13#define SBI_ADDR			_MMIO(0xC6000)
14#define   SBI_ADDR_MASK			REG_GENMASK(31, 16)
15#define   SBI_ADDR_VALUE(addr)		REG_FIELD_PREP(SBI_ADDR_MASK, (addr))
16
17#define SBI_DATA			_MMIO(0xC6004)
18
19#define SBI_CTL_STAT			_MMIO(0xC6008)
20#define   SBI_CTL_DEST_MASK		REG_GENMASK(16, 16)
21#define   SBI_CTL_DEST_ICLK		REG_FIELD_PREP(SBI_CTL_DEST_MASK, 0)
22#define   SBI_CTL_DEST_MPHY		REG_FIELD_PREP(SBI_CTL_DEST_MASK, 1)
23#define   SBI_CTL_OP_MASK		REG_GENMASK(15, 8)
24#define   SBI_CTL_OP_IORD		REG_FIELD_PREP(SBI_CTL_OP_MASK, 2)
25#define   SBI_CTL_OP_IOWR		REG_FIELD_PREP(SBI_CTL_OP_MASK, 3)
26#define   SBI_CTL_OP_CRRD		REG_FIELD_PREP(SBI_CTL_OP_MASK, 6)
27#define   SBI_CTL_OP_CRWR		REG_FIELD_PREP(SBI_CTL_OP_MASK, 7)
28#define   SBI_CTL_OP_WR			REG_BIT(8)
29#define   SBI_RESPONSE_MASK		REG_GENMASK(2, 1)
30#define   SBI_RESPONSE_FAIL		REG_FIELD_PREP(SBI_RESPONSE_MASK, 1)
31#define   SBI_RESPONSE_SUCCESS		REG_FIELD_PREP(SBI_RESPONSE_MASK, 0)
32#define   SBI_STATUS_MASK		REG_GENMASK(0, 0)
33#define   SBI_STATUS_BUSY		REG_FIELD_PREP(SBI_STATUS_MASK, 1)
34#define   SBI_STATUS_READY		REG_FIELD_PREP(SBI_STATUS_MASK, 0)
35
36/* SBI offsets */
37#define SBI_SSCDIVINTPHASE			0x0200
38
39#define SBI_SSCDIVINTPHASE6			0x0600
40#define   SBI_SSCDIVINTPHASE_DIVSEL_SHIFT	1
41#define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	(0x7f << 1)
42#define   SBI_SSCDIVINTPHASE_DIVSEL(x)		((x) << 1)
43#define   SBI_SSCDIVINTPHASE_INCVAL_SHIFT	8
44#define   SBI_SSCDIVINTPHASE_INCVAL_MASK	(0x7f << 8)
45#define   SBI_SSCDIVINTPHASE_INCVAL(x)		((x) << 8)
46#define   SBI_SSCDIVINTPHASE_DIR(x)		((x) << 15)
47#define   SBI_SSCDIVINTPHASE_PROPAGATE		(1 << 0)
48
49#define SBI_SSCDITHPHASE			0x0204
50#define SBI_SSCCTL				0x020c
51#define SBI_SSCCTL6				0x060C
52#define   SBI_SSCCTL_PATHALT			(1 << 3)
53#define   SBI_SSCCTL_DISABLE			(1 << 0)
54
55#define SBI_SSCAUXDIV6				0x0610
56#define   SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT	4
57#define   SBI_SSCAUXDIV_FINALDIV2SEL_MASK	(1 << 4)
58#define   SBI_SSCAUXDIV_FINALDIV2SEL(x)		((x) << 4)
59
60#define SBI_DBUFF0				0x2a00
61
62#define SBI_GEN0				0x1f00
63#define   SBI_GEN0_CFG_BUFFENABLE_DISABLE	(1 << 0)
64
65#endif /* __INTEL_SBI_REGS_H__ */