intel_psr.c

   1/*
   2 * Copyright © 2014 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21 * DEALINGS IN THE SOFTWARE.
  22 */
  23
  24#include <linux/debugfs.h>
  25
  26#include <drm/drm_atomic_helper.h>
  27#include <drm/drm_damage_helper.h>
  28#include <drm/drm_debugfs.h>
  29#include <drm/drm_print.h>
  30#include <drm/drm_vblank.h>
  31
  32#include "i915_reg.h"
  33#include "intel_alpm.h"
  34#include "intel_atomic.h"
  35#include "intel_crtc.h"
  36#include "intel_cursor_regs.h"
  37#include "intel_ddi.h"
  38#include "intel_de.h"
  39#include "intel_display_irq.h"
  40#include "intel_display_regs.h"
  41#include "intel_display_rpm.h"
  42#include "intel_display_types.h"
  43#include "intel_display_utils.h"
  44#include "intel_dmc.h"
  45#include "intel_dp.h"
  46#include "intel_dp_aux.h"
  47#include "intel_dsb.h"
  48#include "intel_frontbuffer.h"
  49#include "intel_hdmi.h"
  50#include "intel_psr.h"
  51#include "intel_psr_regs.h"
  52#include "intel_snps_phy.h"
  53#include "intel_step.h"
  54#include "intel_vblank.h"
  55#include "intel_vdsc.h"
  56#include "intel_vrr.h"
  57#include "skl_universal_plane.h"
  58
  59/**
  60 * DOC: Panel Self Refresh (PSR/SRD)
  61 *
  62 * Since Haswell Display controller supports Panel Self-Refresh on display
  63 * panels witch have a remote frame buffer (RFB) implemented according to PSR
  64 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
  65 * when system is idle but display is on as it eliminates display refresh
  66 * request to DDR memory completely as long as the frame buffer for that
  67 * display is unchanged.
  68 *
  69 * Panel Self Refresh must be supported by both Hardware (source) and
  70 * Panel (sink).
  71 *
  72 * PSR saves power by caching the framebuffer in the panel RFB, which allows us
  73 * to power down the link and memory controller. For DSI panels the same idea
  74 * is called "manual mode".
  75 *
  76 * The implementation uses the hardware-based PSR support which automatically
  77 * enters/exits self-refresh mode. The hardware takes care of sending the
  78 * required DP aux message and could even retrain the link (that part isn't
  79 * enabled yet though). The hardware also keeps track of any frontbuffer
  80 * changes to know when to exit self-refresh mode again. Unfortunately that
  81 * part doesn't work too well, hence why the i915 PSR support uses the
  82 * software frontbuffer tracking to make sure it doesn't miss a screen
  83 * update. For this integration intel_psr_invalidate() and intel_psr_flush()
  84 * get called by the frontbuffer tracking code. Note that because of locking
  85 * issues the self-refresh re-enable code is done from a work queue, which
  86 * must be correctly synchronized/cancelled when shutting down the pipe."
  87 *
  88 * DC3CO (DC3 clock off)
  89 *
  90 * On top of PSR2, GEN12 adds a intermediate power savings state that turns
  91 * clock off automatically during PSR2 idle state.
  92 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep
  93 * entry/exit allows the HW to enter a low-power state even when page flipping
  94 * periodically (for instance a 30fps video playback scenario).
  95 *
  96 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was),
  97 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6
  98 * frames, if no other flip occurs and the function above is executed, DC3CO is
  99 * disabled and PSR2 is configured to enter deep sleep, resetting again in case
 100 * of another flip.
 101 * Front buffer modifications do not trigger DC3CO activation on purpose as it
 102 * would bring a lot of complexity and most of the moderns systems will only
 103 * use page flips.
 104 */
 105
 106/*
 107 * Description of PSR mask bits:
 108 *
 109 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl):
 110 *
 111 *  When unmasked (nearly) all display register writes (eg. even
 112 *  SWF) trigger a PSR exit. Some registers are excluded from this
 113 *  and they have a more specific mask (described below). On icl+
 114 *  this bit no longer exists and is effectively always set.
 115 *
 116 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+):
 117 *
 118 *  When unmasked (nearly) all pipe/plane register writes
 119 *  trigger a PSR exit. Some plane registers are excluded from this
 120 *  and they have a more specific mask (described below).
 121 *
 122 * CHICKEN_PIPESL_1[11]/SKL_PSR_MASK_PLANE_FLIP (skl+):
 123 * PIPE_MISC[23]/PIPE_MISC_PSR_MASK_PRIMARY_FLIP (bdw):
 124 * EDP_PSR_DEBUG[23]/EDP_PSR_DEBUG_MASK_PRIMARY_FLIP (hsw):
 125 *
 126 *  When unmasked PRI_SURF/PLANE_SURF writes trigger a PSR exit.
 127 *  SPR_SURF/CURBASE are not included in this and instead are
 128 *  controlled by PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+) or
 129 *  EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw/bdw).
 130 *
 131 * PIPE_MISC[22]/PIPE_MISC_PSR_MASK_SPRITE_ENABLE (bdw):
 132 * EDP_PSR_DEBUG[21]/EDP_PSR_DEBUG_MASK_SPRITE_ENABLE (hsw):
 133 *
 134 *  When unmasked PSR is blocked as long as the sprite
 135 *  plane is enabled. skl+ with their universal planes no
 136 *  longer have a mask bit like this, and no plane being
 137 *  enabledb blocks PSR.
 138 *
 139 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_CURSOR_MOVE (bdw):
 140 * EDP_PSR_DEBUG[20]/EDP_PSR_DEBUG_MASK_CURSOR_MOVE (hsw):
 141 *
 142 *  When umasked CURPOS writes trigger a PSR exit. On skl+
 143 *  this doesn't exit but CURPOS is included in the
 144 *  PIPE_MISC_PSR_MASK_PIPE_REG_WRITE mask.
 145 *
 146 * PIPE_MISC[20]/PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT (bdw+):
 147 * EDP_PSR_DEBUG[19]/EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT (hsw):
 148 *
 149 *  When unmasked PSR is blocked as long as vblank and/or vsync
 150 *  interrupt is unmasked in IMR *and* enabled in IER.
 151 *
 152 * CHICKEN_TRANS[30]/SKL_UNMASK_VBL_TO_PIPE_IN_SRD (skl+):
 153 * CHICKEN_PAR1_1[15]/HSW_MASK_VBL_TO_PIPE_IN_SRD (hsw/bdw):
 154 *
 155 *  Selectcs whether PSR exit generates an extra vblank before
 156 *  the first frame is transmitted. Also note the opposite polarity
 157 *  if the bit on hsw/bdw vs. skl+ (masked==generate the extra vblank,
 158 *  unmasked==do not generate the extra vblank).
 159 *
 160 *  With DC states enabled the extra vblank happens after link training,
 161 *  with DC states disabled it happens immediately upuon PSR exit trigger.
 162 *  No idea as of now why there is a difference. HSW/BDW (which don't
 163 *  even have DMC) always generate it after link training. Go figure.
 164 *
 165 *  Unfortunately CHICKEN_TRANS itself seems to be double buffered
 166 *  and thus won't latch until the first vblank. So with DC states
 167 *  enabled the register effectively uses the reset value during DC5
 168 *  exit+PSR exit sequence, and thus the bit does nothing until
 169 *  latched by the vblank that it was trying to prevent from being
 170 *  generated in the first place. So we should probably call this
 171 *  one a chicken/egg bit instead on skl+.
 172 *
 173 *  In standby mode (as opposed to link-off) this makes no difference
 174 *  as the timing generator keeps running the whole time generating
 175 *  normal periodic vblanks.
 176 *
 177 *  WaPsrDPAMaskVBlankInSRD asks us to set the bit on hsw/bdw,
 178 *  and doing so makes the behaviour match the skl+ reset value.
 179 *
 180 * CHICKEN_PIPESL_1[0]/BDW_UNMASK_VBL_TO_REGS_IN_SRD (bdw):
 181 * CHICKEN_PIPESL_1[15]/HSW_UNMASK_VBL_TO_REGS_IN_SRD (hsw):
 182 *
 183 *  On BDW without this bit is no vblanks whatsoever are
 184 *  generated after PSR exit. On HSW this has no apparent effect.
 185 *  WaPsrDPRSUnmaskVBlankInSRD says to set this.
 186 *
 187 * The rest of the bits are more self-explanatory and/or
 188 * irrelevant for normal operation.
 189 *
 190 * Description of intel_crtc_state variables. has_psr, has_panel_replay and
 191 * has_sel_update:
 192 *
 193 *  has_psr (alone):					PSR1
 194 *  has_psr + has_sel_update:				PSR2
 195 *  has_psr + has_panel_replay:				Panel Replay
 196 *  has_psr + has_panel_replay + has_sel_update:	Panel Replay Selective Update
 197 *
 198 * Description of some intel_psr variables. enabled, panel_replay_enabled,
 199 * sel_update_enabled
 200 *
 201 *  enabled (alone):						PSR1
 202 *  enabled + sel_update_enabled:				PSR2
 203 *  enabled + panel_replay_enabled:				Panel Replay
 204 *  enabled + panel_replay_enabled + sel_update_enabled:	Panel Replay SU
 205 */
 206
 207#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
 208			   (intel_dp)->psr.source_support)
 209
 210bool intel_encoder_can_psr(struct intel_encoder *encoder)
 211{
 212	if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST)
 213		return CAN_PSR(enc_to_intel_dp(encoder)) ||
 214		       CAN_PANEL_REPLAY(enc_to_intel_dp(encoder));
 215	else
 216		return false;
 217}
 218
 219bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder,
 220				  const struct intel_crtc_state *crtc_state)
 221{
 222	/*
 223	 * For PSR/PR modes only eDP requires the AUX IO power to be enabled whenever
 224	 * the output is enabled. For non-eDP outputs the main link is always
 225	 * on, hence it doesn't require the HW initiated AUX wake-up signaling used
 226	 * for eDP.
 227	 *
 228	 * TODO:
 229	 * - Consider leaving AUX IO disabled for eDP / PR as well, in case
 230	 *   the ALPM with main-link off mode is not enabled.
 231	 * - Leave AUX IO enabled for DP / PR, once support for ALPM with
 232	 *   main-link off mode is added for it and this mode gets enabled.
 233	 */
 234	return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
 235	       intel_encoder_can_psr(encoder);
 236}
 237
 238static bool psr_global_enabled(struct intel_dp *intel_dp)
 239{
 240	struct intel_connector *connector = intel_dp->attached_connector;
 241
 242	switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
 243	case I915_PSR_DEBUG_DEFAULT:
 244		return intel_dp_is_edp(intel_dp) ?
 245			connector->panel.vbt.psr.enable : true;
 246	case I915_PSR_DEBUG_DISABLE:
 247		return false;
 248	default:
 249		return true;
 250	}
 251}
 252
 253static bool sel_update_global_enabled(struct intel_dp *intel_dp)
 254{
 255	switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
 256	case I915_PSR_DEBUG_DISABLE:
 257	case I915_PSR_DEBUG_FORCE_PSR1:
 258		return false;
 259	default:
 260		return true;
 261	}
 262}
 263
 264static bool panel_replay_global_enabled(struct intel_dp *intel_dp)
 265{
 266	struct intel_display *display = to_intel_display(intel_dp);
 267
 268	return !(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE) &&
 269		display->params.enable_panel_replay;
 270}
 271
 272static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp)
 273{
 274	struct intel_display *display = to_intel_display(intel_dp);
 275
 276	return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR :
 277		EDP_PSR_ERROR(intel_dp->psr.transcoder);
 278}
 279
 280static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp)
 281{
 282	struct intel_display *display = to_intel_display(intel_dp);
 283
 284	return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT :
 285		EDP_PSR_POST_EXIT(intel_dp->psr.transcoder);
 286}
 287
 288static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp)
 289{
 290	struct intel_display *display = to_intel_display(intel_dp);
 291
 292	return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY :
 293		EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder);
 294}
 295
 296static u32 psr_irq_mask_get(struct intel_dp *intel_dp)
 297{
 298	struct intel_display *display = to_intel_display(intel_dp);
 299
 300	return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK :
 301		EDP_PSR_MASK(intel_dp->psr.transcoder);
 302}
 303
 304static i915_reg_t psr_ctl_reg(struct intel_display *display,
 305			      enum transcoder cpu_transcoder)
 306{
 307	if (DISPLAY_VER(display) >= 8)
 308		return EDP_PSR_CTL(display, cpu_transcoder);
 309	else
 310		return HSW_SRD_CTL;
 311}
 312
 313static i915_reg_t psr_debug_reg(struct intel_display *display,
 314				enum transcoder cpu_transcoder)
 315{
 316	if (DISPLAY_VER(display) >= 8)
 317		return EDP_PSR_DEBUG(display, cpu_transcoder);
 318	else
 319		return HSW_SRD_DEBUG;
 320}
 321
 322static i915_reg_t psr_perf_cnt_reg(struct intel_display *display,
 323				   enum transcoder cpu_transcoder)
 324{
 325	if (DISPLAY_VER(display) >= 8)
 326		return EDP_PSR_PERF_CNT(display, cpu_transcoder);
 327	else
 328		return HSW_SRD_PERF_CNT;
 329}
 330
 331static i915_reg_t psr_status_reg(struct intel_display *display,
 332				 enum transcoder cpu_transcoder)
 333{
 334	if (DISPLAY_VER(display) >= 8)
 335		return EDP_PSR_STATUS(display, cpu_transcoder);
 336	else
 337		return HSW_SRD_STATUS;
 338}
 339
 340static i915_reg_t psr_imr_reg(struct intel_display *display,
 341			      enum transcoder cpu_transcoder)
 342{
 343	if (DISPLAY_VER(display) >= 12)
 344		return TRANS_PSR_IMR(display, cpu_transcoder);
 345	else
 346		return EDP_PSR_IMR;
 347}
 348
 349static i915_reg_t psr_iir_reg(struct intel_display *display,
 350			      enum transcoder cpu_transcoder)
 351{
 352	if (DISPLAY_VER(display) >= 12)
 353		return TRANS_PSR_IIR(display, cpu_transcoder);
 354	else
 355		return EDP_PSR_IIR;
 356}
 357
 358static i915_reg_t psr_aux_ctl_reg(struct intel_display *display,
 359				  enum transcoder cpu_transcoder)
 360{
 361	if (DISPLAY_VER(display) >= 8)
 362		return EDP_PSR_AUX_CTL(display, cpu_transcoder);
 363	else
 364		return HSW_SRD_AUX_CTL;
 365}
 366
 367static i915_reg_t psr_aux_data_reg(struct intel_display *display,
 368				   enum transcoder cpu_transcoder, int i)
 369{
 370	if (DISPLAY_VER(display) >= 8)
 371		return EDP_PSR_AUX_DATA(display, cpu_transcoder, i);
 372	else
 373		return HSW_SRD_AUX_DATA(i);
 374}
 375
 376static void psr_irq_control(struct intel_dp *intel_dp)
 377{
 378	struct intel_display *display = to_intel_display(intel_dp);
 379	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
 380	u32 mask;
 381
 382	if (intel_dp->psr.panel_replay_enabled)
 383		return;
 384
 385	mask = psr_irq_psr_error_bit_get(intel_dp);
 386	if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
 387		mask |= psr_irq_post_exit_bit_get(intel_dp) |
 388			psr_irq_pre_entry_bit_get(intel_dp);
 389
 390	intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder),
 391		     psr_irq_mask_get(intel_dp), ~mask);
 392}
 393
 394static void psr_event_print(struct intel_display *display,
 395			    u32 val, bool sel_update_enabled)
 396{
 397	drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val);
 398	if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
 399		drm_dbg_kms(display->drm, "\tPSR2 watchdog timer expired\n");
 400	if ((val & PSR_EVENT_PSR2_DISABLED) && sel_update_enabled)
 401		drm_dbg_kms(display->drm, "\tPSR2 disabled\n");
 402	if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
 403		drm_dbg_kms(display->drm, "\tSU dirty FIFO underrun\n");
 404	if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
 405		drm_dbg_kms(display->drm, "\tSU CRC FIFO underrun\n");
 406	if (val & PSR_EVENT_GRAPHICS_RESET)
 407		drm_dbg_kms(display->drm, "\tGraphics reset\n");
 408	if (val & PSR_EVENT_PCH_INTERRUPT)
 409		drm_dbg_kms(display->drm, "\tPCH interrupt\n");
 410	if (val & PSR_EVENT_MEMORY_UP)
 411		drm_dbg_kms(display->drm, "\tMemory up\n");
 412	if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
 413		drm_dbg_kms(display->drm, "\tFront buffer modification\n");
 414	if (val & PSR_EVENT_WD_TIMER_EXPIRE)
 415		drm_dbg_kms(display->drm, "\tPSR watchdog timer expired\n");
 416	if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
 417		drm_dbg_kms(display->drm, "\tPIPE registers updated\n");
 418	if (val & PSR_EVENT_REGISTER_UPDATE)
 419		drm_dbg_kms(display->drm, "\tRegister updated\n");
 420	if (val & PSR_EVENT_HDCP_ENABLE)
 421		drm_dbg_kms(display->drm, "\tHDCP enabled\n");
 422	if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
 423		drm_dbg_kms(display->drm, "\tKVMR session enabled\n");
 424	if (val & PSR_EVENT_VBI_ENABLE)
 425		drm_dbg_kms(display->drm, "\tVBI enabled\n");
 426	if (val & PSR_EVENT_LPSP_MODE_EXIT)
 427		drm_dbg_kms(display->drm, "\tLPSP mode exited\n");
 428	if ((val & PSR_EVENT_PSR_DISABLE) && !sel_update_enabled)
 429		drm_dbg_kms(display->drm, "\tPSR disabled\n");
 430}
 431
 432void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
 433{
 434	struct intel_display *display = to_intel_display(intel_dp);
 435	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
 436	ktime_t time_ns =  ktime_get();
 437
 438	if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) {
 439		intel_dp->psr.last_entry_attempt = time_ns;
 440		drm_dbg_kms(display->drm,
 441			    "[transcoder %s] PSR entry attempt in 2 vblanks\n",
 442			    transcoder_name(cpu_transcoder));
 443	}
 444
 445	if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) {
 446		intel_dp->psr.last_exit = time_ns;
 447		drm_dbg_kms(display->drm,
 448			    "[transcoder %s] PSR exit completed\n",
 449			    transcoder_name(cpu_transcoder));
 450
 451		if (DISPLAY_VER(display) >= 9) {
 452			u32 val;
 453
 454			val = intel_de_rmw(display,
 455					   PSR_EVENT(display, cpu_transcoder),
 456					   0, 0);
 457
 458			psr_event_print(display, val, intel_dp->psr.sel_update_enabled);
 459		}
 460	}
 461
 462	if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) {
 463		drm_warn(display->drm, "[transcoder %s] PSR aux error\n",
 464			 transcoder_name(cpu_transcoder));
 465
 466		intel_dp->psr.irq_aux_error = true;
 467
 468		/*
 469		 * If this interruption is not masked it will keep
 470		 * interrupting so fast that it prevents the scheduled
 471		 * work to run.
 472		 * Also after a PSR error, we don't want to arm PSR
 473		 * again so we don't care about unmask the interruption
 474		 * or unset irq_aux_error.
 475		 */
 476		intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder),
 477			     0, psr_irq_psr_error_bit_get(intel_dp));
 478
 479		queue_work(display->wq.unordered, &intel_dp->psr.work);
 480	}
 481}
 482
 483static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
 484{
 485	struct intel_display *display = to_intel_display(intel_dp);
 486	u8 val = 8; /* assume the worst if we can't read the value */
 487
 488	if (drm_dp_dpcd_readb(&intel_dp->aux,
 489			      DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
 490		val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
 491	else
 492		drm_dbg_kms(display->drm,
 493			    "Unable to get sink synchronization latency, assuming 8 frames\n");
 494	return val;
 495}
 496
 497static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp)
 498{
 499	u8 su_capability = 0;
 500
 501	if (intel_dp->psr.sink_panel_replay_su_support) {
 502		if (drm_dp_dpcd_read_byte(&intel_dp->aux,
 503					  DP_PANEL_REPLAY_CAP_CAPABILITY,
 504					  &su_capability) < 0)
 505			return 0;
 506	} else {
 507		su_capability = intel_dp->psr_dpcd[1];
 508	}
 509
 510	return su_capability;
 511}
 512
 513static unsigned int
 514intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp)
 515{
 516	return intel_dp->psr.sink_panel_replay_su_support ?
 517		DP_PANEL_REPLAY_CAP_X_GRANULARITY :
 518		DP_PSR2_SU_X_GRANULARITY;
 519}
 520
 521static unsigned int
 522intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp)
 523{
 524	return intel_dp->psr.sink_panel_replay_su_support ?
 525		DP_PANEL_REPLAY_CAP_Y_GRANULARITY :
 526		DP_PSR2_SU_Y_GRANULARITY;
 527}
 528
 529/*
 530 * Note: Bits related to granularity are same in panel replay and psr
 531 * registers. Rely on PSR definitions on these "common" bits.
 532 */
 533static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 534{
 535	struct intel_display *display = to_intel_display(intel_dp);
 536	ssize_t r;
 537	u16 w;
 538	u8 y;
 539
 540	/*
 541	 * TODO: Do we need to take into account panel supporting both PSR and
 542	 * Panel replay?
 543	 */
 544
 545	/*
 546	 * If sink don't have specific granularity requirements set legacy
 547	 * ones.
 548	 */
 549	if (!(intel_dp_get_su_capability(intel_dp) &
 550	      DP_PSR2_SU_GRANULARITY_REQUIRED)) {
 551		/* As PSR2 HW sends full lines, we do not care about x granularity */
 552		w = 4;
 553		y = 4;
 554		goto exit;
 555	}
 556
 557	r = drm_dp_dpcd_read(&intel_dp->aux,
 558			     intel_dp_get_su_x_granularity_offset(intel_dp),
 559			     &w, 2);
 560	if (r != 2)
 561		drm_dbg_kms(display->drm,
 562			    "Unable to read selective update x granularity\n");
 563	/*
 564	 * Spec says that if the value read is 0 the default granularity should
 565	 * be used instead.
 566	 */
 567	if (r != 2 || w == 0)
 568		w = 4;
 569
 570	r = drm_dp_dpcd_read(&intel_dp->aux,
 571			     intel_dp_get_su_y_granularity_offset(intel_dp),
 572			     &y, 1);
 573	if (r != 1) {
 574		drm_dbg_kms(display->drm,
 575			    "Unable to read selective update y granularity\n");
 576		y = 4;
 577	}
 578	if (y == 0)
 579		y = 1;
 580
 581exit:
 582	intel_dp->psr.su_w_granularity = w;
 583	intel_dp->psr.su_y_granularity = y;
 584}
 585
 586static enum intel_panel_replay_dsc_support
 587compute_pr_dsc_support(struct intel_dp *intel_dp)
 588{
 589	u8 pr_dsc_mode;
 590	u8 val;
 591
 592	val = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)];
 593	pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val);
 594
 595	switch (pr_dsc_mode) {
 596	case DP_DSC_DECODE_CAPABILITY_IN_PR_FULL_FRAME_ONLY:
 597		return INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY;
 598	case DP_DSC_DECODE_CAPABILITY_IN_PR_SUPPORTED:
 599		return INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE;
 600	default:
 601		MISSING_CASE(pr_dsc_mode);
 602		fallthrough;
 603	case DP_DSC_DECODE_CAPABILITY_IN_PR_NOT_SUPPORTED:
 604	case DP_DSC_DECODE_CAPABILITY_IN_PR_RESERVED:
 605		return INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
 606	}
 607}
 608
 609static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_support dsc_support)
 610{
 611	switch (dsc_support) {
 612	case INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED:
 613		return "not supported";
 614	case INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY:
 615		return "full frame only";
 616	case INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE:
 617		return "selective update";
 618	default:
 619		MISSING_CASE(dsc_support);
 620		return "n/a";
 621	};
 622}
 623
 624static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
 625{
 626	struct intel_display *display = to_intel_display(intel_dp);
 627	int ret;
 628
 629	/* TODO: Enable Panel Replay on MST once it's properly implemented. */
 630	if (intel_dp->mst_detect == DRM_DP_MST)
 631		return;
 632
 633	ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT,
 634				    &intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd));
 635	if (ret < 0)
 636		return;
 637
 638	if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 639	      DP_PANEL_REPLAY_SUPPORT))
 640		return;
 641
 642	if (intel_dp_is_edp(intel_dp)) {
 643		if (!intel_alpm_aux_less_wake_supported(intel_dp)) {
 644			drm_dbg_kms(display->drm,
 645				    "Panel doesn't support AUX-less ALPM, eDP Panel Replay not possible\n");
 646			return;
 647		}
 648
 649		if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 650		      DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) {
 651			drm_dbg_kms(display->drm,
 652				    "Panel doesn't support early transport, eDP Panel Replay not possible\n");
 653			return;
 654		}
 655	}
 656
 657	intel_dp->psr.sink_panel_replay_support = true;
 658
 659	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 660	    DP_PANEL_REPLAY_SU_SUPPORT)
 661		intel_dp->psr.sink_panel_replay_su_support = true;
 662
 663	intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp);
 664
 665	drm_dbg_kms(display->drm,
 666		    "Panel replay %sis supported by panel (in DSC mode: %s)\n",
 667		    intel_dp->psr.sink_panel_replay_su_support ?
 668		    "selective_update " : "",
 669		    panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support));
 670}
 671
 672static void _psr_init_dpcd(struct intel_dp *intel_dp)
 673{
 674	struct intel_display *display = to_intel_display(intel_dp);
 675	int ret;
 676
 677	ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
 678				    sizeof(intel_dp->psr_dpcd));
 679	if (ret < 0)
 680		return;
 681
 682	if (!intel_dp->psr_dpcd[0])
 683		return;
 684
 685	drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n",
 686		    intel_dp->psr_dpcd[0]);
 687
 688	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
 689		drm_dbg_kms(display->drm,
 690			    "PSR support not currently available for this panel\n");
 691		return;
 692	}
 693
 694	if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
 695		drm_dbg_kms(display->drm,
 696			    "Panel lacks power state control, PSR cannot be enabled\n");
 697		return;
 698	}
 699
 700	intel_dp->psr.sink_support = true;
 701	intel_dp->psr.sink_sync_latency =
 702		intel_dp_get_sink_sync_latency(intel_dp);
 703
 704	if (DISPLAY_VER(display) >= 9 &&
 705	    intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
 706		bool y_req = intel_dp->psr_dpcd[1] &
 707			     DP_PSR2_SU_Y_COORDINATE_REQUIRED;
 708
 709		/*
 710		 * All panels that supports PSR version 03h (PSR2 +
 711		 * Y-coordinate) can handle Y-coordinates in VSC but we are
 712		 * only sure that it is going to be used when required by the
 713		 * panel. This way panel is capable to do selective update
 714		 * without a aux frame sync.
 715		 *
 716		 * To support PSR version 02h and PSR version 03h without
 717		 * Y-coordinate requirement panels we would need to enable
 718		 * GTC first.
 719		 */
 720		intel_dp->psr.sink_psr2_support = y_req &&
 721			intel_alpm_aux_wake_supported(intel_dp);
 722		drm_dbg_kms(display->drm, "PSR2 %ssupported\n",
 723			    intel_dp->psr.sink_psr2_support ? "" : "not ");
 724	}
 725}
 726
 727void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 728{
 729	_psr_init_dpcd(intel_dp);
 730
 731	_panel_replay_init_dpcd(intel_dp);
 732
 733	if (intel_dp->psr.sink_psr2_support ||
 734	    intel_dp->psr.sink_panel_replay_su_support)
 735		intel_dp_get_su_granularity(intel_dp);
 736}
 737
 738static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 739{
 740	struct intel_display *display = to_intel_display(intel_dp);
 741	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
 742	u32 aux_clock_divider, aux_ctl;
 743	/* write DP_SET_POWER=D0 */
 744	static const u8 aux_msg[] = {
 745		[0] = (DP_AUX_NATIVE_WRITE << 4) | ((DP_SET_POWER >> 16) & 0xf),
 746		[1] = (DP_SET_POWER >> 8) & 0xff,
 747		[2] = DP_SET_POWER & 0xff,
 748		[3] = 1 - 1,
 749		[4] = DP_SET_POWER_D0,
 750	};
 751	int i;
 752
 753	BUILD_BUG_ON(sizeof(aux_msg) > 20);
 754	for (i = 0; i < sizeof(aux_msg); i += 4)
 755		intel_de_write(display,
 756			       psr_aux_data_reg(display, cpu_transcoder, i >> 2),
 757			       intel_dp_aux_pack(&aux_msg[i], sizeof(aux_msg) - i));
 758
 759	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 760
 761	/* Start with bits set for DDI_AUX_CTL register */
 762	aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg),
 763					     aux_clock_divider);
 764
 765	/* Select only valid bits for SRD_AUX_CTL */
 766	aux_ctl &= EDP_PSR_AUX_CTL_TIME_OUT_MASK |
 767		EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK |
 768		EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK |
 769		EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK;
 770
 771	intel_de_write(display, psr_aux_ctl_reg(display, cpu_transcoder),
 772		       aux_ctl);
 773}
 774
 775static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay)
 776{
 777	struct intel_display *display = to_intel_display(intel_dp);
 778
 779	if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) ||
 780	    intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE)
 781		return false;
 782
 783	return panel_replay ?
 784		intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
 785		DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
 786		intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
 787}
 788
 789static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 790				      const struct intel_crtc_state *crtc_state)
 791{
 792	u8 val = DP_PANEL_REPLAY_ENABLE |
 793		DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
 794		DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
 795		DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
 796		DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
 797	u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
 798
 799	if (crtc_state->has_sel_update)
 800		val |= DP_PANEL_REPLAY_SU_ENABLE;
 801
 802	if (crtc_state->enable_psr2_su_region_et)
 803		val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
 804
 805	if (crtc_state->req_psr2_sdp_prior_scanline)
 806		panel_replay_config2 |=
 807			DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE;
 808
 809	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val);
 810
 811	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
 812			   panel_replay_config2);
 813}
 814
 815static void _psr_enable_sink(struct intel_dp *intel_dp,
 816			     const struct intel_crtc_state *crtc_state)
 817{
 818	struct intel_display *display = to_intel_display(intel_dp);
 819	u8 val = 0;
 820
 821	if (crtc_state->has_sel_update) {
 822		val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
 823	} else {
 824		if (intel_dp->psr.link_standby)
 825			val |= DP_PSR_MAIN_LINK_ACTIVE;
 826
 827		if (DISPLAY_VER(display) >= 8)
 828			val |= DP_PSR_CRC_VERIFICATION;
 829	}
 830
 831	if (crtc_state->req_psr2_sdp_prior_scanline)
 832		val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
 833
 834	if (crtc_state->enable_psr2_su_region_et)
 835		val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
 836
 837	if (intel_dp->psr.entry_setup_frames > 0)
 838		val |= DP_PSR_FRAME_CAPTURE;
 839	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);
 840
 841	val |= DP_PSR_ENABLE;
 842	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);
 843}
 844
 845static void intel_psr_enable_sink(struct intel_dp *intel_dp,
 846				  const struct intel_crtc_state *crtc_state)
 847{
 848	intel_alpm_enable_sink(intel_dp, crtc_state);
 849
 850	crtc_state->has_panel_replay ?
 851		_panel_replay_enable_sink(intel_dp, crtc_state) :
 852		_psr_enable_sink(intel_dp, crtc_state);
 853
 854	if (intel_dp_is_edp(intel_dp))
 855		drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 856}
 857
 858void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp)
 859{
 860	/*
 861	 * NOTE: We might want to trigger mode set when
 862	 * disabling/enabling Panel Replay via debugfs interface to
 863	 * ensure this bit is cleared/set accordingly.
 864	 */
 865	if (CAN_PANEL_REPLAY(intel_dp) && panel_replay_global_enabled(intel_dp))
 866		drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
 867				   DP_PANEL_REPLAY_ENABLE);
 868}
 869
 870static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
 871{
 872	struct intel_display *display = to_intel_display(intel_dp);
 873	struct intel_connector *connector = intel_dp->attached_connector;
 874	u32 val = 0;
 875
 876	if (DISPLAY_VER(display) >= 11)
 877		val |= EDP_PSR_TP4_TIME_0us;
 878
 879	if (display->params.psr_safest_params) {
 880		val |= EDP_PSR_TP1_TIME_2500us;
 881		val |= EDP_PSR_TP2_TP3_TIME_2500us;
 882		goto check_tp3_sel;
 883	}
 884
 885	if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0)
 886		val |= EDP_PSR_TP1_TIME_0us;
 887	else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100)
 888		val |= EDP_PSR_TP1_TIME_100us;
 889	else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500)
 890		val |= EDP_PSR_TP1_TIME_500us;
 891	else
 892		val |= EDP_PSR_TP1_TIME_2500us;
 893
 894	if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
 895		val |= EDP_PSR_TP2_TP3_TIME_0us;
 896	else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 897		val |= EDP_PSR_TP2_TP3_TIME_100us;
 898	else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500)
 899		val |= EDP_PSR_TP2_TP3_TIME_500us;
 900	else
 901		val |= EDP_PSR_TP2_TP3_TIME_2500us;
 902
 903	/*
 904	 * WA 0479: hsw,bdw
 905	 * "Do not skip both TP1 and TP2/TP3"
 906	 */
 907	if (DISPLAY_VER(display) < 9 &&
 908	    connector->panel.vbt.psr.tp1_wakeup_time_us == 0 &&
 909	    connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
 910		val |= EDP_PSR_TP2_TP3_TIME_100us;
 911
 912check_tp3_sel:
 913	if (intel_dp_source_supports_tps3(display) &&
 914	    drm_dp_tps3_supported(intel_dp->dpcd))
 915		val |= EDP_PSR_TP_TP1_TP3;
 916	else
 917		val |= EDP_PSR_TP_TP1_TP2;
 918
 919	return val;
 920}
 921
 922static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
 923{
 924	struct intel_display *display = to_intel_display(intel_dp);
 925	struct intel_connector *connector = intel_dp->attached_connector;
 926	int idle_frames;
 927
 928	/* Let's use 6 as the minimum to cover all known cases including the
 929	 * off-by-one issue that HW has in some cases.
 930	 */
 931	idle_frames = max(6, connector->panel.vbt.psr.idle_frames);
 932	idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
 933
 934	if (drm_WARN_ON(display->drm, idle_frames > 0xf))
 935		idle_frames = 0xf;
 936
 937	return idle_frames;
 938}
 939
 940static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp)
 941{
 942	struct intel_display *display = to_intel_display(intel_dp);
 943	u32 current_dc_state = intel_display_power_get_current_dc_state(display);
 944	struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe);
 945	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
 946
 947	return (current_dc_state != DC_STATE_EN_UPTO_DC5 &&
 948		current_dc_state != DC_STATE_EN_UPTO_DC6) ||
 949		intel_dp->psr.active_non_psr_pipes ||
 950		READ_ONCE(vblank->enabled);
 951}
 952
 953static void hsw_activate_psr1(struct intel_dp *intel_dp)
 954{
 955	struct intel_display *display = to_intel_display(intel_dp);
 956	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
 957	u32 max_sleep_time = 0x1f;
 958	u32 val = EDP_PSR_ENABLE;
 959
 960	val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
 961
 962	if (DISPLAY_VER(display) < 20)
 963		val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time);
 964
 965	if (display->platform.haswell)
 966		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 967
 968	if (intel_dp->psr.link_standby)
 969		val |= EDP_PSR_LINK_STANDBY;
 970
 971	val |= intel_psr1_get_tp_time(intel_dp);
 972
 973	if (DISPLAY_VER(display) >= 8)
 974		val |= EDP_PSR_CRC_ENABLE;
 975
 976	if (DISPLAY_VER(display) >= 20)
 977		val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);
 978
 979	intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder),
 980		     ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val);
 981
 982	/* Wa_16025596647 */
 983	if ((DISPLAY_VER(display) == 20 ||
 984	     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
 985	    is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
 986		intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,
 987								       intel_dp->psr.pipe,
 988								       true);
 989}
 990
 991static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
 992{
 993	struct intel_display *display = to_intel_display(intel_dp);
 994	struct intel_connector *connector = intel_dp->attached_connector;
 995	u32 val = 0;
 996
 997	if (display->params.psr_safest_params)
 998		return EDP_PSR2_TP2_TIME_2500us;
 999
1000	if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
1001	    connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
1002		val |= EDP_PSR2_TP2_TIME_50us;
1003	else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
1004		val |= EDP_PSR2_TP2_TIME_100us;
1005	else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
1006		val |= EDP_PSR2_TP2_TIME_500us;
1007	else
1008		val |= EDP_PSR2_TP2_TIME_2500us;
1009
1010	return val;
1011}
1012
1013static int
1014psr2_block_count_lines(u8 io_wake_lines, u8 fast_wake_lines)
1015{
1016	return io_wake_lines < 9 && fast_wake_lines < 9 ? 8 : 12;
1017}
1018
1019static int psr2_block_count(struct intel_dp *intel_dp)
1020{
1021	return psr2_block_count_lines(intel_dp->psr.io_wake_lines,
1022				      intel_dp->psr.fast_wake_lines) / 4;
1023}
1024
1025static u8 frames_before_su_entry(struct intel_dp *intel_dp)
1026{
1027	u8 frames_before_su_entry;
1028
1029	frames_before_su_entry = max_t(u8,
1030				       intel_dp->psr.sink_sync_latency + 1,
1031				       2);
1032
1033	/* Entry setup frames must be at least 1 less than frames before SU entry */
1034	if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry)
1035		frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1;
1036
1037	return frames_before_su_entry;
1038}
1039
1040static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
1041{
1042	struct intel_display *display = to_intel_display(intel_dp);
1043	struct intel_psr *psr = &intel_dp->psr;
1044	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1045
1046	if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) {
1047		u32 val = psr->su_region_et_enabled ?
1048			LNL_EDP_PSR2_SU_REGION_ET_ENABLE : 0;
1049
1050		if (intel_dp->psr.req_psr2_sdp_prior_scanline)
1051			val |= EDP_PSR2_SU_SDP_SCANLINE;
1052
1053		intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder),
1054			       val);
1055	}
1056
1057	intel_de_rmw(display,
1058		     PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder),
1059		     0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME);
1060
1061	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
1062		     TRANS_DP2_PANEL_REPLAY_ENABLE);
1063}
1064
1065static void hsw_activate_psr2(struct intel_dp *intel_dp)
1066{
1067	struct intel_display *display = to_intel_display(intel_dp);
1068	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1069	u32 val = EDP_PSR2_ENABLE;
1070	u32 psr_val = 0;
1071	u8 idle_frames;
1072
1073	/* Wa_16025596647 */
1074	if ((DISPLAY_VER(display) == 20 ||
1075	     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
1076	    is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
1077		idle_frames = 0;
1078	else
1079		idle_frames = psr_compute_idle_frames(intel_dp);
1080	val |= EDP_PSR2_IDLE_FRAMES(idle_frames);
1081
1082	if (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)
1083		val |= EDP_SU_TRACK_ENABLE;
1084
1085	if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13)
1086		val |= EDP_Y_COORDINATE_ENABLE;
1087
1088	val |= EDP_PSR2_FRAME_BEFORE_SU(frames_before_su_entry(intel_dp));
1089
1090	val |= intel_psr2_get_tp_time(intel_dp);
1091
1092	if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) {
1093		if (psr2_block_count(intel_dp) > 2)
1094			val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3;
1095		else
1096			val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
1097	}
1098
1099	/* Wa_22012278275:adl-p */
1100	if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_E0)) {
1101		static const u8 map[] = {
1102			2, /* 5 lines */
1103			1, /* 6 lines */
1104			0, /* 7 lines */
1105			3, /* 8 lines */
1106			6, /* 9 lines */
1107			5, /* 10 lines */
1108			4, /* 11 lines */
1109			7, /* 12 lines */
1110		};
1111		/*
1112		 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see
1113		 * comments below for more information
1114		 */
1115		int tmp;
1116
1117		tmp = map[intel_dp->psr.io_wake_lines -
1118			  TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
1119		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp + TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES);
1120
1121		tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
1122		val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES);
1123	} else if (DISPLAY_VER(display) >= 20) {
1124		val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);
1125	} else if (DISPLAY_VER(display) >= 12) {
1126		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);
1127		val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);
1128	} else if (DISPLAY_VER(display) >= 9) {
1129		val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);
1130		val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);
1131	}
1132
1133	if (intel_dp->psr.req_psr2_sdp_prior_scanline)
1134		val |= EDP_PSR2_SU_SDP_SCANLINE;
1135
1136	if (DISPLAY_VER(display) >= 20)
1137		psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);
1138
1139	if (intel_dp->psr.psr2_sel_fetch_enabled) {
1140		u32 tmp;
1141
1142		tmp = intel_de_read(display,
1143				    PSR2_MAN_TRK_CTL(display, cpu_transcoder));
1144		drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
1145	} else if (HAS_PSR2_SEL_FETCH(display)) {
1146		intel_de_write(display,
1147			       PSR2_MAN_TRK_CTL(display, cpu_transcoder), 0);
1148	}
1149
1150	if (intel_dp->psr.su_region_et_enabled)
1151		val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE;
1152
1153	/*
1154	 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
1155	 * recommending keep this bit unset while PSR2 is enabled.
1156	 */
1157	intel_de_write(display, psr_ctl_reg(display, cpu_transcoder), psr_val);
1158
1159	intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), val);
1160}
1161
1162static bool
1163transcoder_has_psr2(struct intel_display *display, enum transcoder cpu_transcoder)
1164{
1165	if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
1166		return cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B;
1167	else if (DISPLAY_VER(display) >= 12)
1168		return cpu_transcoder == TRANSCODER_A;
1169	else if (DISPLAY_VER(display) >= 9)
1170		return cpu_transcoder == TRANSCODER_EDP;
1171	else
1172		return false;
1173}
1174
1175static u32 intel_get_frame_time_us(const struct intel_crtc_state *crtc_state)
1176{
1177	if (!crtc_state->hw.active)
1178		return 0;
1179
1180	return DIV_ROUND_UP(1000 * 1000,
1181			    drm_mode_vrefresh(&crtc_state->hw.adjusted_mode));
1182}
1183
1184static void psr2_program_idle_frames(struct intel_dp *intel_dp,
1185				     u32 idle_frames)
1186{
1187	struct intel_display *display = to_intel_display(intel_dp);
1188	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1189
1190	intel_de_rmw(display, EDP_PSR2_CTL(display, cpu_transcoder),
1191		     EDP_PSR2_IDLE_FRAMES_MASK,
1192		     EDP_PSR2_IDLE_FRAMES(idle_frames));
1193}
1194
1195static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
1196{
1197	struct intel_display *display = to_intel_display(intel_dp);
1198
1199	psr2_program_idle_frames(intel_dp, 0);
1200	intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO);
1201}
1202
1203static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
1204{
1205	struct intel_display *display = to_intel_display(intel_dp);
1206
1207	intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
1208	psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
1209}
1210
1211static void tgl_dc3co_disable_work(struct work_struct *work)
1212{
1213	struct intel_dp *intel_dp =
1214		container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
1215
1216	mutex_lock(&intel_dp->psr.lock);
1217	/* If delayed work is pending, it is not idle */
1218	if (delayed_work_pending(&intel_dp->psr.dc3co_work))
1219		goto unlock;
1220
1221	tgl_psr2_disable_dc3co(intel_dp);
1222unlock:
1223	mutex_unlock(&intel_dp->psr.lock);
1224}
1225
1226static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
1227{
1228	if (!intel_dp->psr.dc3co_exitline)
1229		return;
1230
1231	cancel_delayed_work(&intel_dp->psr.dc3co_work);
1232	/* Before PSR2 exit disallow dc3co*/
1233	tgl_psr2_disable_dc3co(intel_dp);
1234}
1235
1236static bool
1237dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,
1238			      struct intel_crtc_state *crtc_state)
1239{
1240	struct intel_display *display = to_intel_display(intel_dp);
1241	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1242	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1243	enum port port = dig_port->base.port;
1244
1245	if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
1246		return pipe <= PIPE_B && port <= PORT_B;
1247	else
1248		return pipe == PIPE_A && port == PORT_A;
1249}
1250
1251static void
1252tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
1253				  struct intel_crtc_state *crtc_state)
1254{
1255	struct intel_display *display = to_intel_display(intel_dp);
1256	const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
1257	struct i915_power_domains *power_domains = &display->power.domains;
1258	u32 exit_scanlines;
1259
1260	/*
1261	 * FIXME: Due to the changed sequence of activating/deactivating DC3CO,
1262	 * disable DC3CO until the changed dc3co activating/deactivating sequence
1263	 * is applied. B.Specs:49196
1264	 */
1265	return;
1266
1267	/*
1268	 * DMC's DC3CO exit mechanism has an issue with Selective Fecth
1269	 * TODO: when the issue is addressed, this restriction should be removed.
1270	 */
1271	if (crtc_state->enable_psr2_sel_fetch)
1272		return;
1273
1274	if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO))
1275		return;
1276
1277	if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
1278		return;
1279
1280	/* Wa_16011303918:adl-p */
1281	if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))
1282		return;
1283
1284	/*
1285	 * DC3CO Exit time 200us B.Spec 49196
1286	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
1287	 */
1288	exit_scanlines =
1289		intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
1290
1291	if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay))
1292		return;
1293
1294	crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
1295}
1296
1297static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
1298					      struct intel_crtc_state *crtc_state)
1299{
1300	struct intel_display *display = to_intel_display(intel_dp);
1301
1302	if (!display->params.enable_psr2_sel_fetch &&
1303	    intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
1304		drm_dbg_kms(display->drm,
1305			    "PSR2 sel fetch not enabled, disabled by parameter\n");
1306		return false;
1307	}
1308
1309	return crtc_state->enable_psr2_sel_fetch = true;
1310}
1311
1312static bool psr2_granularity_check(struct intel_dp *intel_dp,
1313				   struct intel_crtc_state *crtc_state)
1314{
1315	struct intel_display *display = to_intel_display(intel_dp);
1316	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1317	const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
1318	const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1319	u16 y_granularity = 0;
1320
1321	/* PSR2 HW only send full lines so we only need to validate the width */
1322	if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
1323		return false;
1324
1325	if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
1326		return false;
1327
1328	/* HW tracking is only aligned to 4 lines */
1329	if (!crtc_state->enable_psr2_sel_fetch)
1330		return intel_dp->psr.su_y_granularity == 4;
1331
1332	/*
1333	 * adl_p and mtl platforms have 1 line granularity.
1334	 * For other platforms with SW tracking we can adjust the y coordinates
1335	 * to match sink requirement if multiple of 4.
1336	 */
1337	if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
1338		y_granularity = intel_dp->psr.su_y_granularity;
1339	else if (intel_dp->psr.su_y_granularity <= 2)
1340		y_granularity = 4;
1341	else if ((intel_dp->psr.su_y_granularity % 4) == 0)
1342		y_granularity = intel_dp->psr.su_y_granularity;
1343
1344	if (y_granularity == 0 || crtc_vdisplay % y_granularity)
1345		return false;
1346
1347	if (crtc_state->dsc.compression_enable &&
1348	    vdsc_cfg->slice_height % y_granularity)
1349		return false;
1350
1351	crtc_state->su_y_granularity = y_granularity;
1352	return true;
1353}
1354
1355static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp,
1356							struct intel_crtc_state *crtc_state)
1357{
1358	struct intel_display *display = to_intel_display(intel_dp);
1359	const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode;
1360	u32 hblank_total, hblank_ns, req_ns;
1361
1362	hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
1363	hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock);
1364
1365	/* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */
1366	req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000);
1367
1368	if ((hblank_ns - req_ns) > 100)
1369		return true;
1370
1371	/* Not supported <13 / Wa_22012279113:adl-p */
1372	if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
1373		return false;
1374
1375	crtc_state->req_psr2_sdp_prior_scanline = true;
1376	return true;
1377}
1378
1379static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp,
1380					const struct drm_display_mode *adjusted_mode)
1381{
1382	struct intel_display *display = to_intel_display(intel_dp);
1383	int psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
1384	int entry_setup_frames = 0;
1385
1386	if (psr_setup_time < 0) {
1387		drm_dbg_kms(display->drm,
1388			    "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
1389			    intel_dp->psr_dpcd[1]);
1390		return -ETIME;
1391	}
1392
1393	if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
1394	    adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
1395		if (DISPLAY_VER(display) >= 20) {
1396			/* setup entry frames can be up to 3 frames */
1397			entry_setup_frames = 1;
1398			drm_dbg_kms(display->drm,
1399				    "PSR setup entry frames %d\n",
1400				    entry_setup_frames);
1401		} else {
1402			drm_dbg_kms(display->drm,
1403				    "PSR condition failed: PSR setup time (%d us) too long\n",
1404				    psr_setup_time);
1405			return -ETIME;
1406		}
1407	}
1408
1409	return entry_setup_frames;
1410}
1411
1412static
1413int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state,
1414				       bool needs_panel_replay,
1415				       bool needs_sel_update)
1416{
1417	struct intel_display *display = to_intel_display(crtc_state);
1418
1419	if (!crtc_state->has_psr)
1420		return 0;
1421
1422	/* Wa_14015401596 */
1423	if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14))
1424		return 1;
1425
1426	/* Rest is for SRD_STATUS needed on LunarLake and onwards */
1427	if (DISPLAY_VER(display) < 20)
1428		return 0;
1429
1430	/*
1431	 * Comment on SRD_STATUS register in Bspec for LunarLake and onwards:
1432	 *
1433	 * To deterministically capture the transition of the state machine
1434	 * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least
1435	 * one line after the non-delayed V. Blank.
1436	 *
1437	 * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0
1438	 * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ]
1439	 * - TRANS_VTOTAL[ Vertical Active ])
1440	 *
1441	 * SRD_STATUS is used only by PSR1 on PantherLake.
1442	 * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake.
1443	 */
1444
1445	if (DISPLAY_VER(display) >= 30 && (needs_panel_replay ||
1446					   needs_sel_update))
1447		return 0;
1448	else if (DISPLAY_VER(display) < 30 && (needs_sel_update ||
1449					       intel_crtc_has_type(crtc_state,
1450								   INTEL_OUTPUT_EDP)))
1451		return 0;
1452	else
1453		return 1;
1454}
1455
1456static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state,
1457					int vblank,
1458					int wake_lines)
1459{
1460	if (crtc_state->req_psr2_sdp_prior_scanline)
1461		vblank -= 1;
1462
1463	/* Vblank >= PSR2_CTL Block Count Number maximum line count */
1464	if (vblank < wake_lines)
1465		return false;
1466
1467	return true;
1468}
1469
1470static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
1471				       const struct intel_crtc_state *crtc_state,
1472				       bool aux_less,
1473				       bool needs_panel_replay,
1474				       bool needs_sel_update)
1475{
1476	struct intel_display *display = to_intel_display(intel_dp);
1477	int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
1478		crtc_state->hw.adjusted_mode.crtc_vblank_start;
1479	int wake_lines;
1480	int scl = _intel_psr_min_set_context_latency(crtc_state,
1481						     needs_panel_replay,
1482						     needs_sel_update);
1483	vblank -= scl;
1484
1485	if (aux_less)
1486		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
1487	else
1488		wake_lines = DISPLAY_VER(display) < 20 ?
1489			psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
1490					       crtc_state->alpm_state.fast_wake_lines) :
1491			crtc_state->alpm_state.io_wake_lines;
1492
1493	/*
1494	 * Guardband has not been computed yet, so we conservatively check if the
1495	 * full vblank duration is sufficient to accommodate wake line requirements
1496	 * for PSR features like Panel Replay and Selective Update.
1497	 *
1498	 * Once the actual guardband is available, a more accurate validation is
1499	 * performed in intel_psr_compute_config_late(), and PSR features are
1500	 * disabled if wake lines exceed the available guardband.
1501	 */
1502	return _wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines);
1503}
1504
1505static bool alpm_config_valid(struct intel_dp *intel_dp,
1506			      struct intel_crtc_state *crtc_state,
1507			      bool aux_less,
1508			      bool needs_panel_replay,
1509			      bool needs_sel_update)
1510{
1511	struct intel_display *display = to_intel_display(intel_dp);
1512
1513	if (!intel_alpm_compute_params(intel_dp, crtc_state)) {
1514		drm_dbg_kms(display->drm,
1515			    "PSR2/Panel Replay  not enabled, Unable to use long enough wake times\n");
1516		return false;
1517	}
1518
1519	if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less,
1520					needs_panel_replay, needs_sel_update)) {
1521		drm_dbg_kms(display->drm,
1522			    "PSR2/Panel Replay not enabled, too short vblank time\n");
1523		return false;
1524	}
1525
1526	return true;
1527}
1528
1529static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
1530				    struct intel_crtc_state *crtc_state)
1531{
1532	struct intel_display *display = to_intel_display(intel_dp);
1533	int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
1534	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1535	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
1536
1537	if (!intel_dp->psr.sink_psr2_support || display->params.enable_psr == 1)
1538		return false;
1539
1540	/* JSL and EHL only supports eDP 1.3 */
1541	if (display->platform.jasperlake || display->platform.elkhartlake) {
1542		drm_dbg_kms(display->drm, "PSR2 not supported by phy\n");
1543		return false;
1544	}
1545
1546	/* Wa_16011181250 */
1547	if (display->platform.rocketlake || display->platform.alderlake_s ||
1548	    display->platform.dg2) {
1549		drm_dbg_kms(display->drm,
1550			    "PSR2 is defeatured for this platform\n");
1551		return false;
1552	}
1553
1554	if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {
1555		drm_dbg_kms(display->drm,
1556			    "PSR2 not completely functional in this stepping\n");
1557		return false;
1558	}
1559
1560	if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) {
1561		drm_dbg_kms(display->drm,
1562			    "PSR2 not supported in transcoder %s\n",
1563			    transcoder_name(crtc_state->cpu_transcoder));
1564		return false;
1565	}
1566
1567	/*
1568	 * DSC and PSR2 cannot be enabled simultaneously. If a requested
1569	 * resolution requires DSC to be enabled, priority is given to DSC
1570	 * over PSR2.
1571	 */
1572	if (crtc_state->dsc.compression_enable &&
1573	    (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)) {
1574		drm_dbg_kms(display->drm,
1575			    "PSR2 cannot be enabled since DSC is enabled\n");
1576		return false;
1577	}
1578
1579	if (DISPLAY_VER(display) >= 20) {
1580		psr_max_h = crtc_hdisplay;
1581		psr_max_v = crtc_vdisplay;
1582		max_bpp = crtc_state->pipe_bpp;
1583	} else if (IS_DISPLAY_VER(display, 12, 14)) {
1584		psr_max_h = 5120;
1585		psr_max_v = 3200;
1586		max_bpp = 30;
1587	} else if (IS_DISPLAY_VER(display, 10, 11)) {
1588		psr_max_h = 4096;
1589		psr_max_v = 2304;
1590		max_bpp = 24;
1591	} else if (DISPLAY_VER(display) == 9) {
1592		psr_max_h = 3640;
1593		psr_max_v = 2304;
1594		max_bpp = 24;
1595	}
1596
1597	if (crtc_state->pipe_bpp > max_bpp) {
1598		drm_dbg_kms(display->drm,
1599			    "PSR2 not enabled, pipe bpp %d > max supported %d\n",
1600			    crtc_state->pipe_bpp, max_bpp);
1601		return false;
1602	}
1603
1604	/* Wa_16011303918:adl-p */
1605	if (crtc_state->vrr.enable &&
1606	    display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {
1607		drm_dbg_kms(display->drm,
1608			    "PSR2 not enabled, not compatible with HW stepping + VRR\n");
1609		return false;
1610	}
1611
1612	if (!alpm_config_valid(intel_dp, crtc_state, false, false, true))
1613		return false;
1614
1615	if (!crtc_state->enable_psr2_sel_fetch &&
1616	    (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
1617		drm_dbg_kms(display->drm,
1618			    "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
1619			    crtc_hdisplay, crtc_vdisplay,
1620			    psr_max_h, psr_max_v);
1621		return false;
1622	}
1623
1624	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
1625
1626	return true;
1627}
1628
1629static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
1630					  struct intel_crtc_state *crtc_state)
1631{
1632	struct intel_display *display = to_intel_display(intel_dp);
1633
1634	if (HAS_PSR2_SEL_FETCH(display) &&
1635	    !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
1636	    !HAS_PSR_HW_TRACKING(display)) {
1637		drm_dbg_kms(display->drm,
1638			    "Selective update not enabled, selective fetch not valid and no HW tracking available\n");
1639		goto unsupported;
1640	}
1641
1642	if (!sel_update_global_enabled(intel_dp)) {
1643		drm_dbg_kms(display->drm,
1644			    "Selective update disabled by flag\n");
1645		goto unsupported;
1646	}
1647
1648	if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state))
1649		goto unsupported;
1650
1651	if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
1652		drm_dbg_kms(display->drm,
1653			    "Selective update not enabled, SDP indication do not fit in hblank\n");
1654		goto unsupported;
1655	}
1656
1657	if (crtc_state->has_panel_replay) {
1658		if (DISPLAY_VER(display) < 14)
1659			goto unsupported;
1660
1661		if (!intel_dp->psr.sink_panel_replay_su_support)
1662			goto unsupported;
1663
1664		if (intel_dsc_enabled_on_link(crtc_state) &&
1665		    intel_dp->psr.sink_panel_replay_dsc_support !=
1666		    INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) {
1667			drm_dbg_kms(display->drm,
1668				    "Selective update with Panel Replay not enabled because it's not supported with DSC\n");
1669			goto unsupported;
1670		}
1671	}
1672
1673	if (crtc_state->crc_enabled) {
1674		drm_dbg_kms(display->drm,
1675			    "Selective update not enabled because it would inhibit pipe CRC calculation\n");
1676		goto unsupported;
1677	}
1678
1679	if (!psr2_granularity_check(intel_dp, crtc_state)) {
1680		drm_dbg_kms(display->drm,
1681			    "Selective update not enabled, SU granularity not compatible\n");
1682		goto unsupported;
1683	}
1684
1685	crtc_state->enable_psr2_su_region_et =
1686		psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay);
1687
1688	return true;
1689
1690unsupported:
1691	crtc_state->enable_psr2_sel_fetch = false;
1692	return false;
1693}
1694
1695static bool _psr_compute_config(struct intel_dp *intel_dp,
1696				struct intel_crtc_state *crtc_state)
1697{
1698	struct intel_display *display = to_intel_display(intel_dp);
1699	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1700	int entry_setup_frames;
1701
1702	if (!CAN_PSR(intel_dp) || !display->params.enable_psr)
1703		return false;
1704
1705	/*
1706	 * Currently PSR doesn't work reliably with VRR enabled.
1707	 */
1708	if (crtc_state->vrr.enable)
1709		return false;
1710
1711	entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, adjusted_mode);
1712
1713	if (entry_setup_frames >= 0) {
1714		crtc_state->entry_setup_frames = entry_setup_frames;
1715	} else {
1716		crtc_state->no_psr_reason = "PSR setup timing not met";
1717		drm_dbg_kms(display->drm,
1718			    "PSR condition failed: PSR setup timing not met\n");
1719		return false;
1720	}
1721
1722	return true;
1723}
1724
1725static bool
1726_panel_replay_compute_config(struct intel_dp *intel_dp,
1727			     struct intel_crtc_state *crtc_state,
1728			     const struct drm_connector_state *conn_state)
1729{
1730	struct intel_display *display = to_intel_display(intel_dp);
1731	struct intel_connector *connector =
1732		to_intel_connector(conn_state->connector);
1733	struct intel_hdcp *hdcp = &connector->hdcp;
1734
1735	if (!CAN_PANEL_REPLAY(intel_dp))
1736		return false;
1737
1738	if (!panel_replay_global_enabled(intel_dp)) {
1739		drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n");
1740		return false;
1741	}
1742
1743	if (crtc_state->crc_enabled) {
1744		drm_dbg_kms(display->drm,
1745			    "Panel Replay not enabled because it would inhibit pipe CRC calculation\n");
1746		return false;
1747	}
1748
1749	if (intel_dsc_enabled_on_link(crtc_state) &&
1750	    intel_dp->psr.sink_panel_replay_dsc_support ==
1751	    INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) {
1752		drm_dbg_kms(display->drm,
1753			    "Panel Replay not enabled because it's not supported with DSC\n");
1754		return false;
1755	}
1756
1757	if (!intel_dp_is_edp(intel_dp))
1758		return true;
1759
1760	/* Remaining checks are for eDP only */
1761
1762	if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A &&
1763	    to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B)
1764		return false;
1765
1766	/* 128b/132b Panel Replay is not supported on eDP */
1767	if (intel_dp_is_uhbr(crtc_state)) {
1768		drm_dbg_kms(display->drm,
1769			    "Panel Replay is not supported with 128b/132b\n");
1770		return false;
1771	}
1772
1773	/* HW will not allow Panel Replay on eDP when HDCP enabled */
1774	if (conn_state->content_protection ==
1775	    DRM_MODE_CONTENT_PROTECTION_DESIRED ||
1776	    (conn_state->content_protection ==
1777	     DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value ==
1778	     DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) {
1779		drm_dbg_kms(display->drm,
1780			    "Panel Replay is not supported with HDCP\n");
1781		return false;
1782	}
1783
1784	if (!alpm_config_valid(intel_dp, crtc_state, true, true, false))
1785		return false;
1786
1787	return true;
1788}
1789
1790static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp,
1791					   struct intel_crtc_state *crtc_state)
1792{
1793	struct intel_display *display = to_intel_display(intel_dp);
1794
1795	return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 &&
1796		!crtc_state->has_sel_update);
1797}
1798
1799static
1800void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp,
1801				 struct intel_crtc_state *crtc_state)
1802{
1803	struct intel_display *display = to_intel_display(intel_dp);
1804	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
1805	struct intel_crtc *crtc;
1806	u8 active_pipes = 0;
1807
1808	/* Wa_16025596647 */
1809	if (DISPLAY_VER(display) != 20 &&
1810	    !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
1811		return;
1812
1813	/* Not needed by Panel Replay  */
1814	if (crtc_state->has_panel_replay)
1815		return;
1816
1817	/* We ignore possible secondary PSR/Panel Replay capable eDP */
1818	for_each_intel_crtc(display->drm, crtc)
1819		active_pipes |= crtc->active ? BIT(crtc->pipe) : 0;
1820
1821	active_pipes = intel_calc_active_pipes(state, active_pipes);
1822
1823	crtc_state->active_non_psr_pipes = active_pipes &
1824		~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe);
1825}
1826
1827void intel_psr_compute_config(struct intel_dp *intel_dp,
1828			      struct intel_crtc_state *crtc_state,
1829			      struct drm_connector_state *conn_state)
1830{
1831	struct intel_display *display = to_intel_display(intel_dp);
1832	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1833
1834	if (!psr_global_enabled(intel_dp)) {
1835		drm_dbg_kms(display->drm, "PSR disabled by flag\n");
1836		return;
1837	}
1838
1839	if (intel_dp->psr.sink_not_reliable) {
1840		drm_dbg_kms(display->drm,
1841			    "PSR sink implementation is not reliable\n");
1842		return;
1843	}
1844
1845	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1846		drm_dbg_kms(display->drm,
1847			    "PSR condition failed: Interlaced mode enabled\n");
1848		return;
1849	}
1850
1851	/*
1852	 * FIXME figure out what is wrong with PSR+joiner and
1853	 * fix it. Presumably something related to the fact that
1854	 * PSR is a transcoder level feature.
1855	 */
1856	if (crtc_state->joiner_pipes) {
1857		drm_dbg_kms(display->drm,
1858			    "PSR disabled due to joiner\n");
1859		return;
1860	}
1861
1862	/* Only used for state verification. */
1863	crtc_state->panel_replay_dsc_support = intel_dp->psr.sink_panel_replay_dsc_support;
1864	crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp,
1865								    crtc_state,
1866								    conn_state);
1867
1868	crtc_state->has_psr = crtc_state->has_panel_replay ? true :
1869		_psr_compute_config(intel_dp, crtc_state);
1870
1871	if (!crtc_state->has_psr)
1872		return;
1873
1874	crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
1875}
1876
1877void intel_psr_get_config(struct intel_encoder *encoder,
1878			  struct intel_crtc_state *pipe_config)
1879{
1880	struct intel_display *display = to_intel_display(encoder);
1881	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1882	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
1883	struct intel_dp *intel_dp;
1884	u32 val;
1885
1886	if (!dig_port)
1887		return;
1888
1889	intel_dp = &dig_port->dp;
1890	if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))
1891		return;
1892
1893	mutex_lock(&intel_dp->psr.lock);
1894	if (!intel_dp->psr.enabled)
1895		goto unlock;
1896
1897	if (intel_dp->psr.panel_replay_enabled) {
1898		pipe_config->has_psr = pipe_config->has_panel_replay = true;
1899	} else {
1900		/*
1901		 * Not possible to read EDP_PSR/PSR2_CTL registers as it is
1902		 * enabled/disabled because of frontbuffer tracking and others.
1903		 */
1904		pipe_config->has_psr = true;
1905	}
1906
1907	pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled;
1908	pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1909
1910	if (!intel_dp->psr.sel_update_enabled)
1911		goto unlock;
1912
1913	if (HAS_PSR2_SEL_FETCH(display)) {
1914		val = intel_de_read(display,
1915				    PSR2_MAN_TRK_CTL(display, cpu_transcoder));
1916		if (val & PSR2_MAN_TRK_CTL_ENABLE)
1917			pipe_config->enable_psr2_sel_fetch = true;
1918	}
1919
1920	pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled;
1921
1922	if (DISPLAY_VER(display) >= 12) {
1923		val = intel_de_read(display,
1924				    TRANS_EXITLINE(display, cpu_transcoder));
1925		pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val);
1926	}
1927unlock:
1928	mutex_unlock(&intel_dp->psr.lock);
1929}
1930
1931static void intel_psr_activate(struct intel_dp *intel_dp)
1932{
1933	struct intel_display *display = to_intel_display(intel_dp);
1934	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1935
1936	drm_WARN_ON(display->drm,
1937		    transcoder_has_psr2(display, cpu_transcoder) &&
1938		    intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE);
1939
1940	drm_WARN_ON(display->drm,
1941		    intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE);
1942
1943	drm_WARN_ON(display->drm, intel_dp->psr.active);
1944
1945	drm_WARN_ON(display->drm, !intel_dp->psr.enabled);
1946
1947	lockdep_assert_held(&intel_dp->psr.lock);
1948
1949	/* psr1, psr2 and panel-replay are mutually exclusive.*/
1950	if (intel_dp->psr.panel_replay_enabled)
1951		dg2_activate_panel_replay(intel_dp);
1952	else if (intel_dp->psr.sel_update_enabled)
1953		hsw_activate_psr2(intel_dp);
1954	else
1955		hsw_activate_psr1(intel_dp);
1956
1957	intel_dp->psr.active = true;
1958	intel_dp->psr.no_psr_reason = NULL;
1959}
1960
1961/*
1962 * Wa_16013835468
1963 * Wa_14015648006
1964 */
1965static void wm_optimization_wa(struct intel_dp *intel_dp,
1966			       const struct intel_crtc_state *crtc_state)
1967{
1968	struct intel_display *display = to_intel_display(intel_dp);
1969	enum pipe pipe = intel_dp->psr.pipe;
1970	bool activate = false;
1971
1972	/* Wa_14015648006 */
1973	if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled)
1974		activate = true;
1975
1976	/* Wa_16013835468 */
1977	if (DISPLAY_VER(display) == 12 &&
1978	    crtc_state->hw.adjusted_mode.crtc_vblank_start !=
1979	    crtc_state->hw.adjusted_mode.crtc_vdisplay)
1980		activate = true;
1981
1982	if (activate)
1983		intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,
1984			     0, LATENCY_REPORTING_REMOVED(pipe));
1985	else
1986		intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,
1987			     LATENCY_REPORTING_REMOVED(pipe), 0);
1988}
1989
1990static void intel_psr_enable_source(struct intel_dp *intel_dp,
1991				    const struct intel_crtc_state *crtc_state)
1992{
1993	struct intel_display *display = to_intel_display(intel_dp);
1994	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1995	u32 mask = 0;
1996
1997	/*
1998	 * Only HSW and BDW have PSR AUX registers that need to be setup.
1999	 * SKL+ use hardcoded values PSR AUX transactions
2000	 */
2001	if (DISPLAY_VER(display) < 9)
2002		hsw_psr_setup_aux(intel_dp);
2003
2004	/*
2005	 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
2006	 * mask LPSP to avoid dependency on other drivers that might block
2007	 * runtime_pm besides preventing  other hw tracking issues now we
2008	 * can rely on frontbuffer tracking.
2009	 *
2010	 * From bspec prior LunarLake:
2011	 * Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug] are used in
2012	 * panel replay mode.
2013	 *
2014	 * From bspec beyod LunarLake:
2015	 * Panel Replay on DP: No bits are applicable
2016	 * Panel Replay on eDP: All bits are applicable
2017	 */
2018	if (DISPLAY_VER(display) < 20 || intel_dp_is_edp(intel_dp))
2019		mask = EDP_PSR_DEBUG_MASK_HPD;
2020
2021	if (intel_dp_is_edp(intel_dp)) {
2022		mask |= EDP_PSR_DEBUG_MASK_MEMUP;
2023
2024		/*
2025		 * For some unknown reason on HSW non-ULT (or at least on
2026		 * Dell Latitude E6540) external displays start to flicker
2027		 * when PSR is enabled on the eDP. SR/PC6 residency is much
2028		 * higher than should be possible with an external display.
2029		 * As a workaround leave LPSP unmasked to prevent PSR entry
2030		 * when external displays are active.
2031		 */
2032		if (DISPLAY_VER(display) >= 8 || display->platform.haswell_ult)
2033			mask |= EDP_PSR_DEBUG_MASK_LPSP;
2034
2035		if (DISPLAY_VER(display) < 20)
2036			mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
2037
2038		/*
2039		 * No separate pipe reg write mask on hsw/bdw, so have to unmask all
2040		 * registers in order to keep the CURSURFLIVE tricks working :(
2041		 */
2042		if (IS_DISPLAY_VER(display, 9, 10))
2043			mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
2044
2045		/* allow PSR with sprite enabled */
2046		if (display->platform.haswell)
2047			mask |= EDP_PSR_DEBUG_MASK_SPRITE_ENABLE;
2048	}
2049
2050	intel_de_write(display, psr_debug_reg(display, cpu_transcoder), mask);
2051
2052	psr_irq_control(intel_dp);
2053
2054	/*
2055	 * TODO: if future platforms supports DC3CO in more than one
2056	 * transcoder, EXITLINE will need to be unset when disabling PSR
2057	 */
2058	if (intel_dp->psr.dc3co_exitline)
2059		intel_de_rmw(display,
2060			     TRANS_EXITLINE(display, cpu_transcoder),
2061			     EXITLINE_MASK,
2062			     intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE);
2063
2064	if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display))
2065		intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
2066			     intel_dp->psr.psr2_sel_fetch_enabled ?
2067			     IGNORE_PSR2_HW_TRACKING : 0);
2068
2069	/*
2070	 * Wa_16013835468
2071	 * Wa_14015648006
2072	 */
2073	wm_optimization_wa(intel_dp, crtc_state);
2074
2075	if (intel_dp->psr.sel_update_enabled) {
2076		if (DISPLAY_VER(display) == 9)
2077			intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0,
2078				     PSR2_VSC_ENABLE_PROG_HEADER |
2079				     PSR2_ADD_VERTICAL_LINE_COUNT);
2080
2081		/*
2082		 * Wa_16014451276:adlp,mtl[a0,b0]
2083		 * All supported adlp panels have 1-based X granularity, this may
2084		 * cause issues if non-supported panels are used.
2085		 */
2086		if (!intel_dp->psr.panel_replay_enabled &&
2087		    (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) ||
2088		     display->platform.alderlake_p))
2089			intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
2090				     0, ADLP_1_BASED_X_GRANULARITY);
2091
2092		/* Wa_16012604467:adlp,mtl[a0,b0] */
2093		if (!intel_dp->psr.panel_replay_enabled &&
2094		    IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0))
2095			intel_de_rmw(display,
2096				     MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder),
2097				     0,
2098				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
2099		else if (display->platform.alderlake_p)
2100			intel_de_rmw(display, CLKGATE_DIS_MISC, 0,
2101				     CLKGATE_DIS_MISC_DMASC_GATING_DIS);
2102	}
2103
2104	/* Wa_16025596647 */
2105	if ((DISPLAY_VER(display) == 20 ||
2106	     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
2107	    !intel_dp->psr.panel_replay_enabled)
2108		intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true);
2109
2110	intel_alpm_configure(intel_dp, crtc_state);
2111}
2112
2113static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
2114{
2115	struct intel_display *display = to_intel_display(intel_dp);
2116	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2117	u32 val;
2118
2119	if (intel_dp->psr.panel_replay_enabled)
2120		goto no_err;
2121
2122	/*
2123	 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
2124	 * will still keep the error set even after the reset done in the
2125	 * irq_preinstall and irq_uninstall hooks.
2126	 * And enabling in this situation cause the screen to freeze in the
2127	 * first time that PSR HW tries to activate so lets keep PSR disabled
2128	 * to avoid any rendering problems.
2129	 */
2130	val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder));
2131	val &= psr_irq_psr_error_bit_get(intel_dp);
2132	if (val) {
2133		intel_dp->psr.sink_not_reliable = true;
2134		drm_dbg_kms(display->drm,
2135			    "PSR interruption error set, not enabling PSR\n");
2136		return false;
2137	}
2138
2139no_err:
2140	return true;
2141}
2142
2143static void intel_psr_enable_locked(struct intel_dp *intel_dp,
2144				    const struct intel_crtc_state *crtc_state)
2145{
2146	struct intel_display *display = to_intel_display(intel_dp);
2147	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2148	u32 val;
2149
2150	drm_WARN_ON(display->drm, intel_dp->psr.enabled);
2151
2152	intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update;
2153	intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
2154	intel_dp->psr.busy_frontbuffer_bits = 0;
2155	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
2156	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
2157	/* DC5/DC6 requires at least 6 idle frames */
2158	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
2159	intel_dp->psr.dc3co_exit_delay = val;
2160	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
2161	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
2162	intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et;
2163	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
2164	intel_dp->psr.req_psr2_sdp_prior_scanline =
2165		crtc_state->req_psr2_sdp_prior_scanline;
2166	intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes;
2167	intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used;
2168	intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines;
2169	intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines;
2170	intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames;
2171
2172	if (!psr_interrupt_error_check(intel_dp))
2173		return;
2174
2175	if (intel_dp->psr.panel_replay_enabled)
2176		drm_dbg_kms(display->drm, "Enabling Panel Replay\n");
2177	else
2178		drm_dbg_kms(display->drm, "Enabling PSR%s\n",
2179			    intel_dp->psr.sel_update_enabled ? "2" : "1");
2180
2181	/*
2182	 * Enabling sink PSR/Panel Replay here only for PSR. Panel Replay enable
2183	 * bit is already written at this point. Sink ALPM is enabled here for
2184	 * PSR and Panel Replay. See
2185	 * intel_psr_panel_replay_enable_sink. Modifiers/options:
2186	 *  - Selective Update
2187	 *  - Region Early Transport
2188	 *  - Selective Update Region Scanline Capture
2189	 *  - VSC_SDP_CRC
2190	 *  - HPD on different Errors
2191	 *  - CRC verification
2192	 * are written for PSR and Panel Replay here.
2193	 */
2194	intel_psr_enable_sink(intel_dp, crtc_state);
2195
2196	if (intel_dp_is_edp(intel_dp))
2197		intel_snps_phy_update_psr_power_state(&dig_port->base, true);
2198
2199	intel_psr_enable_source(intel_dp, crtc_state);
2200	intel_dp->psr.enabled = true;
2201	intel_dp->psr.pause_counter = 0;
2202
2203	/*
2204	 * Link_ok is sticky and set here on PSR enable. We can assume link
2205	 * training is complete as we never continue to PSR enable with
2206	 * untrained link. Link_ok is kept as set until first short pulse
2207	 * interrupt. This is targeted to workaround panels stating bad link
2208	 * after PSR is enabled.
2209	 */
2210	intel_dp->psr.link_ok = true;
2211
2212	intel_psr_activate(intel_dp);
2213}
2214
2215static void intel_psr_exit(struct intel_dp *intel_dp)
2216{
2217	struct intel_display *display = to_intel_display(intel_dp);
2218	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2219	u32 val;
2220
2221	if (!intel_dp->psr.active) {
2222		if (transcoder_has_psr2(display, cpu_transcoder)) {
2223			val = intel_de_read(display,
2224					    EDP_PSR2_CTL(display, cpu_transcoder));
2225			drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE);
2226		}
2227
2228		val = intel_de_read(display,
2229				    psr_ctl_reg(display, cpu_transcoder));
2230		drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE);
2231
2232		return;
2233	}
2234
2235	if (intel_dp->psr.panel_replay_enabled) {
2236		intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),
2237			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
2238	} else if (intel_dp->psr.sel_update_enabled) {
2239		tgl_disallow_dc3co_on_psr2_exit(intel_dp);
2240
2241		val = intel_de_rmw(display,
2242				   EDP_PSR2_CTL(display, cpu_transcoder),
2243				   EDP_PSR2_ENABLE, 0);
2244
2245		drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE));
2246	} else {
2247		if ((DISPLAY_VER(display) == 20 ||
2248		     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
2249			intel_dp->psr.pkg_c_latency_used)
2250			intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,
2251								       intel_dp->psr.pipe,
2252								       false);
2253
2254		val = intel_de_rmw(display,
2255				   psr_ctl_reg(display, cpu_transcoder),
2256				   EDP_PSR_ENABLE, 0);
2257
2258		drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE));
2259	}
2260	intel_dp->psr.active = false;
2261}
2262
2263static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
2264{
2265	struct intel_display *display = to_intel_display(intel_dp);
2266	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2267	i915_reg_t psr_status;
2268	u32 psr_status_mask;
2269
2270	if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
2271					  intel_dp->psr.panel_replay_enabled)) {
2272		psr_status = EDP_PSR2_STATUS(display, cpu_transcoder);
2273		psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
2274	} else {
2275		psr_status = psr_status_reg(display, cpu_transcoder);
2276		psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
2277	}
2278
2279	/* Wait till PSR is idle */
2280	if (intel_de_wait_for_clear_ms(display, psr_status,
2281				       psr_status_mask, 2000))
2282		drm_err(display->drm, "Timed out waiting PSR idle state\n");
2283}
2284
2285static void intel_psr_disable_locked(struct intel_dp *intel_dp)
2286{
2287	struct intel_display *display = to_intel_display(intel_dp);
2288	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2289
2290	lockdep_assert_held(&intel_dp->psr.lock);
2291
2292	if (!intel_dp->psr.enabled)
2293		return;
2294
2295	if (intel_dp->psr.panel_replay_enabled)
2296		drm_dbg_kms(display->drm, "Disabling Panel Replay\n");
2297	else
2298		drm_dbg_kms(display->drm, "Disabling PSR%s\n",
2299			    intel_dp->psr.sel_update_enabled ? "2" : "1");
2300
2301	intel_psr_exit(intel_dp);
2302	intel_psr_wait_exit_locked(intel_dp);
2303
2304	/*
2305	 * Wa_16013835468
2306	 * Wa_14015648006
2307	 */
2308	if (DISPLAY_VER(display) >= 11)
2309		intel_de_rmw(display, GEN8_CHICKEN_DCPR_1,
2310			     LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0);
2311
2312	if (intel_dp->psr.sel_update_enabled) {
2313		/* Wa_16012604467:adlp,mtl[a0,b0] */
2314		if (!intel_dp->psr.panel_replay_enabled &&
2315		    IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0))
2316			intel_de_rmw(display,
2317				     MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder),
2318				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
2319		else if (display->platform.alderlake_p)
2320			intel_de_rmw(display, CLKGATE_DIS_MISC,
2321				     CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
2322	}
2323
2324	if (intel_dp_is_edp(intel_dp))
2325		intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false);
2326
2327	if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp))
2328		intel_alpm_disable(intel_dp);
2329
2330	/* Disable PSR on Sink */
2331	if (!intel_dp->psr.panel_replay_enabled) {
2332		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
2333
2334		if (intel_dp->psr.sel_update_enabled)
2335			drm_dp_dpcd_writeb(&intel_dp->aux,
2336					   DP_RECEIVER_ALPM_CONFIG, 0);
2337	}
2338
2339	/* Wa_16025596647 */
2340	if ((DISPLAY_VER(display) == 20 ||
2341	     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
2342	    !intel_dp->psr.panel_replay_enabled)
2343		intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false);
2344
2345	intel_dp->psr.enabled = false;
2346	intel_dp->psr.panel_replay_enabled = false;
2347	intel_dp->psr.sel_update_enabled = false;
2348	intel_dp->psr.psr2_sel_fetch_enabled = false;
2349	intel_dp->psr.su_region_et_enabled = false;
2350	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
2351	intel_dp->psr.active_non_psr_pipes = 0;
2352	intel_dp->psr.pkg_c_latency_used = 0;
2353}
2354
2355/**
2356 * intel_psr_disable - Disable PSR
2357 * @intel_dp: Intel DP
2358 * @old_crtc_state: old CRTC state
2359 *
2360 * This function needs to be called before disabling pipe.
2361 */
2362void intel_psr_disable(struct intel_dp *intel_dp,
2363		       const struct intel_crtc_state *old_crtc_state)
2364{
2365	struct intel_display *display = to_intel_display(intel_dp);
2366
2367	if (!old_crtc_state->has_psr)
2368		return;
2369
2370	if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp) &&
2371			!CAN_PANEL_REPLAY(intel_dp)))
2372		return;
2373
2374	mutex_lock(&intel_dp->psr.lock);
2375
2376	intel_psr_disable_locked(intel_dp);
2377
2378	intel_dp->psr.link_ok = false;
2379
2380	mutex_unlock(&intel_dp->psr.lock);
2381	cancel_work_sync(&intel_dp->psr.work);
2382	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
2383}
2384
2385/**
2386 * intel_psr_pause - Pause PSR
2387 * @intel_dp: Intel DP
2388 *
2389 * This function need to be called after enabling psr.
2390 */
2391void intel_psr_pause(struct intel_dp *intel_dp)
2392{
2393	struct intel_psr *psr = &intel_dp->psr;
2394
2395	if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))
2396		return;
2397
2398	mutex_lock(&psr->lock);
2399
2400	if (!psr->enabled) {
2401		mutex_unlock(&psr->lock);
2402		return;
2403	}
2404
2405	if (intel_dp->psr.pause_counter++ == 0) {
2406		intel_psr_exit(intel_dp);
2407		intel_psr_wait_exit_locked(intel_dp);
2408	}
2409
2410	mutex_unlock(&psr->lock);
2411
2412	cancel_work_sync(&psr->work);
2413	cancel_delayed_work_sync(&psr->dc3co_work);
2414}
2415
2416/**
2417 * intel_psr_resume - Resume PSR
2418 * @intel_dp: Intel DP
2419 *
2420 * This function need to be called after pausing psr.
2421 */
2422void intel_psr_resume(struct intel_dp *intel_dp)
2423{
2424	struct intel_display *display = to_intel_display(intel_dp);
2425	struct intel_psr *psr = &intel_dp->psr;
2426
2427	if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))
2428		return;
2429
2430	mutex_lock(&psr->lock);
2431
2432	if (!psr->enabled)
2433		goto out;
2434
2435	if (!psr->pause_counter) {
2436		drm_warn(display->drm, "Unbalanced PSR pause/resume!\n");
2437		goto out;
2438	}
2439
2440	if (--intel_dp->psr.pause_counter == 0)
2441		intel_psr_activate(intel_dp);
2442
2443out:
2444	mutex_unlock(&psr->lock);
2445}
2446
2447/**
2448 * intel_psr_needs_vblank_notification - Check if PSR need vblank enable/disable
2449 * notification.
2450 * @crtc_state: CRTC status
2451 *
2452 * We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't
2453 * prevent it in case of Panel Replay. Panel Replay switches main link off on
2454 * DC entry. This means vblank interrupts are not fired and is a problem if
2455 * user-space is polling for vblank events. Also Wa_16025596647 needs
2456 * information when vblank is enabled/disabled.
2457 */
2458bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state)
2459{
2460	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2461	struct intel_display *display = to_intel_display(crtc_state);
2462	struct intel_encoder *encoder;
2463
2464	for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder) {
2465		struct intel_dp *intel_dp;
2466
2467		if (!intel_encoder_is_dp(encoder))
2468			continue;
2469
2470		intel_dp = enc_to_intel_dp(encoder);
2471
2472		if (!intel_dp_is_edp(intel_dp))
2473			continue;
2474
2475		if (CAN_PANEL_REPLAY(intel_dp))
2476			return true;
2477
2478		if ((DISPLAY_VER(display) == 20 ||
2479		     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
2480		    CAN_PSR(intel_dp))
2481			return true;
2482	}
2483
2484	return false;
2485}
2486
2487/**
2488 * intel_psr_trigger_frame_change_event - Trigger "Frame Change" event
2489 * @dsb: DSB context
2490 * @state: the atomic state
2491 * @crtc: the CRTC
2492 *
2493 * Generate PSR "Frame Change" event.
2494 */
2495void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
2496					  struct intel_atomic_state *state,
2497					  struct intel_crtc *crtc)
2498{
2499	const struct intel_crtc_state *crtc_state =
2500		intel_pre_commit_crtc_state(state, crtc);
2501	struct intel_display *display = to_intel_display(crtc);
2502
2503	if (crtc_state->has_psr)
2504		intel_de_write_dsb(display, dsb,
2505				   CURSURFLIVE(display, crtc->pipe), 0);
2506}
2507
2508/**
2509 * intel_psr_min_set_context_latency - Minimum 'set context latency' lines needed by PSR
2510 * @crtc_state: the crtc state
2511 *
2512 * Return minimum SCL lines/delay needed by PSR.
2513 */
2514int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state)
2515{
2516
2517	return _intel_psr_min_set_context_latency(crtc_state,
2518						  crtc_state->has_panel_replay,
2519						  crtc_state->has_sel_update);
2520}
2521
2522static u32 man_trk_ctl_enable_bit_get(struct intel_display *display)
2523{
2524	return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 0 :
2525		PSR2_MAN_TRK_CTL_ENABLE;
2526}
2527
2528static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display)
2529{
2530	return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ?
2531	       ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME :
2532	       PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
2533}
2534
2535static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display)
2536{
2537	return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ?
2538	       ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE :
2539	       PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
2540}
2541
2542static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display)
2543{
2544	return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ?
2545	       ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME :
2546	       PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
2547}
2548
2549static void intel_psr_force_update(struct intel_dp *intel_dp)
2550{
2551	struct intel_display *display = to_intel_display(intel_dp);
2552
2553	/*
2554	 * Display WA #0884: skl+
2555	 * This documented WA for bxt can be safely applied
2556	 * broadly so we can force HW tracking to exit PSR
2557	 * instead of disabling and re-enabling.
2558	 * Workaround tells us to write 0 to CUR_SURFLIVE_A,
2559	 * but it makes more sense write to the current active
2560	 * pipe.
2561	 *
2562	 * This workaround do not exist for platforms with display 10 or newer
2563	 * but testing proved that it works for up display 13, for newer
2564	 * than that testing will be needed.
2565	 */
2566	intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0);
2567}
2568
2569void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
2570					  const struct intel_crtc_state *crtc_state)
2571{
2572	struct intel_display *display = to_intel_display(crtc_state);
2573	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2574	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2575	struct intel_encoder *encoder;
2576
2577	if (!crtc_state->enable_psr2_sel_fetch)
2578		return;
2579
2580	for_each_intel_encoder_mask_with_psr(display->drm, encoder,
2581					     crtc_state->uapi.encoder_mask) {
2582		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2583
2584		if (!dsb)
2585			lockdep_assert_held(&intel_dp->psr.lock);
2586
2587		if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled)
2588			return;
2589		break;
2590	}
2591
2592	intel_de_write_dsb(display, dsb,
2593			   PSR2_MAN_TRK_CTL(display, cpu_transcoder),
2594			   crtc_state->psr2_man_track_ctl);
2595
2596	if (!crtc_state->enable_psr2_su_region_et)
2597		return;
2598
2599	intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
2600			   crtc_state->pipe_srcsz_early_tpt);
2601
2602	if (!crtc_state->dsc.compression_enable)
2603		return;
2604
2605	intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state,
2606					     drm_rect_height(&crtc_state->psr2_su_area));
2607}
2608
2609static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
2610				  bool full_update)
2611{
2612	struct intel_display *display = to_intel_display(crtc_state);
2613	u32 val = man_trk_ctl_enable_bit_get(display);
2614
2615	/* SF partial frame enable has to be set even on full update */
2616	val |= man_trk_ctl_partial_frame_bit_get(display);
2617
2618	if (full_update) {
2619		val |= man_trk_ctl_continuos_full_frame(display);
2620		goto exit;
2621	}
2622
2623	if (crtc_state->psr2_su_area.y1 == -1)
2624		goto exit;
2625
2626	if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) {
2627		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1);
2628		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1);
2629	} else {
2630		drm_WARN_ON(crtc_state->uapi.crtc->dev,
2631			    crtc_state->psr2_su_area.y1 % 4 ||
2632			    crtc_state->psr2_su_area.y2 % 4);
2633
2634		val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(
2635			crtc_state->psr2_su_area.y1 / 4 + 1);
2636		val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(
2637			crtc_state->psr2_su_area.y2 / 4 + 1);
2638	}
2639exit:
2640	crtc_state->psr2_man_track_ctl = val;
2641}
2642
2643static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state,
2644					  bool full_update)
2645{
2646	int width, height;
2647
2648	if (!crtc_state->enable_psr2_su_region_et || full_update)
2649		return 0;
2650
2651	width = drm_rect_width(&crtc_state->psr2_su_area);
2652	height = drm_rect_height(&crtc_state->psr2_su_area);
2653
2654	return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1);
2655}
2656
2657static void clip_area_update(struct drm_rect *overlap_damage_area,
2658			     struct drm_rect *damage_area,
2659			     struct drm_rect *display_area)
2660{
2661	if (!drm_rect_intersect(damage_area, display_area))
2662		return;
2663
2664	if (overlap_damage_area->y1 == -1) {
2665		overlap_damage_area->y1 = damage_area->y1;
2666		overlap_damage_area->y2 = damage_area->y2;
2667		return;
2668	}
2669
2670	if (damage_area->y1 < overlap_damage_area->y1)
2671		overlap_damage_area->y1 = damage_area->y1;
2672
2673	if (damage_area->y2 > overlap_damage_area->y2)
2674		overlap_damage_area->y2 = damage_area->y2;
2675}
2676
2677static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state)
2678{
2679	struct intel_display *display = to_intel_display(crtc_state);
2680	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2681	u16 y_alignment;
2682	bool su_area_changed = false;
2683
2684	/* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */
2685	if (crtc_state->dsc.compression_enable &&
2686	    (display->platform.alderlake_p || DISPLAY_VER(display) >= 14))
2687		y_alignment = vdsc_cfg->slice_height;
2688	else
2689		y_alignment = crtc_state->su_y_granularity;
2690
2691	if (crtc_state->psr2_su_area.y1 % y_alignment) {
2692		crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment;
2693		su_area_changed = true;
2694	}
2695
2696	if (crtc_state->psr2_su_area.y2 % y_alignment) {
2697		crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 /
2698						y_alignment) + 1) * y_alignment;
2699		su_area_changed = true;
2700	}
2701
2702	return su_area_changed;
2703}
2704
2705/*
2706 * When early transport is in use we need to extend SU area to cover
2707 * cursor fully when cursor is in SU area.
2708 */
2709static void
2710intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state,
2711				  struct intel_crtc *crtc,
2712				  struct drm_rect *display_area,
2713				  bool *cursor_in_su_area)
2714{
2715	struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
2716	struct intel_plane_state *new_plane_state;
2717	struct intel_plane *plane;
2718	int i;
2719
2720	if (!crtc_state->enable_psr2_su_region_et)
2721		return;
2722
2723	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
2724		struct drm_rect inter;
2725
2726		if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
2727			continue;
2728
2729		if (plane->id != PLANE_CURSOR)
2730			continue;
2731
2732		if (!new_plane_state->uapi.visible)
2733			continue;
2734
2735		inter = crtc_state->psr2_su_area;
2736		if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst))
2737			continue;
2738
2739		clip_area_update(&crtc_state->psr2_su_area, &new_plane_state->uapi.dst,
2740				 display_area);
2741		*cursor_in_su_area = true;
2742	}
2743}
2744
2745/*
2746 * TODO: Not clear how to handle planes with negative position,
2747 * also planes are not updated if they have a negative X
2748 * position so for now doing a full update in this cases
2749 *
2750 * Plane scaling and rotation is not supported by selective fetch and both
2751 * properties can change without a modeset, so need to be check at every
2752 * atomic commit.
2753 */
2754static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state)
2755{
2756	if (plane_state->uapi.dst.y1 < 0 ||
2757	    plane_state->uapi.dst.x1 < 0 ||
2758	    plane_state->scaler_id >= 0 ||
2759	    plane_state->uapi.rotation != DRM_MODE_ROTATE_0)
2760		return false;
2761
2762	return true;
2763}
2764
2765/*
2766 * Check for pipe properties that is not supported by selective fetch.
2767 *
2768 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed
2769 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch
2770 * enabled and going to the full update path.
2771 */
2772static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state)
2773{
2774	if (crtc_state->scaler_state.scaler_id >= 0)
2775		return false;
2776
2777	return true;
2778}
2779
2780/* Wa 14019834836 */
2781static void intel_psr_apply_pr_link_on_su_wa(struct intel_crtc_state *crtc_state)
2782{
2783	struct intel_display *display = to_intel_display(crtc_state);
2784	struct intel_encoder *encoder;
2785	int hactive_limit;
2786
2787	if (crtc_state->psr2_su_area.y1 != 0 ||
2788	    crtc_state->psr2_su_area.y2 != 0)
2789		return;
2790
2791	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2792		hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 : 546;
2793	else
2794		hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 : 273;
2795
2796	if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit)
2797		return;
2798
2799	for_each_intel_encoder_mask_with_psr(display->drm, encoder,
2800					     crtc_state->uapi.encoder_mask) {
2801		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2802
2803		if (!intel_dp_is_edp(intel_dp) &&
2804		    intel_dp->psr.panel_replay_enabled &&
2805		    intel_dp->psr.sel_update_enabled) {
2806			crtc_state->psr2_su_area.y2++;
2807			return;
2808		}
2809	}
2810}
2811
2812static void
2813intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state)
2814{
2815	struct intel_display *display = to_intel_display(crtc_state);
2816
2817	/* Wa_14014971492 */
2818	if (!crtc_state->has_panel_replay &&
2819	    ((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) ||
2820	      display->platform.alderlake_p || display->platform.tigerlake)) &&
2821	    crtc_state->splitter.enable)
2822		crtc_state->psr2_su_area.y1 = 0;
2823
2824	/* Wa 14019834836 */
2825	if (DISPLAY_VER(display) == 30)
2826		intel_psr_apply_pr_link_on_su_wa(crtc_state);
2827}
2828
2829int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
2830				struct intel_crtc *crtc)
2831{
2832	struct intel_display *display = to_intel_display(state);
2833	struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
2834	struct intel_plane_state *new_plane_state, *old_plane_state;
2835	struct intel_plane *plane;
2836	struct drm_rect display_area = {
2837		.x1 = 0,
2838		.y1 = 0,
2839		.x2 = crtc_state->hw.adjusted_mode.crtc_hdisplay,
2840		.y2 = crtc_state->hw.adjusted_mode.crtc_vdisplay,
2841	};
2842	bool full_update = false, su_area_changed;
2843	int i, ret;
2844
2845	if (!crtc_state->enable_psr2_sel_fetch)
2846		return 0;
2847
2848	if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
2849		full_update = true;
2850		goto skip_sel_fetch_set_loop;
2851	}
2852
2853	crtc_state->psr2_su_area.x1 = 0;
2854	crtc_state->psr2_su_area.y1 = -1;
2855	crtc_state->psr2_su_area.x2 = drm_rect_width(&display_area);
2856	crtc_state->psr2_su_area.y2 = -1;
2857
2858	/*
2859	 * Calculate minimal selective fetch area of each plane and calculate
2860	 * the pipe damaged area.
2861	 * In the next loop the plane selective fetch area will actually be set
2862	 * using whole pipe damaged area.
2863	 */
2864	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
2865					     new_plane_state, i) {
2866		struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1,
2867						      .x2 = INT_MAX };
2868
2869		if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
2870			continue;
2871
2872		if (!new_plane_state->uapi.visible &&
2873		    !old_plane_state->uapi.visible)
2874			continue;
2875
2876		if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
2877			full_update = true;
2878			break;
2879		}
2880
2881		/*
2882		 * If visibility or plane moved, mark the whole plane area as
2883		 * damaged as it needs to be complete redraw in the new and old
2884		 * position.
2885		 */
2886		if (new_plane_state->uapi.visible != old_plane_state->uapi.visible ||
2887		    !drm_rect_equals(&new_plane_state->uapi.dst,
2888				     &old_plane_state->uapi.dst)) {
2889			if (old_plane_state->uapi.visible) {
2890				damaged_area.y1 = old_plane_state->uapi.dst.y1;
2891				damaged_area.y2 = old_plane_state->uapi.dst.y2;
2892				clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
2893						 &display_area);
2894			}
2895
2896			if (new_plane_state->uapi.visible) {
2897				damaged_area.y1 = new_plane_state->uapi.dst.y1;
2898				damaged_area.y2 = new_plane_state->uapi.dst.y2;
2899				clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
2900						 &display_area);
2901			}
2902			continue;
2903		} else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
2904			/* If alpha changed mark the whole plane area as damaged */
2905			damaged_area.y1 = new_plane_state->uapi.dst.y1;
2906			damaged_area.y2 = new_plane_state->uapi.dst.y2;
2907			clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
2908					 &display_area);
2909			continue;
2910		}
2911
2912		src = drm_plane_state_src(&new_plane_state->uapi);
2913		drm_rect_fp_to_int(&src, &src);
2914
2915		if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi,
2916						     &new_plane_state->uapi, &damaged_area))
2917			continue;
2918
2919		damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1;
2920		damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1;
2921		damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1;
2922		damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1;
2923
2924		clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &display_area);
2925	}
2926
2927	/*
2928	 * TODO: For now we are just using full update in case
2929	 * selective fetch area calculation fails. To optimize this we
2930	 * should identify cases where this happens and fix the area
2931	 * calculation for those.
2932	 */
2933	if (crtc_state->psr2_su_area.y1 == -1) {
2934		drm_info_once(display->drm,
2935			      "Selective fetch area calculation failed in pipe %c\n",
2936			      pipe_name(crtc->pipe));
2937		full_update = true;
2938	}
2939
2940	if (full_update)
2941		goto skip_sel_fetch_set_loop;
2942
2943	intel_psr_apply_su_area_workarounds(crtc_state);
2944
2945	ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
2946	if (ret)
2947		return ret;
2948
2949	do {
2950		bool cursor_in_su_area;
2951
2952		/*
2953		 * Adjust su area to cover cursor fully as necessary
2954		 * (early transport). This needs to be done after
2955		 * drm_atomic_add_affected_planes to ensure visible
2956		 * cursor is added into affected planes even when
2957		 * cursor is not updated by itself.
2958		 */
2959		intel_psr2_sel_fetch_et_alignment(state, crtc, &display_area,
2960						  &cursor_in_su_area);
2961
2962		su_area_changed = intel_psr2_sel_fetch_pipe_alignment(crtc_state);
2963
2964		/*
2965		 * If the cursor was outside the SU area before
2966		 * alignment, the alignment step (which only expands
2967		 * SU) may pull the cursor partially inside, so we
2968		 * must run ET alignment again to fully cover it. But
2969		 * if the cursor was already fully inside before
2970		 * alignment, expanding the SU area won't change that,
2971		 * so no further work is needed.
2972		 */
2973		if (cursor_in_su_area)
2974			break;
2975	} while (su_area_changed);
2976
2977	/*
2978	 * Now that we have the pipe damaged area check if it intersect with
2979	 * every plane, if it does set the plane selective fetch area.
2980	 */
2981	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
2982					     new_plane_state, i) {
2983		struct drm_rect *sel_fetch_area, inter;
2984		struct intel_plane *linked = new_plane_state->planar_linked_plane;
2985
2986		if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc ||
2987		    !new_plane_state->uapi.visible)
2988			continue;
2989
2990		inter = crtc_state->psr2_su_area;
2991		sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
2992		if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) {
2993			sel_fetch_area->y1 = -1;
2994			sel_fetch_area->y2 = -1;
2995			/*
2996			 * if plane sel fetch was previously enabled ->
2997			 * disable it
2998			 */
2999			if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0)
3000				crtc_state->update_planes |= BIT(plane->id);
3001
3002			continue;
3003		}
3004
3005		if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
3006			full_update = true;
3007			break;
3008		}
3009
3010		sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
3011		sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1;
3012		sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1;
3013		crtc_state->update_planes |= BIT(plane->id);
3014
3015		/*
3016		 * Sel_fetch_area is calculated for UV plane. Use
3017		 * same area for Y plane as well.
3018		 */
3019		if (linked) {
3020			struct intel_plane_state *linked_new_plane_state;
3021			struct drm_rect *linked_sel_fetch_area;
3022
3023			linked_new_plane_state = intel_atomic_get_plane_state(state, linked);
3024			if (IS_ERR(linked_new_plane_state))
3025				return PTR_ERR(linked_new_plane_state);
3026
3027			linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area;
3028			linked_sel_fetch_area->y1 = sel_fetch_area->y1;
3029			linked_sel_fetch_area->y2 = sel_fetch_area->y2;
3030			crtc_state->update_planes |= BIT(linked->id);
3031		}
3032	}
3033
3034skip_sel_fetch_set_loop:
3035	if (full_update)
3036		clip_area_update(&crtc_state->psr2_su_area, &display_area,
3037				 &display_area);
3038
3039	psr2_man_trk_ctl_calc(crtc_state, full_update);
3040	crtc_state->pipe_srcsz_early_tpt =
3041		psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
3042	return 0;
3043}
3044
3045void intel_psr2_panic_force_full_update(struct intel_display *display,
3046					struct intel_crtc_state *crtc_state)
3047{
3048	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3049	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3050	u32 val = man_trk_ctl_enable_bit_get(display);
3051
3052	/* SF partial frame enable has to be set even on full update */
3053	val |= man_trk_ctl_partial_frame_bit_get(display);
3054	val |= man_trk_ctl_continuos_full_frame(display);
3055
3056	/* Directly write the register */
3057	intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val);
3058
3059	if (!crtc_state->enable_psr2_su_region_et)
3060		return;
3061
3062	intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0);
3063}
3064
3065void intel_psr_pre_plane_update(struct intel_atomic_state *state,
3066				struct intel_crtc *crtc)
3067{
3068	struct intel_display *display = to_intel_display(state);
3069	const struct intel_crtc_state *old_crtc_state =
3070		intel_atomic_get_old_crtc_state(state, crtc);
3071	const struct intel_crtc_state *new_crtc_state =
3072		intel_atomic_get_new_crtc_state(state, crtc);
3073	struct intel_encoder *encoder;
3074
3075	if (!HAS_PSR(display))
3076		return;
3077
3078	for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
3079					     old_crtc_state->uapi.encoder_mask) {
3080		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3081		struct intel_psr *psr = &intel_dp->psr;
3082
3083		mutex_lock(&psr->lock);
3084
3085		if (!new_crtc_state->has_psr)
3086			psr->no_psr_reason = new_crtc_state->no_psr_reason;
3087
3088		if (psr->enabled) {
3089			/*
3090			 * Reasons to disable:
3091			 * - PSR disabled in new state
3092			 * - All planes will go inactive
3093			 * - Changing between PSR versions
3094			 * - Region Early Transport changing
3095			 * - Display WA #1136: skl, bxt
3096			 */
3097			if (intel_crtc_needs_modeset(new_crtc_state) ||
3098			    new_crtc_state->update_m_n ||
3099			    new_crtc_state->update_lrr ||
3100			    !new_crtc_state->has_psr ||
3101			    !new_crtc_state->active_planes ||
3102			    new_crtc_state->has_sel_update != psr->sel_update_enabled ||
3103			    new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled ||
3104			    new_crtc_state->has_panel_replay != psr->panel_replay_enabled ||
3105			    (DISPLAY_VER(display) < 11 && new_crtc_state->wm_level_disabled))
3106				intel_psr_disable_locked(intel_dp);
3107			else if (new_crtc_state->wm_level_disabled)
3108				/* Wa_14015648006 */
3109				wm_optimization_wa(intel_dp, new_crtc_state);
3110		}
3111
3112		mutex_unlock(&psr->lock);
3113	}
3114}
3115
3116static void
3117verify_panel_replay_dsc_state(const struct intel_crtc_state *crtc_state)
3118{
3119	struct intel_display *display = to_intel_display(crtc_state);
3120
3121	if (!crtc_state->has_panel_replay)
3122		return;
3123
3124	drm_WARN_ON(display->drm,
3125		    intel_dsc_enabled_on_link(crtc_state) &&
3126		    crtc_state->panel_replay_dsc_support ==
3127		    INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED);
3128}
3129
3130void intel_psr_post_plane_update(struct intel_atomic_state *state,
3131				 struct intel_crtc *crtc)
3132{
3133	struct intel_display *display = to_intel_display(state);
3134	const struct intel_crtc_state *crtc_state =
3135		intel_atomic_get_new_crtc_state(state, crtc);
3136	struct intel_encoder *encoder;
3137
3138	if (!crtc_state->has_psr)
3139		return;
3140
3141	verify_panel_replay_dsc_state(crtc_state);
3142
3143	for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
3144					     crtc_state->uapi.encoder_mask) {
3145		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3146		struct intel_psr *psr = &intel_dp->psr;
3147		bool keep_disabled = false;
3148
3149		mutex_lock(&psr->lock);
3150
3151		drm_WARN_ON(display->drm,
3152			    psr->enabled && !crtc_state->active_planes);
3153
3154		if (psr->sink_not_reliable)
3155			keep_disabled = true;
3156
3157		if (!crtc_state->active_planes) {
3158			psr->no_psr_reason = "All planes inactive";
3159			keep_disabled = true;
3160		}
3161
3162		/* Display WA #1136: skl, bxt */
3163		if (DISPLAY_VER(display) < 11 && crtc_state->wm_level_disabled) {
3164			psr->no_psr_reason = "Workaround #1136 for skl, bxt";
3165			keep_disabled = true;
3166		}
3167
3168		if (!psr->enabled && !keep_disabled)
3169			intel_psr_enable_locked(intel_dp, crtc_state);
3170		else if (psr->enabled && !crtc_state->wm_level_disabled)
3171			/* Wa_14015648006 */
3172			wm_optimization_wa(intel_dp, crtc_state);
3173
3174		/* Force a PSR exit when enabling CRC to avoid CRC timeouts */
3175		if (crtc_state->crc_enabled && psr->enabled)
3176			intel_psr_force_update(intel_dp);
3177
3178		/*
3179		 * Clear possible busy bits in case we have
3180		 * invalidate -> flip -> flush sequence.
3181		 */
3182		intel_dp->psr.busy_frontbuffer_bits = 0;
3183
3184		mutex_unlock(&psr->lock);
3185	}
3186}
3187
3188/*
3189 * From bspec: Panel Self Refresh (BDW+)
3190 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
3191 * exit training time + 1.5 ms of aux channel handshake. 50 ms is
3192 * defensive enough to cover everything.
3193 */
3194#define PSR_IDLE_TIMEOUT_MS 50
3195
3196static int
3197_psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state,
3198				   struct intel_dsb *dsb)
3199{
3200	struct intel_display *display = to_intel_display(new_crtc_state);
3201	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
3202
3203	/*
3204	 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough.
3205	 * As all higher states has bit 4 of PSR2 state set we can just wait for
3206	 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared.
3207	 */
3208	if (dsb) {
3209		intel_dsb_poll(dsb, EDP_PSR2_STATUS(display, cpu_transcoder),
3210			       EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 0, 200,
3211			       PSR_IDLE_TIMEOUT_MS * 1000 / 200);
3212		return true;
3213	}
3214
3215	return intel_de_wait_for_clear_ms(display,
3216				       EDP_PSR2_STATUS(display, cpu_transcoder),
3217				       EDP_PSR2_STATUS_STATE_DEEP_SLEEP,
3218				       PSR_IDLE_TIMEOUT_MS);
3219}
3220
3221static int
3222_psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state,
3223				   struct intel_dsb *dsb)
3224{
3225	struct intel_display *display = to_intel_display(new_crtc_state);
3226	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
3227
3228	if (dsb) {
3229		intel_dsb_poll(dsb, psr_status_reg(display, cpu_transcoder),
3230			       EDP_PSR_STATUS_STATE_MASK, 0, 200,
3231			       PSR_IDLE_TIMEOUT_MS * 1000 / 200);
3232		return true;
3233	}
3234
3235	return intel_de_wait_for_clear_ms(display,
3236				       psr_status_reg(display, cpu_transcoder),
3237				       EDP_PSR_STATUS_STATE_MASK,
3238				       PSR_IDLE_TIMEOUT_MS);
3239}
3240
3241/**
3242 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
3243 * @new_crtc_state: new CRTC state
3244 *
3245 * This function is expected to be called from pipe_update_start() where it is
3246 * not expected to race with PSR enable or disable.
3247 */
3248void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state)
3249{
3250	struct intel_display *display = to_intel_display(new_crtc_state);
3251	struct intel_encoder *encoder;
3252
3253	if (!new_crtc_state->has_psr)
3254		return;
3255
3256	for_each_intel_encoder_mask_with_psr(display->drm, encoder,
3257					     new_crtc_state->uapi.encoder_mask) {
3258		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3259		int ret;
3260
3261		lockdep_assert_held(&intel_dp->psr.lock);
3262
3263		if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled)
3264			continue;
3265
3266		if (intel_dp->psr.sel_update_enabled)
3267			ret = _psr2_ready_for_pipe_update_locked(new_crtc_state,
3268								 NULL);
3269		else
3270			ret = _psr1_ready_for_pipe_update_locked(new_crtc_state,
3271								 NULL);
3272
3273		if (ret)
3274			drm_err(display->drm,
3275				"PSR wait timed out, atomic update may fail\n");
3276	}
3277}
3278
3279void intel_psr_wait_for_idle_dsb(struct intel_dsb *dsb,
3280				 const struct intel_crtc_state *new_crtc_state)
3281{
3282	if (!new_crtc_state->has_psr || new_crtc_state->has_panel_replay)
3283		return;
3284
3285	if (new_crtc_state->has_sel_update)
3286		_psr2_ready_for_pipe_update_locked(new_crtc_state, dsb);
3287	else
3288		_psr1_ready_for_pipe_update_locked(new_crtc_state, dsb);
3289}
3290
3291static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
3292{
3293	struct intel_display *display = to_intel_display(intel_dp);
3294	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
3295	i915_reg_t reg;
3296	u32 mask;
3297	int err;
3298
3299	if (!intel_dp->psr.enabled)
3300		return false;
3301
3302	if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
3303					  intel_dp->psr.panel_replay_enabled)) {
3304		reg = EDP_PSR2_STATUS(display, cpu_transcoder);
3305		mask = EDP_PSR2_STATUS_STATE_MASK;
3306	} else {
3307		reg = psr_status_reg(display, cpu_transcoder);
3308		mask = EDP_PSR_STATUS_STATE_MASK;
3309	}
3310
3311	mutex_unlock(&intel_dp->psr.lock);
3312
3313	err = intel_de_wait_for_clear_ms(display, reg, mask, 50);
3314	if (err)
3315		drm_err(display->drm,
3316			"Timed out waiting for PSR Idle for re-enable\n");
3317
3318	/* After the unlocked wait, verify that PSR is still wanted! */
3319	mutex_lock(&intel_dp->psr.lock);
3320	return err == 0 && intel_dp->psr.enabled && !intel_dp->psr.pause_counter;
3321}
3322
3323static int intel_psr_fastset_force(struct intel_display *display)
3324{
3325	struct drm_connector_list_iter conn_iter;
3326	struct drm_modeset_acquire_ctx ctx;
3327	struct drm_atomic_state *state;
3328	struct drm_connector *conn;
3329	int err = 0;
3330
3331	state = drm_atomic_state_alloc(display->drm);
3332	if (!state)
3333		return -ENOMEM;
3334
3335	drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
3336
3337	state->acquire_ctx = &ctx;
3338	to_intel_atomic_state(state)->internal = true;
3339
3340retry:
3341	drm_connector_list_iter_begin(display->drm, &conn_iter);
3342	drm_for_each_connector_iter(conn, &conn_iter) {
3343		struct drm_connector_state *conn_state;
3344		struct drm_crtc_state *crtc_state;
3345
3346		if (conn->connector_type != DRM_MODE_CONNECTOR_eDP)
3347			continue;
3348
3349		conn_state = drm_atomic_get_connector_state(state, conn);
3350		if (IS_ERR(conn_state)) {
3351			err = PTR_ERR(conn_state);
3352			break;
3353		}
3354
3355		if (!conn_state->crtc)
3356			continue;
3357
3358		crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
3359		if (IS_ERR(crtc_state)) {
3360			err = PTR_ERR(crtc_state);
3361			break;
3362		}
3363
3364		/* Mark mode as changed to trigger a pipe->update() */
3365		crtc_state->mode_changed = true;
3366	}
3367	drm_connector_list_iter_end(&conn_iter);
3368
3369	if (err == 0)
3370		err = drm_atomic_commit(state);
3371
3372	if (err == -EDEADLK) {
3373		drm_atomic_state_clear(state);
3374		err = drm_modeset_backoff(&ctx);
3375		if (!err)
3376			goto retry;
3377	}
3378
3379	drm_modeset_drop_locks(&ctx);
3380	drm_modeset_acquire_fini(&ctx);
3381	drm_atomic_state_put(state);
3382
3383	return err;
3384}
3385
3386int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
3387{
3388	struct intel_display *display = to_intel_display(intel_dp);
3389	const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
3390	const u32 disable_bits = val & (I915_PSR_DEBUG_SU_REGION_ET_DISABLE |
3391					I915_PSR_DEBUG_PANEL_REPLAY_DISABLE);
3392	u32 old_mode, old_disable_bits;
3393	int ret;
3394
3395	if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_SU_REGION_ET_DISABLE |
3396		    I915_PSR_DEBUG_PANEL_REPLAY_DISABLE |
3397		    I915_PSR_DEBUG_MODE_MASK) ||
3398	    mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
3399		drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val);
3400		return -EINVAL;
3401	}
3402
3403	ret = mutex_lock_interruptible(&intel_dp->psr.lock);
3404	if (ret)
3405		return ret;
3406
3407	old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
3408	old_disable_bits = intel_dp->psr.debug &
3409		(I915_PSR_DEBUG_SU_REGION_ET_DISABLE |
3410		 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE);
3411
3412	intel_dp->psr.debug = val;
3413
3414	/*
3415	 * Do it right away if it's already enabled, otherwise it will be done
3416	 * when enabling the source.
3417	 */
3418	if (intel_dp->psr.enabled)
3419		psr_irq_control(intel_dp);
3420
3421	mutex_unlock(&intel_dp->psr.lock);
3422
3423	if (old_mode != mode || old_disable_bits != disable_bits)
3424		ret = intel_psr_fastset_force(display);
3425
3426	return ret;
3427}
3428
3429static void intel_psr_handle_irq(struct intel_dp *intel_dp)
3430{
3431	struct intel_psr *psr = &intel_dp->psr;
3432
3433	intel_psr_disable_locked(intel_dp);
3434	psr->sink_not_reliable = true;
3435	/* let's make sure that sink is awaken */
3436	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
3437}
3438
3439static void intel_psr_work(struct work_struct *work)
3440{
3441	struct intel_dp *intel_dp =
3442		container_of(work, typeof(*intel_dp), psr.work);
3443
3444	mutex_lock(&intel_dp->psr.lock);
3445
3446	if (!intel_dp->psr.enabled)
3447		goto unlock;
3448
3449	if (READ_ONCE(intel_dp->psr.irq_aux_error)) {
3450		intel_psr_handle_irq(intel_dp);
3451		goto unlock;
3452	}
3453
3454	if (intel_dp->psr.pause_counter)
3455		goto unlock;
3456
3457	/*
3458	 * We have to make sure PSR is ready for re-enable
3459	 * otherwise it keeps disabled until next full enable/disable cycle.
3460	 * PSR might take some time to get fully disabled
3461	 * and be ready for re-enable.
3462	 */
3463	if (!__psr_wait_for_idle_locked(intel_dp))
3464		goto unlock;
3465
3466	/*
3467	 * The delayed work can race with an invalidate hence we need to
3468	 * recheck. Since psr_flush first clears this and then reschedules we
3469	 * won't ever miss a flush when bailing out here.
3470	 */
3471	if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
3472		goto unlock;
3473
3474	intel_psr_activate(intel_dp);
3475unlock:
3476	mutex_unlock(&intel_dp->psr.lock);
3477}
3478
3479static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp)
3480{
3481	struct intel_display *display = to_intel_display(intel_dp);
3482	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
3483
3484	if (!intel_dp->psr.psr2_sel_fetch_enabled)
3485		return;
3486
3487	if (DISPLAY_VER(display) >= 20)
3488		intel_de_write(display, LNL_SFF_CTL(cpu_transcoder),
3489			       LNL_SFF_CTL_SF_SINGLE_FULL_FRAME);
3490	else
3491		intel_de_write(display,
3492			       PSR2_MAN_TRK_CTL(display, cpu_transcoder),
3493			       man_trk_ctl_enable_bit_get(display) |
3494			       man_trk_ctl_partial_frame_bit_get(display) |
3495			       man_trk_ctl_single_full_frame_bit_get(display) |
3496			       man_trk_ctl_continuos_full_frame(display));
3497}
3498
3499static void _psr_invalidate_handle(struct intel_dp *intel_dp)
3500{
3501	struct intel_display *display = to_intel_display(intel_dp);
3502
3503	if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {
3504		if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) {
3505			intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
3506			intel_psr_configure_full_frame_update(intel_dp);
3507		}
3508
3509		intel_psr_force_update(intel_dp);
3510	} else {
3511		intel_psr_exit(intel_dp);
3512	}
3513}
3514
3515/**
3516 * intel_psr_invalidate - Invalidate PSR
3517 * @display: display device
3518 * @frontbuffer_bits: frontbuffer plane tracking bits
3519 * @origin: which operation caused the invalidate
3520 *
3521 * Since the hardware frontbuffer tracking has gaps we need to integrate
3522 * with the software frontbuffer tracking. This function gets called every
3523 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
3524 * disabled if the frontbuffer mask contains a buffer relevant to PSR.
3525 *
3526 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
3527 */
3528void intel_psr_invalidate(struct intel_display *display,
3529			  unsigned frontbuffer_bits, enum fb_op_origin origin)
3530{
3531	struct intel_encoder *encoder;
3532
3533	if (origin == ORIGIN_FLIP)
3534		return;
3535
3536	for_each_intel_encoder_with_psr(display->drm, encoder) {
3537		unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
3538		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3539
3540		mutex_lock(&intel_dp->psr.lock);
3541		if (!intel_dp->psr.enabled) {
3542			mutex_unlock(&intel_dp->psr.lock);
3543			continue;
3544		}
3545
3546		pipe_frontbuffer_bits &=
3547			INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
3548		intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
3549
3550		if (pipe_frontbuffer_bits)
3551			_psr_invalidate_handle(intel_dp);
3552
3553		mutex_unlock(&intel_dp->psr.lock);
3554	}
3555}
3556/*
3557 * When we will be completely rely on PSR2 S/W tracking in future,
3558 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
3559 * event also therefore tgl_dc3co_flush_locked() require to be changed
3560 * accordingly in future.
3561 */
3562static void
3563tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
3564		       enum fb_op_origin origin)
3565{
3566	struct intel_display *display = to_intel_display(intel_dp);
3567
3568	if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled ||
3569	    !intel_dp->psr.active)
3570		return;
3571
3572	/*
3573	 * At every frontbuffer flush flip event modified delay of delayed work,
3574	 * when delayed work schedules that means display has been idle.
3575	 */
3576	if (!(frontbuffer_bits &
3577	    INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
3578		return;
3579
3580	tgl_psr2_enable_dc3co(intel_dp);
3581	mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,
3582			 intel_dp->psr.dc3co_exit_delay);
3583}
3584
3585static void _psr_flush_handle(struct intel_dp *intel_dp)
3586{
3587	struct intel_display *display = to_intel_display(intel_dp);
3588
3589	if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {
3590		/* Selective fetch prior LNL */
3591		if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
3592			/* can we turn CFF off? */
3593			if (intel_dp->psr.busy_frontbuffer_bits == 0)
3594				intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
3595		}
3596
3597		/*
3598		 * Still keep cff bit enabled as we don't have proper SU
3599		 * configuration in case update is sent for any reason after
3600		 * sff bit gets cleared by the HW on next vblank.
3601		 *
3602		 * NOTE: Setting cff bit is not needed for LunarLake onwards as
3603		 * we have own register for SFF bit and we are not overwriting
3604		 * existing SU configuration
3605		 */
3606		intel_psr_configure_full_frame_update(intel_dp);
3607
3608		intel_psr_force_update(intel_dp);
3609	} else if (!intel_dp->psr.psr2_sel_fetch_enabled) {
3610		/*
3611		 * PSR1 on all platforms
3612		 * PSR2 HW tracking
3613		 * Panel Replay Full frame update
3614		 */
3615		intel_psr_force_update(intel_dp);
3616	} else {
3617		/* Selective update LNL onwards */
3618		intel_psr_exit(intel_dp);
3619	}
3620
3621	if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
3622		queue_work(display->wq.unordered, &intel_dp->psr.work);
3623}
3624
3625/**
3626 * intel_psr_flush - Flush PSR
3627 * @display: display device
3628 * @frontbuffer_bits: frontbuffer plane tracking bits
3629 * @origin: which operation caused the flush
3630 *
3631 * Since the hardware frontbuffer tracking has gaps we need to integrate
3632 * with the software frontbuffer tracking. This function gets called every
3633 * time frontbuffer rendering has completed and flushed out to memory. PSR
3634 * can be enabled again if no other frontbuffer relevant to PSR is dirty.
3635 *
3636 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
3637 */
3638void intel_psr_flush(struct intel_display *display,
3639		     unsigned frontbuffer_bits, enum fb_op_origin origin)
3640{
3641	struct intel_encoder *encoder;
3642
3643	for_each_intel_encoder_with_psr(display->drm, encoder) {
3644		unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
3645		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3646
3647		mutex_lock(&intel_dp->psr.lock);
3648		if (!intel_dp->psr.enabled) {
3649			mutex_unlock(&intel_dp->psr.lock);
3650			continue;
3651		}
3652
3653		pipe_frontbuffer_bits &=
3654			INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
3655		intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
3656
3657		/*
3658		 * If the PSR is paused by an explicit intel_psr_paused() call,
3659		 * we have to ensure that the PSR is not activated until
3660		 * intel_psr_resume() is called.
3661		 */
3662		if (intel_dp->psr.pause_counter)
3663			goto unlock;
3664
3665		if (origin == ORIGIN_FLIP ||
3666		    (origin == ORIGIN_CURSOR_UPDATE &&
3667		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
3668			tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);
3669			goto unlock;
3670		}
3671
3672		if (pipe_frontbuffer_bits == 0)
3673			goto unlock;
3674
3675		/* By definition flush = invalidate + flush */
3676		_psr_flush_handle(intel_dp);
3677unlock:
3678		mutex_unlock(&intel_dp->psr.lock);
3679	}
3680}
3681
3682/**
3683 * intel_psr_init - Init basic PSR work and mutex.
3684 * @intel_dp: Intel DP
3685 *
3686 * This function is called after the initializing connector.
3687 * (the initializing of connector treats the handling of connector capabilities)
3688 * And it initializes basic PSR stuff for each DP Encoder.
3689 */
3690void intel_psr_init(struct intel_dp *intel_dp)
3691{
3692	struct intel_display *display = to_intel_display(intel_dp);
3693	struct intel_connector *connector = intel_dp->attached_connector;
3694	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3695
3696	if (!(HAS_PSR(display) || HAS_DP20(display)))
3697		return;
3698
3699	/*
3700	 * HSW spec explicitly says PSR is tied to port A.
3701	 * BDW+ platforms have a instance of PSR registers per transcoder but
3702	 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder
3703	 * than eDP one.
3704	 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11.
3705	 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11.
3706	 * But GEN12 supports a instance of PSR registers per transcoder.
3707	 */
3708	if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) {
3709		drm_dbg_kms(display->drm,
3710			    "PSR condition failed: Port not supported\n");
3711		return;
3712	}
3713
3714	if ((HAS_DP20(display) && !intel_dp_is_edp(intel_dp)) ||
3715	    DISPLAY_VER(display) >= 20)
3716		intel_dp->psr.source_panel_replay_support = true;
3717
3718	if (HAS_PSR(display) && intel_dp_is_edp(intel_dp))
3719		intel_dp->psr.source_support = true;
3720
3721	/* Set link_standby x link_off defaults */
3722	if (DISPLAY_VER(display) < 12)
3723		/* For new platforms up to TGL let's respect VBT back again */
3724		intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
3725
3726	INIT_WORK(&intel_dp->psr.work, intel_psr_work);
3727	INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
3728	mutex_init(&intel_dp->psr.lock);
3729}
3730
3731static int psr_get_status_and_error_status(struct intel_dp *intel_dp,
3732					   u8 *status, u8 *error_status)
3733{
3734	struct drm_dp_aux *aux = &intel_dp->aux;
3735	int ret;
3736	unsigned int offset;
3737
3738	offset = intel_dp->psr.panel_replay_enabled ?
3739		 DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS : DP_PSR_STATUS;
3740
3741	ret = drm_dp_dpcd_readb(aux, offset, status);
3742	if (ret != 1)
3743		return ret;
3744
3745	offset = intel_dp->psr.panel_replay_enabled ?
3746		 DP_PANEL_REPLAY_ERROR_STATUS : DP_PSR_ERROR_STATUS;
3747
3748	ret = drm_dp_dpcd_readb(aux, offset, error_status);
3749	if (ret != 1)
3750		return ret;
3751
3752	*status = *status & DP_PSR_SINK_STATE_MASK;
3753
3754	return 0;
3755}
3756
3757static void psr_alpm_check(struct intel_dp *intel_dp)
3758{
3759	struct intel_psr *psr = &intel_dp->psr;
3760
3761	if (!psr->sel_update_enabled)
3762		return;
3763
3764	if (intel_alpm_get_error(intel_dp)) {
3765		intel_psr_disable_locked(intel_dp);
3766		psr->sink_not_reliable = true;
3767	}
3768}
3769
3770static void psr_capability_changed_check(struct intel_dp *intel_dp)
3771{
3772	struct intel_display *display = to_intel_display(intel_dp);
3773	struct intel_psr *psr = &intel_dp->psr;
3774	u8 val;
3775	int r;
3776
3777	r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
3778	if (r != 1) {
3779		drm_err(display->drm, "Error reading DP_PSR_ESI\n");
3780		return;
3781	}
3782
3783	if (val & DP_PSR_CAPS_CHANGE) {
3784		intel_psr_disable_locked(intel_dp);
3785		psr->sink_not_reliable = true;
3786		drm_dbg_kms(display->drm,
3787			    "Sink PSR capability changed, disabling PSR\n");
3788
3789		/* Clearing it */
3790		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);
3791	}
3792}
3793
3794/*
3795 * On common bits:
3796 * DP_PSR_RFB_STORAGE_ERROR == DP_PANEL_REPLAY_RFB_STORAGE_ERROR
3797 * DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR == DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR
3798 * DP_PSR_LINK_CRC_ERROR == DP_PANEL_REPLAY_LINK_CRC_ERROR
3799 * this function is relying on PSR definitions
3800 */
3801void intel_psr_short_pulse(struct intel_dp *intel_dp)
3802{
3803	struct intel_display *display = to_intel_display(intel_dp);
3804	struct intel_psr *psr = &intel_dp->psr;
3805	u8 status, error_status;
3806	const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
3807			  DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
3808			  DP_PSR_LINK_CRC_ERROR;
3809
3810	if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))
3811		return;
3812
3813	mutex_lock(&psr->lock);
3814
3815	psr->link_ok = false;
3816
3817	if (!psr->enabled)
3818		goto exit;
3819
3820	if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
3821		drm_err(display->drm,
3822			"Error reading PSR status or error status\n");
3823		goto exit;
3824	}
3825
3826	if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) ||
3827	    (error_status & errors)) {
3828		intel_psr_disable_locked(intel_dp);
3829		psr->sink_not_reliable = true;
3830	}
3831
3832	if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR &&
3833	    !error_status)
3834		drm_dbg_kms(display->drm,
3835			    "PSR sink internal error, disabling PSR\n");
3836	if (error_status & DP_PSR_RFB_STORAGE_ERROR)
3837		drm_dbg_kms(display->drm,
3838			    "PSR RFB storage error, disabling PSR\n");
3839	if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
3840		drm_dbg_kms(display->drm,
3841			    "PSR VSC SDP uncorrectable error, disabling PSR\n");
3842	if (error_status & DP_PSR_LINK_CRC_ERROR)
3843		drm_dbg_kms(display->drm,
3844			    "PSR Link CRC error, disabling PSR\n");
3845
3846	if (error_status & ~errors)
3847		drm_err(display->drm,
3848			"PSR_ERROR_STATUS unhandled errors %x\n",
3849			error_status & ~errors);
3850	/* clear status register */
3851	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
3852
3853	if (!psr->panel_replay_enabled) {
3854		psr_alpm_check(intel_dp);
3855		psr_capability_changed_check(intel_dp);
3856	}
3857
3858exit:
3859	mutex_unlock(&psr->lock);
3860}
3861
3862bool intel_psr_enabled(struct intel_dp *intel_dp)
3863{
3864	bool ret;
3865
3866	if (!CAN_PSR(intel_dp))
3867		return false;
3868
3869	mutex_lock(&intel_dp->psr.lock);
3870	ret = intel_dp->psr.enabled;
3871	mutex_unlock(&intel_dp->psr.lock);
3872
3873	return ret;
3874}
3875
3876/**
3877 * intel_psr_link_ok - return psr->link_ok
3878 * @intel_dp: struct intel_dp
3879 *
3880 * We are seeing unexpected link re-trainings with some panels. This is caused
3881 * by panel stating bad link status after PSR is enabled. Code checking link
3882 * status can call this to ensure it can ignore bad link status stated by the
3883 * panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link
3884 * is ok caller should rely on latter.
3885 *
3886 * Return value of link_ok
3887 */
3888bool intel_psr_link_ok(struct intel_dp *intel_dp)
3889{
3890	bool ret;
3891
3892	if ((!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) ||
3893	    !intel_dp_is_edp(intel_dp))
3894		return false;
3895
3896	mutex_lock(&intel_dp->psr.lock);
3897	ret = intel_dp->psr.link_ok;
3898	mutex_unlock(&intel_dp->psr.lock);
3899
3900	return ret;
3901}
3902
3903/**
3904 * intel_psr_lock - grab PSR lock
3905 * @crtc_state: the crtc state
3906 *
3907 * This is initially meant to be used by around CRTC update, when
3908 * vblank sensitive registers are updated and we need grab the lock
3909 * before it to avoid vblank evasion.
3910 */
3911void intel_psr_lock(const struct intel_crtc_state *crtc_state)
3912{
3913	struct intel_display *display = to_intel_display(crtc_state);
3914	struct intel_encoder *encoder;
3915
3916	if (!crtc_state->has_psr)
3917		return;
3918
3919	for_each_intel_encoder_mask_with_psr(display->drm, encoder,
3920					     crtc_state->uapi.encoder_mask) {
3921		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3922
3923		mutex_lock(&intel_dp->psr.lock);
3924		break;
3925	}
3926}
3927
3928/**
3929 * intel_psr_unlock - release PSR lock
3930 * @crtc_state: the crtc state
3931 *
3932 * Release the PSR lock that was held during pipe update.
3933 */
3934void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
3935{
3936	struct intel_display *display = to_intel_display(crtc_state);
3937	struct intel_encoder *encoder;
3938
3939	if (!crtc_state->has_psr)
3940		return;
3941
3942	for_each_intel_encoder_mask_with_psr(display->drm, encoder,
3943					     crtc_state->uapi.encoder_mask) {
3944		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3945
3946		mutex_unlock(&intel_dp->psr.lock);
3947		break;
3948	}
3949}
3950
3951/* Wa_16025596647 */
3952static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp)
3953{
3954	struct intel_display *display = to_intel_display(intel_dp);
3955	bool dc5_dc6_blocked;
3956
3957	if (!intel_dp->psr.active || !intel_dp->psr.pkg_c_latency_used)
3958		return;
3959
3960	dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp);
3961
3962	if (intel_dp->psr.sel_update_enabled)
3963		psr2_program_idle_frames(intel_dp, dc5_dc6_blocked ? 0 :
3964					 psr_compute_idle_frames(intel_dp));
3965	else
3966		intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display,
3967								       intel_dp->psr.pipe,
3968								       dc5_dc6_blocked);
3969}
3970
3971static void psr_dc5_dc6_wa_work(struct work_struct *work)
3972{
3973	struct intel_display *display = container_of(work, typeof(*display),
3974						     psr_dc5_dc6_wa_work);
3975	struct intel_encoder *encoder;
3976
3977	for_each_intel_encoder_with_psr(display->drm, encoder) {
3978		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3979
3980		mutex_lock(&intel_dp->psr.lock);
3981
3982		if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled &&
3983		    !intel_dp->psr.pkg_c_latency_used)
3984			intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);
3985
3986		mutex_unlock(&intel_dp->psr.lock);
3987	}
3988}
3989
3990/**
3991 * intel_psr_notify_dc5_dc6 - Notify PSR about enable/disable dc5/dc6
3992 * @display: intel atomic state
3993 *
3994 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to schedule
3995 * psr_dc5_dc6_wa_work used for applying/removing the workaround.
3996 */
3997void intel_psr_notify_dc5_dc6(struct intel_display *display)
3998{
3999	if (DISPLAY_VER(display) != 20 &&
4000	    !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
4001		return;
4002
4003	schedule_work(&display->psr_dc5_dc6_wa_work);
4004}
4005
4006/**
4007 * intel_psr_dc5_dc6_wa_init - Init work for underrun on idle PSR HW bug wa
4008 * @display: intel atomic state
4009 *
4010 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init
4011 * psr_dc5_dc6_wa_work used for applying the workaround.
4012 */
4013void intel_psr_dc5_dc6_wa_init(struct intel_display *display)
4014{
4015	if (DISPLAY_VER(display) != 20 &&
4016	    !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
4017		return;
4018
4019	INIT_WORK(&display->psr_dc5_dc6_wa_work, psr_dc5_dc6_wa_work);
4020}
4021
4022/**
4023 * intel_psr_notify_pipe_change - Notify PSR about enable/disable of a pipe
4024 * @state: intel atomic state
4025 * @crtc: intel crtc
4026 * @enable: enable/disable
4027 *
4028 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply
4029 * remove the workaround when pipe is getting enabled/disabled
4030 */
4031void intel_psr_notify_pipe_change(struct intel_atomic_state *state,
4032				  struct intel_crtc *crtc, bool enable)
4033{
4034	struct intel_display *display = to_intel_display(state);
4035	struct intel_encoder *encoder;
4036
4037	if (DISPLAY_VER(display) != 20 &&
4038	    !IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0))
4039		return;
4040
4041	for_each_intel_encoder_with_psr(display->drm, encoder) {
4042		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4043		u8 active_non_psr_pipes;
4044
4045		mutex_lock(&intel_dp->psr.lock);
4046
4047		if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled)
4048			goto unlock;
4049
4050		active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes;
4051
4052		if (enable)
4053			active_non_psr_pipes |= BIT(crtc->pipe);
4054		else
4055			active_non_psr_pipes &= ~BIT(crtc->pipe);
4056
4057		if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes)
4058			goto unlock;
4059
4060		if ((enable && intel_dp->psr.active_non_psr_pipes) ||
4061		    (!enable && !intel_dp->psr.active_non_psr_pipes) ||
4062		    !intel_dp->psr.pkg_c_latency_used) {
4063			intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;
4064			goto unlock;
4065		}
4066
4067		intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;
4068
4069		intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);
4070unlock:
4071		mutex_unlock(&intel_dp->psr.lock);
4072	}
4073}
4074
4075/**
4076 * intel_psr_notify_vblank_enable_disable - Notify PSR about enable/disable of vblank
4077 * @display: intel display struct
4078 * @enable: enable/disable
4079 *
4080 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply
4081 * remove the workaround when vblank is getting enabled/disabled
4082 */
4083void intel_psr_notify_vblank_enable_disable(struct intel_display *display,
4084					    bool enable)
4085{
4086	struct intel_encoder *encoder;
4087
4088	for_each_intel_encoder_with_psr(display->drm, encoder) {
4089		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4090
4091		mutex_lock(&intel_dp->psr.lock);
4092		if (intel_dp->psr.panel_replay_enabled) {
4093			mutex_unlock(&intel_dp->psr.lock);
4094			break;
4095		}
4096
4097		if (intel_dp->psr.enabled && intel_dp->psr.pkg_c_latency_used)
4098			intel_psr_apply_underrun_on_idle_wa_locked(intel_dp);
4099
4100		mutex_unlock(&intel_dp->psr.lock);
4101		return;
4102	}
4103
4104	/*
4105	 * NOTE: intel_display_power_set_target_dc_state is used
4106	 * only by PSR * code for DC3CO handling. DC3CO target
4107	 * state is currently disabled in * PSR code. If DC3CO
4108	 * is taken into use we need take that into account here
4109	 * as well.
4110	 */
4111	intel_display_power_set_target_dc_state(display, enable ? DC_STATE_DISABLE :
4112						DC_STATE_EN_UPTO_DC6);
4113}
4114
4115static void
4116psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
4117{
4118	struct intel_display *display = to_intel_display(intel_dp);
4119	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
4120	const char *status = "unknown";
4121	u32 val, status_val;
4122
4123	if ((intel_dp_is_edp(intel_dp) || DISPLAY_VER(display) >= 30) &&
4124	    (intel_dp->psr.sel_update_enabled || intel_dp->psr.panel_replay_enabled)) {
4125		static const char * const live_status[] = {
4126			"IDLE",
4127			"CAPTURE",
4128			"CAPTURE_FS",
4129			"SLEEP",
4130			"BUFON_FW",
4131			"ML_UP",
4132			"SU_STANDBY",
4133			"FAST_SLEEP",
4134			"DEEP_SLEEP",
4135			"BUF_ON",
4136			"TG_ON"
4137		};
4138		val = intel_de_read(display,
4139				    EDP_PSR2_STATUS(display, cpu_transcoder));
4140		status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
4141		if (status_val < ARRAY_SIZE(live_status))
4142			status = live_status[status_val];
4143	} else {
4144		static const char * const live_status[] = {
4145			"IDLE",
4146			"SRDONACK",
4147			"SRDENT",
4148			"BUFOFF",
4149			"BUFON",
4150			"AUXACK",
4151			"SRDOFFACK",
4152			"SRDENT_ON",
4153		};
4154		val = intel_de_read(display,
4155				    psr_status_reg(display, cpu_transcoder));
4156		status_val = REG_FIELD_GET(EDP_PSR_STATUS_STATE_MASK, val);
4157		if (status_val < ARRAY_SIZE(live_status))
4158			status = live_status[status_val];
4159	}
4160
4161	seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val);
4162}
4163
4164static void intel_psr_sink_capability(struct intel_dp *intel_dp,
4165				      struct seq_file *m)
4166{
4167	struct intel_psr *psr = &intel_dp->psr;
4168
4169	seq_printf(m, "Sink support: PSR = %s",
4170		   str_yes_no(psr->sink_support));
4171
4172	if (psr->sink_support)
4173		seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
4174	if (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED)
4175		seq_printf(m, " (Early Transport)");
4176	seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support));
4177	seq_printf(m, ", Panel Replay Selective Update = %s",
4178		   str_yes_no(psr->sink_panel_replay_su_support));
4179	seq_printf(m, ", Panel Replay DSC support = %s",
4180		   panel_replay_dsc_support_str(psr->sink_panel_replay_dsc_support));
4181	if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] &
4182	    DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)
4183		seq_printf(m, " (Early Transport)");
4184	seq_printf(m, "\n");
4185}
4186
4187static void intel_psr_print_mode(struct intel_dp *intel_dp,
4188				 struct seq_file *m)
4189{
4190	struct intel_psr *psr = &intel_dp->psr;
4191	const char *status, *mode, *region_et;
4192
4193	if (psr->enabled)
4194		status = " enabled";
4195	else
4196		status = "disabled";
4197
4198	if (psr->panel_replay_enabled && psr->sel_update_enabled)
4199		mode = "Panel Replay Selective Update";
4200	else if (psr->panel_replay_enabled)
4201		mode = "Panel Replay";
4202	else if (psr->sel_update_enabled)
4203		mode = "PSR2";
4204	else if (psr->enabled)
4205		mode = "PSR1";
4206	else
4207		mode = "";
4208
4209	if (psr->su_region_et_enabled)
4210		region_et = " (Early Transport)";
4211	else
4212		region_et = "";
4213
4214	seq_printf(m, "PSR mode: %s%s%s\n", mode, status, region_et);
4215	if (psr->no_psr_reason)
4216		seq_printf(m, "  %s\n", psr->no_psr_reason);
4217}
4218
4219static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
4220{
4221	struct intel_display *display = to_intel_display(intel_dp);
4222	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
4223	struct intel_psr *psr = &intel_dp->psr;
4224	struct ref_tracker *wakeref;
4225	bool enabled;
4226	u32 val, psr2_ctl;
4227
4228	intel_psr_sink_capability(intel_dp, m);
4229
4230	if (!(psr->sink_support || psr->sink_panel_replay_support))
4231		return 0;
4232
4233	wakeref = intel_display_rpm_get(display);
4234	mutex_lock(&psr->lock);
4235
4236	intel_psr_print_mode(intel_dp, m);
4237
4238	if (!psr->enabled) {
4239		seq_printf(m, "PSR sink not reliable: %s\n",
4240			   str_yes_no(psr->sink_not_reliable));
4241
4242		goto unlock;
4243	}
4244
4245	if (psr->panel_replay_enabled) {
4246		val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder));
4247
4248		if (intel_dp_is_edp(intel_dp))
4249			psr2_ctl = intel_de_read(display,
4250						 EDP_PSR2_CTL(display,
4251							      cpu_transcoder));
4252
4253		enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE;
4254	} else if (psr->sel_update_enabled) {
4255		val = intel_de_read(display,
4256				    EDP_PSR2_CTL(display, cpu_transcoder));
4257		enabled = val & EDP_PSR2_ENABLE;
4258	} else {
4259		val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder));
4260		enabled = val & EDP_PSR_ENABLE;
4261	}
4262	seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n",
4263		   str_enabled_disabled(enabled), val);
4264	if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp))
4265		seq_printf(m, "PSR2_CTL: 0x%08x\n",
4266			   psr2_ctl);
4267	psr_source_status(intel_dp, m);
4268	seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
4269		   psr->busy_frontbuffer_bits);
4270
4271	/*
4272	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
4273	 */
4274	val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder));
4275	seq_printf(m, "Performance counter: %u\n",
4276		   REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val));
4277
4278	if (psr->debug & I915_PSR_DEBUG_IRQ) {
4279		seq_printf(m, "Last attempted entry at: %lld\n",
4280			   psr->last_entry_attempt);
4281		seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
4282	}
4283
4284	if (psr->sel_update_enabled) {
4285		u32 su_frames_val[3];
4286		int frame;
4287
4288		/*
4289		 * PSR2_SU_STATUS register has been tied-off since DG2/ADL-P
4290		 * (it returns zeros only) and it has been removed on Xe2_LPD.
4291		 */
4292		if (DISPLAY_VER(display) < 13) {
4293			/*
4294			 * Reading all 3 registers before hand to minimize crossing a
4295			 * frame boundary between register reads
4296			 */
4297			for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) {
4298				val = intel_de_read(display,
4299						    PSR2_SU_STATUS(display, cpu_transcoder, frame));
4300				su_frames_val[frame / 3] = val;
4301			}
4302
4303			seq_puts(m, "Frame:\tPSR2 SU blocks:\n");
4304
4305			for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) {
4306				u32 su_blocks;
4307
4308				su_blocks = su_frames_val[frame / 3] &
4309					PSR2_SU_STATUS_MASK(frame);
4310				su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame);
4311				seq_printf(m, "%d\t%d\n", frame, su_blocks);
4312			}
4313		}
4314
4315		seq_printf(m, "PSR2 selective fetch: %s\n",
4316			   str_enabled_disabled(psr->psr2_sel_fetch_enabled));
4317	}
4318
4319unlock:
4320	mutex_unlock(&psr->lock);
4321	intel_display_rpm_put(display, wakeref);
4322
4323	return 0;
4324}
4325
4326static int i915_edp_psr_status_show(struct seq_file *m, void *data)
4327{
4328	struct intel_display *display = m->private;
4329	struct intel_dp *intel_dp = NULL;
4330	struct intel_encoder *encoder;
4331
4332	if (!HAS_PSR(display))
4333		return -ENODEV;
4334
4335	/* Find the first EDP which supports PSR */
4336	for_each_intel_encoder_with_psr(display->drm, encoder) {
4337		intel_dp = enc_to_intel_dp(encoder);
4338		break;
4339	}
4340
4341	if (!intel_dp)
4342		return -ENODEV;
4343
4344	return intel_psr_status(m, intel_dp);
4345}
4346DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status);
4347
4348static int
4349i915_edp_psr_debug_set(void *data, u64 val)
4350{
4351	struct intel_display *display = data;
4352	struct intel_encoder *encoder;
4353	int ret = -ENODEV;
4354
4355	if (!HAS_PSR(display))
4356		return ret;
4357
4358	for_each_intel_encoder_with_psr(display->drm, encoder) {
4359		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4360
4361		drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val);
4362
4363		// TODO: split to each transcoder's PSR debug state
4364		with_intel_display_rpm(display)
4365			ret = intel_psr_debug_set(intel_dp, val);
4366	}
4367
4368	return ret;
4369}
4370
4371static int
4372i915_edp_psr_debug_get(void *data, u64 *val)
4373{
4374	struct intel_display *display = data;
4375	struct intel_encoder *encoder;
4376
4377	if (!HAS_PSR(display))
4378		return -ENODEV;
4379
4380	for_each_intel_encoder_with_psr(display->drm, encoder) {
4381		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4382
4383		// TODO: split to each transcoder's PSR debug state
4384		*val = READ_ONCE(intel_dp->psr.debug);
4385		return 0;
4386	}
4387
4388	return -ENODEV;
4389}
4390
4391DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops,
4392			i915_edp_psr_debug_get, i915_edp_psr_debug_set,
4393			"%llu\n");
4394
4395void intel_psr_debugfs_register(struct intel_display *display)
4396{
4397	struct dentry *debugfs_root = display->drm->debugfs_root;
4398
4399	debugfs_create_file("i915_edp_psr_debug", 0644, debugfs_root,
4400			    display, &i915_edp_psr_debug_fops);
4401
4402	debugfs_create_file("i915_edp_psr_status", 0444, debugfs_root,
4403			    display, &i915_edp_psr_status_fops);
4404}
4405
4406static const char *psr_mode_str(struct intel_dp *intel_dp)
4407{
4408	if (intel_dp->psr.panel_replay_enabled)
4409		return "PANEL-REPLAY";
4410	else if (intel_dp->psr.enabled)
4411		return "PSR";
4412
4413	return "unknown";
4414}
4415
4416static int i915_psr_sink_status_show(struct seq_file *m, void *data)
4417{
4418	struct intel_connector *connector = m->private;
4419	struct intel_dp *intel_dp = intel_attached_dp(connector);
4420	static const char * const sink_status[] = {
4421		"inactive",
4422		"transition to active, capture and display",
4423		"active, display from RFB",
4424		"active, capture and display on sink device timings",
4425		"transition to inactive, capture and display, timing re-sync",
4426		"reserved",
4427		"reserved",
4428		"sink internal error",
4429	};
4430	const char *str;
4431	int ret;
4432	u8 status, error_status;
4433
4434	if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) {
4435		seq_puts(m, "PSR/Panel-Replay Unsupported\n");
4436		return -ENODEV;
4437	}
4438
4439	if (connector->base.status != connector_status_connected)
4440		return -ENODEV;
4441
4442	ret = psr_get_status_and_error_status(intel_dp, &status, &error_status);
4443	if (ret)
4444		return ret;
4445
4446	status &= DP_PSR_SINK_STATE_MASK;
4447	if (status < ARRAY_SIZE(sink_status))
4448		str = sink_status[status];
4449	else
4450		str = "unknown";
4451
4452	seq_printf(m, "Sink %s status: 0x%x [%s]\n", psr_mode_str(intel_dp), status, str);
4453
4454	seq_printf(m, "Sink %s error status: 0x%x", psr_mode_str(intel_dp), error_status);
4455
4456	if (error_status & (DP_PSR_RFB_STORAGE_ERROR |
4457			    DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
4458			    DP_PSR_LINK_CRC_ERROR))
4459		seq_puts(m, ":\n");
4460	else
4461		seq_puts(m, "\n");
4462	if (error_status & DP_PSR_RFB_STORAGE_ERROR)
4463		seq_printf(m, "\t%s RFB storage error\n", psr_mode_str(intel_dp));
4464	if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
4465		seq_printf(m, "\t%s VSC SDP uncorrectable error\n", psr_mode_str(intel_dp));
4466	if (error_status & DP_PSR_LINK_CRC_ERROR)
4467		seq_printf(m, "\t%s Link CRC error\n", psr_mode_str(intel_dp));
4468
4469	return ret;
4470}
4471DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status);
4472
4473static int i915_psr_status_show(struct seq_file *m, void *data)
4474{
4475	struct intel_connector *connector = m->private;
4476	struct intel_dp *intel_dp = intel_attached_dp(connector);
4477
4478	return intel_psr_status(m, intel_dp);
4479}
4480DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
4481
4482void intel_psr_connector_debugfs_add(struct intel_connector *connector)
4483{
4484	struct intel_display *display = to_intel_display(connector);
4485	struct dentry *root = connector->base.debugfs_entry;
4486
4487	if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP &&
4488	    connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort)
4489		return;
4490
4491	debugfs_create_file("i915_psr_sink_status", 0444, root,
4492			    connector, &i915_psr_sink_status_fops);
4493
4494	if (HAS_PSR(display) || HAS_DP20(display))
4495		debugfs_create_file("i915_psr_status", 0444, root,
4496				    connector, &i915_psr_status_fops);
4497}
4498
4499bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state)
4500{
4501	/*
4502	 * eDP Panel Replay uses always ALPM
4503	 * PSR2 uses ALPM but PSR1 doesn't
4504	 */
4505	return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update ||
4506					     crtc_state->has_panel_replay);
4507}
4508
4509bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
4510				   const struct intel_crtc_state *crtc_state)
4511{
4512	return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay;
4513}
4514
4515void intel_psr_compute_config_late(struct intel_dp *intel_dp,
4516				   struct intel_crtc_state *crtc_state)
4517{
4518	struct intel_display *display = to_intel_display(intel_dp);
4519	int vblank = intel_crtc_vblank_length(crtc_state);
4520	int wake_lines;
4521
4522	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state))
4523		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
4524	else if (intel_psr_needs_alpm(intel_dp, crtc_state))
4525		wake_lines = DISPLAY_VER(display) < 20 ?
4526			     psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
4527						    crtc_state->alpm_state.fast_wake_lines) :
4528			     crtc_state->alpm_state.io_wake_lines;
4529	else
4530		wake_lines = 0;
4531
4532	/*
4533	 * Disable the PSR features if wake lines exceed the available vblank.
4534	 * Though SCL is computed based on these PSR features, it is not reset
4535	 * even if the PSR features are disabled to avoid changing vblank start
4536	 * at this stage.
4537	 */
4538	if (wake_lines && !_wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines)) {
4539		drm_dbg_kms(display->drm,
4540			    "Adjusting PSR/PR mode: vblank too short for wake lines = %d\n",
4541			    wake_lines);
4542
4543		if (crtc_state->has_panel_replay) {
4544			crtc_state->has_panel_replay = false;
4545			/*
4546			 * #TODO : Add fall back to PSR/PSR2
4547			 * Since panel replay cannot be supported, we can fall back to PSR/PSR2.
4548			 * This will require calling compute_config for psr and psr2 with check for
4549			 * actual guardband instead of vblank_length.
4550			 */
4551			crtc_state->has_psr = false;
4552		}
4553
4554		crtc_state->has_sel_update = false;
4555		crtc_state->enable_psr2_su_region_et = false;
4556		crtc_state->enable_psr2_sel_fetch = false;
4557	}
4558
4559	/* Wa_18037818876 */
4560	if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) {
4561		crtc_state->has_psr = false;
4562		drm_dbg_kms(display->drm,
4563			    "PSR disabled to workaround PSR FSM hang issue\n");
4564	}
4565
4566	intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
4567}
4568
4569int intel_psr_min_guardband(struct intel_crtc_state *crtc_state)
4570{
4571	struct intel_display *display = to_intel_display(crtc_state);
4572	int psr_min_guardband;
4573	int wake_lines;
4574
4575	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
4576		return 0;
4577
4578	if (crtc_state->has_panel_replay)
4579		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
4580	else if (crtc_state->has_sel_update)
4581		wake_lines = DISPLAY_VER(display) < 20 ?
4582			     psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
4583						    crtc_state->alpm_state.fast_wake_lines) :
4584			     crtc_state->alpm_state.io_wake_lines;
4585	else
4586		return 0;
4587
4588	psr_min_guardband = wake_lines + crtc_state->set_context_latency;
4589
4590	if (crtc_state->req_psr2_sdp_prior_scanline)
4591		psr_min_guardband++;
4592
4593	return psr_min_guardband;
4594}