intel_plane.c

   1/*
   2 * Copyright © 2014 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21 * DEALINGS IN THE SOFTWARE.
  22 */
  23
  24/**
  25 * DOC: atomic plane helpers
  26 *
  27 * The functions here are used by the atomic plane helper functions to
  28 * implement legacy plane updates (i.e., drm_plane->update_plane() and
  29 * drm_plane->disable_plane()).  This allows plane updates to use the
  30 * atomic state infrastructure and perform plane updates as separate
  31 * prepare/check/commit/cleanup steps.
  32 */
  33
  34#include <linux/dma-fence-chain.h>
  35#include <linux/dma-resv.h>
  36#include <linux/iosys-map.h>
  37
  38#include <drm/drm_atomic_helper.h>
  39#include <drm/drm_blend.h>
  40#include <drm/drm_cache.h>
  41#include <drm/drm_damage_helper.h>
  42#include <drm/drm_fourcc.h>
  43#include <drm/drm_gem.h>
  44#include <drm/drm_gem_atomic_helper.h>
  45#include <drm/drm_panic.h>
  46#include <drm/drm_print.h>
  47
  48#include "gem/i915_gem_object.h"
  49#include "i9xx_plane_regs.h"
  50#include "intel_cdclk.h"
  51#include "intel_cursor.h"
  52#include "intel_colorop.h"
  53#include "intel_display_rps.h"
  54#include "intel_display_trace.h"
  55#include "intel_display_types.h"
  56#include "intel_fb.h"
  57#include "intel_fb_pin.h"
  58#include "intel_fbdev.h"
  59#include "intel_panic.h"
  60#include "intel_plane.h"
  61#include "intel_psr.h"
  62#include "skl_scaler.h"
  63#include "skl_universal_plane.h"
  64#include "skl_watermark.h"
  65
  66static void intel_plane_state_reset(struct intel_plane_state *plane_state,
  67				    struct intel_plane *plane)
  68{
  69	memset(plane_state, 0, sizeof(*plane_state));
  70
  71	__drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base);
  72
  73	plane_state->scaler_id = -1;
  74}
  75
  76struct intel_plane *intel_plane_alloc(void)
  77{
  78	struct intel_plane_state *plane_state;
  79	struct intel_plane *plane;
  80
  81	plane = kzalloc(sizeof(*plane), GFP_KERNEL);
  82	if (!plane)
  83		return ERR_PTR(-ENOMEM);
  84
  85	plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
  86	if (!plane_state) {
  87		kfree(plane);
  88		return ERR_PTR(-ENOMEM);
  89	}
  90
  91	intel_plane_state_reset(plane_state, plane);
  92
  93	plane->base.state = &plane_state->uapi;
  94
  95	return plane;
  96}
  97
  98void intel_plane_free(struct intel_plane *plane)
  99{
 100	intel_plane_destroy_state(&plane->base, plane->base.state);
 101	kfree(plane);
 102}
 103
 104/**
 105 * intel_plane_destroy - destroy a plane
 106 * @plane: plane to destroy
 107 *
 108 * Common destruction function for all types of planes (primary, cursor,
 109 * sprite).
 110 */
 111void intel_plane_destroy(struct drm_plane *plane)
 112{
 113	drm_plane_cleanup(plane);
 114	kfree(to_intel_plane(plane));
 115}
 116
 117/**
 118 * intel_plane_duplicate_state - duplicate plane state
 119 * @plane: drm plane
 120 *
 121 * Allocates and returns a copy of the plane state (both common and
 122 * Intel-specific) for the specified plane.
 123 *
 124 * Returns: The newly allocated plane state, or NULL on failure.
 125 */
 126struct drm_plane_state *
 127intel_plane_duplicate_state(struct drm_plane *plane)
 128{
 129	struct intel_plane_state *intel_state;
 130
 131	intel_state = to_intel_plane_state(plane->state);
 132	intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
 133
 134	if (!intel_state)
 135		return NULL;
 136
 137	__drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
 138
 139	intel_state->ggtt_vma = NULL;
 140	intel_state->dpt_vma = NULL;
 141	intel_state->flags = 0;
 142	intel_state->damage = DRM_RECT_INIT(0, 0, 0, 0);
 143
 144	/* add reference to fb */
 145	if (intel_state->hw.fb)
 146		drm_framebuffer_get(intel_state->hw.fb);
 147
 148	return &intel_state->uapi;
 149}
 150
 151/**
 152 * intel_plane_destroy_state - destroy plane state
 153 * @plane: drm plane
 154 * @state: state object to destroy
 155 *
 156 * Destroys the plane state (both common and Intel-specific) for the
 157 * specified plane.
 158 */
 159void
 160intel_plane_destroy_state(struct drm_plane *plane,
 161			  struct drm_plane_state *state)
 162{
 163	struct intel_plane_state *plane_state = to_intel_plane_state(state);
 164
 165	drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
 166	drm_WARN_ON(plane->dev, plane_state->dpt_vma);
 167
 168	__drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
 169	if (plane_state->hw.fb)
 170		drm_framebuffer_put(plane_state->hw.fb);
 171	kfree(plane_state);
 172}
 173
 174bool intel_plane_needs_physical(struct intel_plane *plane)
 175{
 176	struct intel_display *display = to_intel_display(plane);
 177
 178	return plane->id == PLANE_CURSOR &&
 179		DISPLAY_INFO(display)->cursor_needs_physical;
 180}
 181
 182bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format,
 183				u64 modifier)
 184{
 185	if (intel_format_info_is_yuv_semiplanar(drm_format_info(format), modifier) ||
 186	    format == DRM_FORMAT_C8)
 187		return false;
 188
 189	return plane->can_async_flip && plane->can_async_flip(modifier);
 190}
 191
 192bool intel_plane_format_mod_supported_async(struct drm_plane *plane,
 193					    u32 format,
 194					    u64 modifier)
 195{
 196	if (!plane->funcs->format_mod_supported(plane, format, modifier))
 197		return false;
 198
 199	return intel_plane_can_async_flip(to_intel_plane(plane),
 200					format, modifier);
 201}
 202
 203unsigned int intel_adjusted_rate(const struct drm_rect *src,
 204				 const struct drm_rect *dst,
 205				 unsigned int rate)
 206{
 207	unsigned int src_w, src_h, dst_w, dst_h;
 208
 209	src_w = drm_rect_width(src) >> 16;
 210	src_h = drm_rect_height(src) >> 16;
 211	dst_w = drm_rect_width(dst);
 212	dst_h = drm_rect_height(dst);
 213
 214	/* Downscaling limits the maximum pixel rate */
 215	dst_w = min(src_w, dst_w);
 216	dst_h = min(src_h, dst_h);
 217
 218	return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
 219				dst_w * dst_h);
 220}
 221
 222unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
 223				    const struct intel_plane_state *plane_state)
 224{
 225	/*
 226	 * Note we don't check for plane visibility here as
 227	 * we want to use this when calculating the cursor
 228	 * watermarks even if the cursor is fully offscreen.
 229	 * That depends on the src/dst rectangles being
 230	 * correctly populated whenever the watermark code
 231	 * considers the cursor to be visible, whether or not
 232	 * it is actually visible.
 233	 *
 234	 * See: intel_wm_plane_visible() and intel_check_cursor()
 235	 */
 236
 237	return intel_adjusted_rate(&plane_state->uapi.src,
 238				   &plane_state->uapi.dst,
 239				   crtc_state->pixel_rate);
 240}
 241
 242unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
 243				   const struct intel_plane_state *plane_state,
 244				   int color_plane)
 245{
 246	const struct drm_framebuffer *fb = plane_state->hw.fb;
 247
 248	if (!plane_state->uapi.visible)
 249		return 0;
 250
 251	return intel_plane_pixel_rate(crtc_state, plane_state) *
 252		fb->format->cpp[color_plane];
 253}
 254
 255static unsigned int
 256intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 257			       const struct intel_plane_state *plane_state,
 258			       int color_plane)
 259{
 260	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 261	const struct drm_framebuffer *fb = plane_state->hw.fb;
 262	unsigned int rel_data_rate;
 263	int width, height;
 264
 265	if (plane->id == PLANE_CURSOR)
 266		return 0;
 267
 268	if (!plane_state->uapi.visible)
 269		return 0;
 270
 271	/*
 272	 * Src coordinates are already rotated by 270 degrees for
 273	 * the 90/270 degree plane rotation cases (to match the
 274	 * GTT mapping), hence no need to account for rotation here.
 275	 */
 276	width = drm_rect_width(&plane_state->uapi.src) >> 16;
 277	height = drm_rect_height(&plane_state->uapi.src) >> 16;
 278
 279	/* UV plane does 1/2 pixel sub-sampling */
 280	if (color_plane == 1) {
 281		width /= 2;
 282		height /= 2;
 283	}
 284
 285	rel_data_rate =
 286		skl_plane_relative_data_rate(crtc_state, plane, width, height,
 287					     fb->format->cpp[color_plane]);
 288	if (!rel_data_rate)
 289		return 0;
 290
 291	return intel_adjusted_rate(&plane_state->uapi.src,
 292				   &plane_state->uapi.dst,
 293				   rel_data_rate);
 294}
 295
 296static void intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
 297				       struct intel_plane *plane)
 298{
 299	const struct intel_plane_state *plane_state =
 300		intel_atomic_get_new_plane_state(state, plane);
 301	struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
 302	struct intel_crtc_state *new_crtc_state;
 303
 304	if (!plane_state->uapi.visible || !plane->min_cdclk)
 305		return;
 306
 307	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 308
 309	new_crtc_state->plane_min_cdclk[plane->id] =
 310		plane->min_cdclk(new_crtc_state, plane_state);
 311}
 312
 313static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
 314{
 315	if (plane_state->hw.fb)
 316		drm_framebuffer_put(plane_state->hw.fb);
 317
 318	memset(&plane_state->hw, 0, sizeof(plane_state->hw));
 319}
 320
 321static void
 322intel_plane_copy_uapi_plane_damage(struct intel_plane_state *new_plane_state,
 323				   const struct intel_plane_state *old_uapi_plane_state,
 324				   const struct intel_plane_state *new_uapi_plane_state)
 325{
 326	struct intel_display *display = to_intel_display(new_plane_state);
 327	struct drm_rect *damage = &new_plane_state->damage;
 328
 329	/* damage property tracking enabled from display version 12 onwards */
 330	if (DISPLAY_VER(display) < 12)
 331		return;
 332
 333	if (!drm_atomic_helper_damage_merged(&old_uapi_plane_state->uapi,
 334					     &new_uapi_plane_state->uapi,
 335					     damage))
 336		/* Incase helper fails, mark whole plane region as damage */
 337		*damage = drm_plane_state_src(&new_uapi_plane_state->uapi);
 338}
 339
 340static bool
 341intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,
 342				 struct intel_colorop *intel_colorop,
 343				 struct drm_property_blob *blob)
 344{
 345	if (intel_colorop->id == INTEL_PLANE_CB_CSC)
 346		return drm_property_replace_blob(&plane_state->hw.ctm, blob);
 347	else if (intel_colorop->id == INTEL_PLANE_CB_PRE_CSC_LUT)
 348		return	drm_property_replace_blob(&plane_state->hw.degamma_lut, blob);
 349	else if (intel_colorop->id == INTEL_PLANE_CB_POST_CSC_LUT)
 350		return drm_property_replace_blob(&plane_state->hw.gamma_lut, blob);
 351	else if (intel_colorop->id == INTEL_PLANE_CB_3DLUT)
 352		return	drm_property_replace_blob(&plane_state->hw.lut_3d, blob);
 353
 354	return false;
 355}
 356
 357static void
 358intel_plane_color_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
 359					const struct intel_plane_state *from_plane_state,
 360					struct intel_crtc *crtc)
 361{
 362	struct drm_colorop *iter_colorop, *colorop;
 363	struct drm_colorop_state *new_colorop_state;
 364	struct drm_atomic_state *state = plane_state->uapi.state;
 365	struct intel_colorop *intel_colorop;
 366	struct drm_property_blob *blob;
 367	struct intel_atomic_state *intel_atomic_state = to_intel_atomic_state(state);
 368	struct intel_crtc_state *new_crtc_state = intel_atomic_state ?
 369		intel_atomic_get_new_crtc_state(intel_atomic_state, crtc) : NULL;
 370	bool changed = false;
 371	int i = 0;
 372
 373	iter_colorop = plane_state->uapi.color_pipeline;
 374
 375	while (iter_colorop) {
 376		for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {
 377			if (new_colorop_state->colorop == iter_colorop) {
 378				blob = new_colorop_state->bypass ? NULL : new_colorop_state->data;
 379				intel_colorop = to_intel_colorop(colorop);
 380				changed |= intel_plane_colorop_replace_blob(plane_state,
 381									    intel_colorop,
 382									    blob);
 383			}
 384		}
 385		iter_colorop = iter_colorop->next;
 386	}
 387
 388	if (new_crtc_state && changed)
 389		new_crtc_state->plane_color_changed = true;
 390}
 391
 392void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
 393				       const struct intel_plane_state *from_plane_state,
 394				       struct intel_crtc *crtc)
 395{
 396	intel_plane_clear_hw_state(plane_state);
 397
 398	/*
 399	 * For the joiner secondary uapi.crtc will point at
 400	 * the primary crtc. So we explicitly assign the right
 401	 * secondary crtc to hw.crtc. uapi.crtc!=NULL simply
 402	 * indicates the plane is logically enabled on the uapi level.
 403	 */
 404	plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;
 405
 406	plane_state->hw.fb = from_plane_state->uapi.fb;
 407	if (plane_state->hw.fb)
 408		drm_framebuffer_get(plane_state->hw.fb);
 409
 410	plane_state->hw.alpha = from_plane_state->uapi.alpha;
 411	plane_state->hw.pixel_blend_mode =
 412		from_plane_state->uapi.pixel_blend_mode;
 413	plane_state->hw.rotation = from_plane_state->uapi.rotation;
 414	plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
 415	plane_state->hw.color_range = from_plane_state->uapi.color_range;
 416	plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;
 417
 418	plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
 419	plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
 420
 421	intel_plane_color_copy_uapi_to_hw_state(plane_state, from_plane_state, crtc);
 422}
 423
 424void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
 425			       const struct intel_plane_state *from_plane_state)
 426{
 427	intel_plane_clear_hw_state(plane_state);
 428
 429	memcpy(&plane_state->hw, &from_plane_state->hw,
 430	       sizeof(plane_state->hw));
 431
 432	if (plane_state->hw.fb)
 433		drm_framebuffer_get(plane_state->hw.fb);
 434}
 435
 436static void unlink_nv12_plane(struct intel_crtc_state *crtc_state,
 437			      struct intel_plane_state *plane_state);
 438
 439void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
 440			       struct intel_plane_state *plane_state)
 441{
 442	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 443
 444	unlink_nv12_plane(crtc_state, plane_state);
 445
 446	crtc_state->active_planes &= ~BIT(plane->id);
 447	crtc_state->scaled_planes &= ~BIT(plane->id);
 448	crtc_state->nv12_planes &= ~BIT(plane->id);
 449	crtc_state->c8_planes &= ~BIT(plane->id);
 450	crtc_state->async_flip_planes &= ~BIT(plane->id);
 451	crtc_state->data_rate[plane->id] = 0;
 452	crtc_state->data_rate_y[plane->id] = 0;
 453	crtc_state->rel_data_rate[plane->id] = 0;
 454	crtc_state->rel_data_rate_y[plane->id] = 0;
 455	crtc_state->plane_min_cdclk[plane->id] = 0;
 456
 457	plane_state->uapi.visible = false;
 458}
 459
 460static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)
 461{
 462	int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 463	int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 464	int dst_w = drm_rect_width(&plane_state->uapi.dst);
 465	int dst_h = drm_rect_height(&plane_state->uapi.dst);
 466
 467	return src_w != dst_w || src_h != dst_h;
 468}
 469
 470static bool intel_plane_do_async_flip(struct intel_plane *plane,
 471				      const struct intel_crtc_state *old_crtc_state,
 472				      const struct intel_crtc_state *new_crtc_state)
 473{
 474	struct intel_display *display = to_intel_display(plane);
 475
 476	if (!plane->async_flip)
 477		return false;
 478
 479	if (!new_crtc_state->uapi.async_flip)
 480		return false;
 481
 482	/*
 483	 * In platforms after DISPLAY13, we might need to override
 484	 * first async flip in order to change watermark levels
 485	 * as part of optimization.
 486	 *
 487	 * And let's do this for all skl+ so that we can eg. change the
 488	 * modifier as well.
 489	 *
 490	 * TODO: For older platforms there is less reason to do this as
 491	 * only X-tile is supported with async flips, though we could
 492	 * extend this so other scanout parameters (stride/etc) could
 493	 * be changed as well...
 494	 */
 495	return DISPLAY_VER(display) < 9 || old_crtc_state->uapi.async_flip;
 496}
 497
 498static bool i9xx_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
 499				   const struct intel_plane_state *old_plane_state,
 500				   const struct intel_plane_state *new_plane_state)
 501{
 502	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 503	bool old_visible = old_plane_state->uapi.visible;
 504	bool new_visible = new_plane_state->uapi.visible;
 505	u32 old_ctl = old_plane_state->ctl;
 506	u32 new_ctl = new_plane_state->ctl;
 507	bool modeset, turn_on, turn_off;
 508
 509	if (plane->id == PLANE_CURSOR)
 510		return false;
 511
 512	modeset = intel_crtc_needs_modeset(new_crtc_state);
 513	turn_off = old_visible && (!new_visible || modeset);
 514	turn_on = new_visible && (!old_visible || modeset);
 515
 516	/* Must disable CxSR around plane enable/disable */
 517	if (turn_on || turn_off)
 518		return true;
 519
 520	if (!old_visible || !new_visible)
 521		return false;
 522
 523	/*
 524	 * Most plane control register updates are blocked while in CxSR.
 525	 *
 526	 * Tiling mode is one exception where the primary plane can
 527	 * apparently handle it, whereas the sprites can not (the
 528	 * sprite issue being only relevant on VLV/CHV where CxSR
 529	 * is actually possible with a sprite enabled).
 530	 */
 531	if (plane->id == PLANE_PRIMARY) {
 532		old_ctl &= ~DISP_TILED;
 533		new_ctl &= ~DISP_TILED;
 534	}
 535
 536	return old_ctl != new_ctl;
 537}
 538
 539static bool ilk_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
 540				  const struct intel_plane_state *old_plane_state,
 541				  const struct intel_plane_state *new_plane_state)
 542{
 543	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 544	bool old_visible = old_plane_state->uapi.visible;
 545	bool new_visible = new_plane_state->uapi.visible;
 546	bool modeset, turn_on;
 547
 548	if (plane->id == PLANE_CURSOR)
 549		return false;
 550
 551	modeset = intel_crtc_needs_modeset(new_crtc_state);
 552	turn_on = new_visible && (!old_visible || modeset);
 553
 554	/*
 555	 * ILK/SNB DVSACNTR/Sprite Enable
 556	 * IVB SPR_CTL/Sprite Enable
 557	 * "When in Self Refresh Big FIFO mode, a write to enable the
 558	 *  plane will be internally buffered and delayed while Big FIFO
 559	 *  mode is exiting."
 560	 *
 561	 * Which means that enabling the sprite can take an extra frame
 562	 * when we start in big FIFO mode (LP1+). Thus we need to drop
 563	 * down to LP0 and wait for vblank in order to make sure the
 564	 * sprite gets enabled on the next vblank after the register write.
 565	 * Doing otherwise would risk enabling the sprite one frame after
 566	 * we've already signalled flip completion. We can resume LP1+
 567	 * once the sprite has been enabled.
 568	 *
 569	 * With experimental results seems this is needed also for primary
 570	 * plane, not only sprite plane.
 571	 */
 572	if (turn_on)
 573		return true;
 574
 575	/*
 576	 * WaCxSRDisabledForSpriteScaling:ivb
 577	 * IVB SPR_SCALE/Scaling Enable
 578	 * "Low Power watermarks must be disabled for at least one
 579	 *  frame before enabling sprite scaling, and kept disabled
 580	 *  until sprite scaling is disabled."
 581	 *
 582	 * ILK/SNB DVSASCALE/Scaling Enable
 583	 * "When in Self Refresh Big FIFO mode, scaling enable will be
 584	 *  masked off while Big FIFO mode is exiting."
 585	 *
 586	 * Despite the w/a only being listed for IVB we assume that
 587	 * the ILK/SNB note has similar ramifications, hence we apply
 588	 * the w/a on all three platforms.
 589	 */
 590	return !intel_plane_is_scaled(old_plane_state) &&
 591		intel_plane_is_scaled(new_plane_state);
 592}
 593
 594static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
 595					   struct intel_crtc_state *new_crtc_state,
 596					   const struct intel_plane_state *old_plane_state,
 597					   struct intel_plane_state *new_plane_state)
 598{
 599	struct intel_display *display = to_intel_display(new_crtc_state);
 600	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 601	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 602	bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
 603	bool was_crtc_enabled = old_crtc_state->hw.active;
 604	bool is_crtc_enabled = new_crtc_state->hw.active;
 605	bool turn_off, turn_on, visible, was_visible;
 606	int ret;
 607
 608	if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_CURSOR) {
 609		ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);
 610		if (ret)
 611			return ret;
 612	}
 613
 614	was_visible = old_plane_state->uapi.visible;
 615	visible = new_plane_state->uapi.visible;
 616
 617	if (!was_crtc_enabled && drm_WARN_ON(display->drm, was_visible))
 618		was_visible = false;
 619
 620	/*
 621	 * Visibility is calculated as if the crtc was on, but
 622	 * after scaler setup everything depends on it being off
 623	 * when the crtc isn't active.
 624	 *
 625	 * FIXME this is wrong for watermarks. Watermarks should also
 626	 * be computed as if the pipe would be active. Perhaps move
 627	 * per-plane wm computation to the .check_plane() hook, and
 628	 * only combine the results from all planes in the current place?
 629	 */
 630	if (!is_crtc_enabled) {
 631		intel_plane_set_invisible(new_crtc_state, new_plane_state);
 632		visible = false;
 633	}
 634
 635	if (!was_visible && !visible)
 636		return 0;
 637
 638	turn_off = was_visible && (!visible || mode_changed);
 639	turn_on = visible && (!was_visible || mode_changed);
 640
 641	drm_dbg_atomic(display->drm,
 642		       "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
 643		       crtc->base.base.id, crtc->base.name,
 644		       plane->base.base.id, plane->base.name,
 645		       was_visible, visible,
 646		       turn_off, turn_on, mode_changed);
 647
 648	if (visible || was_visible)
 649		new_crtc_state->fb_bits |= plane->frontbuffer_bit;
 650
 651	if (HAS_GMCH(display) &&
 652	    i9xx_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))
 653		new_crtc_state->disable_cxsr = true;
 654
 655	if ((display->platform.ironlake || display->platform.sandybridge || display->platform.ivybridge) &&
 656	    ilk_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))
 657		new_crtc_state->disable_cxsr = true;
 658
 659	if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
 660		new_crtc_state->do_async_flip = true;
 661		new_crtc_state->async_flip_planes |= BIT(plane->id);
 662	} else if (plane->need_async_flip_toggle_wa &&
 663		   new_crtc_state->uapi.async_flip) {
 664		/*
 665		 * On platforms with double buffered async flip bit we
 666		 * set the bit already one frame early during the sync
 667		 * flip (see {i9xx,skl}_plane_update_arm()). The
 668		 * hardware will therefore be ready to perform a real
 669		 * async flip during the next commit, without having
 670		 * to wait yet another frame for the bit to latch.
 671		 */
 672		new_crtc_state->async_flip_planes |= BIT(plane->id);
 673	}
 674
 675	return 0;
 676}
 677
 678int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
 679					struct intel_crtc_state *new_crtc_state,
 680					const struct intel_plane_state *old_plane_state,
 681					struct intel_plane_state *new_plane_state)
 682{
 683	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 684	const struct drm_framebuffer *fb = new_plane_state->hw.fb;
 685	int ret;
 686
 687	intel_plane_set_invisible(new_crtc_state, new_plane_state);
 688	new_crtc_state->enabled_planes &= ~BIT(plane->id);
 689
 690	if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
 691		return 0;
 692
 693	ret = plane->check_plane(new_crtc_state, new_plane_state);
 694	if (ret)
 695		return ret;
 696
 697	if (fb)
 698		new_crtc_state->enabled_planes |= BIT(plane->id);
 699
 700	/* FIXME pre-g4x don't work like this */
 701	if (new_plane_state->uapi.visible)
 702		new_crtc_state->active_planes |= BIT(plane->id);
 703
 704	if (new_plane_state->uapi.visible &&
 705	    intel_plane_is_scaled(new_plane_state))
 706		new_crtc_state->scaled_planes |= BIT(plane->id);
 707
 708	if (new_plane_state->uapi.visible &&
 709	    intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
 710		new_crtc_state->nv12_planes |= BIT(plane->id);
 711
 712	if (new_plane_state->uapi.visible &&
 713	    fb->format->format == DRM_FORMAT_C8)
 714		new_crtc_state->c8_planes |= BIT(plane->id);
 715
 716	if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
 717		new_crtc_state->update_planes |= BIT(plane->id);
 718
 719	if (new_plane_state->uapi.visible &&
 720	    intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
 721		new_crtc_state->data_rate_y[plane->id] =
 722			intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
 723		new_crtc_state->data_rate[plane->id] =
 724			intel_plane_data_rate(new_crtc_state, new_plane_state, 1);
 725
 726		new_crtc_state->rel_data_rate_y[plane->id] =
 727			intel_plane_relative_data_rate(new_crtc_state,
 728						       new_plane_state, 0);
 729		new_crtc_state->rel_data_rate[plane->id] =
 730			intel_plane_relative_data_rate(new_crtc_state,
 731						       new_plane_state, 1);
 732	} else if (new_plane_state->uapi.visible) {
 733		new_crtc_state->data_rate[plane->id] =
 734			intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
 735
 736		new_crtc_state->rel_data_rate[plane->id] =
 737			intel_plane_relative_data_rate(new_crtc_state,
 738						       new_plane_state, 0);
 739	}
 740
 741	return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
 742					       old_plane_state, new_plane_state);
 743}
 744
 745struct intel_plane *
 746intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
 747{
 748	struct intel_display *display = to_intel_display(crtc);
 749	struct intel_plane *plane;
 750
 751	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
 752		if (plane->id == plane_id)
 753			return plane;
 754	}
 755
 756	return NULL;
 757}
 758
 759static int plane_atomic_check(struct intel_atomic_state *state,
 760			      struct intel_plane *plane)
 761{
 762	struct intel_display *display = to_intel_display(state);
 763	struct intel_plane_state *new_plane_state =
 764		intel_atomic_get_new_plane_state(state, plane);
 765	const struct intel_plane_state *old_plane_state =
 766		intel_atomic_get_old_plane_state(state, plane);
 767	const struct intel_plane_state *new_primary_crtc_plane_state;
 768	const struct intel_plane_state *old_primary_crtc_plane_state;
 769	struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);
 770	const struct intel_crtc_state *old_crtc_state =
 771		intel_atomic_get_old_crtc_state(state, crtc);
 772	struct intel_crtc_state *new_crtc_state =
 773		intel_atomic_get_new_crtc_state(state, crtc);
 774
 775	if (new_crtc_state && intel_crtc_is_joiner_secondary(new_crtc_state)) {
 776		struct intel_crtc *primary_crtc =
 777			intel_primary_crtc(new_crtc_state);
 778		struct intel_plane *primary_crtc_plane =
 779			intel_crtc_get_plane(primary_crtc, plane->id);
 780
 781		new_primary_crtc_plane_state =
 782			intel_atomic_get_new_plane_state(state, primary_crtc_plane);
 783		old_primary_crtc_plane_state =
 784			intel_atomic_get_old_plane_state(state, primary_crtc_plane);
 785	} else {
 786		new_primary_crtc_plane_state = new_plane_state;
 787		old_primary_crtc_plane_state = old_plane_state;
 788	}
 789
 790	intel_plane_copy_uapi_plane_damage(new_plane_state,
 791					   old_primary_crtc_plane_state,
 792					   new_primary_crtc_plane_state);
 793
 794	intel_plane_copy_uapi_to_hw_state(new_plane_state,
 795					  new_primary_crtc_plane_state,
 796					  crtc);
 797
 798	new_plane_state->uapi.visible = false;
 799	if (!new_crtc_state)
 800		return 0;
 801
 802	return intel_plane_atomic_check_with_state(old_crtc_state,
 803						   new_crtc_state,
 804						   old_plane_state,
 805						   new_plane_state);
 806}
 807
 808static struct intel_plane *
 809skl_next_plane_to_commit(struct intel_atomic_state *state,
 810			 struct intel_crtc *crtc,
 811			 struct skl_ddb_entry ddb[I915_MAX_PLANES],
 812			 struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
 813			 unsigned int *update_mask)
 814{
 815	struct intel_crtc_state *crtc_state =
 816		intel_atomic_get_new_crtc_state(state, crtc);
 817	struct intel_plane_state __maybe_unused *plane_state;
 818	struct intel_plane *plane;
 819	int i;
 820
 821	if (*update_mask == 0)
 822		return NULL;
 823
 824	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
 825		enum plane_id plane_id = plane->id;
 826
 827		if (crtc->pipe != plane->pipe ||
 828		    !(*update_mask & BIT(plane_id)))
 829			continue;
 830
 831		if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],
 832						ddb, I915_MAX_PLANES, plane_id) ||
 833		    skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
 834						ddb_y, I915_MAX_PLANES, plane_id))
 835			continue;
 836
 837		*update_mask &= ~BIT(plane_id);
 838		ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
 839		ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
 840
 841		return plane;
 842	}
 843
 844	/* should never happen */
 845	drm_WARN_ON(state->base.dev, 1);
 846
 847	return NULL;
 848}
 849
 850void intel_plane_update_noarm(struct intel_dsb *dsb,
 851			      struct intel_plane *plane,
 852			      const struct intel_crtc_state *crtc_state,
 853			      const struct intel_plane_state *plane_state)
 854{
 855	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 856
 857	trace_intel_plane_update_noarm(plane_state, crtc);
 858
 859	if (plane->fbc)
 860		intel_fbc_dirty_rect_update_noarm(dsb, plane);
 861
 862	if (plane->update_noarm)
 863		plane->update_noarm(dsb, plane, crtc_state, plane_state);
 864}
 865
 866void intel_plane_async_flip(struct intel_dsb *dsb,
 867			    struct intel_plane *plane,
 868			    const struct intel_crtc_state *crtc_state,
 869			    const struct intel_plane_state *plane_state,
 870			    bool async_flip)
 871{
 872	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 873
 874	trace_intel_plane_async_flip(plane, crtc, async_flip);
 875	plane->async_flip(dsb, plane, crtc_state, plane_state, async_flip);
 876}
 877
 878void intel_plane_update_arm(struct intel_dsb *dsb,
 879			    struct intel_plane *plane,
 880			    const struct intel_crtc_state *crtc_state,
 881			    const struct intel_plane_state *plane_state)
 882{
 883	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 884
 885	if (crtc_state->do_async_flip && plane->async_flip) {
 886		intel_plane_async_flip(dsb, plane, crtc_state, plane_state, true);
 887		return;
 888	}
 889
 890	trace_intel_plane_update_arm(plane_state, crtc);
 891	plane->update_arm(dsb, plane, crtc_state, plane_state);
 892}
 893
 894void intel_plane_disable_arm(struct intel_dsb *dsb,
 895			     struct intel_plane *plane,
 896			     const struct intel_crtc_state *crtc_state)
 897{
 898	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 899
 900	trace_intel_plane_disable_arm(plane, crtc);
 901	plane->disable_arm(dsb, plane, crtc_state);
 902}
 903
 904void intel_crtc_planes_update_noarm(struct intel_dsb *dsb,
 905				    struct intel_atomic_state *state,
 906				    struct intel_crtc *crtc)
 907{
 908	struct intel_crtc_state *new_crtc_state =
 909		intel_atomic_get_new_crtc_state(state, crtc);
 910	u32 update_mask = new_crtc_state->update_planes;
 911	struct intel_plane_state *new_plane_state;
 912	struct intel_plane *plane;
 913	int i;
 914
 915	if (new_crtc_state->do_async_flip)
 916		return;
 917
 918	/*
 919	 * Since we only write non-arming registers here,
 920	 * the order does not matter even for skl+.
 921	 */
 922	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
 923		if (crtc->pipe != plane->pipe ||
 924		    !(update_mask & BIT(plane->id)))
 925			continue;
 926
 927		/* TODO: for mailbox updates this should be skipped */
 928		if (new_plane_state->uapi.visible ||
 929		    new_plane_state->is_y_plane)
 930			intel_plane_update_noarm(dsb, plane,
 931						 new_crtc_state, new_plane_state);
 932	}
 933}
 934
 935static void skl_crtc_planes_update_arm(struct intel_dsb *dsb,
 936				       struct intel_atomic_state *state,
 937				       struct intel_crtc *crtc)
 938{
 939	struct intel_crtc_state *old_crtc_state =
 940		intel_atomic_get_old_crtc_state(state, crtc);
 941	struct intel_crtc_state *new_crtc_state =
 942		intel_atomic_get_new_crtc_state(state, crtc);
 943	struct skl_ddb_entry ddb[I915_MAX_PLANES];
 944	struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
 945	u32 update_mask = new_crtc_state->update_planes;
 946	struct intel_plane *plane;
 947
 948	memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,
 949	       sizeof(old_crtc_state->wm.skl.plane_ddb));
 950	memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,
 951	       sizeof(old_crtc_state->wm.skl.plane_ddb_y));
 952
 953	while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {
 954		struct intel_plane_state *new_plane_state =
 955			intel_atomic_get_new_plane_state(state, plane);
 956
 957		/*
 958		 * TODO: for mailbox updates intel_plane_update_noarm()
 959		 * would have to be called here as well.
 960		 */
 961		if (new_plane_state->uapi.visible ||
 962		    new_plane_state->is_y_plane)
 963			intel_plane_update_arm(dsb, plane, new_crtc_state, new_plane_state);
 964		else
 965			intel_plane_disable_arm(dsb, plane, new_crtc_state);
 966	}
 967}
 968
 969static void i9xx_crtc_planes_update_arm(struct intel_dsb *dsb,
 970					struct intel_atomic_state *state,
 971					struct intel_crtc *crtc)
 972{
 973	struct intel_crtc_state *new_crtc_state =
 974		intel_atomic_get_new_crtc_state(state, crtc);
 975	u32 update_mask = new_crtc_state->update_planes;
 976	struct intel_plane_state *new_plane_state;
 977	struct intel_plane *plane;
 978	int i;
 979
 980	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
 981		if (crtc->pipe != plane->pipe ||
 982		    !(update_mask & BIT(plane->id)))
 983			continue;
 984
 985		/*
 986		 * TODO: for mailbox updates intel_plane_update_noarm()
 987		 * would have to be called here as well.
 988		 */
 989		if (new_plane_state->uapi.visible)
 990			intel_plane_update_arm(dsb, plane, new_crtc_state, new_plane_state);
 991		else
 992			intel_plane_disable_arm(dsb, plane, new_crtc_state);
 993	}
 994}
 995
 996void intel_crtc_planes_update_arm(struct intel_dsb *dsb,
 997				  struct intel_atomic_state *state,
 998				  struct intel_crtc *crtc)
 999{
1000	struct intel_display *display = to_intel_display(state);
1001
1002	if (DISPLAY_VER(display) >= 9)
1003		skl_crtc_planes_update_arm(dsb, state, crtc);
1004	else
1005		i9xx_crtc_planes_update_arm(dsb, state, crtc);
1006}
1007
1008int intel_plane_check_clipping(struct intel_plane_state *plane_state,
1009			       struct intel_crtc_state *crtc_state,
1010			       int min_scale, int max_scale,
1011			       bool can_position)
1012{
1013	struct intel_display *display = to_intel_display(plane_state);
1014	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1015	struct drm_framebuffer *fb = plane_state->hw.fb;
1016	struct drm_rect *src = &plane_state->uapi.src;
1017	struct drm_rect *dst = &plane_state->uapi.dst;
1018	const struct drm_rect *clip = &crtc_state->pipe_src;
1019	unsigned int rotation = plane_state->hw.rotation;
1020	int hscale, vscale;
1021
1022	if (!fb) {
1023		plane_state->uapi.visible = false;
1024		return 0;
1025	}
1026
1027	drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
1028
1029	/* Check scaling */
1030	hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
1031	vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
1032	if (hscale < 0 || vscale < 0) {
1033		drm_dbg_kms(display->drm,
1034			    "[PLANE:%d:%s] invalid scaling "DRM_RECT_FP_FMT " -> " DRM_RECT_FMT "\n",
1035			    plane->base.base.id, plane->base.name,
1036			    DRM_RECT_FP_ARG(src), DRM_RECT_ARG(dst));
1037		return -ERANGE;
1038	}
1039
1040	/*
1041	 * FIXME: This might need further adjustment for seamless scaling
1042	 * with phase information, for the 2p2 and 2p1 scenarios.
1043	 */
1044	plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, clip);
1045
1046	drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
1047
1048	if (!can_position && plane_state->uapi.visible &&
1049	    !drm_rect_equals(dst, clip)) {
1050		drm_dbg_kms(display->drm,
1051			    "[PLANE:%d:%s] plane (" DRM_RECT_FMT ") must cover entire CRTC (" DRM_RECT_FMT ")\n",
1052			    plane->base.base.id, plane->base.name,
1053			    DRM_RECT_ARG(dst), DRM_RECT_ARG(clip));
1054		return -EINVAL;
1055	}
1056
1057	/* final plane coordinates will be relative to the plane's pipe */
1058	drm_rect_translate(dst, -clip->x1, -clip->y1);
1059
1060	return 0;
1061}
1062
1063int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
1064{
1065	struct intel_display *display = to_intel_display(plane_state);
1066	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1067	const struct drm_framebuffer *fb = plane_state->hw.fb;
1068	struct drm_rect *src = &plane_state->uapi.src;
1069	u32 src_x, src_y, src_w, src_h, hsub, vsub;
1070	bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);
1071
1072	/*
1073	 * FIXME hsub/vsub vs. block size is a mess. Pre-tgl CCS
1074	 * abuses hsub/vsub so we can't use them here. But as they
1075	 * are limited to 32bpp RGB formats we don't actually need
1076	 * to check anything.
1077	 */
1078	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
1079	    fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)
1080		return 0;
1081
1082	/*
1083	 * Hardware doesn't handle subpixel coordinates.
1084	 * Adjust to (macro)pixel boundary, but be careful not to
1085	 * increase the source viewport size, because that could
1086	 * push the downscaling factor out of bounds.
1087	 */
1088	src_x = src->x1 >> 16;
1089	src_w = drm_rect_width(src) >> 16;
1090	src_y = src->y1 >> 16;
1091	src_h = drm_rect_height(src) >> 16;
1092
1093	drm_rect_init(src, src_x << 16, src_y << 16,
1094		      src_w << 16, src_h << 16);
1095
1096	if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
1097		hsub = 2;
1098		vsub = 2;
1099	} else if (DISPLAY_VER(display) >= 20 &&
1100		   intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
1101		/*
1102		 * This allows NV12 and P0xx formats to have odd size and/or odd
1103		 * source coordinates on DISPLAY_VER(display) >= 20
1104		 */
1105		hsub = 1;
1106		vsub = 1;
1107
1108		/* Wa_16023981245 */
1109		if ((DISPLAY_VERx100(display) == 2000 ||
1110		     DISPLAY_VERx100(display) == 3000 ||
1111		     DISPLAY_VERx100(display) == 3002) &&
1112		     src_x % 2 != 0)
1113			hsub = 2;
1114
1115		if (DISPLAY_VER(display) == 35)
1116			vsub = 2;
1117	} else {
1118		hsub = fb->format->hsub;
1119		vsub = fb->format->vsub;
1120	}
1121
1122	if (rotated)
1123		hsub = vsub = max(hsub, vsub);
1124
1125	if (src_x % hsub || src_w % hsub) {
1126		drm_dbg_kms(display->drm,
1127			    "[PLANE:%d:%s] src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",
1128			    plane->base.base.id, plane->base.name,
1129			    src_x, src_w, hsub, str_yes_no(rotated));
1130		return -EINVAL;
1131	}
1132
1133	if (src_y % vsub || src_h % vsub) {
1134		drm_dbg_kms(display->drm,
1135			    "[PLANE:%d:%s] src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",
1136			    plane->base.base.id, plane->base.name,
1137			    src_y, src_h, vsub, str_yes_no(rotated));
1138		return -EINVAL;
1139	}
1140
1141	return 0;
1142}
1143
1144static int add_dma_resv_fences(struct dma_resv *resv,
1145			       struct drm_plane_state *new_plane_state)
1146{
1147	struct dma_fence *fence = dma_fence_get(new_plane_state->fence);
1148	struct dma_fence *new;
1149	int ret;
1150
1151	ret = dma_resv_get_singleton(resv, dma_resv_usage_rw(false), &new);
1152	if (ret)
1153		goto error;
1154
1155	if (new && fence) {
1156		struct dma_fence_chain *chain = dma_fence_chain_alloc();
1157
1158		if (!chain) {
1159			ret = -ENOMEM;
1160			goto error;
1161		}
1162
1163		dma_fence_chain_init(chain, fence, new, 1);
1164		fence = &chain->base;
1165
1166	} else if (new) {
1167		fence = new;
1168	}
1169
1170	dma_fence_put(new_plane_state->fence);
1171	new_plane_state->fence = fence;
1172	return 0;
1173
1174error:
1175	dma_fence_put(fence);
1176	return ret;
1177}
1178
1179/**
1180 * intel_prepare_plane_fb - Prepare fb for usage on plane
1181 * @_plane: drm plane to prepare for
1182 * @_new_plane_state: the plane state being prepared
1183 *
1184 * Prepares a framebuffer for usage on a display plane.  Generally this
1185 * involves pinning the underlying object and updating the frontbuffer tracking
1186 * bits.  Some older platforms need special physical address handling for
1187 * cursor planes.
1188 *
1189 * Returns 0 on success, negative error code on failure.
1190 */
1191static int
1192intel_prepare_plane_fb(struct drm_plane *_plane,
1193		       struct drm_plane_state *_new_plane_state)
1194{
1195	struct intel_plane *plane = to_intel_plane(_plane);
1196	struct intel_display *display = to_intel_display(plane);
1197	struct intel_plane_state *new_plane_state =
1198		to_intel_plane_state(_new_plane_state);
1199	struct intel_atomic_state *state =
1200		to_intel_atomic_state(new_plane_state->uapi.state);
1201	struct intel_plane_state *old_plane_state =
1202		intel_atomic_get_old_plane_state(state, plane);
1203	struct drm_gem_object *obj = intel_fb_bo(new_plane_state->hw.fb);
1204	struct drm_gem_object *old_obj = intel_fb_bo(old_plane_state->hw.fb);
1205	int ret;
1206
1207	if (old_obj) {
1208		const struct intel_crtc_state *new_crtc_state =
1209			intel_atomic_get_new_crtc_state(state,
1210							to_intel_crtc(old_plane_state->hw.crtc));
1211
1212		/* Big Hammer, we also need to ensure that any pending
1213		 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1214		 * current scanout is retired before unpinning the old
1215		 * framebuffer. Note that we rely on userspace rendering
1216		 * into the buffer attached to the pipe they are waiting
1217		 * on. If not, userspace generates a GPU hang with IPEHR
1218		 * point to the MI_WAIT_FOR_EVENT.
1219		 *
1220		 * This should only fail upon a hung GPU, in which case we
1221		 * can safely continue.
1222		 */
1223		if (intel_crtc_needs_modeset(new_crtc_state)) {
1224			ret = add_dma_resv_fences(old_obj->resv,
1225						  &new_plane_state->uapi);
1226			if (ret < 0)
1227				return ret;
1228		}
1229	}
1230
1231	if (!obj)
1232		return 0;
1233
1234	ret = intel_plane_pin_fb(new_plane_state, old_plane_state);
1235	if (ret)
1236		return ret;
1237
1238	ret = drm_gem_plane_helper_prepare_fb(&plane->base, &new_plane_state->uapi);
1239	if (ret < 0)
1240		goto unpin_fb;
1241
1242	if (new_plane_state->uapi.fence) {
1243		i915_gem_fence_wait_priority_display(new_plane_state->uapi.fence);
1244
1245		intel_display_rps_boost_after_vblank(new_plane_state->hw.crtc,
1246						     new_plane_state->uapi.fence);
1247	}
1248
1249	/*
1250	 * We declare pageflips to be interactive and so merit a small bias
1251	 * towards upclocking to deliver the frame on time. By only changing
1252	 * the RPS thresholds to sample more regularly and aim for higher
1253	 * clocks we can hopefully deliver low power workloads (like kodi)
1254	 * that are not quite steady state without resorting to forcing
1255	 * maximum clocks following a vblank miss (see do_rps_boost()).
1256	 */
1257	intel_display_rps_mark_interactive(display, state, true);
1258
1259	return 0;
1260
1261unpin_fb:
1262	intel_plane_unpin_fb(new_plane_state);
1263
1264	return ret;
1265}
1266
1267/**
1268 * intel_cleanup_plane_fb - Cleans up an fb after plane use
1269 * @plane: drm plane to clean up for
1270 * @_old_plane_state: the state from the previous modeset
1271 *
1272 * Cleans up a framebuffer that has just been removed from a plane.
1273 */
1274static void
1275intel_cleanup_plane_fb(struct drm_plane *plane,
1276		       struct drm_plane_state *_old_plane_state)
1277{
1278	struct intel_display *display = to_intel_display(plane->dev);
1279	struct intel_plane_state *old_plane_state =
1280		to_intel_plane_state(_old_plane_state);
1281	struct intel_atomic_state *state =
1282		to_intel_atomic_state(old_plane_state->uapi.state);
1283	struct drm_gem_object *obj = intel_fb_bo(old_plane_state->hw.fb);
1284
1285	if (!obj)
1286		return;
1287
1288	intel_display_rps_mark_interactive(display, state, false);
1289
1290	intel_plane_unpin_fb(old_plane_state);
1291}
1292
1293/* Handle Y-tiling, only if DPT is enabled (otherwise disabling tiling is easier)
1294 * All DPT hardware have 128-bytes width tiling, so Y-tile dimension is 32x32
1295 * pixels for 32bits pixels.
1296 */
1297#define YTILE_WIDTH	32
1298#define YTILE_HEIGHT	32
1299#define YTILE_SIZE (YTILE_WIDTH * YTILE_HEIGHT * 4)
1300
1301static unsigned int intel_ytile_get_offset(unsigned int width, unsigned int x, unsigned int y)
1302{
1303	u32 offset;
1304	unsigned int swizzle;
1305	unsigned int width_in_blocks = DIV_ROUND_UP(width, 32);
1306
1307	/* Block offset */
1308	offset = ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * YTILE_SIZE;
1309
1310	x = x % YTILE_WIDTH;
1311	y = y % YTILE_HEIGHT;
1312
1313	/* bit order inside a block is x4 x3 x2 y4 y3 y2 y1 y0 x1 x0 */
1314	swizzle = (x & 3) | ((y & 0x1f) << 2) | ((x & 0x1c) << 5);
1315	offset += swizzle * 4;
1316	return offset;
1317}
1318
1319static unsigned int intel_4tile_get_offset(unsigned int width, unsigned int x, unsigned int y)
1320{
1321	u32 offset;
1322	unsigned int swizzle;
1323	unsigned int width_in_blocks = DIV_ROUND_UP(width, 32);
1324
1325	/* Block offset */
1326	offset = ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * YTILE_SIZE;
1327
1328	x = x % YTILE_WIDTH;
1329	y = y % YTILE_HEIGHT;
1330
1331	/* bit order inside a block is y4 y3 x4 y2 x3 x2 y1 y0 x1 x0 */
1332	swizzle = (x & 3) | ((y & 3) << 2) | ((x & 0xc) << 2) | (y & 4) << 4 |
1333		  ((x & 0x10) << 3) | ((y & 0x18) << 5);
1334	offset += swizzle * 4;
1335	return offset;
1336}
1337
1338static void intel_panic_flush(struct drm_plane *plane)
1339{
1340	struct intel_plane_state *plane_state = to_intel_plane_state(plane->state);
1341	struct intel_crtc_state *crtc_state = to_intel_crtc_state(plane->state->crtc->state);
1342	struct intel_plane *iplane = to_intel_plane(plane);
1343	struct intel_display *display = to_intel_display(iplane);
1344	struct drm_framebuffer *fb = plane_state->hw.fb;
1345	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1346
1347	intel_panic_finish(intel_fb->panic);
1348
1349	if (crtc_state->enable_psr2_sel_fetch) {
1350		/* Force a full update for psr2 */
1351		intel_psr2_panic_force_full_update(display, crtc_state);
1352	}
1353
1354	/* Flush the cache and don't disable tiling if it's the fbdev framebuffer.*/
1355	if (intel_fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) {
1356		struct iosys_map map;
1357
1358		intel_fbdev_get_map(display->fbdev.fbdev, &map);
1359		drm_clflush_virt_range(map.vaddr, fb->pitches[0] * fb->height);
1360		return;
1361	}
1362
1363	if (fb->modifier && iplane->disable_tiling)
1364		iplane->disable_tiling(iplane);
1365}
1366
1367static unsigned int (*intel_get_tiling_func(u64 fb_modifier))(unsigned int width,
1368							      unsigned int x,
1369							      unsigned int y)
1370{
1371	switch (fb_modifier) {
1372	case I915_FORMAT_MOD_Y_TILED:
1373	case I915_FORMAT_MOD_Y_TILED_CCS:
1374	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
1375	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
1376	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
1377		return intel_ytile_get_offset;
1378	case I915_FORMAT_MOD_4_TILED:
1379	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
1380	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
1381	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
1382	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
1383	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
1384	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
1385	case I915_FORMAT_MOD_4_TILED_BMG_CCS:
1386	case I915_FORMAT_MOD_4_TILED_LNL_CCS:
1387		return intel_4tile_get_offset;
1388	case I915_FORMAT_MOD_X_TILED:
1389	case I915_FORMAT_MOD_Yf_TILED:
1390	case I915_FORMAT_MOD_Yf_TILED_CCS:
1391	default:
1392	/* Not supported yet */
1393		return NULL;
1394	}
1395}
1396
1397static int intel_get_scanout_buffer(struct drm_plane *plane,
1398				    struct drm_scanout_buffer *sb)
1399{
1400	struct intel_plane_state *plane_state;
1401	struct drm_gem_object *obj;
1402	struct drm_framebuffer *fb;
1403	struct intel_framebuffer *intel_fb;
1404	struct intel_display *display = to_intel_display(plane->dev);
1405
1406	if (!plane->state || !plane->state->fb || !plane->state->visible)
1407		return -ENODEV;
1408
1409	plane_state = to_intel_plane_state(plane->state);
1410	fb = plane_state->hw.fb;
1411	intel_fb = to_intel_framebuffer(fb);
1412
1413	obj = intel_fb_bo(fb);
1414	if (!obj)
1415		return -ENODEV;
1416
1417	if (intel_fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) {
1418		intel_fbdev_get_map(display->fbdev.fbdev, &sb->map[0]);
1419	} else {
1420		int ret;
1421		/* Can't disable tiling if DPT is in use */
1422		if (intel_fb_uses_dpt(fb)) {
1423			if (fb->format->cpp[0] != 4)
1424				return -EOPNOTSUPP;
1425			intel_fb->panic_tiling = intel_get_tiling_func(fb->modifier);
1426			if (!intel_fb->panic_tiling)
1427				return -EOPNOTSUPP;
1428		}
1429		sb->private = intel_fb;
1430		ret = intel_panic_setup(intel_fb->panic, sb);
1431		if (ret)
1432			return ret;
1433	}
1434	sb->width = fb->width;
1435	sb->height = fb->height;
1436	/* Use the generic linear format, because tiling, RC, CCS, CC
1437	 * will be disabled in disable_tiling()
1438	 */
1439	sb->format = drm_format_info(fb->format->format);
1440	sb->pitch[0] = fb->pitches[0];
1441
1442	return 0;
1443}
1444
1445static const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
1446	.prepare_fb = intel_prepare_plane_fb,
1447	.cleanup_fb = intel_cleanup_plane_fb,
1448};
1449
1450static const struct drm_plane_helper_funcs intel_primary_plane_helper_funcs = {
1451	.prepare_fb = intel_prepare_plane_fb,
1452	.cleanup_fb = intel_cleanup_plane_fb,
1453	.get_scanout_buffer = intel_get_scanout_buffer,
1454	.panic_flush = intel_panic_flush,
1455};
1456
1457void intel_plane_helper_add(struct intel_plane *plane)
1458{
1459	if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1460		drm_plane_helper_add(&plane->base, &intel_primary_plane_helper_funcs);
1461	else
1462		drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
1463}
1464
1465void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_plane_state,
1466					 struct intel_plane_state *new_plane_state)
1467{
1468	if (!old_plane_state->ggtt_vma ||
1469	    old_plane_state->ggtt_vma == new_plane_state->ggtt_vma)
1470		return;
1471
1472	drm_vblank_work_init(&old_plane_state->unpin_work, old_plane_state->uapi.crtc,
1473			     intel_cursor_unpin_work);
1474}
1475
1476static void link_nv12_planes(struct intel_crtc_state *crtc_state,
1477			     struct intel_plane_state *uv_plane_state,
1478			     struct intel_plane_state *y_plane_state)
1479{
1480	struct intel_display *display = to_intel_display(uv_plane_state);
1481	struct intel_plane *uv_plane = to_intel_plane(uv_plane_state->uapi.plane);
1482	struct intel_plane *y_plane = to_intel_plane(y_plane_state->uapi.plane);
1483
1484	drm_dbg_kms(display->drm, "UV plane [PLANE:%d:%s] using Y plane [PLANE:%d:%s]\n",
1485		    uv_plane->base.base.id, uv_plane->base.name,
1486		    y_plane->base.base.id, y_plane->base.name);
1487
1488	uv_plane_state->planar_linked_plane = y_plane;
1489
1490	y_plane_state->is_y_plane = true;
1491	y_plane_state->planar_linked_plane = uv_plane;
1492
1493	crtc_state->enabled_planes |= BIT(y_plane->id);
1494	crtc_state->active_planes |= BIT(y_plane->id);
1495	crtc_state->update_planes |= BIT(y_plane->id);
1496
1497	crtc_state->data_rate[y_plane->id] = crtc_state->data_rate_y[uv_plane->id];
1498	crtc_state->rel_data_rate[y_plane->id] = crtc_state->rel_data_rate_y[uv_plane->id];
1499
1500	/* Copy parameters to Y plane */
1501	intel_plane_copy_hw_state(y_plane_state, uv_plane_state);
1502	y_plane_state->uapi.src = uv_plane_state->uapi.src;
1503	y_plane_state->uapi.dst = uv_plane_state->uapi.dst;
1504
1505	y_plane_state->ctl = uv_plane_state->ctl;
1506	y_plane_state->color_ctl = uv_plane_state->color_ctl;
1507	y_plane_state->view = uv_plane_state->view;
1508	y_plane_state->decrypt = uv_plane_state->decrypt;
1509
1510	icl_link_nv12_planes(uv_plane_state, y_plane_state);
1511}
1512
1513static void unlink_nv12_plane(struct intel_crtc_state *crtc_state,
1514			      struct intel_plane_state *plane_state)
1515{
1516	struct intel_display *display = to_intel_display(plane_state);
1517	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1518
1519	if (!plane_state->planar_linked_plane)
1520		return;
1521
1522	plane_state->planar_linked_plane = NULL;
1523
1524	if (!plane_state->is_y_plane)
1525		return;
1526
1527	drm_WARN_ON(display->drm, plane_state->uapi.visible);
1528
1529	plane_state->is_y_plane = false;
1530
1531	crtc_state->enabled_planes &= ~BIT(plane->id);
1532	crtc_state->active_planes &= ~BIT(plane->id);
1533	crtc_state->update_planes |= BIT(plane->id);
1534	crtc_state->data_rate[plane->id] = 0;
1535	crtc_state->rel_data_rate[plane->id] = 0;
1536}
1537
1538static int icl_check_nv12_planes(struct intel_atomic_state *state,
1539				 struct intel_crtc *crtc)
1540{
1541	struct intel_display *display = to_intel_display(state);
1542	struct intel_crtc_state *crtc_state =
1543		intel_atomic_get_new_crtc_state(state, crtc);
1544	struct intel_plane_state *plane_state;
1545	struct intel_plane *plane;
1546	int i;
1547
1548	if (DISPLAY_VER(display) < 11)
1549		return 0;
1550
1551	/*
1552	 * Destroy all old plane links and make the Y plane invisible
1553	 * in the crtc_state->active_planes mask.
1554	 */
1555	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1556		if (plane->pipe != crtc->pipe)
1557			continue;
1558
1559		unlink_nv12_plane(crtc_state, plane_state);
1560	}
1561
1562	if (!crtc_state->nv12_planes)
1563		return 0;
1564
1565	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1566		struct intel_plane_state *y_plane_state = NULL;
1567		struct intel_plane *y_plane;
1568
1569		if (plane->pipe != crtc->pipe)
1570			continue;
1571
1572		if ((crtc_state->nv12_planes & BIT(plane->id)) == 0)
1573			continue;
1574
1575		for_each_intel_plane_on_crtc(display->drm, crtc, y_plane) {
1576			if (!icl_is_nv12_y_plane(display, y_plane->id))
1577				continue;
1578
1579			if (crtc_state->active_planes & BIT(y_plane->id))
1580				continue;
1581
1582			y_plane_state = intel_atomic_get_plane_state(state, y_plane);
1583			if (IS_ERR(y_plane_state))
1584				return PTR_ERR(y_plane_state);
1585
1586			break;
1587		}
1588
1589		if (!y_plane_state) {
1590			drm_dbg_kms(display->drm,
1591				    "[CRTC:%d:%s] need %d free Y planes for planar YUV\n",
1592				    crtc->base.base.id, crtc->base.name,
1593				    hweight8(crtc_state->nv12_planes));
1594			return -EINVAL;
1595		}
1596
1597		link_nv12_planes(crtc_state, plane_state, y_plane_state);
1598	}
1599
1600	return 0;
1601}
1602
1603static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
1604					  struct intel_crtc *crtc,
1605					  u8 plane_ids_mask)
1606{
1607	struct intel_display *display = to_intel_display(state);
1608	struct intel_plane *plane;
1609
1610	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
1611		struct intel_plane_state *plane_state;
1612
1613		if ((plane_ids_mask & BIT(plane->id)) == 0)
1614			continue;
1615
1616		plane_state = intel_atomic_get_plane_state(state, plane);
1617		if (IS_ERR(plane_state))
1618			return PTR_ERR(plane_state);
1619	}
1620
1621	return 0;
1622}
1623
1624int intel_plane_add_affected(struct intel_atomic_state *state,
1625			     struct intel_crtc *crtc)
1626{
1627	const struct intel_crtc_state *old_crtc_state =
1628		intel_atomic_get_old_crtc_state(state, crtc);
1629	const struct intel_crtc_state *new_crtc_state =
1630		intel_atomic_get_new_crtc_state(state, crtc);
1631
1632	return intel_crtc_add_planes_to_state(state, crtc,
1633					      old_crtc_state->enabled_planes |
1634					      new_crtc_state->enabled_planes);
1635}
1636
1637static bool active_planes_affects_min_cdclk(struct intel_display *display)
1638{
1639	/* See {hsw,vlv,ivb}_plane_ratio() */
1640	return display->platform.broadwell || display->platform.haswell ||
1641		display->platform.cherryview || display->platform.valleyview ||
1642		display->platform.ivybridge;
1643}
1644
1645static u8 intel_joiner_affected_planes(struct intel_atomic_state *state,
1646				       u8 joined_pipes)
1647{
1648	const struct intel_plane_state *plane_state;
1649	struct intel_plane *plane;
1650	u8 affected_planes = 0;
1651	int i;
1652
1653	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1654		struct intel_plane *linked = plane_state->planar_linked_plane;
1655
1656		if ((joined_pipes & BIT(plane->pipe)) == 0)
1657			continue;
1658
1659		affected_planes |= BIT(plane->id);
1660		if (linked)
1661			affected_planes |= BIT(linked->id);
1662	}
1663
1664	return affected_planes;
1665}
1666
1667static int intel_joiner_add_affected_planes(struct intel_atomic_state *state,
1668					    u8 joined_pipes)
1669{
1670	u8 prev_affected_planes, affected_planes = 0;
1671
1672	/*
1673	 * We want all the joined pipes to have the same
1674	 * set of planes in the atomic state, to make sure
1675	 * state copying always works correctly, and the
1676	 * UV<->Y plane linkage is always up to date.
1677	 * Keep pulling planes in until we've determined
1678	 * the full set of affected planes. A bit complicated
1679	 * on account of each pipe being capable of selecting
1680	 * their own Y planes independently of the other pipes,
1681	 * and the selection being done from the set of
1682	 * inactive planes.
1683	 */
1684	do {
1685		struct intel_crtc *crtc;
1686
1687		for_each_intel_crtc_in_pipe_mask(state->base.dev, crtc, joined_pipes) {
1688			int ret;
1689
1690			ret = intel_crtc_add_planes_to_state(state, crtc, affected_planes);
1691			if (ret)
1692				return ret;
1693		}
1694
1695		prev_affected_planes = affected_planes;
1696		affected_planes = intel_joiner_affected_planes(state, joined_pipes);
1697	} while (affected_planes != prev_affected_planes);
1698
1699	return 0;
1700}
1701
1702static int intel_add_affected_planes(struct intel_atomic_state *state)
1703{
1704	const struct intel_crtc_state *crtc_state;
1705	struct intel_crtc *crtc;
1706	int i;
1707
1708	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
1709		int ret;
1710
1711		ret = intel_joiner_add_affected_planes(state, intel_crtc_joined_pipe_mask(crtc_state));
1712		if (ret)
1713			return ret;
1714	}
1715
1716	return 0;
1717}
1718
1719int intel_plane_atomic_check(struct intel_atomic_state *state)
1720{
1721	struct intel_display *display = to_intel_display(state);
1722	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
1723	struct intel_plane_state __maybe_unused *plane_state;
1724	struct intel_plane *plane;
1725	struct intel_crtc *crtc;
1726	int i, ret;
1727
1728	ret = intel_add_affected_planes(state);
1729	if (ret)
1730		return ret;
1731
1732	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1733		ret = plane_atomic_check(state, plane);
1734		if (ret) {
1735			drm_dbg_atomic(display->drm,
1736				       "[PLANE:%d:%s] atomic driver check failed\n",
1737				       plane->base.base.id, plane->base.name);
1738			return ret;
1739		}
1740	}
1741
1742	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
1743					    new_crtc_state, i) {
1744		u8 old_active_planes, new_active_planes;
1745
1746		ret = icl_check_nv12_planes(state, crtc);
1747		if (ret)
1748			return ret;
1749
1750		/*
1751		 * On some platforms the number of active planes affects
1752		 * the planes' minimum cdclk calculation. Add such planes
1753		 * to the state before we compute the minimum cdclk.
1754		 */
1755		if (!active_planes_affects_min_cdclk(display))
1756			continue;
1757
1758		old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1759		new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1760
1761		if (hweight8(old_active_planes) == hweight8(new_active_planes))
1762			continue;
1763
1764		ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
1765		if (ret)
1766			return ret;
1767	}
1768
1769	for_each_new_intel_plane_in_state(state, plane, plane_state, i)
1770		intel_plane_calc_min_cdclk(state, plane);
1771
1772	return 0;
1773}