intel_pipe_crc_regs.h

  1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2024 Intel Corporation
  4 */
  5
  6#ifndef __INTEL_PIPE_CRC_REGS_H__
  7#define __INTEL_PIPE_CRC_REGS_H__
  8
  9#include "intel_display_reg_defs.h"
 10
 11#define _PIPE_CRC_CTL_A			0x60050
 12#define PIPE_CRC_CTL(dev_priv, pipe)		_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_CTL_A)
 13#define   PIPE_CRC_ENABLE		REG_BIT(31)
 14/* skl+ source selection */
 15#define   PIPE_CRC_SOURCE_MASK_SKL	REG_GENMASK(30, 28)
 16#define   PIPE_CRC_SOURCE_PLANE_1_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)
 17#define   PIPE_CRC_SOURCE_PLANE_2_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2)
 18#define   PIPE_CRC_SOURCE_DMUX_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4)
 19#define   PIPE_CRC_SOURCE_PLANE_3_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6)
 20#define   PIPE_CRC_SOURCE_PLANE_4_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7)
 21#define   PIPE_CRC_SOURCE_PLANE_5_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5)
 22#define   PIPE_CRC_SOURCE_PLANE_6_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3)
 23#define   PIPE_CRC_SOURCE_PLANE_7_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1)
 24/* ivb+ source selection */
 25#define   PIPE_CRC_SOURCE_MASK_IVB	REG_GENMASK(30, 29)
 26#define   PIPE_CRC_SOURCE_PRIMARY_IVB	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)
 27#define   PIPE_CRC_SOURCE_SPRITE_IVB	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1)
 28#define   PIPE_CRC_SOURCE_PF_IVB	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2)
 29/* ilk+ source selection */
 30#define   PIPE_CRC_SOURCE_MASK_ILK	REG_GENMASK(30, 28)
 31#define   PIPE_CRC_SOURCE_PRIMARY_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)
 32#define   PIPE_CRC_SOURCE_SPRITE_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1)
 33#define   PIPE_CRC_SOURCE_PIPE_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2)
 34/* embedded DP port on the north display block */
 35#define   PIPE_CRC_SOURCE_PORT_A_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4)
 36#define   PIPE_CRC_SOURCE_FDI_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5)
 37/* vlv source selection */
 38#define   PIPE_CRC_SOURCE_MASK_VLV	REG_GENMASK(30, 27)
 39#define   PIPE_CRC_SOURCE_PIPE_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)
 40#define   PIPE_CRC_SOURCE_HDMIB_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1)
 41#define   PIPE_CRC_SOURCE_HDMIC_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2)
 42/* with DP port the pipe source is invalid */
 43#define   PIPE_CRC_SOURCE_DP_D_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3)
 44#define   PIPE_CRC_SOURCE_DP_B_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6)
 45#define   PIPE_CRC_SOURCE_DP_C_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7)
 46/* gen3+ source selection */
 47#define   PIPE_CRC_SOURCE_MASK_I9XX	REG_GENMASK(30, 28)
 48#define   PIPE_CRC_SOURCE_PIPE_I9XX	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)
 49#define   PIPE_CRC_SOURCE_SDVOB_I9XX	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1)
 50#define   PIPE_CRC_SOURCE_SDVOC_I9XX	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2)
 51/* with DP/TV port the pipe source is invalid */
 52#define   PIPE_CRC_SOURCE_DP_D_G4X	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3)
 53#define   PIPE_CRC_SOURCE_TV_PRE	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4)
 54#define   PIPE_CRC_SOURCE_TV_POST	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5)
 55#define   PIPE_CRC_SOURCE_DP_B_G4X	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6)
 56#define   PIPE_CRC_SOURCE_DP_C_G4X	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7)
 57/* gen2 doesn't have source selection bits */
 58#define   PIPE_CRC_INCLUDE_BORDER_I8XX	REG_BIT(30)
 59#define   PIPE_CRC_EXP_RED_MASK		REG_BIT(22, 0) /* pre-ivb */
 60#define   PIPE_CRC_EXP_1_MASK_IVB	REG_BIT(22, 0) /* ivb */
 61
 62#define _PIPE_CRC_EXP_GREEN_A		0x60054
 63#define PIPE_CRC_EXP_GREEN(dev_priv, pipe)	_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_GREEN_A)
 64#define   PIPE_CRC_EXP_GREEN_MASK	REG_BIT(22, 0) /* pre-ivb */
 65
 66#define _PIPE_CRC_EXP_BLUE_A		0x60058
 67#define PIPE_CRC_EXP_BLUE(dev_priv, pipe)	_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_BLUE_A)
 68#define   PIPE_CRC_EXP_BLUE_MASK	REG_BIT(22, 0) /* pre-ivb */
 69
 70#define _PIPE_CRC_EXP_RES1_A_I915	0x6005c /* i915+ */
 71#define PIPE_CRC_EXP_RES1_I915(dev_priv, pipe)	_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES1_A_I915)
 72#define   PIPE_CRC_EXP_RES1_MASK	REG_BIT(22, 0) /* pre-ivb */
 73
 74#define _PIPE_CRC_EXP_RES2_A_G4X	0x60080 /* g4x+ */
 75#define PIPE_CRC_EXP_RES2_G4X(dev_priv, pipe)	_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES2_A_G4X)
 76#define   PIPE_CRC_EXP_RES2_MASK	REG_BIT(22, 0) /* pre-ivb */
 77
 78#define _PIPE_CRC_RES_RED_A		0x60060
 79#define PIPE_CRC_RES_RED(dev_priv, pipe)	_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RED_A)
 80
 81#define _PIPE_CRC_RES_GREEN_A		0x60064
 82#define PIPE_CRC_RES_GREEN(dev_priv, pipe)	_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_GREEN_A)
 83
 84#define _PIPE_CRC_RES_BLUE_A		0x60068
 85#define PIPE_CRC_RES_BLUE(dev_priv, pipe)	_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_BLUE_A)
 86
 87#define _PIPE_CRC_RES_RES1_A_I915	0x6006c /* i915+ */
 88#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe)	_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES1_A_I915)
 89
 90#define _PIPE_CRC_RES_RES2_A_G4X	0x60080 /* g4x+ */
 91#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)	_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES2_A_G4X)
 92
 93/* ivb */
 94#define _PIPE_CRC_EXP_2_A_IVB		0x60054
 95#define _PIPE_CRC_EXP_2_B_IVB		0x61054
 96#define PIPE_CRC_EXP_2_IVB(pipe)		_MMIO_PIPE(pipe, _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB)
 97#define   PIPE_CRC_EXP_2_MASK_IVB	REG_BIT(22, 0) /* ivb */
 98
 99/* ivb */
100#define _PIPE_CRC_EXP_3_A_IVB		0x60058
101#define _PIPE_CRC_EXP_3_B_IVB		0x61058
102#define PIPE_CRC_EXP_3_IVB(pipe)		_MMIO_PIPE(pipe, _PIPE_CRC_EXP_3_A_IVB, _PIPE_CRC_EXP_3_B_IVB)
103#define   PIPE_CRC_EXP_3_MASK_IVB	REG_BIT(22, 0) /* ivb */
104
105/* ivb */
106#define _PIPE_CRC_EXP_4_A_IVB		0x6005c
107#define _PIPE_CRC_EXP_4_B_IVB		0x6105c
108#define PIPE_CRC_EXP_4_IVB(pipe)		_MMIO_PIPE(pipe, _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB)
109#define   PIPE_CRC_EXP_4_MASK_IVB	REG_BIT(22, 0) /* ivb */
110
111/* ivb */
112#define _PIPE_CRC_EXP_5_A_IVB		0x60060
113#define _PIPE_CRC_EXP_5_B_IVB		0x61060
114#define PIPE_CRC_EXP_5_IVB(pipe)		_MMIO_PIPE(pipe, _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB)
115#define   PIPE_CRC_EXP_5_MASK_IVB	REG_BIT(22, 0) /* ivb */
116
117/* ivb */
118#define _PIPE_CRC_RES_1_A_IVB		0x60064
119#define _PIPE_CRC_RES_1_B_IVB		0x61064
120#define PIPE_CRC_RES_1_IVB(pipe)		_MMIO_PIPE((pipe), _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB)
121
122/* ivb */
123#define _PIPE_CRC_RES_2_A_IVB		0x60068
124#define _PIPE_CRC_RES_2_B_IVB		0x61068
125#define PIPE_CRC_RES_2_IVB(pipe)		_MMIO_PIPE((pipe), _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB)
126
127/* ivb */
128#define _PIPE_CRC_RES_3_A_IVB		0x6006c
129#define _PIPE_CRC_RES_3_B_IVB		0x6106c
130#define PIPE_CRC_RES_3_IVB(pipe)		_MMIO_PIPE((pipe), _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB)
131
132/* ivb */
133#define _PIPE_CRC_RES_4_A_IVB		0x60070
134#define _PIPE_CRC_RES_4_B_IVB		0x61070
135#define PIPE_CRC_RES_4_IVB(pipe)		_MMIO_PIPE((pipe), _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB)
136
137/* ivb */
138#define _PIPE_CRC_RES_5_A_IVB		0x60074
139#define _PIPE_CRC_RES_5_B_IVB		0x61074
140#define PIPE_CRC_RES_5_IVB(pipe)		_MMIO_PIPE((pipe), _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
141
142/* hsw+ */
143#define _PIPE_CRC_EXP_A_HSW		0x60054
144#define _PIPE_CRC_EXP_B_HSW		0x61054
145#define PIPE_CRC_EXP_HSW(pipe)			_MMIO_PIPE((pipe), _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW)
146
147/* hsw+ */
148#define _PIPE_CRC_RES_A_HSW		0x60064
149#define _PIPE_CRC_RES_B_HSW		0x61064
150#define PIPE_CRC_RES_HSW(pipe)			_MMIO_PIPE((pipe), _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW)
151
152#endif /* __INTEL_PIPE_CRC_REGS_H__ */