intel_pch_display.c

  1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright © 2021 Intel Corporation
  4 */
  5
  6#include <drm/drm_print.h>
  7
  8#include "g4x_dp.h"
  9#include "i915_reg.h"
 10#include "intel_crt.h"
 11#include "intel_crt_regs.h"
 12#include "intel_de.h"
 13#include "intel_display_regs.h"
 14#include "intel_display_types.h"
 15#include "intel_dpll.h"
 16#include "intel_fdi.h"
 17#include "intel_fdi_regs.h"
 18#include "intel_lvds.h"
 19#include "intel_lvds_regs.h"
 20#include "intel_pch_display.h"
 21#include "intel_pch_refclk.h"
 22#include "intel_pps.h"
 23#include "intel_sdvo.h"
 24
 25bool intel_has_pch_trancoder(struct intel_display *display,
 26			     enum pipe pch_transcoder)
 27{
 28	return HAS_PCH_IBX(display) || HAS_PCH_CPT(display) ||
 29		(HAS_PCH_LPT_H(display) && pch_transcoder == PIPE_A);
 30}
 31
 32enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
 33{
 34	struct intel_display *display = to_intel_display(crtc);
 35
 36	if (HAS_PCH_LPT(display))
 37		return PIPE_A;
 38	else
 39		return crtc->pipe;
 40}
 41
 42static void assert_pch_dp_disabled(struct intel_display *display,
 43				   enum pipe pipe, enum port port,
 44				   i915_reg_t dp_reg)
 45{
 46	enum pipe port_pipe;
 47	bool state;
 48
 49	state = g4x_dp_port_enabled(display, dp_reg, port, &port_pipe);
 50
 51	INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
 52				 "PCH DP %c enabled on transcoder %c, should be disabled\n",
 53				 port_name(port), pipe_name(pipe));
 54
 55	INTEL_DISPLAY_STATE_WARN(display,
 56				 HAS_PCH_IBX(display) && !state && port_pipe == PIPE_B,
 57				 "IBX PCH DP %c still using transcoder B\n",
 58				 port_name(port));
 59}
 60
 61static void assert_pch_hdmi_disabled(struct intel_display *display,
 62				     enum pipe pipe, enum port port,
 63				     i915_reg_t hdmi_reg)
 64{
 65	enum pipe port_pipe;
 66	bool state;
 67
 68	state = intel_sdvo_port_enabled(display, hdmi_reg, &port_pipe);
 69
 70	INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
 71				 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
 72				 port_name(port), pipe_name(pipe));
 73
 74	INTEL_DISPLAY_STATE_WARN(display,
 75				 HAS_PCH_IBX(display) && !state && port_pipe == PIPE_B,
 76				 "IBX PCH HDMI %c still using transcoder B\n",
 77				 port_name(port));
 78}
 79
 80static void assert_pch_ports_disabled(struct intel_display *display,
 81				      enum pipe pipe)
 82{
 83	enum pipe port_pipe;
 84
 85	assert_pch_dp_disabled(display, pipe, PORT_B, PCH_DP_B);
 86	assert_pch_dp_disabled(display, pipe, PORT_C, PCH_DP_C);
 87	assert_pch_dp_disabled(display, pipe, PORT_D, PCH_DP_D);
 88
 89	INTEL_DISPLAY_STATE_WARN(display,
 90				 intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe,
 91				 "PCH VGA enabled on transcoder %c, should be disabled\n",
 92				 pipe_name(pipe));
 93
 94	INTEL_DISPLAY_STATE_WARN(display,
 95				 intel_lvds_port_enabled(display, PCH_LVDS, &port_pipe) && port_pipe == pipe,
 96				 "PCH LVDS enabled on transcoder %c, should be disabled\n",
 97				 pipe_name(pipe));
 98
 99	/* PCH SDVOB multiplex with HDMIB */
100	assert_pch_hdmi_disabled(display, pipe, PORT_B, PCH_HDMIB);
101	assert_pch_hdmi_disabled(display, pipe, PORT_C, PCH_HDMIC);
102	assert_pch_hdmi_disabled(display, pipe, PORT_D, PCH_HDMID);
103}
104
105static void assert_pch_transcoder_disabled(struct intel_display *display,
106					   enum pipe pipe)
107{
108	u32 val;
109	bool enabled;
110
111	val = intel_de_read(display, PCH_TRANSCONF(pipe));
112	enabled = !!(val & TRANS_ENABLE);
113	INTEL_DISPLAY_STATE_WARN(display, enabled,
114				 "transcoder assertion failed, should be off on pipe %c but is still active\n",
115				 pipe_name(pipe));
116}
117
118static void ibx_sanitize_pch_hdmi_port(struct intel_display *display,
119				       enum port port, i915_reg_t hdmi_reg)
120{
121	u32 val = intel_de_read(display, hdmi_reg);
122
123	if (val & SDVO_ENABLE ||
124	    (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A))
125		return;
126
127	drm_dbg_kms(display->drm,
128		    "Sanitizing transcoder select for HDMI %c\n",
129		    port_name(port));
130
131	val &= ~SDVO_PIPE_SEL_MASK;
132	val |= SDVO_PIPE_SEL(PIPE_A);
133
134	intel_de_write(display, hdmi_reg, val);
135}
136
137static void ibx_sanitize_pch_dp_port(struct intel_display *display,
138				     enum port port, i915_reg_t dp_reg)
139{
140	u32 val = intel_de_read(display, dp_reg);
141
142	if (val & DP_PORT_EN ||
143	    (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A))
144		return;
145
146	drm_dbg_kms(display->drm,
147		    "Sanitizing transcoder select for DP %c\n",
148		    port_name(port));
149
150	val &= ~DP_PIPE_SEL_MASK;
151	val |= DP_PIPE_SEL(PIPE_A);
152
153	intel_de_write(display, dp_reg, val);
154}
155
156static void ibx_sanitize_pch_ports(struct intel_display *display)
157{
158	/*
159	 * The BIOS may select transcoder B on some of the PCH
160	 * ports even it doesn't enable the port. This would trip
161	 * assert_pch_dp_disabled() and assert_pch_hdmi_disabled().
162	 * Sanitize the transcoder select bits to prevent that. We
163	 * assume that the BIOS never actually enabled the port,
164	 * because if it did we'd actually have to toggle the port
165	 * on and back off to make the transcoder A select stick
166	 * (see. intel_dp_link_down(), intel_disable_hdmi(),
167	 * intel_disable_sdvo()).
168	 */
169	ibx_sanitize_pch_dp_port(display, PORT_B, PCH_DP_B);
170	ibx_sanitize_pch_dp_port(display, PORT_C, PCH_DP_C);
171	ibx_sanitize_pch_dp_port(display, PORT_D, PCH_DP_D);
172
173	/* PCH SDVOB multiplex with HDMIB */
174	ibx_sanitize_pch_hdmi_port(display, PORT_B, PCH_HDMIB);
175	ibx_sanitize_pch_hdmi_port(display, PORT_C, PCH_HDMIC);
176	ibx_sanitize_pch_hdmi_port(display, PORT_D, PCH_HDMID);
177}
178
179static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc,
180					   const struct intel_link_m_n *m_n)
181{
182	struct intel_display *display = to_intel_display(crtc);
183	enum pipe pipe = crtc->pipe;
184
185	intel_set_m_n(display, m_n,
186		      PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
187		      PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
188}
189
190static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc,
191					   const struct intel_link_m_n *m_n)
192{
193	struct intel_display *display = to_intel_display(crtc);
194	enum pipe pipe = crtc->pipe;
195
196	intel_set_m_n(display, m_n,
197		      PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
198		      PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
199}
200
201void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc,
202				    struct intel_link_m_n *m_n)
203{
204	struct intel_display *display = to_intel_display(crtc);
205	enum pipe pipe = crtc->pipe;
206
207	intel_get_m_n(display, m_n,
208		      PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
209		      PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
210}
211
212void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc,
213				    struct intel_link_m_n *m_n)
214{
215	struct intel_display *display = to_intel_display(crtc);
216	enum pipe pipe = crtc->pipe;
217
218	intel_get_m_n(display, m_n,
219		      PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe),
220		      PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe));
221}
222
223static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state,
224					   enum pipe pch_transcoder)
225{
226	struct intel_display *display = to_intel_display(crtc_state);
227	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
228
229	intel_de_write(display, PCH_TRANS_HTOTAL(pch_transcoder),
230		       intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder)));
231	intel_de_write(display, PCH_TRANS_HBLANK(pch_transcoder),
232		       intel_de_read(display, TRANS_HBLANK(display, cpu_transcoder)));
233	intel_de_write(display, PCH_TRANS_HSYNC(pch_transcoder),
234		       intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder)));
235
236	intel_de_write(display, PCH_TRANS_VTOTAL(pch_transcoder),
237		       intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)));
238	intel_de_write(display, PCH_TRANS_VBLANK(pch_transcoder),
239		       intel_de_read(display, TRANS_VBLANK(display, cpu_transcoder)));
240	intel_de_write(display, PCH_TRANS_VSYNC(pch_transcoder),
241		       intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder)));
242	intel_de_write(display, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
243		       intel_de_read(display, TRANS_VSYNCSHIFT(display, cpu_transcoder)));
244}
245
246static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
247{
248	struct intel_display *display = to_intel_display(crtc_state);
249	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
250	enum pipe pipe = crtc->pipe;
251	i915_reg_t reg;
252	u32 val, pipeconf_val;
253
254	/* Make sure PCH DPLL is enabled */
255	assert_dpll_enabled(display, crtc_state->intel_dpll);
256
257	/* FDI must be feeding us bits for PCH ports */
258	assert_fdi_tx_enabled(display, pipe);
259	assert_fdi_rx_enabled(display, pipe);
260
261	if (HAS_PCH_CPT(display)) {
262		reg = TRANS_CHICKEN2(pipe);
263		val = intel_de_read(display, reg);
264		/*
265		 * Workaround: Set the timing override bit
266		 * before enabling the pch transcoder.
267		 */
268		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
269		/* Configure frame start delay to match the CPU */
270		val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
271		val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
272		intel_de_write(display, reg, val);
273	}
274
275	reg = PCH_TRANSCONF(pipe);
276	val = intel_de_read(display, reg);
277	pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe));
278
279	if (HAS_PCH_IBX(display)) {
280		/* Configure frame start delay to match the CPU */
281		val &= ~TRANS_FRAME_START_DELAY_MASK;
282		val |= TRANS_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
283
284		/*
285		 * Make the BPC in transcoder be consistent with
286		 * that in pipeconf reg. For HDMI we must use 8bpc
287		 * here for both 8bpc and 12bpc.
288		 */
289		val &= ~TRANSCONF_BPC_MASK;
290		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
291			val |= TRANSCONF_BPC_8;
292		else
293			val |= pipeconf_val & TRANSCONF_BPC_MASK;
294	}
295
296	val &= ~TRANS_INTERLACE_MASK;
297	if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_ILK) == TRANSCONF_INTERLACE_IF_ID_ILK) {
298		if (HAS_PCH_IBX(display) &&
299		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
300			val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
301		else
302			val |= TRANS_INTERLACE_INTERLACED;
303	} else {
304		val |= TRANS_INTERLACE_PROGRESSIVE;
305	}
306
307	intel_de_write(display, reg, val | TRANS_ENABLE);
308	if (intel_de_wait_for_set_ms(display, reg, TRANS_STATE_ENABLE, 100))
309		drm_err(display->drm, "failed to enable transcoder %c\n",
310			pipe_name(pipe));
311}
312
313static void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
314{
315	struct intel_display *display = to_intel_display(crtc);
316	enum pipe pipe = crtc->pipe;
317	i915_reg_t reg;
318
319	/* FDI relies on the transcoder */
320	assert_fdi_tx_disabled(display, pipe);
321	assert_fdi_rx_disabled(display, pipe);
322
323	/* Ports must be off as well */
324	assert_pch_ports_disabled(display, pipe);
325
326	reg = PCH_TRANSCONF(pipe);
327	intel_de_rmw(display, reg, TRANS_ENABLE, 0);
328	/* wait for PCH transcoder off, transcoder state */
329	if (intel_de_wait_for_clear_ms(display, reg, TRANS_STATE_ENABLE, 50))
330		drm_err(display->drm, "failed to disable transcoder %c\n",
331			pipe_name(pipe));
332
333	if (HAS_PCH_CPT(display))
334		/* Workaround: Clear the timing override chicken bit again. */
335		intel_de_rmw(display, TRANS_CHICKEN2(pipe),
336			     TRANS_CHICKEN2_TIMING_OVERRIDE, 0);
337}
338
339void ilk_pch_pre_enable(struct intel_atomic_state *state,
340			struct intel_crtc *crtc)
341{
342	const struct intel_crtc_state *crtc_state =
343		intel_atomic_get_new_crtc_state(state, crtc);
344
345	/*
346	 * Note: FDI PLL enabling _must_ be done before we enable the
347	 * cpu pipes, hence this is separate from all the other fdi/pch
348	 * enabling.
349	 */
350	ilk_fdi_pll_enable(crtc_state);
351}
352
353/*
354 * Enable PCH resources required for PCH ports:
355 *   - PCH PLLs
356 *   - FDI training & RX/TX
357 *   - update transcoder timings
358 *   - DP transcoding bits
359 *   - transcoder
360 */
361void ilk_pch_enable(struct intel_atomic_state *state,
362		    struct intel_crtc *crtc)
363{
364	struct intel_display *display = to_intel_display(crtc);
365	const struct intel_crtc_state *crtc_state =
366		intel_atomic_get_new_crtc_state(state, crtc);
367	enum pipe pipe = crtc->pipe;
368	u32 temp;
369
370	assert_pch_transcoder_disabled(display, pipe);
371
372	/* For PCH output, training FDI link */
373	intel_fdi_link_train(crtc, crtc_state);
374
375	/*
376	 * We need to program the right clock selection
377	 * before writing the pixel multiplier into the DPLL.
378	 */
379	if (HAS_PCH_CPT(display)) {
380		u32 sel;
381
382		temp = intel_de_read(display, PCH_DPLL_SEL);
383		temp |= TRANS_DPLL_ENABLE(pipe);
384		sel = TRANS_DPLLB_SEL(pipe);
385		if (crtc_state->intel_dpll ==
386		    intel_get_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
387			temp |= sel;
388		else
389			temp &= ~sel;
390		intel_de_write(display, PCH_DPLL_SEL, temp);
391	}
392
393	/*
394	 * XXX: pch pll's can be enabled any time before we enable the PCH
395	 * transcoder, and we actually should do this to not upset any PCH
396	 * transcoder that already use the clock when we share it.
397	 *
398	 * Note that dpll_enable tries to do the right thing, but
399	 * get_dpll unconditionally resets the pll - we need that
400	 * to have the right LVDS enable sequence.
401	 */
402	intel_dpll_enable(crtc_state);
403
404	/* set transcoder timing, panel must allow it */
405	assert_pps_unlocked(display, pipe);
406	if (intel_crtc_has_dp_encoder(crtc_state)) {
407		intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n);
408		intel_pch_transcoder_set_m2_n2(crtc, &crtc_state->dp_m2_n2);
409	}
410	ilk_pch_transcoder_set_timings(crtc_state, pipe);
411
412	intel_fdi_normal_train(crtc);
413
414	/* For PCH DP, enable TRANS_DP_CTL */
415	if (HAS_PCH_CPT(display) &&
416	    intel_crtc_has_dp_encoder(crtc_state)) {
417		const struct drm_display_mode *adjusted_mode =
418			&crtc_state->hw.adjusted_mode;
419		u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))
420			   & TRANSCONF_BPC_MASK) >> 5;
421		i915_reg_t reg = TRANS_DP_CTL(pipe);
422		enum port port;
423
424		temp = intel_de_read(display, reg);
425		temp &= ~(TRANS_DP_PORT_SEL_MASK |
426			  TRANS_DP_VSYNC_ACTIVE_HIGH |
427			  TRANS_DP_HSYNC_ACTIVE_HIGH |
428			  TRANS_DP_BPC_MASK);
429		temp |= TRANS_DP_OUTPUT_ENABLE;
430		temp |= bpc << 9; /* same format but at 11:9 */
431
432		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
433			temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
434		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
435			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
436
437		port = intel_get_crtc_new_encoder(state, crtc_state)->port;
438		drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D);
439		temp |= TRANS_DP_PORT_SEL(port);
440
441		intel_de_write(display, reg, temp);
442	}
443
444	ilk_enable_pch_transcoder(crtc_state);
445}
446
447void ilk_pch_disable(struct intel_atomic_state *state,
448		     struct intel_crtc *crtc)
449{
450	ilk_fdi_disable(crtc);
451}
452
453void ilk_pch_post_disable(struct intel_atomic_state *state,
454			  struct intel_crtc *crtc)
455{
456	struct intel_display *display = to_intel_display(crtc);
457	const struct intel_crtc_state *old_crtc_state =
458		intel_atomic_get_old_crtc_state(state, crtc);
459	enum pipe pipe = crtc->pipe;
460
461	ilk_disable_pch_transcoder(crtc);
462
463	if (HAS_PCH_CPT(display)) {
464		/* disable TRANS_DP_CTL */
465		intel_de_rmw(display, TRANS_DP_CTL(pipe),
466			     TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK,
467			     TRANS_DP_PORT_SEL_NONE);
468
469		/* disable DPLL_SEL */
470		intel_de_rmw(display, PCH_DPLL_SEL,
471			     TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe), 0);
472	}
473
474	ilk_fdi_pll_disable(crtc);
475
476	intel_dpll_disable(old_crtc_state);
477}
478
479static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
480{
481	struct intel_display *display = to_intel_display(crtc_state);
482
483	/* read out port_clock from the DPLL */
484	i9xx_crtc_clock_get(crtc_state);
485
486	/*
487	 * In case there is an active pipe without active ports,
488	 * we may need some idea for the dotclock anyway.
489	 * Calculate one based on the FDI configuration.
490	 */
491	crtc_state->hw.adjusted_mode.crtc_clock =
492		intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state),
493					 &crtc_state->fdi_m_n);
494}
495
496void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
497{
498	struct intel_display *display = to_intel_display(crtc_state);
499	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
500	struct intel_dpll *pll;
501	enum pipe pipe = crtc->pipe;
502	enum intel_dpll_id pll_id;
503	bool pll_active;
504	u32 tmp;
505
506	if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
507		return;
508
509	crtc_state->has_pch_encoder = true;
510
511	tmp = intel_de_read(display, FDI_RX_CTL(pipe));
512	crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
513				 FDI_DP_PORT_WIDTH_SHIFT) + 1;
514
515	intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
516				       &crtc_state->fdi_m_n);
517
518	if (HAS_PCH_IBX(display)) {
519		/*
520		 * The pipe->pch transcoder and pch transcoder->pll
521		 * mapping is fixed.
522		 */
523		pll_id = (enum intel_dpll_id) pipe;
524	} else {
525		tmp = intel_de_read(display, PCH_DPLL_SEL);
526		if (tmp & TRANS_DPLLB_SEL(pipe))
527			pll_id = DPLL_ID_PCH_PLL_B;
528		else
529			pll_id = DPLL_ID_PCH_PLL_A;
530	}
531
532	crtc_state->intel_dpll = intel_get_dpll_by_id(display, pll_id);
533	pll = crtc_state->intel_dpll;
534
535	pll_active = intel_dpll_get_hw_state(display, pll,
536					     &crtc_state->dpll_hw_state);
537	drm_WARN_ON(display->drm, !pll_active);
538
539	tmp = crtc_state->dpll_hw_state.i9xx.dpll;
540	crtc_state->pixel_multiplier =
541		((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
542		 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
543
544	ilk_pch_clock_get(crtc_state);
545}
546
547static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
548{
549	struct intel_display *display = to_intel_display(crtc_state);
550	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
551	u32 val, pipeconf_val;
552
553	/* FDI must be feeding us bits for PCH ports */
554	assert_fdi_tx_enabled(display, (enum pipe)cpu_transcoder);
555	assert_fdi_rx_enabled(display, PIPE_A);
556
557	val = intel_de_read(display, TRANS_CHICKEN2(PIPE_A));
558	/* Workaround: set timing override bit. */
559	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
560	/* Configure frame start delay to match the CPU */
561	val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
562	val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
563	intel_de_write(display, TRANS_CHICKEN2(PIPE_A), val);
564
565	val = TRANS_ENABLE;
566	pipeconf_val = intel_de_read(display,
567				     TRANSCONF(display, cpu_transcoder));
568
569	if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_HSW) == TRANSCONF_INTERLACE_IF_ID_ILK)
570		val |= TRANS_INTERLACE_INTERLACED;
571	else
572		val |= TRANS_INTERLACE_PROGRESSIVE;
573
574	intel_de_write(display, LPT_TRANSCONF, val);
575	if (intel_de_wait_for_set_ms(display, LPT_TRANSCONF,
576				     TRANS_STATE_ENABLE, 100))
577		drm_err(display->drm, "Failed to enable PCH transcoder\n");
578}
579
580static void lpt_disable_pch_transcoder(struct intel_display *display)
581{
582	intel_de_rmw(display, LPT_TRANSCONF, TRANS_ENABLE, 0);
583	/* wait for PCH transcoder off, transcoder state */
584	if (intel_de_wait_for_clear_ms(display, LPT_TRANSCONF,
585				       TRANS_STATE_ENABLE, 50))
586		drm_err(display->drm, "Failed to disable PCH transcoder\n");
587
588	/* Workaround: clear timing override bit. */
589	intel_de_rmw(display, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0);
590}
591
592void lpt_pch_enable(struct intel_atomic_state *state,
593		    struct intel_crtc *crtc)
594{
595	struct intel_display *display = to_intel_display(crtc);
596	const struct intel_crtc_state *crtc_state =
597		intel_atomic_get_new_crtc_state(state, crtc);
598
599	assert_pch_transcoder_disabled(display, PIPE_A);
600
601	lpt_program_iclkip(crtc_state);
602
603	/* Set transcoder timing. */
604	ilk_pch_transcoder_set_timings(crtc_state, PIPE_A);
605
606	lpt_enable_pch_transcoder(crtc_state);
607}
608
609void lpt_pch_disable(struct intel_atomic_state *state,
610		     struct intel_crtc *crtc)
611{
612	struct intel_display *display = to_intel_display(crtc);
613
614	lpt_disable_pch_transcoder(display);
615
616	lpt_disable_iclkip(display);
617}
618
619void lpt_pch_get_config(struct intel_crtc_state *crtc_state)
620{
621	struct intel_display *display = to_intel_display(crtc_state);
622	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
623	u32 tmp;
624
625	if ((intel_de_read(display, LPT_TRANSCONF) & TRANS_ENABLE) == 0)
626		return;
627
628	crtc_state->has_pch_encoder = true;
629
630	tmp = intel_de_read(display, FDI_RX_CTL(PIPE_A));
631	crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
632				 FDI_DP_PORT_WIDTH_SHIFT) + 1;
633
634	intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
635				       &crtc_state->fdi_m_n);
636
637	crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(display);
638}
639
640void intel_pch_sanitize(struct intel_display *display)
641{
642	if (HAS_PCH_IBX(display))
643		ibx_sanitize_pch_ports(display);
644}