intel_overlay.c

   1/*
   2 * Copyright © 2009
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21 * SOFTWARE.
  22 *
  23 * Authors:
  24 *    Daniel Vetter <daniel@ffwll.ch>
  25 *
  26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27 */
  28
  29#include <drm/drm_fourcc.h>
  30#include <drm/drm_print.h>
  31
  32#include "gem/i915_gem_internal.h"
  33#include "gem/i915_gem_object_frontbuffer.h"
  34#include "gem/i915_gem_pm.h"
  35
  36#include "gt/intel_gpu_commands.h"
  37#include "gt/intel_ring.h"
  38
  39#include "i915_drv.h"
  40#include "i915_reg.h"
  41#include "intel_color_regs.h"
  42#include "intel_de.h"
  43#include "intel_display_regs.h"
  44#include "intel_display_types.h"
  45#include "intel_frontbuffer.h"
  46#include "intel_overlay.h"
  47#include "intel_pci_config.h"
  48#include "intel_pfit_regs.h"
  49
  50/* Limits for overlay size. According to intel doc, the real limits are:
  51 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  52 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  53 * the minimum of both.
  54 */
  55#define IMAGE_MAX_WIDTH		2048
  56#define IMAGE_MAX_HEIGHT	2046 /* 2 * 1023 */
  57/* on 830 and 845 these large limits result in the card hanging */
  58#define IMAGE_MAX_WIDTH_LEGACY	1024
  59#define IMAGE_MAX_HEIGHT_LEGACY	1088
  60
  61/* overlay register definitions */
  62/* OCMD register */
  63#define OCMD_TILED_SURFACE	(0x1<<19)
  64#define OCMD_MIRROR_MASK	(0x3<<17)
  65#define OCMD_MIRROR_MODE	(0x3<<17)
  66#define OCMD_MIRROR_HORIZONTAL	(0x1<<17)
  67#define OCMD_MIRROR_VERTICAL	(0x2<<17)
  68#define OCMD_MIRROR_BOTH	(0x3<<17)
  69#define OCMD_BYTEORDER_MASK	(0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  70#define OCMD_UV_SWAP		(0x1<<14) /* YVYU */
  71#define OCMD_Y_SWAP		(0x2<<14) /* UYVY or FOURCC UYVY */
  72#define OCMD_Y_AND_UV_SWAP	(0x3<<14) /* VYUY */
  73#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  74#define OCMD_RGB_888		(0x1<<10) /* not in i965 Intel docs */
  75#define OCMD_RGB_555		(0x2<<10) /* not in i965 Intel docs */
  76#define OCMD_RGB_565		(0x3<<10) /* not in i965 Intel docs */
  77#define OCMD_YUV_422_PACKED	(0x8<<10)
  78#define OCMD_YUV_411_PACKED	(0x9<<10) /* not in i965 Intel docs */
  79#define OCMD_YUV_420_PLANAR	(0xc<<10)
  80#define OCMD_YUV_422_PLANAR	(0xd<<10)
  81#define OCMD_YUV_410_PLANAR	(0xe<<10) /* also 411 */
  82#define OCMD_TVSYNCFLIP_PARITY	(0x1<<9)
  83#define OCMD_TVSYNCFLIP_ENABLE	(0x1<<7)
  84#define OCMD_BUF_TYPE_MASK	(0x1<<5)
  85#define OCMD_BUF_TYPE_FRAME	(0x0<<5)
  86#define OCMD_BUF_TYPE_FIELD	(0x1<<5)
  87#define OCMD_TEST_MODE		(0x1<<4)
  88#define OCMD_BUFFER_SELECT	(0x3<<2)
  89#define OCMD_BUFFER0		(0x0<<2)
  90#define OCMD_BUFFER1		(0x1<<2)
  91#define OCMD_FIELD_SELECT	(0x1<<2)
  92#define OCMD_FIELD0		(0x0<<1)
  93#define OCMD_FIELD1		(0x1<<1)
  94#define OCMD_ENABLE		(0x1<<0)
  95
  96/* OCONFIG register */
  97#define OCONF_PIPE_MASK		(0x1<<18)
  98#define OCONF_PIPE_A		(0x0<<18)
  99#define OCONF_PIPE_B		(0x1<<18)
 100#define OCONF_GAMMA2_ENABLE	(0x1<<16)
 101#define OCONF_CSC_MODE_BT601	(0x0<<5)
 102#define OCONF_CSC_MODE_BT709	(0x1<<5)
 103#define OCONF_CSC_BYPASS	(0x1<<4)
 104#define OCONF_CC_OUT_8BIT	(0x1<<3)
 105#define OCONF_TEST_MODE		(0x1<<2)
 106#define OCONF_THREE_LINE_BUFFER	(0x1<<0)
 107#define OCONF_TWO_LINE_BUFFER	(0x0<<0)
 108
 109/* DCLRKM (dst-key) register */
 110#define DST_KEY_ENABLE		(0x1<<31)
 111#define CLK_RGB24_MASK		0x0
 112#define CLK_RGB16_MASK		0x070307
 113#define CLK_RGB15_MASK		0x070707
 114
 115#define RGB30_TO_COLORKEY(c) \
 116	((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2))
 117#define RGB16_TO_COLORKEY(c) \
 118	((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3))
 119#define RGB15_TO_COLORKEY(c) \
 120	((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3))
 121#define RGB8I_TO_COLORKEY(c) \
 122	((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0))
 123
 124/* overlay flip addr flag */
 125#define OFC_UPDATE		0x1
 126
 127/* polyphase filter coefficients */
 128#define N_HORIZ_Y_TAPS          5
 129#define N_VERT_Y_TAPS           3
 130#define N_HORIZ_UV_TAPS         3
 131#define N_VERT_UV_TAPS          3
 132#define N_PHASES                17
 133#define MAX_TAPS                5
 134
 135/* memory bufferd overlay registers */
 136struct overlay_registers {
 137	u32 OBUF_0Y;
 138	u32 OBUF_1Y;
 139	u32 OBUF_0U;
 140	u32 OBUF_0V;
 141	u32 OBUF_1U;
 142	u32 OBUF_1V;
 143	u32 OSTRIDE;
 144	u32 YRGB_VPH;
 145	u32 UV_VPH;
 146	u32 HORZ_PH;
 147	u32 INIT_PHS;
 148	u32 DWINPOS;
 149	u32 DWINSZ;
 150	u32 SWIDTH;
 151	u32 SWIDTHSW;
 152	u32 SHEIGHT;
 153	u32 YRGBSCALE;
 154	u32 UVSCALE;
 155	u32 OCLRC0;
 156	u32 OCLRC1;
 157	u32 DCLRKV;
 158	u32 DCLRKM;
 159	u32 SCLRKVH;
 160	u32 SCLRKVL;
 161	u32 SCLRKEN;
 162	u32 OCONFIG;
 163	u32 OCMD;
 164	u32 RESERVED1; /* 0x6C */
 165	u32 OSTART_0Y;
 166	u32 OSTART_1Y;
 167	u32 OSTART_0U;
 168	u32 OSTART_0V;
 169	u32 OSTART_1U;
 170	u32 OSTART_1V;
 171	u32 OTILEOFF_0Y;
 172	u32 OTILEOFF_1Y;
 173	u32 OTILEOFF_0U;
 174	u32 OTILEOFF_0V;
 175	u32 OTILEOFF_1U;
 176	u32 OTILEOFF_1V;
 177	u32 FASTHSCALE; /* 0xA0 */
 178	u32 UVSCALEV; /* 0xA4 */
 179	u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
 180	u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
 181	u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
 182	u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
 183	u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
 184	u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
 185	u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
 186	u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
 187	u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
 188};
 189
 190struct intel_overlay {
 191	struct intel_display *display;
 192	struct intel_context *context;
 193	struct intel_crtc *crtc;
 194	struct i915_vma *vma;
 195	struct i915_vma *old_vma;
 196	struct intel_frontbuffer *frontbuffer;
 197	bool active;
 198	bool pfit_active;
 199	u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 200	u32 color_key:24;
 201	u32 color_key_enabled:1;
 202	u32 brightness, contrast, saturation;
 203	u32 old_xscale, old_yscale;
 204	/* register access */
 205	struct drm_i915_gem_object *reg_bo;
 206	struct overlay_registers __iomem *regs;
 207	u32 flip_addr;
 208	/* flip handling */
 209	struct i915_active last_flip;
 210	void (*flip_complete)(struct intel_overlay *ovl);
 211};
 212
 213static void i830_overlay_clock_gating(struct intel_display *display,
 214				      bool enable)
 215{
 216	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
 217	u8 val;
 218
 219	/* WA_OVERLAY_CLKGATE:alm */
 220	if (enable)
 221		intel_de_write(display, DSPCLK_GATE_D, 0);
 222	else
 223		intel_de_write(display, DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
 224
 225	/* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
 226	pci_bus_read_config_byte(pdev->bus,
 227				 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
 228	if (enable)
 229		val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
 230	else
 231		val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
 232	pci_bus_write_config_byte(pdev->bus,
 233				  PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
 234}
 235
 236static struct i915_request *
 237alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *))
 238{
 239	struct i915_request *rq;
 240	int err;
 241
 242	overlay->flip_complete = fn;
 243
 244	rq = i915_request_create(overlay->context);
 245	if (IS_ERR(rq))
 246		return rq;
 247
 248	err = i915_active_add_request(&overlay->last_flip, rq);
 249	if (err) {
 250		i915_request_add(rq);
 251		return ERR_PTR(err);
 252	}
 253
 254	return rq;
 255}
 256
 257/* overlay needs to be disable in OCMD reg */
 258static int intel_overlay_on(struct intel_overlay *overlay)
 259{
 260	struct intel_display *display = overlay->display;
 261	struct i915_request *rq;
 262	u32 *cs;
 263
 264	drm_WARN_ON(display->drm, overlay->active);
 265
 266	rq = alloc_request(overlay, NULL);
 267	if (IS_ERR(rq))
 268		return PTR_ERR(rq);
 269
 270	cs = intel_ring_begin(rq, 4);
 271	if (IS_ERR(cs)) {
 272		i915_request_add(rq);
 273		return PTR_ERR(cs);
 274	}
 275
 276	overlay->active = true;
 277
 278	if (display->platform.i830)
 279		i830_overlay_clock_gating(display, false);
 280
 281	*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON;
 282	*cs++ = overlay->flip_addr | OFC_UPDATE;
 283	*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 284	*cs++ = MI_NOOP;
 285	intel_ring_advance(rq, cs);
 286
 287	i915_request_add(rq);
 288
 289	return i915_active_wait(&overlay->last_flip);
 290}
 291
 292static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
 293				       struct i915_vma *vma)
 294{
 295	struct intel_display *display = overlay->display;
 296	enum pipe pipe = overlay->crtc->pipe;
 297	struct intel_frontbuffer *frontbuffer = NULL;
 298
 299	drm_WARN_ON(display->drm, overlay->old_vma);
 300
 301	if (vma)
 302		frontbuffer = intel_frontbuffer_get(intel_bo_to_drm_bo(vma->obj));
 303
 304	intel_frontbuffer_track(overlay->frontbuffer, frontbuffer,
 305				INTEL_FRONTBUFFER_OVERLAY(pipe));
 306
 307	if (overlay->frontbuffer)
 308		intel_frontbuffer_put(overlay->frontbuffer);
 309	overlay->frontbuffer = frontbuffer;
 310
 311	overlay->old_vma = overlay->vma;
 312	if (vma)
 313		overlay->vma = i915_vma_get(vma);
 314	else
 315		overlay->vma = NULL;
 316}
 317
 318/* overlay needs to be enabled in OCMD reg */
 319static int intel_overlay_continue(struct intel_overlay *overlay,
 320				  struct i915_vma *vma,
 321				  bool load_polyphase_filter)
 322{
 323	struct intel_display *display = overlay->display;
 324	struct i915_request *rq;
 325	u32 flip_addr = overlay->flip_addr;
 326	u32 tmp, *cs;
 327
 328	drm_WARN_ON(display->drm, !overlay->active);
 329
 330	if (load_polyphase_filter)
 331		flip_addr |= OFC_UPDATE;
 332
 333	/* check for underruns */
 334	tmp = intel_de_read(display, DOVSTA);
 335	if (tmp & (1 << 17))
 336		drm_dbg(display->drm, "overlay underrun, DOVSTA: %x\n", tmp);
 337
 338	rq = alloc_request(overlay, NULL);
 339	if (IS_ERR(rq))
 340		return PTR_ERR(rq);
 341
 342	cs = intel_ring_begin(rq, 2);
 343	if (IS_ERR(cs)) {
 344		i915_request_add(rq);
 345		return PTR_ERR(cs);
 346	}
 347
 348	*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
 349	*cs++ = flip_addr;
 350	intel_ring_advance(rq, cs);
 351
 352	intel_overlay_flip_prepare(overlay, vma);
 353	i915_request_add(rq);
 354
 355	return 0;
 356}
 357
 358static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
 359{
 360	struct intel_display *display = overlay->display;
 361	struct i915_vma *vma;
 362
 363	vma = fetch_and_zero(&overlay->old_vma);
 364	if (drm_WARN_ON(display->drm, !vma))
 365		return;
 366
 367	intel_frontbuffer_flip(display, INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
 368
 369	i915_vma_unpin(vma);
 370	i915_vma_put(vma);
 371}
 372
 373static void
 374intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
 375{
 376	intel_overlay_release_old_vma(overlay);
 377}
 378
 379static void intel_overlay_off_tail(struct intel_overlay *overlay)
 380{
 381	struct intel_display *display = overlay->display;
 382
 383	intel_overlay_release_old_vma(overlay);
 384
 385	overlay->crtc->overlay = NULL;
 386	overlay->crtc = NULL;
 387	overlay->active = false;
 388
 389	if (display->platform.i830)
 390		i830_overlay_clock_gating(display, true);
 391}
 392
 393static void intel_overlay_last_flip_retire(struct i915_active *active)
 394{
 395	struct intel_overlay *overlay =
 396		container_of(active, typeof(*overlay), last_flip);
 397
 398	if (overlay->flip_complete)
 399		overlay->flip_complete(overlay);
 400}
 401
 402/* overlay needs to be disabled in OCMD reg */
 403static int intel_overlay_off(struct intel_overlay *overlay)
 404{
 405	struct intel_display *display = overlay->display;
 406	struct i915_request *rq;
 407	u32 *cs, flip_addr = overlay->flip_addr;
 408
 409	drm_WARN_ON(display->drm, !overlay->active);
 410
 411	/*
 412	 * According to intel docs the overlay hw may hang (when switching
 413	 * off) without loading the filter coeffs. It is however unclear whether
 414	 * this applies to the disabling of the overlay or to the switching off
 415	 * of the hw. Do it in both cases.
 416	 */
 417	flip_addr |= OFC_UPDATE;
 418
 419	rq = alloc_request(overlay, intel_overlay_off_tail);
 420	if (IS_ERR(rq))
 421		return PTR_ERR(rq);
 422
 423	cs = intel_ring_begin(rq, 6);
 424	if (IS_ERR(cs)) {
 425		i915_request_add(rq);
 426		return PTR_ERR(cs);
 427	}
 428
 429	/* wait for overlay to go idle */
 430	*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
 431	*cs++ = flip_addr;
 432	*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 433
 434	/* turn overlay off */
 435	*cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF;
 436	*cs++ = flip_addr;
 437	*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 438
 439	intel_ring_advance(rq, cs);
 440
 441	intel_overlay_flip_prepare(overlay, NULL);
 442	i915_request_add(rq);
 443
 444	return i915_active_wait(&overlay->last_flip);
 445}
 446
 447/*
 448 * Recover from an interruption due to a signal.
 449 * We have to be careful not to repeat work forever an make forward progress.
 450 */
 451static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
 452{
 453	return i915_active_wait(&overlay->last_flip);
 454}
 455
 456/*
 457 * Wait for pending overlay flip and release old frame.
 458 * Needs to be called before the overlay register are changed
 459 * via intel_overlay_(un)map_regs.
 460 */
 461static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
 462{
 463	struct intel_display *display = overlay->display;
 464	struct i915_request *rq;
 465	u32 *cs;
 466
 467	/*
 468	 * Only wait if there is actually an old frame to release to
 469	 * guarantee forward progress.
 470	 */
 471	if (!overlay->old_vma)
 472		return 0;
 473
 474	if (!(intel_de_read(display, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {
 475		intel_overlay_release_old_vid_tail(overlay);
 476		return 0;
 477	}
 478
 479	rq = alloc_request(overlay, intel_overlay_release_old_vid_tail);
 480	if (IS_ERR(rq))
 481		return PTR_ERR(rq);
 482
 483	cs = intel_ring_begin(rq, 2);
 484	if (IS_ERR(cs)) {
 485		i915_request_add(rq);
 486		return PTR_ERR(cs);
 487	}
 488
 489	*cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 490	*cs++ = MI_NOOP;
 491	intel_ring_advance(rq, cs);
 492
 493	i915_request_add(rq);
 494
 495	return i915_active_wait(&overlay->last_flip);
 496}
 497
 498void intel_overlay_reset(struct intel_display *display)
 499{
 500	struct intel_overlay *overlay = display->overlay;
 501
 502	if (!overlay)
 503		return;
 504
 505	overlay->old_xscale = 0;
 506	overlay->old_yscale = 0;
 507	overlay->crtc = NULL;
 508	overlay->active = false;
 509}
 510
 511static int packed_depth_bytes(u32 format)
 512{
 513	switch (format & I915_OVERLAY_DEPTH_MASK) {
 514	case I915_OVERLAY_YUV422:
 515		return 4;
 516	case I915_OVERLAY_YUV411:
 517		/* return 6; not implemented */
 518	default:
 519		return -EINVAL;
 520	}
 521}
 522
 523static int packed_width_bytes(u32 format, short width)
 524{
 525	switch (format & I915_OVERLAY_DEPTH_MASK) {
 526	case I915_OVERLAY_YUV422:
 527		return width << 1;
 528	default:
 529		return -EINVAL;
 530	}
 531}
 532
 533static int uv_hsubsampling(u32 format)
 534{
 535	switch (format & I915_OVERLAY_DEPTH_MASK) {
 536	case I915_OVERLAY_YUV422:
 537	case I915_OVERLAY_YUV420:
 538		return 2;
 539	case I915_OVERLAY_YUV411:
 540	case I915_OVERLAY_YUV410:
 541		return 4;
 542	default:
 543		return -EINVAL;
 544	}
 545}
 546
 547static int uv_vsubsampling(u32 format)
 548{
 549	switch (format & I915_OVERLAY_DEPTH_MASK) {
 550	case I915_OVERLAY_YUV420:
 551	case I915_OVERLAY_YUV410:
 552		return 2;
 553	case I915_OVERLAY_YUV422:
 554	case I915_OVERLAY_YUV411:
 555		return 1;
 556	default:
 557		return -EINVAL;
 558	}
 559}
 560
 561static u32 calc_swidthsw(struct intel_display *display, u32 offset, u32 width)
 562{
 563	u32 sw;
 564
 565	if (DISPLAY_VER(display) == 2)
 566		sw = ALIGN((offset & 31) + width, 32);
 567	else
 568		sw = ALIGN((offset & 63) + width, 64);
 569
 570	if (sw == 0)
 571		return 0;
 572
 573	return (sw - 32) >> 3;
 574}
 575
 576static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
 577	[ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
 578	[ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
 579	[ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
 580	[ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
 581	[ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
 582	[ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
 583	[ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
 584	[ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
 585	[ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
 586	[ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
 587	[10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
 588	[11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
 589	[12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
 590	[13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
 591	[14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
 592	[15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
 593	[16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
 594};
 595
 596static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {
 597	[ 0] = { 0x3000, 0x1800, 0x1800, },
 598	[ 1] = { 0xb000, 0x18d0, 0x2e60, },
 599	[ 2] = { 0xb000, 0x1990, 0x2ce0, },
 600	[ 3] = { 0xb020, 0x1a68, 0x2b40, },
 601	[ 4] = { 0xb040, 0x1b20, 0x29e0, },
 602	[ 5] = { 0xb060, 0x1bd8, 0x2880, },
 603	[ 6] = { 0xb080, 0x1c88, 0x3e60, },
 604	[ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
 605	[ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
 606	[ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
 607	[10] = { 0xb100, 0x1eb8, 0x3620, },
 608	[11] = { 0xb100, 0x1f18, 0x34a0, },
 609	[12] = { 0xb100, 0x1f68, 0x3360, },
 610	[13] = { 0xb0e0, 0x1fa8, 0x3240, },
 611	[14] = { 0xb0c0, 0x1fe0, 0x3140, },
 612	[15] = { 0xb060, 0x1ff0, 0x30a0, },
 613	[16] = { 0x3000, 0x0800, 0x3000, },
 614};
 615
 616static void update_polyphase_filter(struct overlay_registers __iomem *regs)
 617{
 618	memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
 619	memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
 620		    sizeof(uv_static_hcoeffs));
 621}
 622
 623static bool update_scaling_factors(struct intel_overlay *overlay,
 624				   struct overlay_registers __iomem *regs,
 625				   struct drm_intel_overlay_put_image *params)
 626{
 627	/* fixed point with a 12 bit shift */
 628	u32 xscale, yscale, xscale_UV, yscale_UV;
 629#define FP_SHIFT 12
 630#define FRACT_MASK 0xfff
 631	bool scale_changed = false;
 632	int uv_hscale = uv_hsubsampling(params->flags);
 633	int uv_vscale = uv_vsubsampling(params->flags);
 634
 635	if (params->dst_width > 1)
 636		xscale = ((params->src_scan_width - 1) << FP_SHIFT) /
 637			params->dst_width;
 638	else
 639		xscale = 1 << FP_SHIFT;
 640
 641	if (params->dst_height > 1)
 642		yscale = ((params->src_scan_height - 1) << FP_SHIFT) /
 643			params->dst_height;
 644	else
 645		yscale = 1 << FP_SHIFT;
 646
 647	/*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
 648	xscale_UV = xscale/uv_hscale;
 649	yscale_UV = yscale/uv_vscale;
 650	/* make the Y scale to UV scale ratio an exact multiply */
 651	xscale = xscale_UV * uv_hscale;
 652	yscale = yscale_UV * uv_vscale;
 653	/*} else {
 654	  xscale_UV = 0;
 655	  yscale_UV = 0;
 656	  }*/
 657
 658	if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
 659		scale_changed = true;
 660	overlay->old_xscale = xscale;
 661	overlay->old_yscale = yscale;
 662
 663	iowrite32(((yscale & FRACT_MASK) << 20) |
 664		  ((xscale >> FP_SHIFT)  << 16) |
 665		  ((xscale & FRACT_MASK) << 3),
 666		 &regs->YRGBSCALE);
 667
 668	iowrite32(((yscale_UV & FRACT_MASK) << 20) |
 669		  ((xscale_UV >> FP_SHIFT)  << 16) |
 670		  ((xscale_UV & FRACT_MASK) << 3),
 671		 &regs->UVSCALE);
 672
 673	iowrite32((((yscale    >> FP_SHIFT) << 16) |
 674		   ((yscale_UV >> FP_SHIFT) << 0)),
 675		 &regs->UVSCALEV);
 676
 677	if (scale_changed)
 678		update_polyphase_filter(regs);
 679
 680	return scale_changed;
 681}
 682
 683static void update_colorkey(struct intel_overlay *overlay,
 684			    struct overlay_registers __iomem *regs)
 685{
 686	const struct intel_plane_state *state =
 687		to_intel_plane_state(overlay->crtc->base.primary->state);
 688	u32 key = overlay->color_key;
 689	u32 format = 0;
 690	u32 flags = 0;
 691
 692	if (overlay->color_key_enabled)
 693		flags |= DST_KEY_ENABLE;
 694
 695	if (state->uapi.visible)
 696		format = state->hw.fb->format->format;
 697
 698	switch (format) {
 699	case DRM_FORMAT_C8:
 700		key = RGB8I_TO_COLORKEY(key);
 701		flags |= CLK_RGB24_MASK;
 702		break;
 703	case DRM_FORMAT_XRGB1555:
 704		key = RGB15_TO_COLORKEY(key);
 705		flags |= CLK_RGB15_MASK;
 706		break;
 707	case DRM_FORMAT_RGB565:
 708		key = RGB16_TO_COLORKEY(key);
 709		flags |= CLK_RGB16_MASK;
 710		break;
 711	case DRM_FORMAT_XRGB2101010:
 712	case DRM_FORMAT_XBGR2101010:
 713		key = RGB30_TO_COLORKEY(key);
 714		flags |= CLK_RGB24_MASK;
 715		break;
 716	default:
 717		flags |= CLK_RGB24_MASK;
 718		break;
 719	}
 720
 721	iowrite32(key, &regs->DCLRKV);
 722	iowrite32(flags, &regs->DCLRKM);
 723}
 724
 725static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params)
 726{
 727	u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
 728
 729	if (params->flags & I915_OVERLAY_YUV_PLANAR) {
 730		switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
 731		case I915_OVERLAY_YUV422:
 732			cmd |= OCMD_YUV_422_PLANAR;
 733			break;
 734		case I915_OVERLAY_YUV420:
 735			cmd |= OCMD_YUV_420_PLANAR;
 736			break;
 737		case I915_OVERLAY_YUV411:
 738		case I915_OVERLAY_YUV410:
 739			cmd |= OCMD_YUV_410_PLANAR;
 740			break;
 741		}
 742	} else { /* YUV packed */
 743		switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
 744		case I915_OVERLAY_YUV422:
 745			cmd |= OCMD_YUV_422_PACKED;
 746			break;
 747		case I915_OVERLAY_YUV411:
 748			cmd |= OCMD_YUV_411_PACKED;
 749			break;
 750		}
 751
 752		switch (params->flags & I915_OVERLAY_SWAP_MASK) {
 753		case I915_OVERLAY_NO_SWAP:
 754			break;
 755		case I915_OVERLAY_UV_SWAP:
 756			cmd |= OCMD_UV_SWAP;
 757			break;
 758		case I915_OVERLAY_Y_SWAP:
 759			cmd |= OCMD_Y_SWAP;
 760			break;
 761		case I915_OVERLAY_Y_AND_UV_SWAP:
 762			cmd |= OCMD_Y_AND_UV_SWAP;
 763			break;
 764		}
 765	}
 766
 767	return cmd;
 768}
 769
 770static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo)
 771{
 772	struct i915_gem_ww_ctx ww;
 773	struct i915_vma *vma;
 774	int ret;
 775
 776	i915_gem_ww_ctx_init(&ww, true);
 777retry:
 778	ret = i915_gem_object_lock(new_bo, &ww);
 779	if (!ret) {
 780		vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0, 0,
 781							   NULL, PIN_MAPPABLE);
 782		ret = PTR_ERR_OR_ZERO(vma);
 783	}
 784	if (ret == -EDEADLK) {
 785		ret = i915_gem_ww_ctx_backoff(&ww);
 786		if (!ret)
 787			goto retry;
 788	}
 789	i915_gem_ww_ctx_fini(&ww);
 790	if (ret)
 791		return ERR_PTR(ret);
 792
 793	return vma;
 794}
 795
 796static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 797				      struct drm_i915_gem_object *new_bo,
 798				      struct drm_intel_overlay_put_image *params)
 799{
 800	struct intel_display *display = overlay->display;
 801	struct overlay_registers __iomem *regs = overlay->regs;
 802	u32 swidth, swidthsw, sheight, ostride;
 803	enum pipe pipe = overlay->crtc->pipe;
 804	bool scale_changed = false;
 805	struct i915_vma *vma;
 806	int ret, tmp_width;
 807
 808	drm_WARN_ON(display->drm,
 809		    !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));
 810
 811	ret = intel_overlay_release_old_vid(overlay);
 812	if (ret != 0)
 813		return ret;
 814
 815	atomic_inc(&display->restore.pending_fb_pin);
 816
 817	vma = intel_overlay_pin_fb(new_bo);
 818	if (IS_ERR(vma)) {
 819		ret = PTR_ERR(vma);
 820		goto out_pin_section;
 821	}
 822
 823	if (!overlay->active) {
 824		const struct intel_crtc_state *crtc_state =
 825			overlay->crtc->config;
 826		u32 oconfig = 0;
 827
 828		if (crtc_state->gamma_enable &&
 829		    crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
 830			oconfig |= OCONF_CC_OUT_8BIT;
 831		if (crtc_state->gamma_enable)
 832			oconfig |= OCONF_GAMMA2_ENABLE;
 833		if (DISPLAY_VER(display) == 4)
 834			oconfig |= OCONF_CSC_MODE_BT709;
 835		oconfig |= pipe == 0 ?
 836			OCONF_PIPE_A : OCONF_PIPE_B;
 837		iowrite32(oconfig, &regs->OCONFIG);
 838
 839		ret = intel_overlay_on(overlay);
 840		if (ret != 0)
 841			goto out_unpin;
 842	}
 843
 844	iowrite32(params->dst_y << 16 | params->dst_x, &regs->DWINPOS);
 845	iowrite32(params->dst_height << 16 | params->dst_width, &regs->DWINSZ);
 846
 847	if (params->flags & I915_OVERLAY_YUV_PACKED)
 848		tmp_width = packed_width_bytes(params->flags,
 849					       params->src_width);
 850	else
 851		tmp_width = params->src_width;
 852
 853	swidth = params->src_width;
 854	swidthsw = calc_swidthsw(display, params->offset_Y, tmp_width);
 855	sheight = params->src_height;
 856	iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);
 857	ostride = params->stride_Y;
 858
 859	if (params->flags & I915_OVERLAY_YUV_PLANAR) {
 860		int uv_hscale = uv_hsubsampling(params->flags);
 861		int uv_vscale = uv_vsubsampling(params->flags);
 862		u32 tmp_U, tmp_V;
 863
 864		swidth |= (params->src_width / uv_hscale) << 16;
 865		sheight |= (params->src_height / uv_vscale) << 16;
 866
 867		tmp_U = calc_swidthsw(display, params->offset_U,
 868				      params->src_width / uv_hscale);
 869		tmp_V = calc_swidthsw(display, params->offset_V,
 870				      params->src_width / uv_hscale);
 871		swidthsw |= max(tmp_U, tmp_V) << 16;
 872
 873		iowrite32(i915_ggtt_offset(vma) + params->offset_U,
 874			  &regs->OBUF_0U);
 875		iowrite32(i915_ggtt_offset(vma) + params->offset_V,
 876			  &regs->OBUF_0V);
 877
 878		ostride |= params->stride_UV << 16;
 879	}
 880
 881	iowrite32(swidth, &regs->SWIDTH);
 882	iowrite32(swidthsw, &regs->SWIDTHSW);
 883	iowrite32(sheight, &regs->SHEIGHT);
 884	iowrite32(ostride, &regs->OSTRIDE);
 885
 886	scale_changed = update_scaling_factors(overlay, regs, params);
 887
 888	update_colorkey(overlay, regs);
 889
 890	iowrite32(overlay_cmd_reg(params), &regs->OCMD);
 891
 892	ret = intel_overlay_continue(overlay, vma, scale_changed);
 893	if (ret)
 894		goto out_unpin;
 895
 896	return 0;
 897
 898out_unpin:
 899	i915_vma_unpin(vma);
 900out_pin_section:
 901	atomic_dec(&display->restore.pending_fb_pin);
 902
 903	return ret;
 904}
 905
 906int intel_overlay_switch_off(struct intel_overlay *overlay)
 907{
 908	struct intel_display *display = overlay->display;
 909	int ret;
 910
 911	drm_WARN_ON(display->drm,
 912		    !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));
 913
 914	ret = intel_overlay_recover_from_interrupt(overlay);
 915	if (ret != 0)
 916		return ret;
 917
 918	if (!overlay->active)
 919		return 0;
 920
 921	ret = intel_overlay_release_old_vid(overlay);
 922	if (ret != 0)
 923		return ret;
 924
 925	iowrite32(0, &overlay->regs->OCMD);
 926
 927	return intel_overlay_off(overlay);
 928}
 929
 930static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
 931					  struct intel_crtc *crtc)
 932{
 933	if (!crtc->active)
 934		return -EINVAL;
 935
 936	/* can't use the overlay with double wide pipe */
 937	if (crtc->config->double_wide)
 938		return -EINVAL;
 939
 940	return 0;
 941}
 942
 943static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 944{
 945	struct intel_display *display = overlay->display;
 946	u32 ratio;
 947
 948	/* XXX: This is not the same logic as in the xorg driver, but more in
 949	 * line with the intel documentation for the i965
 950	 */
 951	if (DISPLAY_VER(display) >= 4) {
 952		u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));
 953
 954		/* on i965 use the PGM reg to read out the autoscaler values */
 955		ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp);
 956	} else {
 957		u32 tmp;
 958
 959		if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE)
 960			tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display));
 961		else
 962			tmp = intel_de_read(display, PFIT_PGM_RATIOS(display));
 963
 964		ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp);
 965	}
 966
 967	overlay->pfit_vscale_ratio = ratio;
 968}
 969
 970static int check_overlay_dst(struct intel_overlay *overlay,
 971			     struct drm_intel_overlay_put_image *rec)
 972{
 973	const struct intel_crtc_state *crtc_state =
 974		overlay->crtc->config;
 975	struct drm_rect req, clipped;
 976
 977	drm_rect_init(&req, rec->dst_x, rec->dst_y,
 978		      rec->dst_width, rec->dst_height);
 979
 980	clipped = req;
 981
 982	if (!drm_rect_intersect(&clipped, &crtc_state->pipe_src))
 983		return -EINVAL;
 984
 985	if (!drm_rect_equals(&clipped, &req))
 986		return -EINVAL;
 987
 988	return 0;
 989}
 990
 991static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec)
 992{
 993	u32 tmp;
 994
 995	/* downscaling limit is 8.0 */
 996	tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16;
 997	if (tmp > 7)
 998		return -EINVAL;
 999
1000	tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16;
1001	if (tmp > 7)
1002		return -EINVAL;
1003
1004	return 0;
1005}
1006
1007static int check_overlay_src(struct intel_display *display,
1008			     struct drm_intel_overlay_put_image *rec,
1009			     struct drm_i915_gem_object *new_bo)
1010{
1011	int uv_hscale = uv_hsubsampling(rec->flags);
1012	int uv_vscale = uv_vsubsampling(rec->flags);
1013	u32 stride_mask;
1014	int depth;
1015	u32 tmp;
1016
1017	/* check src dimensions */
1018	if (display->platform.i845g || display->platform.i830) {
1019		if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
1020		    rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
1021			return -EINVAL;
1022	} else {
1023		if (rec->src_height > IMAGE_MAX_HEIGHT ||
1024		    rec->src_width  > IMAGE_MAX_WIDTH)
1025			return -EINVAL;
1026	}
1027
1028	/* better safe than sorry, use 4 as the maximal subsampling ratio */
1029	if (rec->src_height < N_VERT_Y_TAPS*4 ||
1030	    rec->src_width  < N_HORIZ_Y_TAPS*4)
1031		return -EINVAL;
1032
1033	/* check alignment constraints */
1034	switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1035	case I915_OVERLAY_RGB:
1036		/* not implemented */
1037		return -EINVAL;
1038
1039	case I915_OVERLAY_YUV_PACKED:
1040		if (uv_vscale != 1)
1041			return -EINVAL;
1042
1043		depth = packed_depth_bytes(rec->flags);
1044		if (depth < 0)
1045			return depth;
1046
1047		/* ignore UV planes */
1048		rec->stride_UV = 0;
1049		rec->offset_U = 0;
1050		rec->offset_V = 0;
1051		/* check pixel alignment */
1052		if (rec->offset_Y % depth)
1053			return -EINVAL;
1054		break;
1055
1056	case I915_OVERLAY_YUV_PLANAR:
1057		if (uv_vscale < 0 || uv_hscale < 0)
1058			return -EINVAL;
1059		/* no offset restrictions for planar formats */
1060		break;
1061
1062	default:
1063		return -EINVAL;
1064	}
1065
1066	if (rec->src_width % uv_hscale)
1067		return -EINVAL;
1068
1069	/* stride checking */
1070	if (display->platform.i830 || display->platform.i845g)
1071		stride_mask = 255;
1072	else
1073		stride_mask = 63;
1074
1075	if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1076		return -EINVAL;
1077	if (DISPLAY_VER(display) == 4 && rec->stride_Y < 512)
1078		return -EINVAL;
1079
1080	tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1081		4096 : 8192;
1082	if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1083		return -EINVAL;
1084
1085	/* check buffer dimensions */
1086	switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1087	case I915_OVERLAY_RGB:
1088	case I915_OVERLAY_YUV_PACKED:
1089		/* always 4 Y values per depth pixels */
1090		if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1091			return -EINVAL;
1092
1093		tmp = rec->stride_Y*rec->src_height;
1094		if (rec->offset_Y + tmp > new_bo->base.size)
1095			return -EINVAL;
1096		break;
1097
1098	case I915_OVERLAY_YUV_PLANAR:
1099		if (rec->src_width > rec->stride_Y)
1100			return -EINVAL;
1101		if (rec->src_width/uv_hscale > rec->stride_UV)
1102			return -EINVAL;
1103
1104		tmp = rec->stride_Y * rec->src_height;
1105		if (rec->offset_Y + tmp > new_bo->base.size)
1106			return -EINVAL;
1107
1108		tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1109		if (rec->offset_U + tmp > new_bo->base.size ||
1110		    rec->offset_V + tmp > new_bo->base.size)
1111			return -EINVAL;
1112		break;
1113	}
1114
1115	return 0;
1116}
1117
1118int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1119				  struct drm_file *file_priv)
1120{
1121	struct intel_display *display = to_intel_display(dev);
1122	struct drm_intel_overlay_put_image *params = data;
1123	struct intel_overlay *overlay;
1124	struct drm_crtc *drmmode_crtc;
1125	struct intel_crtc *crtc;
1126	struct drm_i915_gem_object *new_bo;
1127	int ret;
1128
1129	overlay = display->overlay;
1130	if (!overlay) {
1131		drm_dbg(display->drm, "userspace bug: no overlay\n");
1132		return -ENODEV;
1133	}
1134
1135	if (!(params->flags & I915_OVERLAY_ENABLE)) {
1136		drm_modeset_lock_all(dev);
1137		ret = intel_overlay_switch_off(overlay);
1138		drm_modeset_unlock_all(dev);
1139
1140		return ret;
1141	}
1142
1143	drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id);
1144	if (!drmmode_crtc)
1145		return -ENOENT;
1146	crtc = to_intel_crtc(drmmode_crtc);
1147
1148	new_bo = i915_gem_object_lookup(file_priv, params->bo_handle);
1149	if (!new_bo)
1150		return -ENOENT;
1151
1152	drm_modeset_lock_all(dev);
1153
1154	if (i915_gem_object_is_tiled(new_bo)) {
1155		drm_dbg_kms(display->drm,
1156			    "buffer used for overlay image can not be tiled\n");
1157		ret = -EINVAL;
1158		goto out_unlock;
1159	}
1160
1161	ret = intel_overlay_recover_from_interrupt(overlay);
1162	if (ret != 0)
1163		goto out_unlock;
1164
1165	if (overlay->crtc != crtc) {
1166		ret = intel_overlay_switch_off(overlay);
1167		if (ret != 0)
1168			goto out_unlock;
1169
1170		ret = check_overlay_possible_on_crtc(overlay, crtc);
1171		if (ret != 0)
1172			goto out_unlock;
1173
1174		overlay->crtc = crtc;
1175		crtc->overlay = overlay;
1176
1177		/* line too wide, i.e. one-line-mode */
1178		if (drm_rect_width(&crtc->config->pipe_src) > 1024 &&
1179		    crtc->config->gmch_pfit.control & PFIT_ENABLE) {
1180			overlay->pfit_active = true;
1181			update_pfit_vscale_ratio(overlay);
1182		} else
1183			overlay->pfit_active = false;
1184	}
1185
1186	ret = check_overlay_dst(overlay, params);
1187	if (ret != 0)
1188		goto out_unlock;
1189
1190	if (overlay->pfit_active) {
1191		params->dst_y = (((u32)params->dst_y << 12) /
1192				 overlay->pfit_vscale_ratio);
1193		/* shifting right rounds downwards, so add 1 */
1194		params->dst_height = (((u32)params->dst_height << 12) /
1195				 overlay->pfit_vscale_ratio) + 1;
1196	}
1197
1198	if (params->src_scan_height > params->src_height ||
1199	    params->src_scan_width > params->src_width) {
1200		ret = -EINVAL;
1201		goto out_unlock;
1202	}
1203
1204	ret = check_overlay_src(display, params, new_bo);
1205	if (ret != 0)
1206		goto out_unlock;
1207
1208	/* Check scaling after src size to prevent a divide-by-zero. */
1209	ret = check_overlay_scaling(params);
1210	if (ret != 0)
1211		goto out_unlock;
1212
1213	ret = intel_overlay_do_put_image(overlay, new_bo, params);
1214	if (ret != 0)
1215		goto out_unlock;
1216
1217	drm_modeset_unlock_all(dev);
1218	i915_gem_object_put(new_bo);
1219
1220	return 0;
1221
1222out_unlock:
1223	drm_modeset_unlock_all(dev);
1224	i915_gem_object_put(new_bo);
1225
1226	return ret;
1227}
1228
1229static void update_reg_attrs(struct intel_overlay *overlay,
1230			     struct overlay_registers __iomem *regs)
1231{
1232	iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1233		  &regs->OCLRC0);
1234	iowrite32(overlay->saturation, &regs->OCLRC1);
1235}
1236
1237static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1238{
1239	int i;
1240
1241	if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1242		return false;
1243
1244	for (i = 0; i < 3; i++) {
1245		if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1246			return false;
1247	}
1248
1249	return true;
1250}
1251
1252static bool check_gamma5_errata(u32 gamma5)
1253{
1254	int i;
1255
1256	for (i = 0; i < 3; i++) {
1257		if (((gamma5 >> i*8) & 0xff) == 0x80)
1258			return false;
1259	}
1260
1261	return true;
1262}
1263
1264static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1265{
1266	if (!check_gamma_bounds(0, attrs->gamma0) ||
1267	    !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1268	    !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1269	    !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1270	    !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1271	    !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1272	    !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1273		return -EINVAL;
1274
1275	if (!check_gamma5_errata(attrs->gamma5))
1276		return -EINVAL;
1277
1278	return 0;
1279}
1280
1281int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1282			      struct drm_file *file_priv)
1283{
1284	struct intel_display *display = to_intel_display(dev);
1285	struct drm_intel_overlay_attrs *attrs = data;
1286	struct intel_overlay *overlay;
1287	int ret;
1288
1289	overlay = display->overlay;
1290	if (!overlay) {
1291		drm_dbg(display->drm, "userspace bug: no overlay\n");
1292		return -ENODEV;
1293	}
1294
1295	drm_modeset_lock_all(dev);
1296
1297	ret = -EINVAL;
1298	if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1299		attrs->color_key  = overlay->color_key;
1300		attrs->brightness = overlay->brightness;
1301		attrs->contrast   = overlay->contrast;
1302		attrs->saturation = overlay->saturation;
1303
1304		if (DISPLAY_VER(display) != 2) {
1305			attrs->gamma0 = intel_de_read(display, OGAMC0);
1306			attrs->gamma1 = intel_de_read(display, OGAMC1);
1307			attrs->gamma2 = intel_de_read(display, OGAMC2);
1308			attrs->gamma3 = intel_de_read(display, OGAMC3);
1309			attrs->gamma4 = intel_de_read(display, OGAMC4);
1310			attrs->gamma5 = intel_de_read(display, OGAMC5);
1311		}
1312	} else {
1313		if (attrs->brightness < -128 || attrs->brightness > 127)
1314			goto out_unlock;
1315		if (attrs->contrast > 255)
1316			goto out_unlock;
1317		if (attrs->saturation > 1023)
1318			goto out_unlock;
1319
1320		overlay->color_key  = attrs->color_key;
1321		overlay->brightness = attrs->brightness;
1322		overlay->contrast   = attrs->contrast;
1323		overlay->saturation = attrs->saturation;
1324
1325		update_reg_attrs(overlay, overlay->regs);
1326
1327		if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1328			if (DISPLAY_VER(display) == 2)
1329				goto out_unlock;
1330
1331			if (overlay->active) {
1332				ret = -EBUSY;
1333				goto out_unlock;
1334			}
1335
1336			ret = check_gamma(attrs);
1337			if (ret)
1338				goto out_unlock;
1339
1340			intel_de_write(display, OGAMC0, attrs->gamma0);
1341			intel_de_write(display, OGAMC1, attrs->gamma1);
1342			intel_de_write(display, OGAMC2, attrs->gamma2);
1343			intel_de_write(display, OGAMC3, attrs->gamma3);
1344			intel_de_write(display, OGAMC4, attrs->gamma4);
1345			intel_de_write(display, OGAMC5, attrs->gamma5);
1346		}
1347	}
1348	overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1349
1350	ret = 0;
1351out_unlock:
1352	drm_modeset_unlock_all(dev);
1353
1354	return ret;
1355}
1356
1357static int get_registers(struct intel_overlay *overlay, bool use_phys)
1358{
1359	struct intel_display *display = overlay->display;
1360	struct drm_i915_private *i915 = to_i915(display->drm);
1361	struct drm_i915_gem_object *obj = ERR_PTR(-ENODEV);
1362	struct i915_vma *vma;
1363	int err;
1364
1365	if (!display->platform.meteorlake) /* Wa_22018444074 */
1366		obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
1367	if (IS_ERR(obj))
1368		obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
1369	if (IS_ERR(obj))
1370		return PTR_ERR(obj);
1371
1372	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
1373	if (IS_ERR(vma)) {
1374		err = PTR_ERR(vma);
1375		goto err_put_bo;
1376	}
1377
1378	if (use_phys)
1379		overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl);
1380	else
1381		overlay->flip_addr = i915_ggtt_offset(vma);
1382	overlay->regs = i915_vma_pin_iomap(vma);
1383	i915_vma_unpin(vma);
1384
1385	if (IS_ERR(overlay->regs)) {
1386		err = PTR_ERR(overlay->regs);
1387		goto err_put_bo;
1388	}
1389
1390	overlay->reg_bo = obj;
1391	return 0;
1392
1393err_put_bo:
1394	i915_gem_object_put(obj);
1395	return err;
1396}
1397
1398void intel_overlay_setup(struct intel_display *display)
1399{
1400	struct drm_i915_private *dev_priv = to_i915(display->drm);
1401	struct intel_overlay *overlay;
1402	struct intel_engine_cs *engine;
1403	int ret;
1404
1405	if (!HAS_OVERLAY(display))
1406		return;
1407
1408	engine = to_gt(dev_priv)->engine[RCS0];
1409	if (!engine || !engine->kernel_context)
1410		return;
1411
1412	overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1413	if (!overlay)
1414		return;
1415
1416	overlay->display = display;
1417	overlay->context = engine->kernel_context;
1418	overlay->color_key = 0x0101fe;
1419	overlay->color_key_enabled = true;
1420	overlay->brightness = -19;
1421	overlay->contrast = 75;
1422	overlay->saturation = 146;
1423
1424	i915_active_init(&overlay->last_flip,
1425			 NULL, intel_overlay_last_flip_retire, 0);
1426
1427	ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(display));
1428	if (ret)
1429		goto out_free;
1430
1431	memset_io(overlay->regs, 0, sizeof(struct overlay_registers));
1432	update_polyphase_filter(overlay->regs);
1433	update_reg_attrs(overlay, overlay->regs);
1434
1435	display->overlay = overlay;
1436	drm_info(display->drm, "Initialized overlay support.\n");
1437	return;
1438
1439out_free:
1440	kfree(overlay);
1441}
1442
1443bool intel_overlay_available(struct intel_display *display)
1444{
1445	return display->overlay;
1446}
1447
1448void intel_overlay_cleanup(struct intel_display *display)
1449{
1450	struct intel_overlay *overlay;
1451
1452	overlay = fetch_and_zero(&display->overlay);
1453	if (!overlay)
1454		return;
1455
1456	/*
1457	 * The bo's should be free'd by the generic code already.
1458	 * Furthermore modesetting teardown happens beforehand so the
1459	 * hardware should be off already.
1460	 */
1461	drm_WARN_ON(display->drm, overlay->active);
1462
1463	i915_gem_object_put(overlay->reg_bo);
1464	i915_active_fini(&overlay->last_flip);
1465
1466	kfree(overlay);
1467}
1468
1469#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1470
1471struct intel_overlay_snapshot {
1472	struct overlay_registers regs;
1473	unsigned long base;
1474	u32 dovsta;
1475	u32 isr;
1476};
1477
1478struct intel_overlay_snapshot *
1479intel_overlay_snapshot_capture(struct intel_display *display)
1480{
1481	struct intel_overlay *overlay = display->overlay;
1482	struct intel_overlay_snapshot *error;
1483
1484	if (!overlay || !overlay->active)
1485		return NULL;
1486
1487	error = kmalloc(sizeof(*error), GFP_ATOMIC);
1488	if (error == NULL)
1489		return NULL;
1490
1491	error->dovsta = intel_de_read(display, DOVSTA);
1492	error->isr = intel_de_read(display, GEN2_ISR);
1493	error->base = overlay->flip_addr;
1494
1495	memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));
1496
1497	return error;
1498}
1499
1500void
1501intel_overlay_snapshot_print(const struct intel_overlay_snapshot *error,
1502			     struct drm_printer *p)
1503{
1504	if (!error)
1505		return;
1506
1507	drm_printf(p, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1508		   error->dovsta, error->isr);
1509	drm_printf(p, "  Register file at 0x%08lx:\n", error->base);
1510
1511#define P(x) drm_printf(p, "    " #x ": 0x%08x\n", error->regs.x)
1512	P(OBUF_0Y);
1513	P(OBUF_1Y);
1514	P(OBUF_0U);
1515	P(OBUF_0V);
1516	P(OBUF_1U);
1517	P(OBUF_1V);
1518	P(OSTRIDE);
1519	P(YRGB_VPH);
1520	P(UV_VPH);
1521	P(HORZ_PH);
1522	P(INIT_PHS);
1523	P(DWINPOS);
1524	P(DWINSZ);
1525	P(SWIDTH);
1526	P(SWIDTHSW);
1527	P(SHEIGHT);
1528	P(YRGBSCALE);
1529	P(UVSCALE);
1530	P(OCLRC0);
1531	P(OCLRC1);
1532	P(DCLRKV);
1533	P(DCLRKM);
1534	P(SCLRKVH);
1535	P(SCLRKVL);
1536	P(SCLRKEN);
1537	P(OCONFIG);
1538	P(OCMD);
1539	P(OSTART_0Y);
1540	P(OSTART_1Y);
1541	P(OSTART_0U);
1542	P(OSTART_0V);
1543	P(OSTART_1U);
1544	P(OSTART_1V);
1545	P(OTILEOFF_0Y);
1546	P(OTILEOFF_1Y);
1547	P(OTILEOFF_0U);
1548	P(OTILEOFF_0V);
1549	P(OTILEOFF_1U);
1550	P(OTILEOFF_1V);
1551	P(FASTHSCALE);
1552	P(UVSCALEV);
1553#undef P
1554}
1555
1556#endif