intel_lt_phy_regs.h

 1/* SPDX-License-Identifier: MIT
 2 *
 3 * Copyright © 2025 Intel Corporation
 4 */
 5
 6#ifndef __INTEL_LT_PHY_REGS_H__
 7#define __INTEL_LT_PHY_REGS_H__
 8
 9#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US	500
10#define XE3PLPD_MACCLK_TURNON_LATENCY_MS	2
11#define XE3PLPD_MACCLK_TURNOFF_LATENCY_US	1
12#define XE3PLPD_RATE_CALIB_DONE_LATENCY_MS	1
13#define XE3PLPD_RESET_START_LATENCY_US	10
14#define XE3PLPD_PWRDN_TO_RDY_LATENCY_US	4
15#define XE3PLPD_RESET_END_LATENCY_MS		2
16
17/* LT Phy MAC Register */
18#define LT_PHY_MAC_VDR			_MMIO(0xC00)
19#define    LT_PHY_PCLKIN_GATE		REG_BIT8(0)
20
21/* LT Phy Pipe Spec Registers */
22#define LT_PHY_TXY_CTL8(idx)		(0x408 + (0x200 * (idx)))
23#define  LT_PHY_TX_SWING_LEVEL_MASK	REG_GENMASK8(7, 4)
24#define  LT_PHY_TX_SWING_LEVEL(val)	REG_FIELD_PREP8(LT_PHY_TX_SWING_LEVEL_MASK, val)
25#define  LT_PHY_TX_SWING_MASK		REG_BIT8(3)
26#define  LT_PHY_TX_SWING(val)		REG_FIELD_PREP8(LT_PHY_TX_SWING_MASK, val)
27
28#define LT_PHY_TXY_CTL2(idx)		(0x402 + (0x200 * (idx)))
29#define LT_PHY_TXY_CTL3(idx)		(0x403 + (0x200 * (idx)))
30#define LT_PHY_TXY_CTL4(idx)		(0x404 + (0x200 * (idx)))
31#define  LT_PHY_TX_CURSOR_MASK		REG_GENMASK8(5, 0)
32#define  LT_PHY_TX_CURSOR(val)		REG_FIELD_PREP8(LT_PHY_TX_CURSOR_MASK, val)
33
34#define LT_PHY_TXY_CTL10(idx)		(0x40A + (0x200 * (idx)))
35#define LT_PHY_TXY_CTL10_MAC(idx)	_MMIO(LT_PHY_TXY_CTL10(idx))
36#define  LT_PHY_TX_LANE_ENABLE		REG_BIT8(0)
37
38/* LT Phy Vendor Register */
39#define LT_PHY_VDR_0_CONFIG	0xC02
40#define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
41#define LT_PHY_VDR_1_CONFIG	0xC03
42#define  LT_PHY_VDR_RATE_ENCODING_MASK	REG_GENMASK8(6, 3)
43#define  LT_PHY_VDR_MODE_ENCODING_MASK	REG_GENMASK8(2, 0)
44#define LT_PHY_VDR_2_CONFIG	0xCC3
45
46#define LT_PHY_VDR_X_ADDR_MSB(idx)	(0xC04 + 0x6 * (idx))
47#define LT_PHY_VDR_X_ADDR_LSB(idx)	(0xC05 + 0x6 * (idx))
48
49#define LT_PHY_VDR_X_DATAY(idx, y)	((0xC06 + (3 - (y))) + 0x6 * (idx))
50
51#define LT_PHY_RATE_UPDATE		0xCC4
52#define    LT_PHY_RATE_CONTROL_VDR_UPDATE	REG_BIT8(0)
53
54#define _XE3PLPD_PORT_BUF_CTL5(idx)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
55								 _XELPDP_PORT_BUF_CTL1_LN0_A, \
56								 _XELPDP_PORT_BUF_CTL1_LN0_B, \
57								 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
58								 _XELPDP_PORT_BUF_CTL1_LN0_USBC2) \
59								+ 0x34)
60#define XE3PLPD_PORT_BUF_CTL5(port)	_XE3PLPD_PORT_BUF_CTL5(__xe2lpd_port_idx(port))
61#define  XE3PLPD_MACCLK_RESET_0		REG_BIT(11)
62#define  XE3PLPD_MACCLK_RATE_MASK	REG_GENMASK(4, 0)
63#define  XE3PLPD_MACCLK_RATE_DEF	REG_FIELD_PREP(XE3PLPD_MACCLK_RATE_MASK, 0x1F)
64
65#define _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(idx, lane)	_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
66										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
67										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
68										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
69										 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) \
70										 + 0x60 + (lane) * 0x4)
71#define XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(port, lane)	 _XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(__xe2lpd_port_idx(port), \
72											    lane)
73#define   XE3LPD_PORT_P2M_ADDR_MASK			REG_GENMASK(11, 0)
74
75#define PLL_REG4_ADDR		0x8510
76#define PLL_REG3_ADDR		0x850C
77#define PLL_REG5_ADDR		0x8514
78#define PLL_REG57_ADDR		0x85E4
79#define PLL_LF_ADDR		0x860C
80#define PLL_TDC_ADDR		0x8610
81#define PLL_SSC_ADDR		0x8614
82#define PLL_BIAS2_ADDR		0x8618
83#define PLL_BIAS_TRIM_ADDR	0x8648
84#define PLL_DCO_MED_ADDR	0x8640
85#define PLL_DCO_FINE_ADDR	0x864C
86#define PLL_SSC_INJ_ADDR	0x8624
87#define PLL_SURV_BONUS_ADDR	0x8644
88#define PLL_TYPE_OFFSET		0x200
89#define PLL_REG_ADDR(base, pll_type)		((pll_type) ? (base) + PLL_TYPE_OFFSET : (base))
90#endif /* __INTEL_LT_PHY_REGS_H__ */