intel_gmbus.c

   1/*
   2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3 * Copyright © 2006-2008,2010 Intel Corporation
   4 *   Jesse Barnes <jesse.barnes@intel.com>
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a
   7 * copy of this software and associated documentation files (the "Software"),
   8 * to deal in the Software without restriction, including without limitation
   9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10 * and/or sell copies of the Software, and to permit persons to whom the
  11 * Software is furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice (including the next
  14 * paragraph) shall be included in all copies or substantial portions of the
  15 * Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23 * DEALINGS IN THE SOFTWARE.
  24 *
  25 * Authors:
  26 *	Eric Anholt <eric@anholt.net>
  27 *	Chris Wilson <chris@chris-wilson.co.uk>
  28 */
  29
  30#include <linux/export.h>
  31#include <linux/i2c-algo-bit.h>
  32#include <linux/i2c.h>
  33#include <linux/iopoll.h>
  34
  35#include <drm/drm_print.h>
  36#include <drm/display/drm_hdcp_helper.h>
  37
  38#include "i915_drv.h"
  39#include "i915_irq.h"
  40#include "i915_reg.h"
  41#include "intel_de.h"
  42#include "intel_display_regs.h"
  43#include "intel_display_types.h"
  44#include "intel_display_wa.h"
  45#include "intel_gmbus.h"
  46#include "intel_gmbus_regs.h"
  47
  48struct intel_gmbus {
  49	struct i2c_adapter adapter;
  50#define GMBUS_FORCE_BIT_RETRY (1U << 31)
  51	u32 force_bit;
  52	u32 reg0;
  53	i915_reg_t gpio_reg;
  54	struct i2c_algo_bit_data bit_algo;
  55	struct intel_display *display;
  56};
  57
  58enum gmbus_gpio {
  59	GPIOA,
  60	GPIOB,
  61	GPIOC,
  62	GPIOD,
  63	GPIOE,
  64	GPIOF,
  65	GPIOG,
  66	GPIOH,
  67	__GPIOI_UNUSED,
  68	GPIOJ,
  69	GPIOK,
  70	GPIOL,
  71	GPIOM,
  72	GPION,
  73	GPIOO,
  74};
  75
  76struct gmbus_pin {
  77	const char *name;
  78	enum gmbus_gpio gpio;
  79};
  80
  81/* Map gmbus pin pairs to names and registers. */
  82static const struct gmbus_pin gmbus_pins[] = {
  83	[GMBUS_PIN_SSC] = { "ssc", GPIOB },
  84	[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
  85	[GMBUS_PIN_PANEL] = { "panel", GPIOC },
  86	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
  87	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
  88	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
  89};
  90
  91static const struct gmbus_pin gmbus_pins_bdw[] = {
  92	[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
  93	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
  94	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
  95	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
  96};
  97
  98static const struct gmbus_pin gmbus_pins_skl[] = {
  99	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
 100	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
 101	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
 102};
 103
 104static const struct gmbus_pin gmbus_pins_bxt[] = {
 105	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
 106	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
 107	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
 108};
 109
 110static const struct gmbus_pin gmbus_pins_cnp[] = {
 111	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
 112	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
 113	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
 114	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
 115};
 116
 117static const struct gmbus_pin gmbus_pins_icp[] = {
 118	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
 119	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
 120	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
 121	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
 122	[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
 123	[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
 124	[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
 125	[GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
 126	[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
 127};
 128
 129static const struct gmbus_pin gmbus_pins_dg1[] = {
 130	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
 131	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
 132	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
 133	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
 134};
 135
 136static const struct gmbus_pin gmbus_pins_dg2[] = {
 137	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
 138	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
 139	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
 140	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
 141	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
 142};
 143
 144static const struct gmbus_pin gmbus_pins_mtp[] = {
 145	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
 146	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
 147	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
 148	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
 149	[GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
 150	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
 151	[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
 152	[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
 153	[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
 154};
 155
 156static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display,
 157					     unsigned int pin)
 158{
 159	const struct gmbus_pin *pins;
 160	size_t size;
 161
 162	if (INTEL_PCH_TYPE(display) >= PCH_MTL) {
 163		pins = gmbus_pins_mtp;
 164		size = ARRAY_SIZE(gmbus_pins_mtp);
 165	} else if (INTEL_PCH_TYPE(display) >= PCH_DG2) {
 166		pins = gmbus_pins_dg2;
 167		size = ARRAY_SIZE(gmbus_pins_dg2);
 168	} else if (INTEL_PCH_TYPE(display) >= PCH_DG1) {
 169		pins = gmbus_pins_dg1;
 170		size = ARRAY_SIZE(gmbus_pins_dg1);
 171	} else if (INTEL_PCH_TYPE(display) >= PCH_ICP) {
 172		pins = gmbus_pins_icp;
 173		size = ARRAY_SIZE(gmbus_pins_icp);
 174	} else if (HAS_PCH_CNP(display)) {
 175		pins = gmbus_pins_cnp;
 176		size = ARRAY_SIZE(gmbus_pins_cnp);
 177	} else if (display->platform.geminilake || display->platform.broxton) {
 178		pins = gmbus_pins_bxt;
 179		size = ARRAY_SIZE(gmbus_pins_bxt);
 180	} else if (DISPLAY_VER(display) == 9) {
 181		pins = gmbus_pins_skl;
 182		size = ARRAY_SIZE(gmbus_pins_skl);
 183	} else if (display->platform.broadwell) {
 184		pins = gmbus_pins_bdw;
 185		size = ARRAY_SIZE(gmbus_pins_bdw);
 186	} else {
 187		pins = gmbus_pins;
 188		size = ARRAY_SIZE(gmbus_pins);
 189	}
 190
 191	if (pin >= size || !pins[pin].name)
 192		return NULL;
 193
 194	return &pins[pin];
 195}
 196
 197bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin)
 198{
 199	return get_gmbus_pin(display, pin);
 200}
 201
 202/* Intel GPIO access functions */
 203
 204#define I2C_RISEFALL_TIME 10
 205
 206static inline struct intel_gmbus *
 207to_intel_gmbus(struct i2c_adapter *i2c)
 208{
 209	return container_of(i2c, struct intel_gmbus, adapter);
 210}
 211
 212void
 213intel_gmbus_reset(struct intel_display *display)
 214{
 215	intel_de_write(display, GMBUS0(display), 0);
 216	intel_de_write(display, GMBUS4(display), 0);
 217}
 218
 219static void pnv_gmbus_clock_gating(struct intel_display *display,
 220				   bool enable)
 221{
 222	/* When using bit bashing for I2C, this bit needs to be set to 1 */
 223	intel_de_rmw(display, DSPCLK_GATE_D,
 224		     PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
 225		     !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
 226}
 227
 228static void pch_gmbus_clock_gating(struct intel_display *display,
 229				   bool enable)
 230{
 231	intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
 232		     PCH_GMBUSUNIT_CLOCK_GATE_DISABLE,
 233		     !enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
 234}
 235
 236static void bxt_gmbus_clock_gating(struct intel_display *display,
 237				   bool enable)
 238{
 239	intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,
 240		     !enable ? BXT_GMBUS_GATING_DIS : 0);
 241}
 242
 243static u32 get_reserved(struct intel_gmbus *bus)
 244{
 245	struct intel_display *display = bus->display;
 246	u32 preserve_bits = 0;
 247
 248	if (display->platform.i830 || display->platform.i845g)
 249		return 0;
 250
 251	/* On most chips, these bits must be preserved in software. */
 252	preserve_bits |= GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE;
 253
 254	/* Wa_16025573575: the masks bits need to be preserved through out */
 255	if (intel_display_wa(display, 16025573575))
 256		preserve_bits |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK |
 257				 GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK;
 258
 259	return intel_de_read_notrace(display, bus->gpio_reg) & preserve_bits;
 260}
 261
 262static int get_clock(void *data)
 263{
 264	struct intel_gmbus *bus = data;
 265	struct intel_display *display = bus->display;
 266	u32 reserved = get_reserved(bus);
 267
 268	intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
 269	intel_de_write_notrace(display, bus->gpio_reg, reserved);
 270
 271	return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
 272}
 273
 274static int get_data(void *data)
 275{
 276	struct intel_gmbus *bus = data;
 277	struct intel_display *display = bus->display;
 278	u32 reserved = get_reserved(bus);
 279
 280	intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
 281	intel_de_write_notrace(display, bus->gpio_reg, reserved);
 282
 283	return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
 284}
 285
 286static void set_clock(void *data, int state_high)
 287{
 288	struct intel_gmbus *bus = data;
 289	struct intel_display *display = bus->display;
 290	u32 reserved = get_reserved(bus);
 291	u32 clock_bits;
 292
 293	if (state_high)
 294		clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
 295	else
 296		clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
 297			     GPIO_CLOCK_VAL_MASK;
 298
 299	intel_de_write_notrace(display, bus->gpio_reg, reserved | clock_bits);
 300	intel_de_posting_read(display, bus->gpio_reg);
 301}
 302
 303static void set_data(void *data, int state_high)
 304{
 305	struct intel_gmbus *bus = data;
 306	struct intel_display *display = bus->display;
 307	u32 reserved = get_reserved(bus);
 308	u32 data_bits;
 309
 310	if (state_high)
 311		data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
 312	else
 313		data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
 314			GPIO_DATA_VAL_MASK;
 315
 316	intel_de_write_notrace(display, bus->gpio_reg, reserved | data_bits);
 317	intel_de_posting_read(display, bus->gpio_reg);
 318}
 319
 320static void
 321ptl_handle_mask_bits(struct intel_gmbus *bus, bool set)
 322{
 323	struct intel_display *display = bus->display;
 324	u32 reg_val = intel_de_read_notrace(display, bus->gpio_reg);
 325	u32 mask_bits = GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK |
 326			GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK;
 327	if (set)
 328		reg_val |= mask_bits;
 329	else
 330		reg_val &= ~mask_bits;
 331
 332	intel_de_write_notrace(display, bus->gpio_reg, reg_val);
 333	intel_de_posting_read(display, bus->gpio_reg);
 334}
 335
 336static int
 337intel_gpio_pre_xfer(struct i2c_adapter *adapter)
 338{
 339	struct intel_gmbus *bus = to_intel_gmbus(adapter);
 340	struct intel_display *display = bus->display;
 341
 342	intel_gmbus_reset(display);
 343
 344	if (display->platform.pineview)
 345		pnv_gmbus_clock_gating(display, false);
 346
 347	if (intel_display_wa(display, 16025573575))
 348		ptl_handle_mask_bits(bus, true);
 349
 350	set_data(bus, 1);
 351	set_clock(bus, 1);
 352	udelay(I2C_RISEFALL_TIME);
 353	return 0;
 354}
 355
 356static void
 357intel_gpio_post_xfer(struct i2c_adapter *adapter)
 358{
 359	struct intel_gmbus *bus = to_intel_gmbus(adapter);
 360	struct intel_display *display = bus->display;
 361
 362	set_data(bus, 1);
 363	set_clock(bus, 1);
 364
 365	if (display->platform.pineview)
 366		pnv_gmbus_clock_gating(display, true);
 367
 368	if (intel_display_wa(display, 16025573575))
 369		ptl_handle_mask_bits(bus, false);
 370}
 371
 372static void
 373intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg)
 374{
 375	struct i2c_algo_bit_data *algo;
 376
 377	algo = &bus->bit_algo;
 378
 379	bus->gpio_reg = gpio_reg;
 380	bus->adapter.algo_data = algo;
 381	algo->setsda = set_data;
 382	algo->setscl = set_clock;
 383	algo->getsda = get_data;
 384	algo->getscl = get_clock;
 385	algo->pre_xfer = intel_gpio_pre_xfer;
 386	algo->post_xfer = intel_gpio_post_xfer;
 387	algo->udelay = I2C_RISEFALL_TIME;
 388	algo->timeout = usecs_to_jiffies(2200);
 389	algo->data = bus;
 390}
 391
 392static bool has_gmbus_irq(struct intel_display *display)
 393{
 394	struct drm_i915_private *i915 = to_i915(display->drm);
 395	/*
 396	 * encoder->shutdown() may want to use GMBUS
 397	 * after irqs have already been disabled.
 398	 */
 399	return HAS_GMBUS_IRQ(display) && intel_irqs_enabled(i915);
 400}
 401
 402static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en)
 403{
 404	DEFINE_WAIT(wait);
 405	u32 gmbus2;
 406	int ret;
 407
 408	/* Important: The hw handles only the first bit, so set only one! Since
 409	 * we also need to check for NAKs besides the hw ready/idle signal, we
 410	 * need to wake up periodically and check that ourselves.
 411	 */
 412	if (!has_gmbus_irq(display))
 413		irq_en = 0;
 414
 415	add_wait_queue(&display->gmbus.wait_queue, &wait);
 416	intel_de_write_fw(display, GMBUS4(display), irq_en);
 417
 418	status |= GMBUS_SATOER;
 419
 420	ret = poll_timeout_us_atomic(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),
 421				     gmbus2 & status,
 422				     0, 2, false);
 423	if (ret)
 424		ret = poll_timeout_us(gmbus2 = intel_de_read_fw(display, GMBUS2(display)),
 425				      gmbus2 & status,
 426				      500, 50 * 1000, false);
 427
 428	intel_de_write_fw(display, GMBUS4(display), 0);
 429	remove_wait_queue(&display->gmbus.wait_queue, &wait);
 430
 431	if (gmbus2 & GMBUS_SATOER)
 432		return -ENXIO;
 433
 434	return ret;
 435}
 436
 437static int
 438gmbus_wait_idle(struct intel_display *display)
 439{
 440	DEFINE_WAIT(wait);
 441	u32 irq_enable;
 442	int ret;
 443
 444	/* Important: The hw handles only the first bit, so set only one! */
 445	irq_enable = 0;
 446	if (has_gmbus_irq(display))
 447		irq_enable = GMBUS_IDLE_EN;
 448
 449	add_wait_queue(&display->gmbus.wait_queue, &wait);
 450	intel_de_write_fw(display, GMBUS4(display), irq_enable);
 451
 452	ret = intel_de_wait_fw_ms(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10, NULL);
 453
 454	intel_de_write_fw(display, GMBUS4(display), 0);
 455	remove_wait_queue(&display->gmbus.wait_queue, &wait);
 456
 457	return ret;
 458}
 459
 460static unsigned int gmbus_max_xfer_size(struct intel_display *display)
 461{
 462	return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
 463	       GMBUS_BYTE_COUNT_MAX;
 464}
 465
 466static int
 467gmbus_xfer_read_chunk(struct intel_display *display,
 468		      unsigned short addr, u8 *buf, unsigned int len,
 469		      u32 gmbus0_reg, u32 gmbus1_index)
 470{
 471	unsigned int size = len;
 472	bool burst_read = len > gmbus_max_xfer_size(display);
 473	bool extra_byte_added = false;
 474
 475	if (burst_read) {
 476		/*
 477		 * As per HW Spec, for 512Bytes need to read extra Byte and
 478		 * Ignore the extra byte read.
 479		 */
 480		if (len == 512) {
 481			extra_byte_added = true;
 482			len++;
 483		}
 484		size = len % 256 + 256;
 485		intel_de_write_fw(display, GMBUS0(display),
 486				  gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
 487	}
 488
 489	intel_de_write_fw(display, GMBUS1(display),
 490			  gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
 491	while (len) {
 492		int ret;
 493		u32 val, loop = 0;
 494
 495		ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
 496		if (ret)
 497			return ret;
 498
 499		val = intel_de_read_fw(display, GMBUS3(display));
 500		do {
 501			if (extra_byte_added && len == 1) {
 502				len--;
 503				break;
 504			}
 505
 506			*buf++ = val & 0xff;
 507			val >>= 8;
 508		} while (--len && ++loop < 4);
 509
 510		if (burst_read && len == size - 4)
 511			/* Reset the override bit */
 512			intel_de_write_fw(display, GMBUS0(display), gmbus0_reg);
 513	}
 514
 515	return 0;
 516}
 517
 518/*
 519 * HW spec says that 512Bytes in Burst read need special treatment.
 520 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
 521 * an I2C target, which supports such a lengthy burst read too for experiments.
 522 *
 523 * So until things get clarified on HW support, to avoid the burst read length
 524 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
 525 */
 526#define INTEL_GMBUS_BURST_READ_MAX_LEN		767U
 527
 528static int
 529gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg,
 530		u32 gmbus0_reg, u32 gmbus1_index)
 531{
 532	u8 *buf = msg->buf;
 533	unsigned int rx_size = msg->len;
 534	unsigned int len;
 535	int ret;
 536
 537	do {
 538		if (HAS_GMBUS_BURST_READ(display))
 539			len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
 540		else
 541			len = min(rx_size, gmbus_max_xfer_size(display));
 542
 543		ret = gmbus_xfer_read_chunk(display, msg->addr, buf, len,
 544					    gmbus0_reg, gmbus1_index);
 545		if (ret)
 546			return ret;
 547
 548		rx_size -= len;
 549		buf += len;
 550	} while (rx_size != 0);
 551
 552	return 0;
 553}
 554
 555static int
 556gmbus_xfer_write_chunk(struct intel_display *display,
 557		       unsigned short addr, u8 *buf, unsigned int len,
 558		       u32 gmbus1_index)
 559{
 560	unsigned int chunk_size = len;
 561	u32 val, loop;
 562
 563	val = loop = 0;
 564	while (len && loop < 4) {
 565		val |= *buf++ << (8 * loop++);
 566		len -= 1;
 567	}
 568
 569	intel_de_write_fw(display, GMBUS3(display), val);
 570	intel_de_write_fw(display, GMBUS1(display),
 571			  gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
 572	while (len) {
 573		int ret;
 574
 575		val = loop = 0;
 576		do {
 577			val |= *buf++ << (8 * loop);
 578		} while (--len && ++loop < 4);
 579
 580		intel_de_write_fw(display, GMBUS3(display), val);
 581
 582		ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
 583		if (ret)
 584			return ret;
 585	}
 586
 587	return 0;
 588}
 589
 590static int
 591gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg,
 592		 u32 gmbus1_index)
 593{
 594	u8 *buf = msg->buf;
 595	unsigned int tx_size = msg->len;
 596	unsigned int len;
 597	int ret;
 598
 599	do {
 600		len = min(tx_size, gmbus_max_xfer_size(display));
 601
 602		ret = gmbus_xfer_write_chunk(display, msg->addr, buf, len,
 603					     gmbus1_index);
 604		if (ret)
 605			return ret;
 606
 607		buf += len;
 608		tx_size -= len;
 609	} while (tx_size != 0);
 610
 611	return 0;
 612}
 613
 614/*
 615 * The gmbus controller can combine a 1 or 2 byte write with another read/write
 616 * that immediately follows it by using an "INDEX" cycle.
 617 */
 618static bool
 619gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
 620{
 621	return (i + 1 < num &&
 622		msgs[i].addr == msgs[i + 1].addr &&
 623		!(msgs[i].flags & I2C_M_RD) &&
 624		(msgs[i].len == 1 || msgs[i].len == 2) &&
 625		msgs[i + 1].len > 0);
 626}
 627
 628static int
 629gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs,
 630		 u32 gmbus0_reg)
 631{
 632	u32 gmbus1_index = 0;
 633	u32 gmbus5 = 0;
 634	int ret;
 635
 636	if (msgs[0].len == 2)
 637		gmbus5 = GMBUS_2BYTE_INDEX_EN |
 638			 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
 639	if (msgs[0].len == 1)
 640		gmbus1_index = GMBUS_CYCLE_INDEX |
 641			       (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
 642
 643	/* GMBUS5 holds 16-bit index */
 644	if (gmbus5)
 645		intel_de_write_fw(display, GMBUS5(display), gmbus5);
 646
 647	if (msgs[1].flags & I2C_M_RD)
 648		ret = gmbus_xfer_read(display, &msgs[1], gmbus0_reg,
 649				      gmbus1_index);
 650	else
 651		ret = gmbus_xfer_write(display, &msgs[1], gmbus1_index);
 652
 653	/* Clear GMBUS5 after each index transfer */
 654	if (gmbus5)
 655		intel_de_write_fw(display, GMBUS5(display), 0);
 656
 657	return ret;
 658}
 659
 660static int
 661do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
 662	      u32 gmbus0_source)
 663{
 664	struct intel_gmbus *bus = to_intel_gmbus(adapter);
 665	struct intel_display *display = bus->display;
 666	int i = 0, inc, try = 0;
 667	int ret = 0;
 668
 669	/* Display WA #0868: skl,bxt,kbl,cfl,glk */
 670	if (display->platform.geminilake || display->platform.broxton)
 671		bxt_gmbus_clock_gating(display, false);
 672	else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display))
 673		pch_gmbus_clock_gating(display, false);
 674
 675retry:
 676	intel_de_write_fw(display, GMBUS0(display), gmbus0_source | bus->reg0);
 677
 678	for (; i < num; i += inc) {
 679		inc = 1;
 680		if (gmbus_is_index_xfer(msgs, i, num)) {
 681			ret = gmbus_index_xfer(display, &msgs[i],
 682					       gmbus0_source | bus->reg0);
 683			inc = 2; /* an index transmission is two msgs */
 684		} else if (msgs[i].flags & I2C_M_RD) {
 685			ret = gmbus_xfer_read(display, &msgs[i],
 686					      gmbus0_source | bus->reg0, 0);
 687		} else {
 688			ret = gmbus_xfer_write(display, &msgs[i], 0);
 689		}
 690
 691		if (!ret)
 692			ret = gmbus_wait(display,
 693					 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
 694		if (ret == -ETIMEDOUT)
 695			goto timeout;
 696		else if (ret)
 697			goto clear_err;
 698	}
 699
 700	/* Generate a STOP condition on the bus. Note that gmbus can't generata
 701	 * a STOP on the very first cycle. To simplify the code we
 702	 * unconditionally generate the STOP condition with an additional gmbus
 703	 * cycle. */
 704	intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
 705
 706	/* Mark the GMBUS interface as disabled after waiting for idle.
 707	 * We will re-enable it at the start of the next xfer,
 708	 * till then let it sleep.
 709	 */
 710	if (gmbus_wait_idle(display)) {
 711		drm_dbg_kms(display->drm,
 712			    "GMBUS [%s] timed out waiting for idle\n",
 713			    adapter->name);
 714		ret = -ETIMEDOUT;
 715	}
 716	intel_de_write_fw(display, GMBUS0(display), 0);
 717	ret = ret ?: i;
 718	goto out;
 719
 720clear_err:
 721	/*
 722	 * Wait for bus to IDLE before clearing NAK.
 723	 * If we clear the NAK while bus is still active, then it will stay
 724	 * active and the next transaction may fail.
 725	 *
 726	 * If no ACK is received during the address phase of a transaction, the
 727	 * adapter must report -ENXIO. It is not clear what to return if no ACK
 728	 * is received at other times. But we have to be careful to not return
 729	 * spurious -ENXIO because that will prevent i2c and drm edid functions
 730	 * from retrying. So return -ENXIO only when gmbus properly quiescents -
 731	 * timing out seems to happen when there _is_ a ddc chip present, but
 732	 * it's slow responding and only answers on the 2nd retry.
 733	 */
 734	ret = -ENXIO;
 735	if (gmbus_wait_idle(display)) {
 736		drm_dbg_kms(display->drm,
 737			    "GMBUS [%s] timed out after NAK\n",
 738			    adapter->name);
 739		ret = -ETIMEDOUT;
 740	}
 741
 742	/* Toggle the Software Clear Interrupt bit. This has the effect
 743	 * of resetting the GMBUS controller and so clearing the
 744	 * BUS_ERROR raised by the target's NAK.
 745	 */
 746	intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT);
 747	intel_de_write_fw(display, GMBUS1(display), 0);
 748	intel_de_write_fw(display, GMBUS0(display), 0);
 749
 750	drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
 751		    adapter->name, msgs[i].addr,
 752		    (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
 753
 754	/*
 755	 * Passive adapters sometimes NAK the first probe. Retry the first
 756	 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
 757	 * has retries internally. See also the retry loop in
 758	 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
 759	 */
 760	if (ret == -ENXIO && i == 0 && try++ == 0) {
 761		drm_dbg_kms(display->drm,
 762			    "GMBUS [%s] NAK on first message, retry\n",
 763			    adapter->name);
 764		goto retry;
 765	}
 766
 767	goto out;
 768
 769timeout:
 770	drm_dbg_kms(display->drm,
 771		    "GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
 772		    bus->adapter.name, bus->reg0 & 0xff);
 773	intel_de_write_fw(display, GMBUS0(display), 0);
 774
 775	/*
 776	 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
 777	 * instead. Use EAGAIN to have i2c core retry.
 778	 */
 779	ret = -EAGAIN;
 780
 781out:
 782	/* Display WA #0868: skl,bxt,kbl,cfl,glk */
 783	if (display->platform.geminilake || display->platform.broxton)
 784		bxt_gmbus_clock_gating(display, true);
 785	else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display))
 786		pch_gmbus_clock_gating(display, true);
 787
 788	return ret;
 789}
 790
 791static int
 792gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
 793{
 794	struct intel_gmbus *bus = to_intel_gmbus(adapter);
 795	struct intel_display *display = bus->display;
 796	intel_wakeref_t wakeref;
 797	int ret;
 798
 799	wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS);
 800
 801	if (bus->force_bit) {
 802		ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
 803		if (ret < 0)
 804			bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
 805	} else {
 806		ret = do_gmbus_xfer(adapter, msgs, num, 0);
 807		if (ret == -EAGAIN)
 808			bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
 809	}
 810
 811	intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);
 812
 813	return ret;
 814}
 815
 816int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
 817{
 818	struct intel_gmbus *bus = to_intel_gmbus(adapter);
 819	struct intel_display *display = bus->display;
 820	u8 cmd = DRM_HDCP_DDC_AKSV;
 821	u8 buf[DRM_HDCP_KSV_LEN] = {};
 822	struct i2c_msg msgs[] = {
 823		{
 824			.addr = DRM_HDCP_DDC_ADDR,
 825			.flags = 0,
 826			.len = sizeof(cmd),
 827			.buf = &cmd,
 828		},
 829		{
 830			.addr = DRM_HDCP_DDC_ADDR,
 831			.flags = 0,
 832			.len = sizeof(buf),
 833			.buf = buf,
 834		}
 835	};
 836	intel_wakeref_t wakeref;
 837	int ret;
 838
 839	wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS);
 840	mutex_lock(&display->gmbus.mutex);
 841
 842	/*
 843	 * In order to output Aksv to the receiver, use an indexed write to
 844	 * pass the i2c command, and tell GMBUS to use the HW-provided value
 845	 * instead of sourcing GMBUS3 for the data.
 846	 */
 847	ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
 848
 849	mutex_unlock(&display->gmbus.mutex);
 850	intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);
 851
 852	return ret;
 853}
 854
 855static u32 gmbus_func(struct i2c_adapter *adapter)
 856{
 857	return i2c_bit_algo.functionality(adapter) &
 858		(I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 859		/* I2C_FUNC_10BIT_ADDR | */
 860		I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 861		I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
 862}
 863
 864static const struct i2c_algorithm gmbus_algorithm = {
 865	.master_xfer	= gmbus_xfer,
 866	.functionality	= gmbus_func
 867};
 868
 869static void gmbus_lock_bus(struct i2c_adapter *adapter,
 870			   unsigned int flags)
 871{
 872	struct intel_gmbus *bus = to_intel_gmbus(adapter);
 873	struct intel_display *display = bus->display;
 874
 875	mutex_lock(&display->gmbus.mutex);
 876}
 877
 878static int gmbus_trylock_bus(struct i2c_adapter *adapter,
 879			     unsigned int flags)
 880{
 881	struct intel_gmbus *bus = to_intel_gmbus(adapter);
 882	struct intel_display *display = bus->display;
 883
 884	return mutex_trylock(&display->gmbus.mutex);
 885}
 886
 887static void gmbus_unlock_bus(struct i2c_adapter *adapter,
 888			     unsigned int flags)
 889{
 890	struct intel_gmbus *bus = to_intel_gmbus(adapter);
 891	struct intel_display *display = bus->display;
 892
 893	mutex_unlock(&display->gmbus.mutex);
 894}
 895
 896static const struct i2c_lock_operations gmbus_lock_ops = {
 897	.lock_bus =    gmbus_lock_bus,
 898	.trylock_bus = gmbus_trylock_bus,
 899	.unlock_bus =  gmbus_unlock_bus,
 900};
 901
 902/**
 903 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 904 * @display: display device
 905 */
 906int intel_gmbus_setup(struct intel_display *display)
 907{
 908	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
 909	unsigned int pin;
 910	int ret;
 911
 912	if (display->platform.valleyview || display->platform.cherryview)
 913		display->gmbus.mmio_base = VLV_DISPLAY_BASE;
 914	else if (!HAS_GMCH(display))
 915		/*
 916		 * Broxton uses the same PCH offsets for South Display Engine,
 917		 * even though it doesn't have a PCH.
 918		 */
 919		display->gmbus.mmio_base = PCH_DISPLAY_BASE;
 920
 921	mutex_init(&display->gmbus.mutex);
 922	init_waitqueue_head(&display->gmbus.wait_queue);
 923
 924	for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
 925		const struct gmbus_pin *gmbus_pin;
 926		struct intel_gmbus *bus;
 927
 928		gmbus_pin = get_gmbus_pin(display, pin);
 929		if (!gmbus_pin)
 930			continue;
 931
 932		bus = kzalloc(sizeof(*bus), GFP_KERNEL);
 933		if (!bus) {
 934			ret = -ENOMEM;
 935			goto err;
 936		}
 937
 938		bus->adapter.owner = THIS_MODULE;
 939		snprintf(bus->adapter.name,
 940			 sizeof(bus->adapter.name),
 941			 "i915 gmbus %s", gmbus_pin->name);
 942
 943		bus->adapter.dev.parent = &pdev->dev;
 944		bus->display = display;
 945
 946		bus->adapter.algo = &gmbus_algorithm;
 947		bus->adapter.lock_ops = &gmbus_lock_ops;
 948
 949		/*
 950		 * We wish to retry with bit banging
 951		 * after a timed out GMBUS attempt.
 952		 */
 953		bus->adapter.retries = 1;
 954
 955		/* By default use a conservative clock rate */
 956		bus->reg0 = pin | GMBUS_RATE_100KHZ;
 957
 958		/* gmbus seems to be broken on i830 */
 959		if (display->platform.i830)
 960			bus->force_bit = 1;
 961
 962		intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio));
 963
 964		ret = i2c_add_adapter(&bus->adapter);
 965		if (ret) {
 966			kfree(bus);
 967			goto err;
 968		}
 969
 970		display->gmbus.bus[pin] = bus;
 971	}
 972
 973	intel_gmbus_reset(display);
 974
 975	return 0;
 976
 977err:
 978	intel_gmbus_teardown(display);
 979
 980	return ret;
 981}
 982
 983struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display,
 984					    unsigned int pin)
 985{
 986	if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) ||
 987			!display->gmbus.bus[pin]))
 988		return NULL;
 989
 990	return &display->gmbus.bus[pin]->adapter;
 991}
 992
 993void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
 994{
 995	struct intel_gmbus *bus = to_intel_gmbus(adapter);
 996	struct intel_display *display = bus->display;
 997
 998	mutex_lock(&display->gmbus.mutex);
 999
1000	bus->force_bit += force_bit ? 1 : -1;
1001	drm_dbg_kms(display->drm,
1002		    "%sabling bit-banging on %s. force bit now %d\n",
1003		    force_bit ? "en" : "dis", adapter->name,
1004		    bus->force_bit);
1005
1006	mutex_unlock(&display->gmbus.mutex);
1007}
1008
1009bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1010{
1011	struct intel_gmbus *bus = to_intel_gmbus(adapter);
1012
1013	return bus->force_bit;
1014}
1015
1016void intel_gmbus_teardown(struct intel_display *display)
1017{
1018	unsigned int pin;
1019
1020	for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
1021		struct intel_gmbus *bus;
1022
1023		bus = display->gmbus.bus[pin];
1024		if (!bus)
1025			continue;
1026
1027		i2c_del_adapter(&bus->adapter);
1028
1029		kfree(bus);
1030		display->gmbus.bus[pin] = NULL;
1031	}
1032}
1033
1034void intel_gmbus_irq_handler(struct intel_display *display)
1035{
1036	wake_up_all(&display->gmbus.wait_queue);
1037}