intel_fifo_underrun.c

  1/*
  2 * Copyright © 2014 Intel Corporation
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 21 * IN THE SOFTWARE.
 22 *
 23 * Authors:
 24 *    Daniel Vetter <daniel.vetter@ffwll.ch>
 25 *
 26 */
 27
 28#include <drm/drm_print.h>
 29
 30#include "i915_reg.h"
 31#include "intel_de.h"
 32#include "intel_display_irq.h"
 33#include "intel_display_regs.h"
 34#include "intel_display_trace.h"
 35#include "intel_display_types.h"
 36#include "intel_fbc.h"
 37#include "intel_fifo_underrun.h"
 38#include "intel_pch_display.h"
 39
 40/**
 41 * DOC: fifo underrun handling
 42 *
 43 * The i915 driver checks for display fifo underruns using the interrupt signals
 44 * provided by the hardware. This is enabled by default and fairly useful to
 45 * debug display issues, especially watermark settings.
 46 *
 47 * If an underrun is detected this is logged into dmesg. To avoid flooding logs
 48 * and occupying the cpu underrun interrupts are disabled after the first
 49 * occurrence until the next modeset on a given pipe.
 50 *
 51 * Note that underrun detection on gmch platforms is a bit more ugly since there
 52 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
 53 * interrupt register). Also on some other platforms underrun interrupts are
 54 * shared, which means that if we detect an underrun we need to disable underrun
 55 * reporting on all pipes.
 56 *
 57 * The code also supports underrun detection on the PCH transcoder.
 58 */
 59
 60static bool ivb_can_enable_err_int(struct intel_display *display)
 61{
 62	struct intel_crtc *crtc;
 63	enum pipe pipe;
 64
 65	lockdep_assert_held(&display->irq.lock);
 66
 67	for_each_pipe(display, pipe) {
 68		crtc = intel_crtc_for_pipe(display, pipe);
 69
 70		if (crtc->cpu_fifo_underrun_disabled)
 71			return false;
 72	}
 73
 74	return true;
 75}
 76
 77static bool cpt_can_enable_serr_int(struct intel_display *display)
 78{
 79	enum pipe pipe;
 80	struct intel_crtc *crtc;
 81
 82	lockdep_assert_held(&display->irq.lock);
 83
 84	for_each_pipe(display, pipe) {
 85		crtc = intel_crtc_for_pipe(display, pipe);
 86
 87		if (crtc->pch_fifo_underrun_disabled)
 88			return false;
 89	}
 90
 91	return true;
 92}
 93
 94static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
 95{
 96	struct intel_display *display = to_intel_display(crtc);
 97	i915_reg_t reg = PIPESTAT(display, crtc->pipe);
 98	u32 enable_mask;
 99
100	lockdep_assert_held(&display->irq.lock);
101
102	if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
103		return;
104
105	enable_mask = i915_pipestat_enable_mask(display, crtc->pipe);
106	intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
107	intel_de_posting_read(display, reg);
108
109	trace_intel_cpu_fifo_underrun(display, crtc->pipe);
110	drm_err(display->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));
111}
112
113static void i9xx_set_fifo_underrun_reporting(struct intel_display *display,
114					     enum pipe pipe,
115					     bool enable, bool old)
116{
117	i915_reg_t reg = PIPESTAT(display, pipe);
118
119	lockdep_assert_held(&display->irq.lock);
120
121	if (enable) {
122		u32 enable_mask = i915_pipestat_enable_mask(display, pipe);
123
124		intel_de_write(display, reg,
125			       enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
126		intel_de_posting_read(display, reg);
127	} else {
128		if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS)
129			drm_err(display->drm, "pipe %c underrun\n",
130				pipe_name(pipe));
131	}
132}
133
134static void ilk_set_fifo_underrun_reporting(struct intel_display *display,
135					    enum pipe pipe, bool enable)
136{
137	u32 bit = (pipe == PIPE_A) ?
138		DE_PIPEA_FIFO_UNDERRUN : DE_PIPEB_FIFO_UNDERRUN;
139
140	if (enable)
141		ilk_enable_display_irq(display, bit);
142	else
143		ilk_disable_display_irq(display, bit);
144}
145
146static void ivb_check_fifo_underruns(struct intel_crtc *crtc)
147{
148	struct intel_display *display = to_intel_display(crtc);
149	enum pipe pipe = crtc->pipe;
150	u32 err_int = intel_de_read(display, GEN7_ERR_INT);
151
152	lockdep_assert_held(&display->irq.lock);
153
154	if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)
155		return;
156
157	intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
158	intel_de_posting_read(display, GEN7_ERR_INT);
159
160	trace_intel_cpu_fifo_underrun(display, pipe);
161	drm_err(display->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));
162}
163
164static void ivb_set_fifo_underrun_reporting(struct intel_display *display,
165					    enum pipe pipe, bool enable,
166					    bool old)
167{
168	if (enable) {
169		intel_de_write(display, GEN7_ERR_INT,
170			       ERR_INT_FIFO_UNDERRUN(pipe));
171
172		if (!ivb_can_enable_err_int(display))
173			return;
174
175		ilk_enable_display_irq(display, DE_ERR_INT_IVB);
176	} else {
177		ilk_disable_display_irq(display, DE_ERR_INT_IVB);
178
179		if (old &&
180		    intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
181			drm_err(display->drm,
182				"uncleared fifo underrun on pipe %c\n",
183				pipe_name(pipe));
184		}
185	}
186}
187
188static void bdw_set_fifo_underrun_reporting(struct intel_display *display,
189					    enum pipe pipe, bool enable)
190{
191	if (enable)
192		bdw_enable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN);
193	else
194		bdw_disable_pipe_irq(display, pipe, GEN8_PIPE_FIFO_UNDERRUN);
195}
196
197static void ibx_set_fifo_underrun_reporting(struct intel_display *display,
198					    enum pipe pch_transcoder,
199					    bool enable)
200{
201	u32 bit = (pch_transcoder == PIPE_A) ?
202		SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
203
204	if (enable)
205		ibx_enable_display_interrupt(display, bit);
206	else
207		ibx_disable_display_interrupt(display, bit);
208}
209
210static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
211{
212	struct intel_display *display = to_intel_display(crtc);
213	enum pipe pch_transcoder = crtc->pipe;
214	u32 serr_int = intel_de_read(display, SERR_INT);
215
216	lockdep_assert_held(&display->irq.lock);
217
218	if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0)
219		return;
220
221	intel_de_write(display, SERR_INT,
222		       SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
223	intel_de_posting_read(display, SERR_INT);
224
225	trace_intel_pch_fifo_underrun(display, pch_transcoder);
226	drm_err(display->drm, "pch fifo underrun on pch transcoder %c\n",
227		pipe_name(pch_transcoder));
228}
229
230static void cpt_set_fifo_underrun_reporting(struct intel_display *display,
231					    enum pipe pch_transcoder,
232					    bool enable, bool old)
233{
234	if (enable) {
235		intel_de_write(display, SERR_INT,
236			       SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
237
238		if (!cpt_can_enable_serr_int(display))
239			return;
240
241		ibx_enable_display_interrupt(display, SDE_ERROR_CPT);
242	} else {
243		ibx_disable_display_interrupt(display, SDE_ERROR_CPT);
244
245		if (old && intel_de_read(display, SERR_INT) &
246		    SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
247			drm_err(display->drm,
248				"uncleared pch fifo underrun on pch transcoder %c\n",
249				pipe_name(pch_transcoder));
250		}
251	}
252}
253
254static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,
255						    enum pipe pipe, bool enable)
256{
257	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
258	bool old;
259
260	lockdep_assert_held(&display->irq.lock);
261
262	old = !crtc->cpu_fifo_underrun_disabled;
263	crtc->cpu_fifo_underrun_disabled = !enable;
264
265	if (HAS_GMCH(display))
266		i9xx_set_fifo_underrun_reporting(display, pipe, enable, old);
267	else if (display->platform.ironlake || display->platform.sandybridge)
268		ilk_set_fifo_underrun_reporting(display, pipe, enable);
269	else if (DISPLAY_VER(display) == 7)
270		ivb_set_fifo_underrun_reporting(display, pipe, enable, old);
271	else if (DISPLAY_VER(display) >= 8)
272		bdw_set_fifo_underrun_reporting(display, pipe, enable);
273
274	return old;
275}
276
277/**
278 * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrun reporting state
279 * @display: display device instance
280 * @pipe: (CPU) pipe to set state for
281 * @enable: whether underruns should be reported or not
282 *
283 * This function sets the fifo underrun state for @pipe. It is used in the
284 * modeset code to avoid false positives since on many platforms underruns are
285 * expected when disabling or enabling the pipe.
286 *
287 * Notice that on some platforms disabling underrun reports for one pipe
288 * disables for all due to shared interrupts. Actual reporting is still per-pipe
289 * though.
290 *
291 * Returns the previous state of underrun reporting.
292 */
293bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display,
294					   enum pipe pipe, bool enable)
295{
296	unsigned long flags;
297	bool ret;
298
299	spin_lock_irqsave(&display->irq.lock, flags);
300	ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe, enable);
301	spin_unlock_irqrestore(&display->irq.lock, flags);
302
303	return ret;
304}
305
306/**
307 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state
308 * @display: display device instance
309 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
310 * @enable: whether underruns should be reported or not
311 *
312 * This function makes us disable or enable PCH fifo underruns for a specific
313 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
314 * underrun reporting for one transcoder may also disable all the other PCH
315 * error interruts for the other transcoders, due to the fact that there's just
316 * one interrupt mask/enable bit for all the transcoders.
317 *
318 * Returns the previous state of underrun reporting.
319 */
320bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
321					   enum pipe pch_transcoder,
322					   bool enable)
323{
324	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pch_transcoder);
325	unsigned long flags;
326	bool old;
327
328	/*
329	 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
330	 * has only one pch transcoder A that all pipes can use. To avoid racy
331	 * pch transcoder -> pipe lookups from interrupt code simply store the
332	 * underrun statistics in crtc A. Since we never expose this anywhere
333	 * nor use it outside of the fifo underrun code here using the "wrong"
334	 * crtc on LPT won't cause issues.
335	 */
336
337	spin_lock_irqsave(&display->irq.lock, flags);
338
339	old = !crtc->pch_fifo_underrun_disabled;
340	crtc->pch_fifo_underrun_disabled = !enable;
341
342	if (HAS_PCH_IBX(display))
343		ibx_set_fifo_underrun_reporting(display,
344						pch_transcoder,
345						enable);
346	else
347		cpt_set_fifo_underrun_reporting(display,
348						pch_transcoder,
349						enable, old);
350
351	spin_unlock_irqrestore(&display->irq.lock, flags);
352	return old;
353}
354
355/**
356 * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
357 * @display: display device instance
358 * @pipe: (CPU) pipe to set state for
359 *
360 * This handles a CPU fifo underrun interrupt, generating an underrun warning
361 * into dmesg if underrun reporting is enabled and then disables the underrun
362 * interrupt to avoid an irq storm.
363 */
364void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
365					 enum pipe pipe)
366{
367	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
368
369	/* We may be called too early in init, thanks BIOS! */
370	if (crtc == NULL)
371		return;
372
373	/* GMCH can't disable fifo underruns, filter them. */
374	if (HAS_GMCH(display) &&
375	    crtc->cpu_fifo_underrun_disabled)
376		return;
377
378	if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) {
379		trace_intel_cpu_fifo_underrun(display, pipe);
380
381		drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
382	}
383
384	intel_fbc_handle_fifo_underrun_irq(display);
385}
386
387/**
388 * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt
389 * @display: display device instance
390 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
391 *
392 * This handles a PCH fifo underrun interrupt, generating an underrun warning
393 * into dmesg if underrun reporting is enabled and then disables the underrun
394 * interrupt to avoid an irq storm.
395 */
396void intel_pch_fifo_underrun_irq_handler(struct intel_display *display,
397					 enum pipe pch_transcoder)
398{
399	if (intel_set_pch_fifo_underrun_reporting(display, pch_transcoder,
400						  false)) {
401		trace_intel_pch_fifo_underrun(display, pch_transcoder);
402		drm_err(display->drm, "PCH transcoder %c FIFO underrun\n",
403			pipe_name(pch_transcoder));
404	}
405}
406
407/**
408 * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately
409 * @display: display device instance
410 *
411 * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared
412 * error interrupt may have been disabled, and so CPU fifo underruns won't
413 * necessarily raise an interrupt, and on GMCH platforms where underruns never
414 * raise an interrupt.
415 */
416void intel_check_cpu_fifo_underruns(struct intel_display *display)
417{
418	struct intel_crtc *crtc;
419
420	spin_lock_irq(&display->irq.lock);
421
422	for_each_intel_crtc(display->drm, crtc) {
423		if (crtc->cpu_fifo_underrun_disabled)
424			continue;
425
426		if (HAS_GMCH(display))
427			i9xx_check_fifo_underruns(crtc);
428		else if (DISPLAY_VER(display) == 7)
429			ivb_check_fifo_underruns(crtc);
430	}
431
432	spin_unlock_irq(&display->irq.lock);
433}
434
435/**
436 * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately
437 * @display: display device instance
438 *
439 * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared
440 * error interrupt may have been disabled, and so PCH fifo underruns won't
441 * necessarily raise an interrupt.
442 */
443void intel_check_pch_fifo_underruns(struct intel_display *display)
444{
445	struct intel_crtc *crtc;
446
447	spin_lock_irq(&display->irq.lock);
448
449	for_each_intel_crtc(display->drm, crtc) {
450		if (crtc->pch_fifo_underrun_disabled)
451			continue;
452
453		if (HAS_PCH_CPT(display))
454			cpt_check_pch_fifo_underruns(crtc);
455	}
456
457	spin_unlock_irq(&display->irq.lock);
458}
459
460void intel_init_fifo_underrun_reporting(struct intel_display *display,
461					struct intel_crtc *crtc,
462					bool enable)
463{
464	crtc->cpu_fifo_underrun_disabled = !enable;
465
466	/*
467	 * We track the PCH trancoder underrun reporting state
468	 * within the crtc. With crtc for pipe A housing the underrun
469	 * reporting state for PCH transcoder A, crtc for pipe B housing
470	 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
471	 * and marking underrun reporting as disabled for the non-existing
472	 * PCH transcoders B and C would prevent enabling the south
473	 * error interrupt (see cpt_can_enable_serr_int()).
474	 */
475	if (intel_has_pch_trancoder(display, crtc->pipe))
476		crtc->pch_fifo_underrun_disabled = !enable;
477}