intel_fb_pin.c

  1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright © 2021 Intel Corporation
  4 */
  5
  6/**
  7 * DOC: display pinning helpers
  8 */
  9
 10#include <drm/drm_print.h>
 11
 12#include "gem/i915_gem_domain.h"
 13#include "gem/i915_gem_object.h"
 14
 15#include "i915_drv.h"
 16#include "i915_vma.h"
 17#include "intel_display_core.h"
 18#include "intel_display_rpm.h"
 19#include "intel_display_types.h"
 20#include "intel_dpt.h"
 21#include "intel_fb.h"
 22#include "intel_fb_pin.h"
 23#include "intel_plane.h"
 24
 25static struct i915_vma *
 26intel_fb_pin_to_dpt(const struct drm_framebuffer *fb,
 27		    const struct i915_gtt_view *view,
 28		    unsigned int alignment,
 29		    unsigned long *out_flags,
 30		    struct i915_address_space *vm)
 31{
 32	struct drm_device *dev = fb->dev;
 33	struct intel_display *display = to_intel_display(dev);
 34	struct drm_i915_private *dev_priv = to_i915(dev);
 35	struct drm_gem_object *_obj = intel_fb_bo(fb);
 36	struct drm_i915_gem_object *obj = to_intel_bo(_obj);
 37	struct i915_gem_ww_ctx ww;
 38	struct i915_vma *vma;
 39	int ret;
 40
 41	/*
 42	 * We are not syncing against the binding (and potential migrations)
 43	 * below, so this vm must never be async.
 44	 */
 45	if (drm_WARN_ON(&dev_priv->drm, vm->bind_async_flags))
 46		return ERR_PTR(-EINVAL);
 47
 48	if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
 49		return ERR_PTR(-EINVAL);
 50
 51	atomic_inc(&display->restore.pending_fb_pin);
 52
 53	for_i915_gem_ww(&ww, ret, true) {
 54		ret = i915_gem_object_lock(obj, &ww);
 55		if (ret)
 56			continue;
 57
 58		if (HAS_LMEM(dev_priv)) {
 59			unsigned int flags = obj->flags;
 60
 61			/*
 62			 * For this type of buffer we need to able to read from the CPU
 63			 * the clear color value found in the buffer, hence we need to
 64			 * ensure it is always in the mappable part of lmem, if this is
 65			 * a small-bar device.
 66			 */
 67			if (intel_fb_rc_ccs_cc_plane(fb) >= 0)
 68				flags &= ~I915_BO_ALLOC_GPU_ONLY;
 69			ret = __i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0,
 70							flags);
 71			if (ret)
 72				continue;
 73		}
 74
 75		ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
 76		if (ret)
 77			continue;
 78
 79		vma = i915_vma_instance(obj, vm, view);
 80		if (IS_ERR(vma)) {
 81			ret = PTR_ERR(vma);
 82			continue;
 83		}
 84
 85		if (i915_vma_misplaced(vma, 0, alignment, 0)) {
 86			ret = i915_vma_unbind(vma);
 87			if (ret)
 88				continue;
 89		}
 90
 91		ret = i915_vma_pin_ww(vma, &ww, 0, alignment, PIN_GLOBAL);
 92		if (ret)
 93			continue;
 94	}
 95	if (ret) {
 96		vma = ERR_PTR(ret);
 97		goto err;
 98	}
 99
100	vma->display_alignment = max(vma->display_alignment, alignment);
101
102	i915_gem_object_flush_if_display(obj);
103
104	i915_vma_get(vma);
105err:
106	atomic_dec(&display->restore.pending_fb_pin);
107
108	return vma;
109}
110
111struct i915_vma *
112intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb,
113		     const struct i915_gtt_view *view,
114		     unsigned int alignment,
115		     unsigned int phys_alignment,
116		     unsigned int vtd_guard,
117		     bool uses_fence,
118		     unsigned long *out_flags)
119{
120	struct drm_device *dev = fb->dev;
121	struct intel_display *display = to_intel_display(dev);
122	struct drm_i915_private *dev_priv = to_i915(dev);
123	struct drm_gem_object *_obj = intel_fb_bo(fb);
124	struct drm_i915_gem_object *obj = to_intel_bo(_obj);
125	struct ref_tracker *wakeref;
126	struct i915_gem_ww_ctx ww;
127	struct i915_vma *vma;
128	unsigned int pinctl;
129	int ret;
130
131	if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
132		return ERR_PTR(-EINVAL);
133
134	if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment)))
135		return ERR_PTR(-EINVAL);
136
137	/*
138	 * Global gtt pte registers are special registers which actually forward
139	 * writes to a chunk of system memory. Which means that there is no risk
140	 * that the register values disappear as soon as we call
141	 * intel_runtime_pm_put(), so it is correct to wrap only the
142	 * pin/unpin/fence and not more.
143	 */
144	wakeref = intel_display_rpm_get(display);
145
146	atomic_inc(&display->restore.pending_fb_pin);
147
148	/*
149	 * Valleyview is definitely limited to scanning out the first
150	 * 512MiB. Lets presume this behaviour was inherited from the
151	 * g4x display engine and that all earlier gen are similarly
152	 * limited. Testing suggests that it is a little more
153	 * complicated than this. For example, Cherryview appears quite
154	 * happy to scanout from anywhere within its global aperture.
155	 */
156	pinctl = 0;
157	if (HAS_GMCH(display))
158		pinctl |= PIN_MAPPABLE;
159
160	i915_gem_ww_ctx_init(&ww, true);
161retry:
162	ret = i915_gem_object_lock(obj, &ww);
163	if (!ret && phys_alignment)
164		ret = i915_gem_object_attach_phys(obj, phys_alignment);
165	else if (!ret && HAS_LMEM(dev_priv))
166		ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0);
167	if (!ret)
168		ret = i915_gem_object_pin_pages(obj);
169	if (ret)
170		goto err;
171
172	vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment,
173						   vtd_guard, view, pinctl);
174	if (IS_ERR(vma)) {
175		ret = PTR_ERR(vma);
176		goto err_unpin;
177	}
178
179	if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
180		/*
181		 * Install a fence for tiled scan-out. Pre-i965 always needs a
182		 * fence, whereas 965+ only requires a fence if using
183		 * framebuffer compression.  For simplicity, we always, when
184		 * possible, install a fence as the cost is not that onerous.
185		 *
186		 * If we fail to fence the tiled scanout, then either the
187		 * modeset will reject the change (which is highly unlikely as
188		 * the affected systems, all but one, do not have unmappable
189		 * space) or we will not be able to enable full powersaving
190		 * techniques (also likely not to apply due to various limits
191		 * FBC and the like impose on the size of the buffer, which
192		 * presumably we violated anyway with this unmappable buffer).
193		 * Anyway, it is presumably better to stumble onwards with
194		 * something and try to run the system in a "less than optimal"
195		 * mode that matches the user configuration.
196		 */
197		ret = i915_vma_pin_fence(vma);
198		if (ret != 0 && DISPLAY_VER(display) < 4) {
199			i915_vma_unpin(vma);
200			goto err_unpin;
201		}
202		ret = 0;
203
204		if (vma->fence)
205			*out_flags |= PLANE_HAS_FENCE;
206	}
207
208	i915_vma_get(vma);
209
210err_unpin:
211	i915_gem_object_unpin_pages(obj);
212err:
213	if (ret == -EDEADLK) {
214		ret = i915_gem_ww_ctx_backoff(&ww);
215		if (!ret)
216			goto retry;
217	}
218	i915_gem_ww_ctx_fini(&ww);
219	if (ret)
220		vma = ERR_PTR(ret);
221
222	atomic_dec(&display->restore.pending_fb_pin);
223	intel_display_rpm_put(display, wakeref);
224	return vma;
225}
226
227void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags)
228{
229	if (flags & PLANE_HAS_FENCE)
230		i915_vma_unpin_fence(vma);
231	i915_vma_unpin(vma);
232	i915_vma_put(vma);
233}
234
235static unsigned int
236intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state)
237{
238	const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);
239
240	return fb->min_alignment;
241}
242
243static unsigned int
244intel_plane_fb_min_phys_alignment(const struct intel_plane_state *plane_state)
245{
246	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
247	const struct drm_framebuffer *fb = plane_state->hw.fb;
248
249	if (!intel_plane_needs_physical(plane))
250		return 0;
251
252	return plane->min_alignment(plane, fb, 0);
253}
254
255static unsigned int
256intel_plane_fb_vtd_guard(const struct intel_plane_state *plane_state)
257{
258	return intel_fb_view_vtd_guard(plane_state->hw.fb,
259				       &plane_state->view,
260				       plane_state->hw.rotation);
261}
262
263int intel_plane_pin_fb(struct intel_plane_state *plane_state,
264		       const struct intel_plane_state *old_plane_state)
265{
266	struct intel_display *display = to_intel_display(plane_state);
267	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
268	const struct intel_framebuffer *fb =
269		to_intel_framebuffer(plane_state->hw.fb);
270	struct i915_vma *vma;
271
272	if (!intel_fb_uses_dpt(&fb->base)) {
273		vma = intel_fb_pin_to_ggtt(&fb->base, &plane_state->view.gtt,
274					   intel_plane_fb_min_alignment(plane_state),
275					   intel_plane_fb_min_phys_alignment(plane_state),
276					   intel_plane_fb_vtd_guard(plane_state),
277					   intel_plane_uses_fence(plane_state),
278					   &plane_state->flags);
279		if (IS_ERR(vma))
280			return PTR_ERR(vma);
281
282		plane_state->ggtt_vma = vma;
283
284	} else {
285		unsigned int alignment = intel_plane_fb_min_alignment(plane_state);
286
287		vma = intel_dpt_pin_to_ggtt(fb->dpt_vm, alignment / 512);
288		if (IS_ERR(vma))
289			return PTR_ERR(vma);
290
291		plane_state->ggtt_vma = vma;
292
293		vma = intel_fb_pin_to_dpt(&fb->base, &plane_state->view.gtt,
294					  alignment, &plane_state->flags,
295					  fb->dpt_vm);
296		if (IS_ERR(vma)) {
297			intel_dpt_unpin_from_ggtt(fb->dpt_vm);
298			plane_state->ggtt_vma = NULL;
299			return PTR_ERR(vma);
300		}
301
302		plane_state->dpt_vma = vma;
303
304		WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
305
306		/*
307		 * The DPT object contains only one vma, and there is no VT-d
308		 * guard, so the VMA's offset within the DPT is always 0.
309		 */
310		drm_WARN_ON(display->drm, intel_dpt_offset(plane_state->dpt_vma));
311	}
312
313	/*
314	 * Pre-populate the dma address before we enter the vblank
315	 * evade critical section as i915_gem_object_get_dma_address()
316	 * will trigger might_sleep() even if it won't actually sleep,
317	 * which is the case when the fb has already been pinned.
318	 */
319	if (intel_plane_needs_physical(plane)) {
320		struct drm_i915_gem_object *obj = to_intel_bo(intel_fb_bo(&fb->base));
321
322		plane_state->surf = i915_gem_object_get_dma_address(obj, 0) +
323			plane->surf_offset(plane_state);
324	} else {
325		plane_state->surf = i915_ggtt_offset(plane_state->ggtt_vma) +
326			plane->surf_offset(plane_state);
327	}
328
329	return 0;
330}
331
332void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
333{
334	const struct intel_framebuffer *fb =
335		to_intel_framebuffer(old_plane_state->hw.fb);
336	struct i915_vma *vma;
337
338	if (!intel_fb_uses_dpt(&fb->base)) {
339		vma = fetch_and_zero(&old_plane_state->ggtt_vma);
340		if (vma)
341			intel_fb_unpin_vma(vma, old_plane_state->flags);
342	} else {
343		vma = fetch_and_zero(&old_plane_state->dpt_vma);
344		if (vma)
345			intel_fb_unpin_vma(vma, old_plane_state->flags);
346
347		vma = fetch_and_zero(&old_plane_state->ggtt_vma);
348		if (vma)
349			intel_dpt_unpin_from_ggtt(fb->dpt_vm);
350	}
351}
352
353void intel_fb_get_map(struct i915_vma *vma, struct iosys_map *map)
354{
355	iosys_map_set_vaddr_iomem(map, i915_vma_get_iomap(vma));
356}