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intel_dsi_vbt.c
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linux-6.19.14/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
1/* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Shobhit Kumar <shobhit.kumar@intel.com> 24 * 25 */ 26 27#include <linux/gpio/consumer.h> 28#include <linux/gpio/machine.h> 29#include <linux/mfd/intel_soc_pmic.h> 30#include <linux/pinctrl/consumer.h> 31#include <linux/pinctrl/machine.h> 32#include <linux/slab.h> 33#include <linux/string_helpers.h> 34#include <linux/unaligned.h> 35 36#include <drm/drm_crtc.h> 37#include <drm/drm_edid.h> 38#include <drm/drm_print.h> 39#include <video/mipi_display.h> 40 41#include "intel_de.h" 42#include "intel_display_regs.h" 43#include "intel_display_types.h" 44#include "intel_display_utils.h" 45#include "intel_dsi.h" 46#include "intel_dsi_vbt.h" 47#include "intel_gmbus_regs.h" 48#include "intel_pps_regs.h" 49#include "vlv_dsi.h" 50#include "vlv_dsi_regs.h" 51#include "vlv_sideband.h" 52 53#define MIPI_TRANSFER_MODE_SHIFT 0 54#define MIPI_VIRTUAL_CHANNEL_SHIFT 1 55#define MIPI_PORT_SHIFT 3 56 57struct i2c_adapter_lookup { 58 u16 target_addr; 59 struct intel_dsi *intel_dsi; 60 acpi_handle dev_handle; 61}; 62 63#define CHV_GPIO_IDX_START_N 0 64#define CHV_GPIO_IDX_START_E 73 65#define CHV_GPIO_IDX_START_SW 100 66#define CHV_GPIO_IDX_START_SE 198 67 68/* ICL DSI Display GPIO Pins */ 69#define ICL_GPIO_DDSP_HPD_A 0 70#define ICL_GPIO_L_VDDEN_1 1 71#define ICL_GPIO_L_BKLTEN_1 2 72#define ICL_GPIO_DDPA_CTRLCLK_1 3 73#define ICL_GPIO_DDPA_CTRLDATA_1 4 74#define ICL_GPIO_DDSP_HPD_B 5 75#define ICL_GPIO_L_VDDEN_2 6 76#define ICL_GPIO_L_BKLTEN_2 7 77#define ICL_GPIO_DDPA_CTRLCLK_2 8 78#define ICL_GPIO_DDPA_CTRLDATA_2 9 79 80static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi, 81 u8 seq_port) 82{ 83 /* 84 * If single link DSI is being used on any port, the VBT sequence block 85 * send packet apparently always has 0 for the port. Just use the port 86 * we have configured, and ignore the sequence block port. 87 */ 88 if (hweight8(intel_dsi->ports) == 1) 89 return ffs(intel_dsi->ports) - 1; 90 91 if (seq_port) { 92 if (intel_dsi->ports & BIT(PORT_B)) 93 return PORT_B; 94 if (intel_dsi->ports & BIT(PORT_C)) 95 return PORT_C; 96 } 97 98 return PORT_A; 99} 100 101static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 102 const u8 *data) 103{ 104 struct intel_display *display = to_intel_display(&intel_dsi->base); 105 struct mipi_dsi_device *dsi_device; 106 u8 type, flags, seq_port; 107 u16 len; 108 enum port port; 109 ssize_t ret; 110 bool hs_mode; 111 112 flags = *data++; 113 type = *data++; 114 115 len = *((u16 *) data); 116 data += 2; 117 118 seq_port = (flags >> MIPI_PORT_SHIFT) & 3; 119 120 port = intel_dsi_seq_port_to_port(intel_dsi, seq_port); 121 122 if (drm_WARN_ON(display->drm, !intel_dsi->dsi_hosts[port])) 123 goto out; 124 125 dsi_device = intel_dsi->dsi_hosts[port]->device; 126 if (!dsi_device) { 127 drm_dbg_kms(display->drm, "no dsi device for port %c\n", 128 port_name(port)); 129 goto out; 130 } 131 132 hs_mode = (flags >> MIPI_TRANSFER_MODE_SHIFT) & 1; 133 if (hs_mode) 134 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; 135 else 136 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; 137 138 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; 139 140 drm_dbg_kms(display->drm, "DSI packet: Port %c (seq %u), Flags 0x%02x, VC %u, %s, Type 0x%02x, Length %u, Data %*ph\n", 141 port_name(port), seq_port, flags, dsi_device->channel, 142 hs_mode ? "HS" : "LP", type, len, (int)len, data); 143 144 switch (type) { 145 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 146 ret = mipi_dsi_generic_write(dsi_device, NULL, 0); 147 break; 148 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 149 ret = mipi_dsi_generic_write(dsi_device, data, 1); 150 break; 151 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 152 ret = mipi_dsi_generic_write(dsi_device, data, 2); 153 break; 154 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 155 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 156 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 157 ret = -EOPNOTSUPP; 158 break; 159 case MIPI_DSI_GENERIC_LONG_WRITE: 160 ret = mipi_dsi_generic_write(dsi_device, data, len); 161 break; 162 case MIPI_DSI_DCS_SHORT_WRITE: 163 ret = mipi_dsi_dcs_write_buffer(dsi_device, data, 1); 164 break; 165 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 166 ret = mipi_dsi_dcs_write_buffer(dsi_device, data, 2); 167 break; 168 case MIPI_DSI_DCS_READ: 169 ret = -EOPNOTSUPP; 170 break; 171 case MIPI_DSI_DCS_LONG_WRITE: 172 ret = mipi_dsi_dcs_write_buffer(dsi_device, data, len); 173 break; 174 default: 175 ret = -EINVAL; 176 break; 177 } 178 179 if (ret < 0) 180 drm_err(display->drm, "DSI send packet failed with %pe\n", ERR_PTR(ret)); 181 182 if (DISPLAY_VER(display) < 11) 183 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 184 185out: 186 data += len; 187 188 return data; 189} 190 191static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) 192{ 193 struct intel_display *display = to_intel_display(&intel_dsi->base); 194 u32 delay = *((const u32 *) data); 195 196 drm_dbg_kms(display->drm, "%d usecs\n", delay); 197 198 usleep_range(delay, delay + 10); 199 data += 4; 200 201 return data; 202} 203 204static void soc_gpio_set_value(struct intel_connector *connector, u8 gpio_index, 205 const char *con_id, u8 idx, bool value) 206{ 207 struct intel_display *display = to_intel_display(connector); 208 /* XXX: this table is a quick ugly hack. */ 209 static struct gpio_desc *soc_gpio_table[U8_MAX + 1]; 210 struct gpio_desc *gpio_desc = soc_gpio_table[gpio_index]; 211 212 if (gpio_desc) { 213 gpiod_set_value(gpio_desc, value); 214 } else { 215 gpio_desc = devm_gpiod_get_index(display->drm->dev, con_id, idx, 216 value ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW); 217 if (IS_ERR(gpio_desc)) { 218 drm_err(display->drm, 219 "GPIO index %u request failed (%pe)\n", 220 gpio_index, gpio_desc); 221 return; 222 } 223 224 soc_gpio_table[gpio_index] = gpio_desc; 225 } 226} 227 228static void soc_opaque_gpio_set_value(struct intel_connector *connector, 229 u8 gpio_index, const char *chip, 230 const char *con_id, u8 idx, bool value) 231{ 232 struct gpiod_lookup_table *lookup; 233 234 lookup = kzalloc(struct_size(lookup, table, 2), GFP_KERNEL); 235 if (!lookup) 236 return; 237 238 lookup->dev_id = "0000:00:02.0"; 239 lookup->table[0] = 240 GPIO_LOOKUP_IDX(chip, idx, con_id, idx, GPIO_ACTIVE_HIGH); 241 242 gpiod_add_lookup_table(lookup); 243 244 soc_gpio_set_value(connector, gpio_index, con_id, idx, value); 245 246 gpiod_remove_lookup_table(lookup); 247 kfree(lookup); 248} 249 250static void vlv_gpio_set_value(struct intel_connector *connector, 251 u8 gpio_source, u8 gpio_index, bool value) 252{ 253 struct intel_display *display = to_intel_display(connector); 254 255 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ 256 if (connector->panel.vbt.dsi.seq_version < 3) { 257 if (gpio_source == 1) { 258 drm_dbg_kms(display->drm, "SC gpio not supported\n"); 259 return; 260 } 261 if (gpio_source > 1) { 262 drm_dbg_kms(display->drm, 263 "unknown gpio source %u\n", gpio_source); 264 return; 265 } 266 } 267 268 soc_opaque_gpio_set_value(connector, gpio_index, 269 "INT33FC:01", "Panel N", gpio_index, value); 270} 271 272static void chv_gpio_set_value(struct intel_connector *connector, 273 u8 gpio_source, u8 gpio_index, bool value) 274{ 275 struct intel_display *display = to_intel_display(connector); 276 277 if (connector->panel.vbt.dsi.seq_version >= 3) { 278 if (gpio_index >= CHV_GPIO_IDX_START_SE) { 279 /* XXX: it's unclear whether 255->57 is part of SE. */ 280 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:03", "Panel SE", 281 gpio_index - CHV_GPIO_IDX_START_SE, value); 282 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) { 283 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:00", "Panel SW", 284 gpio_index - CHV_GPIO_IDX_START_SW, value); 285 } else if (gpio_index >= CHV_GPIO_IDX_START_E) { 286 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:02", "Panel E", 287 gpio_index - CHV_GPIO_IDX_START_E, value); 288 } else { 289 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:01", "Panel N", 290 gpio_index - CHV_GPIO_IDX_START_N, value); 291 } 292 } else { 293 /* XXX: The spec is unclear about CHV GPIO on seq v2 */ 294 if (gpio_source != 0) { 295 drm_dbg_kms(display->drm, 296 "unknown gpio source %u\n", gpio_source); 297 return; 298 } 299 300 if (gpio_index >= CHV_GPIO_IDX_START_E) { 301 drm_dbg_kms(display->drm, 302 "invalid gpio index %u for GPIO N\n", 303 gpio_index); 304 return; 305 } 306 307 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:01", "Panel N", 308 gpio_index - CHV_GPIO_IDX_START_N, value); 309 } 310} 311 312static void bxt_gpio_set_value(struct intel_connector *connector, 313 u8 gpio_index, bool value) 314{ 315 soc_gpio_set_value(connector, gpio_index, NULL, gpio_index, value); 316} 317 318enum { 319 MIPI_RESET_1 = 0, 320 MIPI_AVDD_EN_1, 321 MIPI_BKLT_EN_1, 322 MIPI_AVEE_EN_1, 323 MIPI_VIO_EN_1, 324 MIPI_RESET_2, 325 MIPI_AVDD_EN_2, 326 MIPI_BKLT_EN_2, 327 MIPI_AVEE_EN_2, 328 MIPI_VIO_EN_2, 329}; 330 331static void icl_native_gpio_set_value(struct intel_display *display, 332 int gpio, bool value) 333{ 334 int index; 335 336 if (drm_WARN_ON(display->drm, DISPLAY_VER(display) == 11 && gpio >= MIPI_RESET_2)) 337 return; 338 339 switch (gpio) { 340 case MIPI_RESET_1: 341 case MIPI_RESET_2: 342 index = gpio == MIPI_RESET_1 ? HPD_PORT_A : HPD_PORT_B; 343 344 /* 345 * Disable HPD to set the pin to output, and set output 346 * value. The HPD pin should not be enabled for DSI anyway, 347 * assuming the board design and VBT are sane, and the pin isn't 348 * used by a non-DSI encoder. 349 * 350 * The locking protects against concurrent SHOTPLUG_CTL_DDI 351 * modifications in irq setup and handling. 352 */ 353 spin_lock_irq(&display->irq.lock); 354 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 355 SHOTPLUG_CTL_DDI_HPD_ENABLE(index) | 356 SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index), 357 value ? SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index) : 0); 358 spin_unlock_irq(&display->irq.lock); 359 break; 360 case MIPI_AVDD_EN_1: 361 case MIPI_AVDD_EN_2: 362 index = gpio == MIPI_AVDD_EN_1 ? 0 : 1; 363 364 intel_de_rmw(display, PP_CONTROL(display, index), PANEL_POWER_ON, 365 value ? PANEL_POWER_ON : 0); 366 break; 367 case MIPI_BKLT_EN_1: 368 case MIPI_BKLT_EN_2: 369 index = gpio == MIPI_BKLT_EN_1 ? 0 : 1; 370 371 intel_de_rmw(display, PP_CONTROL(display, index), EDP_BLC_ENABLE, 372 value ? EDP_BLC_ENABLE : 0); 373 break; 374 case MIPI_AVEE_EN_1: 375 case MIPI_AVEE_EN_2: 376 index = gpio == MIPI_AVEE_EN_1 ? 1 : 2; 377 378 intel_de_rmw(display, GPIO(display, index), 379 GPIO_CLOCK_VAL_OUT, 380 GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | 381 GPIO_CLOCK_VAL_MASK | (value ? GPIO_CLOCK_VAL_OUT : 0)); 382 break; 383 case MIPI_VIO_EN_1: 384 case MIPI_VIO_EN_2: 385 index = gpio == MIPI_VIO_EN_1 ? 1 : 2; 386 387 intel_de_rmw(display, GPIO(display, index), 388 GPIO_DATA_VAL_OUT, 389 GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | 390 GPIO_DATA_VAL_MASK | (value ? GPIO_DATA_VAL_OUT : 0)); 391 break; 392 default: 393 MISSING_CASE(gpio); 394 } 395} 396 397static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 398{ 399 struct intel_display *display = to_intel_display(&intel_dsi->base); 400 struct intel_connector *connector = intel_dsi->attached_connector; 401 u8 gpio_source = 0, gpio_index = 0, gpio_number; 402 bool value; 403 int size; 404 bool native = DISPLAY_VER(display) >= 11; 405 406 if (connector->panel.vbt.dsi.seq_version >= 3) { 407 size = 3; 408 409 gpio_index = data[0]; 410 gpio_number = data[1]; 411 value = data[2] & BIT(0); 412 413 if (connector->panel.vbt.dsi.seq_version >= 4 && data[2] & BIT(1)) 414 native = false; 415 } else { 416 size = 2; 417 418 gpio_number = data[0]; 419 value = data[1] & BIT(0); 420 421 if (connector->panel.vbt.dsi.seq_version == 2) 422 gpio_source = (data[1] >> 1) & 3; 423 } 424 425 drm_dbg_kms(display->drm, "GPIO index %u, number %u, source %u, native %s, set to %s\n", 426 gpio_index, gpio_number, gpio_source, str_yes_no(native), str_on_off(value)); 427 428 if (native) 429 icl_native_gpio_set_value(display, gpio_number, value); 430 else if (DISPLAY_VER(display) >= 9) 431 bxt_gpio_set_value(connector, gpio_index, value); 432 else if (display->platform.valleyview) 433 vlv_gpio_set_value(connector, gpio_source, gpio_number, value); 434 else if (display->platform.cherryview) 435 chv_gpio_set_value(connector, gpio_source, gpio_number, value); 436 437 return data + size; 438} 439 440#ifdef CONFIG_ACPI 441static int i2c_adapter_lookup(struct acpi_resource *ares, void *data) 442{ 443 struct i2c_adapter_lookup *lookup = data; 444 struct intel_dsi *intel_dsi = lookup->intel_dsi; 445 struct acpi_resource_i2c_serialbus *sb; 446 struct i2c_adapter *adapter; 447 acpi_handle adapter_handle; 448 acpi_status status; 449 450 if (!i2c_acpi_get_i2c_resource(ares, &sb)) 451 return 1; 452 453 if (lookup->target_addr != sb->slave_address) 454 return 1; 455 456 status = acpi_get_handle(lookup->dev_handle, 457 sb->resource_source.string_ptr, 458 &adapter_handle); 459 if (ACPI_FAILURE(status)) 460 return 1; 461 462 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle); 463 if (adapter) 464 intel_dsi->i2c_bus_num = adapter->nr; 465 466 return 1; 467} 468 469static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 470 const u16 target_addr) 471{ 472 struct intel_display *display = to_intel_display(&intel_dsi->base); 473 struct acpi_device *adev = ACPI_COMPANION(display->drm->dev); 474 struct i2c_adapter_lookup lookup = { 475 .target_addr = target_addr, 476 .intel_dsi = intel_dsi, 477 .dev_handle = acpi_device_handle(adev), 478 }; 479 LIST_HEAD(resource_list); 480 481 acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup); 482 acpi_dev_free_resource_list(&resource_list); 483} 484#else 485static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 486 const u16 target_addr) 487{ 488} 489#endif 490 491static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data) 492{ 493 struct intel_display *display = to_intel_display(&intel_dsi->base); 494 struct i2c_adapter *adapter; 495 struct i2c_msg msg; 496 int ret; 497 u8 vbt_i2c_bus_num = *(data + 2); 498 u16 target_addr = *(u16 *)(data + 3); 499 u8 reg_offset = *(data + 5); 500 u8 payload_size = *(data + 6); 501 u8 *payload_data; 502 503 drm_dbg_kms(display->drm, "bus %d target-addr 0x%02x reg 0x%02x data %*ph\n", 504 vbt_i2c_bus_num, target_addr, reg_offset, payload_size, data + 7); 505 506 if (intel_dsi->i2c_bus_num < 0) { 507 intel_dsi->i2c_bus_num = vbt_i2c_bus_num; 508 i2c_acpi_find_adapter(intel_dsi, target_addr); 509 } 510 511 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num); 512 if (!adapter) { 513 drm_err(display->drm, "Cannot find a valid i2c bus for xfer\n"); 514 goto err_bus; 515 } 516 517 payload_data = kzalloc(payload_size + 1, GFP_KERNEL); 518 if (!payload_data) 519 goto err_alloc; 520 521 payload_data[0] = reg_offset; 522 memcpy(&payload_data[1], (data + 7), payload_size); 523 524 msg.addr = target_addr; 525 msg.flags = 0; 526 msg.len = payload_size + 1; 527 msg.buf = payload_data; 528 529 ret = i2c_transfer(adapter, &msg, 1); 530 if (ret < 0) 531 drm_err(display->drm, 532 "Failed to xfer payload of size (%u) to reg (%u)\n", 533 payload_size, reg_offset); 534 535 kfree(payload_data); 536err_alloc: 537 i2c_put_adapter(adapter); 538err_bus: 539 return data + payload_size + 7; 540} 541 542static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) 543{ 544 struct intel_display *display = to_intel_display(&intel_dsi->base); 545 546 drm_dbg_kms(display->drm, "Skipping SPI element execution\n"); 547 548 return data + *(data + 5) + 6; 549} 550 551static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) 552{ 553 struct intel_display *display = to_intel_display(&intel_dsi->base); 554#ifdef CONFIG_PMIC_OPREGION 555 u32 value, mask, reg_address; 556 u16 i2c_address; 557 int ret; 558 559 /* byte 0 aka PMIC Flag is reserved */ 560 i2c_address = get_unaligned_le16(data + 1); 561 reg_address = get_unaligned_le32(data + 3); 562 value = get_unaligned_le32(data + 7); 563 mask = get_unaligned_le32(data + 11); 564 565 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address, 566 reg_address, 567 value, mask); 568 if (ret) 569 drm_err(display->drm, "%s failed, error: %d\n", __func__, ret); 570#else 571 drm_err(display->drm, 572 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); 573#endif 574 575 return data + 15; 576} 577 578typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, 579 const u8 *data); 580static const fn_mipi_elem_exec exec_elem[] = { 581 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, 582 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, 583 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, 584 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c, 585 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi, 586 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic, 587}; 588 589/* 590 * MIPI Sequence from VBT #53 parsing logic 591 * We have already separated each sequence during bios parsing 592 * Following is generic execution function for any sequence 593 */ 594 595static const char * const seq_name[] = { 596 [MIPI_SEQ_END] = "MIPI_SEQ_END", 597 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", 598 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", 599 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", 600 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", 601 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", 602 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", 603 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", 604 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", 605 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", 606 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", 607 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", 608}; 609 610static const char *sequence_name(enum mipi_seq seq_id) 611{ 612 if (seq_id < ARRAY_SIZE(seq_name)) 613 return seq_name[seq_id]; 614 615 return "(unknown)"; 616} 617 618static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, 619 enum mipi_seq seq_id) 620{ 621 struct intel_display *display = to_intel_display(&intel_dsi->base); 622 struct intel_connector *connector = intel_dsi->attached_connector; 623 const u8 *data; 624 fn_mipi_elem_exec mipi_elem_exec; 625 626 if (drm_WARN_ON(display->drm, 627 seq_id >= ARRAY_SIZE(connector->panel.vbt.dsi.sequence))) 628 return; 629 630 data = connector->panel.vbt.dsi.sequence[seq_id]; 631 if (!data) 632 return; 633 634 drm_WARN_ON(display->drm, *data != seq_id); 635 636 drm_dbg_kms(display->drm, "Starting MIPI sequence %d - %s\n", 637 seq_id, sequence_name(seq_id)); 638 639 /* Skip Sequence Byte. */ 640 data++; 641 642 /* Skip Size of Sequence. */ 643 if (connector->panel.vbt.dsi.seq_version >= 3) 644 data += 4; 645 646 while (*data != MIPI_SEQ_ELEM_END) { 647 u8 operation_byte = *data++; 648 u8 operation_size = 0; 649 650 if (operation_byte < ARRAY_SIZE(exec_elem)) 651 mipi_elem_exec = exec_elem[operation_byte]; 652 else 653 mipi_elem_exec = NULL; 654 655 /* Size of Operation. */ 656 if (connector->panel.vbt.dsi.seq_version >= 3) 657 operation_size = *data++; 658 659 if (mipi_elem_exec) { 660 const u8 *next = data + operation_size; 661 662 data = mipi_elem_exec(intel_dsi, data); 663 664 /* Consistency check if we have size. */ 665 if (operation_size && data != next) { 666 drm_err(display->drm, 667 "Inconsistent operation size\n"); 668 return; 669 } 670 } else if (operation_size) { 671 /* We have size, skip. */ 672 drm_dbg_kms(display->drm, 673 "Unsupported MIPI operation byte %u\n", 674 operation_byte); 675 data += operation_size; 676 } else { 677 /* No size, can't skip without parsing. */ 678 drm_err(display->drm, 679 "Unsupported MIPI operation byte %u\n", 680 operation_byte); 681 return; 682 } 683 } 684} 685 686void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi, 687 enum mipi_seq seq_id) 688{ 689 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel) 690 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 691 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight) 692 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1); 693 694 intel_dsi_vbt_exec(intel_dsi, seq_id); 695 696 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel) 697 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 698 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight) 699 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0); 700} 701 702void intel_dsi_log_params(struct intel_dsi *intel_dsi) 703{ 704 struct intel_display *display = to_intel_display(&intel_dsi->base); 705 struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, 706 "DSI parameters:"); 707 708 drm_printf(&p, "Pclk %d\n", intel_dsi->pclk); 709 drm_printf(&p, "Pixel overlap %d\n", intel_dsi->pixel_overlap); 710 drm_printf(&p, "Lane count %d\n", intel_dsi->lane_count); 711 drm_printf(&p, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg); 712 drm_printf(&p, "Video mode format %s\n", 713 intel_dsi->video_mode == NON_BURST_SYNC_PULSE ? 714 "non-burst with sync pulse" : 715 intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ? 716 "non-burst with sync events" : 717 intel_dsi->video_mode == BURST_MODE ? 718 "burst" : "<unknown>"); 719 drm_printf(&p, "Burst mode ratio %d\n", intel_dsi->burst_mode_ratio); 720 drm_printf(&p, "Reset timer %d\n", intel_dsi->rst_timer_val); 721 drm_printf(&p, "Eot %s\n", str_enabled_disabled(intel_dsi->eotp_pkt)); 722 drm_printf(&p, "Clockstop %s\n", str_enabled_disabled(!intel_dsi->clock_stop)); 723 drm_printf(&p, "Mode %s\n", intel_dsi->operation_mode ? "command" : "video"); 724 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 725 drm_printf(&p, "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); 726 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) 727 drm_printf(&p, "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); 728 else 729 drm_printf(&p, "Dual link: NONE\n"); 730 drm_printf(&p, "Pixel Format %d\n", intel_dsi->pixel_format); 731 drm_printf(&p, "TLPX %d\n", intel_dsi->escape_clk_div); 732 drm_printf(&p, "LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout); 733 drm_printf(&p, "Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val); 734 drm_printf(&p, "Init Count 0x%x\n", intel_dsi->init_count); 735 drm_printf(&p, "HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count); 736 drm_printf(&p, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk); 737 drm_printf(&p, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer); 738 drm_printf(&p, "LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count); 739 drm_printf(&p, "HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count); 740 drm_printf(&p, "BTA %s\n", 741 str_enabled_disabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); 742} 743 744static enum mipi_dsi_pixel_format vbt_to_dsi_pixel_format(unsigned int format) 745{ 746 switch (format) { 747 case PIXEL_FORMAT_RGB888: 748 return MIPI_DSI_FMT_RGB888; 749 case PIXEL_FORMAT_RGB666_LOOSELY_PACKED: 750 return MIPI_DSI_FMT_RGB666; 751 case PIXEL_FORMAT_RGB666: 752 return MIPI_DSI_FMT_RGB666_PACKED; 753 case PIXEL_FORMAT_RGB565: 754 return MIPI_DSI_FMT_RGB565; 755 default: 756 MISSING_CASE(format); 757 return MIPI_DSI_FMT_RGB666; 758 } 759} 760 761bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 762{ 763 struct intel_display *display = to_intel_display(&intel_dsi->base); 764 struct intel_connector *connector = intel_dsi->attached_connector; 765 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 766 struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps; 767 struct drm_display_mode *mode = connector->panel.vbt.lfp_vbt_mode; 768 u16 burst_mode_ratio; 769 enum port port; 770 771 drm_dbg_kms(display->drm, "\n"); 772 773 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; 774 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; 775 intel_dsi->lane_count = mipi_config->lane_cnt + 1; 776 intel_dsi->pixel_format = 777 vbt_to_dsi_pixel_format(mipi_config->videomode_color_format); 778 779 intel_dsi->dual_link = mipi_config->dual_link; 780 intel_dsi->pixel_overlap = mipi_config->pixel_overlap; 781 intel_dsi->operation_mode = mipi_config->is_cmd_mode; 782 intel_dsi->video_mode = mipi_config->video_transfer_mode; 783 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; 784 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; 785 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout; 786 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; 787 intel_dsi->rst_timer_val = mipi_config->device_reset_timer; 788 intel_dsi->init_count = mipi_config->master_init_timer; 789 intel_dsi->bw_timer = mipi_config->dbi_bw_timer; 790 intel_dsi->video_frmt_cfg_bits = 791 mipi_config->bta_disable ? DISABLE_VIDEO_BTA : 0; 792 intel_dsi->bgr_enabled = mipi_config->rgb_flip; 793 794 /* Starting point, adjusted depending on dual link and burst mode */ 795 intel_dsi->pclk = mode->clock; 796 797 /* In dual link mode each port needs half of pixel clock */ 798 if (intel_dsi->dual_link) { 799 intel_dsi->pclk /= 2; 800 801 /* we can enable pixel_overlap if needed by panel. In this 802 * case we need to increase the pixelclock for extra pixels 803 */ 804 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 805 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); 806 } 807 } 808 809 /* Burst Mode Ratio 810 * Target ddr frequency from VBT / non burst ddr freq 811 * multiply by 100 to preserve remainder 812 */ 813 if (intel_dsi->video_mode == BURST_MODE) { 814 u32 bitrate; 815 816 if (mipi_config->target_burst_mode_freq == 0) { 817 drm_err(display->drm, "Burst mode target is not set\n"); 818 return false; 819 } 820 821 bitrate = intel_dsi_bitrate(intel_dsi); 822 823 /* 824 * Sometimes the VBT contains a slightly lower clock, then 825 * the bitrate we have calculated, in this case just replace it 826 * with the calculated bitrate. 827 */ 828 if (mipi_config->target_burst_mode_freq < bitrate && 829 intel_fuzzy_clock_check(mipi_config->target_burst_mode_freq, 830 bitrate)) 831 mipi_config->target_burst_mode_freq = bitrate; 832 833 if (mipi_config->target_burst_mode_freq < bitrate) { 834 drm_err(display->drm, "Burst mode freq is less than computed\n"); 835 return false; 836 } 837 838 burst_mode_ratio = 839 DIV_ROUND_UP(mipi_config->target_burst_mode_freq * 100, bitrate); 840 841 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); 842 } else 843 burst_mode_ratio = 100; 844 845 intel_dsi->burst_mode_ratio = burst_mode_ratio; 846 847 /* delays in VBT are in unit of 100us, so need to convert 848 * here in ms 849 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ 850 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; 851 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; 852 intel_dsi->panel_on_delay = pps->panel_on_delay / 10; 853 intel_dsi->panel_off_delay = pps->panel_off_delay / 10; 854 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; 855 856 intel_dsi->i2c_bus_num = -1; 857 858 /* a regular driver would get the device in probe */ 859 for_each_dsi_port(port, intel_dsi->ports) { 860 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); 861 } 862 863 return true; 864} 865 866/* 867 * On some BYT/CHT devs some sequences are incomplete and we need to manually 868 * control some GPIOs. We need to add a GPIO lookup table before we get these. 869 * If the GOP did not initialize the panel (HDMI inserted) we may need to also 870 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM. 871 */ 872static struct gpiod_lookup_table pmic_panel_gpio_table = { 873 /* Intel GFX is consumer */ 874 .dev_id = "0000:00:02.0", 875 .table = { 876 /* Panel EN/DISABLE */ 877 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH), 878 { } 879 }, 880}; 881 882static struct gpiod_lookup_table soc_panel_gpio_table = { 883 .dev_id = "0000:00:02.0", 884 .table = { 885 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH), 886 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH), 887 { } 888 }, 889}; 890 891static const struct pinctrl_map soc_pwm_pinctrl_map[] = { 892 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00", 893 "pwm0_grp", "pwm"), 894}; 895 896void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) 897{ 898 struct intel_display *display = to_intel_display(&intel_dsi->base); 899 struct intel_connector *connector = intel_dsi->attached_connector; 900 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 901 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 902 struct gpiod_lookup_table *gpiod_lookup_table = NULL; 903 bool want_backlight_gpio = false; 904 bool want_panel_gpio = false; 905 struct pinctrl *pinctrl; 906 int ret; 907 908 if ((display->platform.valleyview || display->platform.cherryview) && 909 mipi_config->pwm_blc == PPS_BLC_PMIC) { 910 gpiod_lookup_table = &pmic_panel_gpio_table; 911 want_panel_gpio = true; 912 } 913 914 if (display->platform.valleyview && mipi_config->pwm_blc == PPS_BLC_SOC) { 915 gpiod_lookup_table = &soc_panel_gpio_table; 916 want_panel_gpio = true; 917 want_backlight_gpio = true; 918 919 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */ 920 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, 921 ARRAY_SIZE(soc_pwm_pinctrl_map)); 922 if (ret) 923 drm_err(display->drm, 924 "Failed to register pwm0 pinmux mapping\n"); 925 926 pinctrl = devm_pinctrl_get_select(display->drm->dev, "soc_pwm0"); 927 if (IS_ERR(pinctrl)) 928 drm_err(display->drm, 929 "Failed to set pinmux to PWM\n"); 930 } 931 932 if (gpiod_lookup_table) 933 gpiod_add_lookup_table(gpiod_lookup_table); 934 935 if (want_panel_gpio) { 936 intel_dsi->gpio_panel = devm_gpiod_get(display->drm->dev, "panel", flags); 937 if (IS_ERR(intel_dsi->gpio_panel)) { 938 drm_err(display->drm, 939 "Failed to own gpio for panel control\n"); 940 intel_dsi->gpio_panel = NULL; 941 } 942 } 943 944 if (want_backlight_gpio) { 945 intel_dsi->gpio_backlight = 946 devm_gpiod_get(display->drm->dev, "backlight", flags); 947 if (IS_ERR(intel_dsi->gpio_backlight)) { 948 drm_err(display->drm, 949 "Failed to own gpio for backlight control\n"); 950 intel_dsi->gpio_backlight = NULL; 951 } 952 } 953 954 if (gpiod_lookup_table) 955 gpiod_remove_lookup_table(gpiod_lookup_table); 956}
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