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intel_dpio_phy.c
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linux-6.19.14/drivers/gpu/drm/i915/display/intel_dpio_phy.c
1/* 2 * Copyright © 2014-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24#include <drm/drm_print.h> 25 26#include "bxt_dpio_phy_regs.h" 27#include "intel_ddi.h" 28#include "intel_ddi_buf_trans.h" 29#include "intel_de.h" 30#include "intel_display_power_well.h" 31#include "intel_display_regs.h" 32#include "intel_display_types.h" 33#include "intel_display_utils.h" 34#include "intel_dp.h" 35#include "intel_dpio_phy.h" 36#include "vlv_dpio_phy_regs.h" 37#include "vlv_sideband.h" 38 39/** 40 * DOC: DPIO 41 * 42 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI 43 * ports. DPIO is the name given to such a display PHY. These PHYs 44 * don't follow the standard programming model using direct MMIO 45 * registers, and instead their registers must be accessed through IOSF 46 * sideband. VLV has one such PHY for driving ports B and C, and CHV 47 * adds another PHY for driving port D. Each PHY responds to specific 48 * IOSF-SB port. 49 * 50 * Each display PHY is made up of one or two channels. Each channel 51 * houses a common lane part which contains the PLL and other common 52 * logic. CH0 common lane also contains the IOSF-SB logic for the 53 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock 54 * must be running when any DPIO registers are accessed. 55 * 56 * In addition to having their own registers, the PHYs are also 57 * controlled through some dedicated signals from the display 58 * controller. These include PLL reference clock enable, PLL enable, 59 * and CRI clock selection, for example. 60 * 61 * Eeach channel also has two splines (also called data lanes), and 62 * each spline is made up of one Physical Access Coding Sub-Layer 63 * (PCS) block and two TX lanes. So each channel has two PCS blocks 64 * and four TX lanes. The TX lanes are used as DP lanes or TMDS 65 * data/clock pairs depending on the output type. 66 * 67 * Additionally the PHY also contains an AUX lane with AUX blocks 68 * for each channel. This is used for DP AUX communication, but 69 * this fact isn't really relevant for the driver since AUX is 70 * controlled from the display controller side. No DPIO registers 71 * need to be accessed during AUX communication, 72 * 73 * Generally on VLV/CHV the common lane corresponds to the pipe and 74 * the spline (PCS/TX) corresponds to the port. 75 * 76 * For dual channel PHY (VLV/CHV): 77 * 78 * pipe A == CMN/PLL/REF CH0 79 * 80 * pipe B == CMN/PLL/REF CH1 81 * 82 * port B == PCS/TX CH0 83 * 84 * port C == PCS/TX CH1 85 * 86 * This is especially important when we cross the streams 87 * ie. drive port B with pipe B, or port C with pipe A. 88 * 89 * For single channel PHY (CHV): 90 * 91 * pipe C == CMN/PLL/REF CH0 92 * 93 * port D == PCS/TX CH0 94 * 95 * On BXT the entire PHY channel corresponds to the port. That means 96 * the PLL is also now associated with the port rather than the pipe, 97 * and so the clock needs to be routed to the appropriate transcoder. 98 * Port A PLL is directly connected to transcoder EDP and port B/C 99 * PLLs can be routed to any transcoder A/B/C. 100 * 101 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is 102 * digital port D (CHV) or port A (BXT). :: 103 * 104 * 105 * Dual channel PHY (VLV/CHV/BXT) 106 * --------------------------------- 107 * | CH0 | CH1 | 108 * | CMN/PLL/REF | CMN/PLL/REF | 109 * |---------------|---------------| Display PHY 110 * | PCS01 | PCS23 | PCS01 | PCS23 | 111 * |-------|-------|-------|-------| 112 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| 113 * --------------------------------- 114 * | DDI0 | DDI1 | DP/HDMI ports 115 * --------------------------------- 116 * 117 * Single channel PHY (CHV/BXT) 118 * ----------------- 119 * | CH0 | 120 * | CMN/PLL/REF | 121 * |---------------| Display PHY 122 * | PCS01 | PCS23 | 123 * |-------|-------| 124 * |TX0|TX1|TX2|TX3| 125 * ----------------- 126 * | DDI2 | DP/HDMI port 127 * ----------------- 128 */ 129 130/** 131 * struct bxt_dpio_phy_info - Hold info for a broxton DDI phy 132 */ 133struct bxt_dpio_phy_info { 134 /** 135 * @dual_channel: true if this phy has a second channel. 136 */ 137 bool dual_channel; 138 139 /** 140 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor. 141 * Otherwise the GRC value will be copied from the phy indicated by 142 * this field. 143 */ 144 enum dpio_phy rcomp_phy; 145 146 /** 147 * @reset_delay: delay in us to wait before setting the common reset 148 * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy. 149 */ 150 int reset_delay; 151 152 /** 153 * @pwron_mask: Mask with the appropriate bit set that would cause the 154 * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON. 155 */ 156 u32 pwron_mask; 157 158 /** 159 * @channel: struct containing per channel information. 160 */ 161 struct { 162 /** 163 * @channel.port: which port maps to this channel. 164 */ 165 enum port port; 166 } channel[2]; 167}; 168 169static const struct bxt_dpio_phy_info bxt_dpio_phy_info[] = { 170 [DPIO_PHY0] = { 171 .dual_channel = true, 172 .rcomp_phy = DPIO_PHY1, 173 .pwron_mask = BIT(0), 174 175 .channel = { 176 [DPIO_CH0] = { .port = PORT_B }, 177 [DPIO_CH1] = { .port = PORT_C }, 178 } 179 }, 180 [DPIO_PHY1] = { 181 .dual_channel = false, 182 .rcomp_phy = -1, 183 .pwron_mask = BIT(1), 184 185 .channel = { 186 [DPIO_CH0] = { .port = PORT_A }, 187 } 188 }, 189}; 190 191static const struct bxt_dpio_phy_info glk_dpio_phy_info[] = { 192 [DPIO_PHY0] = { 193 .dual_channel = false, 194 .rcomp_phy = DPIO_PHY1, 195 .pwron_mask = BIT(0), 196 .reset_delay = 20, 197 198 .channel = { 199 [DPIO_CH0] = { .port = PORT_B }, 200 } 201 }, 202 [DPIO_PHY1] = { 203 .dual_channel = false, 204 .rcomp_phy = -1, 205 .pwron_mask = BIT(3), 206 .reset_delay = 20, 207 208 .channel = { 209 [DPIO_CH0] = { .port = PORT_A }, 210 } 211 }, 212 [DPIO_PHY2] = { 213 .dual_channel = false, 214 .rcomp_phy = DPIO_PHY1, 215 .pwron_mask = BIT(1), 216 .reset_delay = 20, 217 218 .channel = { 219 [DPIO_CH0] = { .port = PORT_C }, 220 } 221 }, 222}; 223 224static const struct bxt_dpio_phy_info * 225bxt_get_phy_list(struct intel_display *display, int *count) 226{ 227 if (display->platform.geminilake) { 228 *count = ARRAY_SIZE(glk_dpio_phy_info); 229 return glk_dpio_phy_info; 230 } else { 231 *count = ARRAY_SIZE(bxt_dpio_phy_info); 232 return bxt_dpio_phy_info; 233 } 234} 235 236static const struct bxt_dpio_phy_info * 237bxt_get_phy_info(struct intel_display *display, enum dpio_phy phy) 238{ 239 int count; 240 const struct bxt_dpio_phy_info *phy_list = 241 bxt_get_phy_list(display, &count); 242 243 return &phy_list[phy]; 244} 245 246void bxt_port_to_phy_channel(struct intel_display *display, enum port port, 247 enum dpio_phy *phy, enum dpio_channel *ch) 248{ 249 const struct bxt_dpio_phy_info *phy_info, *phys; 250 int i, count; 251 252 phys = bxt_get_phy_list(display, &count); 253 254 for (i = 0; i < count; i++) { 255 phy_info = &phys[i]; 256 257 if (port == phy_info->channel[DPIO_CH0].port) { 258 *phy = i; 259 *ch = DPIO_CH0; 260 return; 261 } 262 263 if (phy_info->dual_channel && 264 port == phy_info->channel[DPIO_CH1].port) { 265 *phy = i; 266 *ch = DPIO_CH1; 267 return; 268 } 269 } 270 271 drm_WARN(display->drm, 1, "PHY not found for PORT %c", 272 port_name(port)); 273 *phy = DPIO_PHY0; 274 *ch = DPIO_CH0; 275} 276 277/* 278 * Like intel_de_rmw() but reads from a single per-lane register and 279 * writes to the group register to write the same value to all the lanes. 280 */ 281static u32 bxt_dpio_phy_rmw_grp(struct intel_display *display, 282 i915_reg_t reg_single, 283 i915_reg_t reg_group, 284 u32 clear, u32 set) 285{ 286 u32 old, val; 287 288 old = intel_de_read(display, reg_single); 289 val = (old & ~clear) | set; 290 intel_de_write(display, reg_group, val); 291 292 return old; 293} 294 295void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder, 296 const struct intel_crtc_state *crtc_state) 297{ 298 struct intel_display *display = to_intel_display(encoder); 299 const struct intel_ddi_buf_trans *trans; 300 enum dpio_channel ch; 301 enum dpio_phy phy; 302 int lane, n_entries; 303 304 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 305 if (drm_WARN_ON_ONCE(display->drm, !trans)) 306 return; 307 308 bxt_port_to_phy_channel(display, encoder->port, &phy, &ch); 309 310 /* 311 * While we write to the group register to program all lanes at once we 312 * can read only lane registers and we pick lanes 0/1 for that. 313 */ 314 bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch), 315 BXT_PORT_PCS_DW10_GRP(phy, ch), 316 TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT, 0); 317 318 for (lane = 0; lane < crtc_state->lane_count; lane++) { 319 int level = intel_ddi_level(encoder, crtc_state, lane); 320 321 intel_de_rmw(display, BXT_PORT_TX_DW2_LN(phy, ch, lane), 322 MARGIN_000_MASK | UNIQ_TRANS_SCALE_MASK, 323 MARGIN_000(trans->entries[level].bxt.margin) | 324 UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale)); 325 } 326 327 for (lane = 0; lane < crtc_state->lane_count; lane++) { 328 int level = intel_ddi_level(encoder, crtc_state, lane); 329 u32 val; 330 331 intel_de_rmw(display, BXT_PORT_TX_DW3_LN(phy, ch, lane), 332 SCALE_DCOMP_METHOD, 333 trans->entries[level].bxt.enable ? 334 SCALE_DCOMP_METHOD : 0); 335 336 val = intel_de_read(display, BXT_PORT_TX_DW3_LN(phy, ch, lane)); 337 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) 338 drm_err(display->drm, 339 "Disabled scaling while ouniqetrangenmethod was set"); 340 } 341 342 for (lane = 0; lane < crtc_state->lane_count; lane++) { 343 int level = intel_ddi_level(encoder, crtc_state, lane); 344 345 intel_de_rmw(display, BXT_PORT_TX_DW4_LN(phy, ch, lane), 346 DE_EMPHASIS_MASK, 347 DE_EMPHASIS(trans->entries[level].bxt.deemphasis)); 348 } 349 350 bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch), 351 BXT_PORT_PCS_DW10_GRP(phy, ch), 352 0, TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); 353} 354 355bool bxt_dpio_phy_is_enabled(struct intel_display *display, 356 enum dpio_phy phy) 357{ 358 const struct bxt_dpio_phy_info *phy_info; 359 360 phy_info = bxt_get_phy_info(display, phy); 361 362 if (!(intel_de_read(display, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) 363 return false; 364 365 if ((intel_de_read(display, BXT_PORT_CL1CM_DW0(phy)) & 366 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) { 367 drm_dbg(display->drm, 368 "DDI PHY %d powered, but power hasn't settled\n", phy); 369 370 return false; 371 } 372 373 if (!(intel_de_read(display, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { 374 drm_dbg(display->drm, 375 "DDI PHY %d powered, but still in reset\n", phy); 376 377 return false; 378 } 379 380 return true; 381} 382 383static u32 bxt_get_grc(struct intel_display *display, enum dpio_phy phy) 384{ 385 u32 val = intel_de_read(display, BXT_PORT_REF_DW6(phy)); 386 387 return REG_FIELD_GET(GRC_CODE_MASK, val); 388} 389 390static void bxt_phy_wait_grc_done(struct intel_display *display, 391 enum dpio_phy phy) 392{ 393 if (intel_de_wait_for_set_ms(display, BXT_PORT_REF_DW3(phy), GRC_DONE, 10)) 394 drm_err(display->drm, "timeout waiting for PHY%d GRC\n", phy); 395} 396 397static void _bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy) 398{ 399 const struct bxt_dpio_phy_info *phy_info; 400 u32 val; 401 402 phy_info = bxt_get_phy_info(display, phy); 403 404 if (bxt_dpio_phy_is_enabled(display, phy)) { 405 /* Still read out the GRC value for state verification */ 406 if (phy_info->rcomp_phy != -1) 407 display->state.bxt_phy_grc = bxt_get_grc(display, phy); 408 409 if (bxt_dpio_phy_verify_state(display, phy)) { 410 drm_dbg(display->drm, "DDI PHY %d already enabled, " 411 "won't reprogram it\n", phy); 412 return; 413 } 414 415 drm_dbg(display->drm, 416 "DDI PHY %d enabled with invalid state, " 417 "force reprogramming it\n", phy); 418 } 419 420 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask); 421 422 /* 423 * The PHY registers start out inaccessible and respond to reads with 424 * all 1s. Eventually they become accessible as they power up, then 425 * the reserved bit will give the default 0. Poll on the reserved bit 426 * becoming 0 to find when the PHY is accessible. 427 * The flag should get set in 100us according to the HW team, but 428 * use 1ms due to occasional timeouts observed with that. 429 */ 430 if (intel_de_wait_ms(display, BXT_PORT_CL1CM_DW0(phy), 431 PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1, NULL)) 432 drm_err(display->drm, "timeout during PHY%d power on\n", 433 phy); 434 435 /* Program PLL Rcomp code offset */ 436 intel_de_rmw(display, BXT_PORT_CL1CM_DW9(phy), 437 IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xE4)); 438 439 intel_de_rmw(display, BXT_PORT_CL1CM_DW10(phy), 440 IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xE4)); 441 442 /* Program power gating */ 443 intel_de_rmw(display, BXT_PORT_CL1CM_DW28(phy), 0, 444 OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG); 445 446 if (phy_info->dual_channel) 447 intel_de_rmw(display, BXT_PORT_CL2CM_DW6(phy), 0, 448 DW6_OLDO_DYN_PWR_DOWN_EN); 449 450 if (phy_info->rcomp_phy != -1) { 451 u32 grc_code; 452 453 bxt_phy_wait_grc_done(display, phy_info->rcomp_phy); 454 455 /* 456 * PHY0 isn't connected to an RCOMP resistor so copy over 457 * the corresponding calibrated value from PHY1, and disable 458 * the automatic calibration on PHY0. 459 */ 460 val = bxt_get_grc(display, phy_info->rcomp_phy); 461 display->state.bxt_phy_grc = val; 462 463 grc_code = GRC_CODE_FAST(val) | 464 GRC_CODE_SLOW(val) | 465 GRC_CODE_NOM(val); 466 intel_de_write(display, BXT_PORT_REF_DW6(phy), grc_code); 467 intel_de_rmw(display, BXT_PORT_REF_DW8(phy), 468 0, GRC_DIS | GRC_RDY_OVRD); 469 } 470 471 if (phy_info->reset_delay) 472 udelay(phy_info->reset_delay); 473 474 intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS); 475} 476 477void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy) 478{ 479 const struct bxt_dpio_phy_info *phy_info; 480 481 phy_info = bxt_get_phy_info(display, phy); 482 483 intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0); 484 485 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0); 486} 487 488void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy) 489{ 490 const struct bxt_dpio_phy_info *phy_info = bxt_get_phy_info(display, phy); 491 enum dpio_phy rcomp_phy = phy_info->rcomp_phy; 492 bool was_enabled; 493 494 lockdep_assert_held(&display->power.domains.lock); 495 496 was_enabled = true; 497 if (rcomp_phy != -1) 498 was_enabled = bxt_dpio_phy_is_enabled(display, rcomp_phy); 499 500 /* 501 * We need to copy the GRC calibration value from rcomp_phy, 502 * so make sure it's powered up. 503 */ 504 if (!was_enabled) 505 _bxt_dpio_phy_init(display, rcomp_phy); 506 507 _bxt_dpio_phy_init(display, phy); 508 509 if (!was_enabled) 510 bxt_dpio_phy_uninit(display, rcomp_phy); 511} 512 513static bool __printf(6, 7) 514__phy_reg_verify_state(struct intel_display *display, enum dpio_phy phy, 515 i915_reg_t reg, u32 mask, u32 expected, 516 const char *reg_fmt, ...) 517{ 518 struct va_format vaf; 519 va_list args; 520 u32 val; 521 522 val = intel_de_read(display, reg); 523 if ((val & mask) == expected) 524 return true; 525 526 va_start(args, reg_fmt); 527 vaf.fmt = reg_fmt; 528 vaf.va = &args; 529 530 drm_dbg(display->drm, "DDI PHY %d reg %pV [%08x] state mismatch: " 531 "current %08x, expected %08x (mask %08x)\n", 532 phy, &vaf, reg.reg, val, (val & ~mask) | expected, 533 mask); 534 535 va_end(args); 536 537 return false; 538} 539 540bool bxt_dpio_phy_verify_state(struct intel_display *display, 541 enum dpio_phy phy) 542{ 543 const struct bxt_dpio_phy_info *phy_info; 544 u32 mask; 545 bool ok; 546 547 phy_info = bxt_get_phy_info(display, phy); 548 549#define _CHK(reg, mask, exp, fmt, ...) \ 550 __phy_reg_verify_state(display, phy, reg, mask, exp, fmt, \ 551 ## __VA_ARGS__) 552 553 if (!bxt_dpio_phy_is_enabled(display, phy)) 554 return false; 555 556 ok = true; 557 558 /* PLL Rcomp code offset */ 559 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy), 560 IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xe4), 561 "BXT_PORT_CL1CM_DW9(%d)", phy); 562 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy), 563 IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xe4), 564 "BXT_PORT_CL1CM_DW10(%d)", phy); 565 566 /* Power gating */ 567 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG; 568 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask, 569 "BXT_PORT_CL1CM_DW28(%d)", phy); 570 571 if (phy_info->dual_channel) 572 ok &= _CHK(BXT_PORT_CL2CM_DW6(phy), 573 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN, 574 "BXT_PORT_CL2CM_DW6(%d)", phy); 575 576 if (phy_info->rcomp_phy != -1) { 577 u32 grc_code = display->state.bxt_phy_grc; 578 579 grc_code = GRC_CODE_FAST(grc_code) | 580 GRC_CODE_SLOW(grc_code) | 581 GRC_CODE_NOM(grc_code); 582 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK | 583 GRC_CODE_NOM_MASK; 584 ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code, 585 "BXT_PORT_REF_DW6(%d)", phy); 586 587 mask = GRC_DIS | GRC_RDY_OVRD; 588 ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask, 589 "BXT_PORT_REF_DW8(%d)", phy); 590 } 591 592 return ok; 593#undef _CHK 594} 595 596u8 597bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count) 598{ 599 switch (lane_count) { 600 case 1: 601 return 0; 602 case 2: 603 return BIT(2) | BIT(0); 604 case 4: 605 return BIT(3) | BIT(2) | BIT(0); 606 default: 607 MISSING_CASE(lane_count); 608 609 return 0; 610 } 611} 612 613void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder, 614 u8 lane_lat_optim_mask) 615{ 616 struct intel_display *display = to_intel_display(encoder); 617 enum port port = encoder->port; 618 enum dpio_phy phy; 619 enum dpio_channel ch; 620 int lane; 621 622 bxt_port_to_phy_channel(display, port, &phy, &ch); 623 624 for (lane = 0; lane < 4; lane++) { 625 /* 626 * Note that on CHV this flag is called UPAR, but has 627 * the same function. 628 */ 629 intel_de_rmw(display, BXT_PORT_TX_DW14_LN(phy, ch, lane), 630 LATENCY_OPTIM, 631 lane_lat_optim_mask & BIT(lane) ? LATENCY_OPTIM : 0); 632 } 633} 634 635u8 636bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder) 637{ 638 struct intel_display *display = to_intel_display(encoder); 639 enum port port = encoder->port; 640 enum dpio_phy phy; 641 enum dpio_channel ch; 642 int lane; 643 u8 mask; 644 645 bxt_port_to_phy_channel(display, port, &phy, &ch); 646 647 mask = 0; 648 for (lane = 0; lane < 4; lane++) { 649 u32 val = intel_de_read(display, 650 BXT_PORT_TX_DW14_LN(phy, ch, lane)); 651 652 if (val & LATENCY_OPTIM) 653 mask |= BIT(lane); 654 } 655 656 return mask; 657} 658 659enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port) 660{ 661 switch (dig_port->base.port) { 662 default: 663 MISSING_CASE(dig_port->base.port); 664 fallthrough; 665 case PORT_B: 666 case PORT_D: 667 return DPIO_CH0; 668 case PORT_C: 669 return DPIO_CH1; 670 } 671} 672 673enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port) 674{ 675 switch (dig_port->base.port) { 676 default: 677 MISSING_CASE(dig_port->base.port); 678 fallthrough; 679 case PORT_B: 680 case PORT_C: 681 return DPIO_PHY0; 682 case PORT_D: 683 return DPIO_PHY1; 684 } 685} 686 687enum dpio_phy vlv_pipe_to_phy(enum pipe pipe) 688{ 689 switch (pipe) { 690 default: 691 MISSING_CASE(pipe); 692 fallthrough; 693 case PIPE_A: 694 case PIPE_B: 695 return DPIO_PHY0; 696 case PIPE_C: 697 return DPIO_PHY1; 698 } 699} 700 701enum dpio_channel vlv_pipe_to_channel(enum pipe pipe) 702{ 703 switch (pipe) { 704 default: 705 MISSING_CASE(pipe); 706 fallthrough; 707 case PIPE_A: 708 case PIPE_C: 709 return DPIO_CH0; 710 case PIPE_B: 711 return DPIO_CH1; 712 } 713} 714 715void chv_set_phy_signal_level(struct intel_encoder *encoder, 716 const struct intel_crtc_state *crtc_state, 717 u32 deemph_reg_value, u32 margin_reg_value, 718 bool uniq_trans_scale) 719{ 720 struct intel_display *display = to_intel_display(encoder); 721 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 722 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 723 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 724 u32 val; 725 int i; 726 727 vlv_dpio_get(display->drm); 728 729 /* Clear calc init */ 730 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch)); 731 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 732 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 733 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 734 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val); 735 736 if (crtc_state->lane_count > 2) { 737 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch)); 738 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 739 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 740 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 741 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val); 742 } 743 744 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW9(ch)); 745 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 746 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 747 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW9(ch), val); 748 749 if (crtc_state->lane_count > 2) { 750 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW9(ch)); 751 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 752 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 753 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW9(ch), val); 754 } 755 756 /* Program swing deemph */ 757 for (i = 0; i < crtc_state->lane_count; i++) { 758 val = vlv_dpio_read(display->drm, phy, CHV_TX_DW4(ch, i)); 759 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 760 val |= DPIO_SWING_DEEMPH9P5(deemph_reg_value); 761 vlv_dpio_write(display->drm, phy, CHV_TX_DW4(ch, i), val); 762 } 763 764 /* Program swing margin */ 765 for (i = 0; i < crtc_state->lane_count; i++) { 766 val = vlv_dpio_read(display->drm, phy, CHV_TX_DW2(ch, i)); 767 768 val &= ~DPIO_SWING_MARGIN000_MASK; 769 val |= DPIO_SWING_MARGIN000(margin_reg_value); 770 771 /* 772 * Supposedly this value shouldn't matter when unique transition 773 * scale is disabled, but in fact it does matter. Let's just 774 * always program the same value and hope it's OK. 775 */ 776 val &= ~DPIO_UNIQ_TRANS_SCALE_MASK; 777 val |= DPIO_UNIQ_TRANS_SCALE(0x9a); 778 779 vlv_dpio_write(display->drm, phy, CHV_TX_DW2(ch, i), val); 780 } 781 782 /* 783 * The document said it needs to set bit 27 for ch0 and bit 26 784 * for ch1. Might be a typo in the doc. 785 * For now, for this unique transition scale selection, set bit 786 * 27 for ch0 and ch1. 787 */ 788 for (i = 0; i < crtc_state->lane_count; i++) { 789 val = vlv_dpio_read(display->drm, phy, CHV_TX_DW3(ch, i)); 790 if (uniq_trans_scale) 791 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; 792 else 793 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 794 vlv_dpio_write(display->drm, phy, CHV_TX_DW3(ch, i), val); 795 } 796 797 /* Start swing calculation */ 798 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW10(ch)); 799 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 800 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW10(ch), val); 801 802 if (crtc_state->lane_count > 2) { 803 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW10(ch)); 804 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 805 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW10(ch), val); 806 } 807 808 vlv_dpio_put(display->drm); 809} 810 811static void __chv_data_lane_soft_reset(struct intel_encoder *encoder, 812 const struct intel_crtc_state *crtc_state, 813 bool reset) 814{ 815 struct intel_display *display = to_intel_display(encoder); 816 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 817 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 818 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 819 u32 val; 820 821 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW0(ch)); 822 if (reset) 823 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 824 else 825 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 826 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW0(ch), val); 827 828 if (crtc_state->lane_count > 2) { 829 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW0(ch)); 830 if (reset) 831 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 832 else 833 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 834 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW0(ch), val); 835 } 836 837 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW1(ch)); 838 val |= CHV_PCS_REQ_SOFTRESET_EN; 839 if (reset) 840 val &= ~DPIO_PCS_CLK_SOFT_RESET; 841 else 842 val |= DPIO_PCS_CLK_SOFT_RESET; 843 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW1(ch), val); 844 845 if (crtc_state->lane_count > 2) { 846 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW1(ch)); 847 val |= CHV_PCS_REQ_SOFTRESET_EN; 848 if (reset) 849 val &= ~DPIO_PCS_CLK_SOFT_RESET; 850 else 851 val |= DPIO_PCS_CLK_SOFT_RESET; 852 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW1(ch), val); 853 } 854} 855 856void chv_data_lane_soft_reset(struct intel_encoder *encoder, 857 const struct intel_crtc_state *crtc_state, 858 bool reset) 859{ 860 struct intel_display *display = to_intel_display(encoder); 861 862 vlv_dpio_get(display->drm); 863 __chv_data_lane_soft_reset(encoder, crtc_state, reset); 864 vlv_dpio_put(display->drm); 865} 866 867void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 868 const struct intel_crtc_state *crtc_state) 869{ 870 struct intel_display *display = to_intel_display(encoder); 871 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 872 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 873 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 874 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 875 enum pipe pipe = crtc->pipe; 876 unsigned int lane_mask = 877 intel_dp_unused_lane_mask(crtc_state->lane_count); 878 u32 val; 879 880 /* 881 * Must trick the second common lane into life. 882 * Otherwise we can't even access the PLL. 883 */ 884 if (ch == DPIO_CH0 && pipe == PIPE_B) 885 dig_port->release_cl2_override = 886 !chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, true); 887 888 chv_phy_powergate_lanes(encoder, true, lane_mask); 889 890 vlv_dpio_get(display->drm); 891 892 /* Assert data lane reset */ 893 __chv_data_lane_soft_reset(encoder, crtc_state, true); 894 895 /* program left/right clock distribution */ 896 if (pipe != PIPE_B) { 897 val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0); 898 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 899 if (ch == DPIO_CH0) 900 val |= CHV_BUFLEFTENA1_FORCE; 901 if (ch == DPIO_CH1) 902 val |= CHV_BUFRIGHTENA1_FORCE; 903 vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val); 904 } else { 905 val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1); 906 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 907 if (ch == DPIO_CH0) 908 val |= CHV_BUFLEFTENA2_FORCE; 909 if (ch == DPIO_CH1) 910 val |= CHV_BUFRIGHTENA2_FORCE; 911 vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val); 912 } 913 914 /* program clock channel usage */ 915 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW8(ch)); 916 val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; 917 if (pipe == PIPE_B) 918 val |= DPIO_PCS_USEDCLKCHANNEL; 919 else 920 val &= ~DPIO_PCS_USEDCLKCHANNEL; 921 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW8(ch), val); 922 923 if (crtc_state->lane_count > 2) { 924 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW8(ch)); 925 val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; 926 if (pipe == PIPE_B) 927 val |= DPIO_PCS_USEDCLKCHANNEL; 928 else 929 val &= ~DPIO_PCS_USEDCLKCHANNEL; 930 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW8(ch), val); 931 } 932 933 /* 934 * This a a bit weird since generally CL 935 * matches the pipe, but here we need to 936 * pick the CL based on the port. 937 */ 938 val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW19(ch)); 939 if (pipe == PIPE_B) 940 val |= CHV_CMN_USEDCLKCHANNEL; 941 else 942 val &= ~CHV_CMN_USEDCLKCHANNEL; 943 vlv_dpio_write(display->drm, phy, CHV_CMN_DW19(ch), val); 944 945 vlv_dpio_put(display->drm); 946} 947 948void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 949 const struct intel_crtc_state *crtc_state) 950{ 951 struct intel_display *display = to_intel_display(encoder); 952 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 953 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 954 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 955 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 956 int data, i, stagger; 957 u32 val; 958 959 vlv_dpio_get(display->drm); 960 961 /* allow hardware to manage TX FIFO reset source */ 962 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch)); 963 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 964 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val); 965 966 if (crtc_state->lane_count > 2) { 967 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch)); 968 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 969 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val); 970 } 971 972 /* Program Tx lane latency optimal setting*/ 973 for (i = 0; i < crtc_state->lane_count; i++) { 974 /* Set the upar bit */ 975 if (crtc_state->lane_count == 1) 976 data = 0; 977 else 978 data = (i == 1) ? 0 : DPIO_UPAR; 979 vlv_dpio_write(display->drm, phy, CHV_TX_DW14(ch, i), data); 980 } 981 982 /* Data lane stagger programming */ 983 if (crtc_state->port_clock > 270000) 984 stagger = 0x18; 985 else if (crtc_state->port_clock > 135000) 986 stagger = 0xd; 987 else if (crtc_state->port_clock > 67500) 988 stagger = 0x7; 989 else if (crtc_state->port_clock > 33750) 990 stagger = 0x4; 991 else 992 stagger = 0x2; 993 994 val = vlv_dpio_read(display->drm, phy, VLV_PCS01_DW11(ch)); 995 val |= DPIO_TX2_STAGGER_MASK(0x1f); 996 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW11(ch), val); 997 998 if (crtc_state->lane_count > 2) { 999 val = vlv_dpio_read(display->drm, phy, VLV_PCS23_DW11(ch)); 1000 val |= DPIO_TX2_STAGGER_MASK(0x1f); 1001 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW11(ch), val); 1002 } 1003 1004 vlv_dpio_write(display->drm, phy, VLV_PCS01_DW12(ch), 1005 DPIO_LANESTAGGER_STRAP(stagger) | 1006 DPIO_LANESTAGGER_STRAP_OVRD | 1007 DPIO_TX1_STAGGER_MASK(0x1f) | 1008 DPIO_TX1_STAGGER_MULT(6) | 1009 DPIO_TX2_STAGGER_MULT(0)); 1010 1011 if (crtc_state->lane_count > 2) { 1012 vlv_dpio_write(display->drm, phy, VLV_PCS23_DW12(ch), 1013 DPIO_LANESTAGGER_STRAP(stagger) | 1014 DPIO_LANESTAGGER_STRAP_OVRD | 1015 DPIO_TX1_STAGGER_MASK(0x1f) | 1016 DPIO_TX1_STAGGER_MULT(7) | 1017 DPIO_TX2_STAGGER_MULT(5)); 1018 } 1019 1020 /* Deassert data lane reset */ 1021 __chv_data_lane_soft_reset(encoder, crtc_state, false); 1022 1023 vlv_dpio_put(display->drm); 1024} 1025 1026void chv_phy_release_cl2_override(struct intel_encoder *encoder) 1027{ 1028 struct intel_display *display = to_intel_display(encoder); 1029 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1030 1031 if (dig_port->release_cl2_override) { 1032 chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, false); 1033 dig_port->release_cl2_override = false; 1034 } 1035} 1036 1037void chv_phy_post_pll_disable(struct intel_encoder *encoder, 1038 const struct intel_crtc_state *old_crtc_state) 1039{ 1040 struct intel_display *display = to_intel_display(encoder); 1041 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); 1042 enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe; 1043 u32 val; 1044 1045 vlv_dpio_get(display->drm); 1046 1047 /* disable left/right clock distribution */ 1048 if (pipe != PIPE_B) { 1049 val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW5_CH0); 1050 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 1051 vlv_dpio_write(display->drm, phy, CHV_CMN_DW5_CH0, val); 1052 } else { 1053 val = vlv_dpio_read(display->drm, phy, CHV_CMN_DW1_CH1); 1054 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 1055 vlv_dpio_write(display->drm, phy, CHV_CMN_DW1_CH1, val); 1056 } 1057 1058 vlv_dpio_put(display->drm); 1059 1060 /* 1061 * Leave the power down bit cleared for at least one 1062 * lane so that chv_powergate_phy_ch() will power 1063 * on something when the channel is otherwise unused. 1064 * When the port is off and the override is removed 1065 * the lanes power down anyway, so otherwise it doesn't 1066 * really matter what the state of power down bits is 1067 * after this. 1068 */ 1069 chv_phy_powergate_lanes(encoder, false, 0x0); 1070} 1071 1072void vlv_set_phy_signal_level(struct intel_encoder *encoder, 1073 const struct intel_crtc_state *crtc_state, 1074 u32 demph_reg_value, u32 preemph_reg_value, 1075 u32 uniqtranscale_reg_value, u32 tx3_demph) 1076{ 1077 struct intel_display *display = to_intel_display(encoder); 1078 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1079 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 1080 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 1081 1082 vlv_dpio_get(display->drm); 1083 1084 vlv_dpio_write(display->drm, phy, VLV_TX_DW5_GRP(ch), 0x00000000); 1085 vlv_dpio_write(display->drm, phy, VLV_TX_DW4_GRP(ch), demph_reg_value); 1086 vlv_dpio_write(display->drm, phy, VLV_TX_DW2_GRP(ch), 1087 uniqtranscale_reg_value); 1088 vlv_dpio_write(display->drm, phy, VLV_TX_DW3_GRP(ch), 0x0C782040); 1089 1090 if (tx3_demph) 1091 vlv_dpio_write(display->drm, phy, VLV_TX_DW4(ch, 3), tx3_demph); 1092 1093 vlv_dpio_write(display->drm, phy, VLV_PCS_DW11_GRP(ch), 0x00030000); 1094 vlv_dpio_write(display->drm, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value); 1095 vlv_dpio_write(display->drm, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN); 1096 1097 vlv_dpio_put(display->drm); 1098} 1099 1100void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, 1101 const struct intel_crtc_state *crtc_state) 1102{ 1103 struct intel_display *display = to_intel_display(encoder); 1104 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1105 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 1106 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 1107 1108 /* Program Tx lane resets to default */ 1109 vlv_dpio_get(display->drm); 1110 1111 vlv_dpio_write(display->drm, phy, VLV_PCS_DW0_GRP(ch), 1112 DPIO_PCS_TX_LANE2_RESET | 1113 DPIO_PCS_TX_LANE1_RESET); 1114 vlv_dpio_write(display->drm, phy, VLV_PCS_DW1_GRP(ch), 1115 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1116 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1117 DPIO_PCS_CLK_DATAWIDTH_8_10 | 1118 DPIO_PCS_CLK_SOFT_RESET); 1119 1120 /* Fix up inter-pair skew failure */ 1121 vlv_dpio_write(display->drm, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00); 1122 vlv_dpio_write(display->drm, phy, VLV_TX_DW11_GRP(ch), 0x00001500); 1123 vlv_dpio_write(display->drm, phy, VLV_TX_DW14_GRP(ch), 0x40400000); 1124 1125 vlv_dpio_put(display->drm); 1126} 1127 1128void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, 1129 const struct intel_crtc_state *crtc_state) 1130{ 1131 struct intel_display *display = to_intel_display(encoder); 1132 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1133 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1134 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1135 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 1136 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 1137 enum pipe pipe = crtc->pipe; 1138 u32 val; 1139 1140 vlv_dpio_get(display->drm); 1141 1142 /* Enable clock channels for this port */ 1143 val = DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; 1144 if (pipe == PIPE_B) 1145 val |= DPIO_PCS_USEDCLKCHANNEL; 1146 val |= 0xc4; 1147 vlv_dpio_write(display->drm, phy, VLV_PCS_DW8_GRP(ch), val); 1148 1149 /* Program lane clock */ 1150 vlv_dpio_write(display->drm, phy, VLV_PCS_DW14_GRP(ch), 0x00760018); 1151 vlv_dpio_write(display->drm, phy, VLV_PCS_DW23_GRP(ch), 0x00400888); 1152 1153 vlv_dpio_put(display->drm); 1154} 1155 1156void vlv_phy_reset_lanes(struct intel_encoder *encoder, 1157 const struct intel_crtc_state *old_crtc_state) 1158{ 1159 struct intel_display *display = to_intel_display(encoder); 1160 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1161 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 1162 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 1163 1164 vlv_dpio_get(display->drm); 1165 vlv_dpio_write(display->drm, phy, VLV_PCS_DW0_GRP(ch), 0x00000000); 1166 vlv_dpio_write(display->drm, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060); 1167 vlv_dpio_put(display->drm); 1168} 1169 1170void vlv_wait_port_ready(struct intel_encoder *encoder, 1171 unsigned int expected_mask) 1172{ 1173 struct intel_display *display = to_intel_display(encoder); 1174 u32 port_mask; 1175 i915_reg_t dpll_reg; 1176 u32 val; 1177 1178 switch (encoder->port) { 1179 default: 1180 MISSING_CASE(encoder->port); 1181 fallthrough; 1182 case PORT_B: 1183 port_mask = DPLL_PORTB_READY_MASK; 1184 dpll_reg = DPLL(display, 0); 1185 break; 1186 case PORT_C: 1187 port_mask = DPLL_PORTC_READY_MASK; 1188 dpll_reg = DPLL(display, 0); 1189 expected_mask <<= 4; 1190 break; 1191 case PORT_D: 1192 port_mask = DPLL_PORTD_READY_MASK; 1193 dpll_reg = DPIO_PHY_STATUS; 1194 break; 1195 } 1196 1197 if (intel_de_wait_ms(display, dpll_reg, port_mask, expected_mask, 1000, &val)) 1198 drm_WARN(display->drm, 1, 1199 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", 1200 encoder->base.base.id, encoder->base.name, 1201 val & port_mask, expected_mask); 1202}
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