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intel_dp_link_training.c
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linux-6.19.14/drivers/gpu/drm/i915/display/intel_dp_link_training.c
1/* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#include <linux/debugfs.h> 25#include <linux/iopoll.h> 26 27#include <drm/display/drm_dp_helper.h> 28#include <drm/drm_print.h> 29 30#include "intel_display_core.h" 31#include "intel_display_jiffies.h" 32#include "intel_display_types.h" 33#include "intel_display_utils.h" 34#include "intel_dp.h" 35#include "intel_dp_link_training.h" 36#include "intel_encoder.h" 37#include "intel_hotplug.h" 38#include "intel_panel.h" 39 40#define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " 41#define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \ 42 (_intel_dp)->attached_connector->base.name, \ 43 dp_to_dig_port(_intel_dp)->base.base.base.id, \ 44 dp_to_dig_port(_intel_dp)->base.base.name, \ 45 drm_dp_phy_name(_dp_phy) 46 47#define lt_dbg(_intel_dp, _dp_phy, _format, ...) \ 48 drm_dbg_kms(to_intel_display(_intel_dp)->drm, \ 49 LT_MSG_PREFIX _format, \ 50 LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__) 51 52#define lt_err(_intel_dp, _dp_phy, _format, ...) do { \ 53 if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \ 54 drm_err(to_intel_display(_intel_dp)->drm, \ 55 LT_MSG_PREFIX _format, \ 56 LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__); \ 57 else \ 58 lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## __VA_ARGS__); \ 59} while (0) 60 61#define MAX_SEQ_TRAIN_FAILURES 2 62 63static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp) 64{ 65 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); 66} 67 68static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) 69{ 70 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - 71 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0; 72} 73 74static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp, 75 enum drm_dp_phy dp_phy) 76{ 77 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; 78} 79 80static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, 81 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 82 enum drm_dp_phy dp_phy) 83{ 84 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 85 86 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { 87 lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n"); 88 return; 89 } 90 91 lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n", 92 (int)sizeof(intel_dp->lttpr_phy_caps[0]), 93 phy_caps); 94} 95 96static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, 97 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 98{ 99 int ret; 100 101 ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd, 102 intel_dp->lttpr_common_caps); 103 if (ret < 0) 104 goto reset_caps; 105 106 lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n", 107 (int)sizeof(intel_dp->lttpr_common_caps), 108 intel_dp->lttpr_common_caps); 109 110 /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */ 111 if (intel_dp->lttpr_common_caps[0] < 0x14) 112 goto reset_caps; 113 114 return true; 115 116reset_caps: 117 intel_dp_reset_lttpr_common_caps(intel_dp); 118 return false; 119} 120 121static bool 122intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) 123{ 124 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 125 DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 126 127 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE - 128 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = val; 129 130 return true; 131} 132 133bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp) 134{ 135 return intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE - 136 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] == 137 DP_PHY_REPEATER_MODE_TRANSPARENT; 138} 139 140/* 141 * Read the LTTPR common capabilities and switch the LTTPR PHYs to 142 * non-transparent mode if this is supported. Preserve the 143 * transparent/non-transparent mode on an active link. 144 * 145 * Return the number of detected LTTPRs in non-transparent mode or 0 if the 146 * LTTPRs are in transparent mode or the detection failed. 147 */ 148static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 149{ 150 int lttpr_count; 151 int ret; 152 153 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) 154 return 0; 155 156 lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 157 /* 158 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are 159 * detected as this breaks link training at least on the Dell WD19TB 160 * dock. 161 */ 162 if (lttpr_count == 0) 163 return 0; 164 165 /* 166 * Don't change the mode on an active link, to prevent a loss of link 167 * synchronization. See DP Standard v2.0 3.6.7. about the LTTPR 168 * resetting its internal state when the mode is changed from 169 * non-transparent to transparent. 170 */ 171 if (intel_dp->link.active) { 172 if (lttpr_count < 0 || intel_dp_lttpr_transparent_mode_enabled(intel_dp)) 173 goto out_reset_lttpr_count; 174 175 return lttpr_count; 176 } 177 178 ret = drm_dp_lttpr_init(&intel_dp->aux, lttpr_count); 179 if (ret) { 180 lt_dbg(intel_dp, DP_PHY_DPRX, 181 "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n"); 182 183 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 184 185 goto out_reset_lttpr_count; 186 } 187 188 intel_dp_set_lttpr_transparent_mode(intel_dp, false); 189 190 return lttpr_count; 191 192out_reset_lttpr_count: 193 intel_dp_reset_lttpr_count(intel_dp); 194 195 return 0; 196} 197 198static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 199{ 200 int lttpr_count; 201 int i; 202 203 lttpr_count = intel_dp_init_lttpr_phys(intel_dp, dpcd); 204 205 for (i = 0; i < lttpr_count; i++) { 206 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i)); 207 drm_dp_dump_lttpr_desc(&intel_dp->aux, DP_PHY_LTTPR(i)); 208 } 209 210 return lttpr_count; 211} 212 213int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]) 214{ 215 struct intel_display *display = to_intel_display(intel_dp); 216 217 if (intel_dp_is_edp(intel_dp)) 218 return 0; 219 220 /* 221 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 222 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 223 */ 224 if (DISPLAY_VER(display) >= 10 && !display->platform.geminilake) 225 if (drm_dp_dpcd_probe(&intel_dp->aux, 226 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV)) 227 return -EIO; 228 229 if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd)) 230 return -EIO; 231 232 return 0; 233} 234 235/** 236 * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode 237 * @intel_dp: Intel DP struct 238 * 239 * Read the LTTPR common and DPRX capabilities and switch to non-transparent 240 * link training mode if any is detected and read the PHY capabilities for all 241 * detected LTTPRs. In case of an LTTPR detection error or if the number of 242 * LTTPRs is more than is supported (8), fall back to the no-LTTPR, 243 * transparent mode link training mode. 244 * 245 * Returns: 246 * >0 if LTTPRs were detected and the non-transparent LT mode was set. The 247 * DPRX capabilities are read out. 248 * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a 249 * detection failure and the transparent LT mode was set. The DPRX 250 * capabilities are read out. 251 * <0 Reading out the DPRX capabilities failed. 252 */ 253int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) 254{ 255 struct intel_display *display = to_intel_display(intel_dp); 256 int lttpr_count = 0; 257 258 /* 259 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 260 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 261 */ 262 if (!intel_dp_is_edp(intel_dp) && 263 (DISPLAY_VER(display) >= 10 && !display->platform.geminilake)) { 264 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 265 int err = intel_dp_read_dprx_caps(intel_dp, dpcd); 266 267 if (err != 0) 268 return err; 269 270 lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd); 271 } 272 273 /* 274 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read 275 * it here. 276 */ 277 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) { 278 intel_dp_reset_lttpr_common_caps(intel_dp); 279 return -EIO; 280 } 281 282 return lttpr_count; 283} 284 285static u8 dp_voltage_max(u8 preemph) 286{ 287 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) { 288 case DP_TRAIN_PRE_EMPH_LEVEL_0: 289 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 290 case DP_TRAIN_PRE_EMPH_LEVEL_1: 291 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 292 case DP_TRAIN_PRE_EMPH_LEVEL_2: 293 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1; 294 case DP_TRAIN_PRE_EMPH_LEVEL_3: 295 default: 296 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 297 } 298} 299 300static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp, 301 enum drm_dp_phy dp_phy) 302{ 303 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 304 305 if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps)) 306 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 307 else 308 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 309} 310 311static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp, 312 enum drm_dp_phy dp_phy) 313{ 314 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 315 316 if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps)) 317 return DP_TRAIN_PRE_EMPH_LEVEL_3; 318 else 319 return DP_TRAIN_PRE_EMPH_LEVEL_2; 320} 321 322static bool 323intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp, 324 enum drm_dp_phy dp_phy) 325{ 326 struct intel_display *display = to_intel_display(intel_dp); 327 int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 328 329 drm_WARN_ON_ONCE(display->drm, 330 lttpr_count <= 0 && dp_phy != DP_PHY_DPRX); 331 332 return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1); 333} 334 335static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp, 336 const struct intel_crtc_state *crtc_state, 337 enum drm_dp_phy dp_phy) 338{ 339 struct intel_display *display = to_intel_display(intel_dp); 340 u8 voltage_max; 341 342 /* 343 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from 344 * the DPRX_PHY we train. 345 */ 346 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 347 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state); 348 else 349 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1); 350 351 drm_WARN_ON_ONCE(display->drm, 352 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 && 353 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3); 354 355 return voltage_max; 356} 357 358static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, 359 enum drm_dp_phy dp_phy) 360{ 361 struct intel_display *display = to_intel_display(intel_dp); 362 u8 preemph_max; 363 364 /* 365 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from 366 * the DPRX_PHY we train. 367 */ 368 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 369 preemph_max = intel_dp->preemph_max(intel_dp); 370 else 371 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1); 372 373 drm_WARN_ON_ONCE(display->drm, 374 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 && 375 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3); 376 377 return preemph_max; 378} 379 380static bool has_per_lane_signal_levels(struct intel_dp *intel_dp, 381 enum drm_dp_phy dp_phy) 382{ 383 struct intel_display *display = to_intel_display(intel_dp); 384 385 return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) || 386 DISPLAY_VER(display) >= 10 || display->platform.broxton; 387} 388 389/* 128b/132b */ 390static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp, 391 const struct intel_crtc_state *crtc_state, 392 enum drm_dp_phy dp_phy, 393 const u8 link_status[DP_LINK_STATUS_SIZE], 394 int lane) 395{ 396 u8 tx_ffe = 0; 397 398 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 399 lane = min(lane, crtc_state->lane_count - 1); 400 tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane); 401 } else { 402 for (lane = 0; lane < crtc_state->lane_count; lane++) 403 tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); 404 } 405 406 return tx_ffe; 407} 408 409/* 8b/10b */ 410static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp, 411 const struct intel_crtc_state *crtc_state, 412 enum drm_dp_phy dp_phy, 413 const u8 link_status[DP_LINK_STATUS_SIZE], 414 int lane) 415{ 416 u8 v = 0; 417 u8 p = 0; 418 u8 voltage_max; 419 u8 preemph_max; 420 421 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 422 lane = min(lane, crtc_state->lane_count - 1); 423 424 v = drm_dp_get_adjust_request_voltage(link_status, lane); 425 p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 426 } else { 427 for (lane = 0; lane < crtc_state->lane_count; lane++) { 428 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); 429 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); 430 } 431 } 432 433 preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); 434 if (p >= preemph_max) 435 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 436 437 v = min(v, dp_voltage_max(p)); 438 439 voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy); 440 if (v >= voltage_max) 441 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 442 443 return v | p; 444} 445 446static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, 447 const struct intel_crtc_state *crtc_state, 448 enum drm_dp_phy dp_phy, 449 const u8 link_status[DP_LINK_STATUS_SIZE], 450 int lane) 451{ 452 if (intel_dp_is_uhbr(crtc_state)) 453 return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state, 454 dp_phy, link_status, lane); 455 else 456 return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state, 457 dp_phy, link_status, lane); 458} 459 460#define TRAIN_REQ_FMT "%d/%d/%d/%d" 461#define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \ 462 (drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT) 463#define TRAIN_REQ_VSWING_ARGS(link_status) \ 464 _TRAIN_REQ_VSWING_ARGS(link_status, 0), \ 465 _TRAIN_REQ_VSWING_ARGS(link_status, 1), \ 466 _TRAIN_REQ_VSWING_ARGS(link_status, 2), \ 467 _TRAIN_REQ_VSWING_ARGS(link_status, 3) 468#define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \ 469 (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT) 470#define TRAIN_REQ_PREEMPH_ARGS(link_status) \ 471 _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \ 472 _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \ 473 _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \ 474 _TRAIN_REQ_PREEMPH_ARGS(link_status, 3) 475#define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) \ 476 drm_dp_get_adjust_tx_ffe_preset((link_status), (lane)) 477#define TRAIN_REQ_TX_FFE_ARGS(link_status) \ 478 _TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \ 479 _TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \ 480 _TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \ 481 _TRAIN_REQ_TX_FFE_ARGS(link_status, 3) 482 483bool 484intel_dp_get_adjust_train(struct intel_dp *intel_dp, 485 const struct intel_crtc_state *crtc_state, 486 enum drm_dp_phy dp_phy, 487 const u8 link_status[DP_LINK_STATUS_SIZE]) 488{ 489 bool changed = false; 490 int lane; 491 492 if (intel_dp_is_uhbr(crtc_state)) { 493 lt_dbg(intel_dp, dp_phy, 494 "128b/132b, lanes: %d, " 495 "TX FFE request: " TRAIN_REQ_FMT "\n", 496 crtc_state->lane_count, 497 TRAIN_REQ_TX_FFE_ARGS(link_status)); 498 } else { 499 lt_dbg(intel_dp, dp_phy, 500 "8b/10b, lanes: %d, " 501 "vswing request: " TRAIN_REQ_FMT ", " 502 "pre-emphasis request: " TRAIN_REQ_FMT "\n", 503 crtc_state->lane_count, 504 TRAIN_REQ_VSWING_ARGS(link_status), 505 TRAIN_REQ_PREEMPH_ARGS(link_status)); 506 } 507 508 for (lane = 0; lane < 4; lane++) { 509 u8 new = intel_dp_get_lane_adjust_train(intel_dp, crtc_state, 510 dp_phy, link_status, lane); 511 if (intel_dp->train_set[lane] == new) 512 continue; 513 514 intel_dp->train_set[lane] = new; 515 changed = true; 516 } 517 518 return changed; 519} 520 521static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, 522 enum drm_dp_phy dp_phy) 523{ 524 return dp_phy == DP_PHY_DPRX ? 525 DP_TRAINING_PATTERN_SET : 526 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy); 527} 528 529static bool 530intel_dp_set_link_train(struct intel_dp *intel_dp, 531 const struct intel_crtc_state *crtc_state, 532 enum drm_dp_phy dp_phy, 533 u8 dp_train_pat) 534{ 535 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 536 u8 buf[sizeof(intel_dp->train_set) + 1]; 537 int len; 538 539 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 540 dp_phy, dp_train_pat); 541 542 buf[0] = dp_train_pat; 543 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 544 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); 545 len = crtc_state->lane_count + 1; 546 547 return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len; 548} 549 550static char dp_training_pattern_name(u8 train_pat) 551{ 552 switch (train_pat) { 553 case DP_TRAINING_PATTERN_1: 554 case DP_TRAINING_PATTERN_2: 555 case DP_TRAINING_PATTERN_3: 556 return '0' + train_pat; 557 case DP_TRAINING_PATTERN_4: 558 return '4'; 559 default: 560 MISSING_CASE(train_pat); 561 return '?'; 562 } 563} 564 565void 566intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 567 const struct intel_crtc_state *crtc_state, 568 enum drm_dp_phy dp_phy, 569 u8 dp_train_pat) 570{ 571 u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat); 572 573 if (train_pat != DP_TRAINING_PATTERN_DISABLE) 574 lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n", 575 dp_training_pattern_name(train_pat)); 576 577 intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat); 578} 579 580#define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s" 581#define _TRAIN_SET_VSWING_ARGS(train_set) \ 582 ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \ 583 (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : "" 584#define TRAIN_SET_VSWING_ARGS(train_set) \ 585 _TRAIN_SET_VSWING_ARGS((train_set)[0]), \ 586 _TRAIN_SET_VSWING_ARGS((train_set)[1]), \ 587 _TRAIN_SET_VSWING_ARGS((train_set)[2]), \ 588 _TRAIN_SET_VSWING_ARGS((train_set)[3]) 589#define _TRAIN_SET_PREEMPH_ARGS(train_set) \ 590 ((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \ 591 (train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : "" 592#define TRAIN_SET_PREEMPH_ARGS(train_set) \ 593 _TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \ 594 _TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \ 595 _TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \ 596 _TRAIN_SET_PREEMPH_ARGS((train_set)[3]) 597#define _TRAIN_SET_TX_FFE_ARGS(train_set) \ 598 ((train_set) & DP_TX_FFE_PRESET_VALUE_MASK), "" 599#define TRAIN_SET_TX_FFE_ARGS(train_set) \ 600 _TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \ 601 _TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \ 602 _TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \ 603 _TRAIN_SET_TX_FFE_ARGS((train_set)[3]) 604 605void intel_dp_set_signal_levels(struct intel_dp *intel_dp, 606 const struct intel_crtc_state *crtc_state, 607 enum drm_dp_phy dp_phy) 608{ 609 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 610 611 if (intel_dp_is_uhbr(crtc_state)) { 612 lt_dbg(intel_dp, dp_phy, 613 "128b/132b, lanes: %d, " 614 "TX FFE presets: " TRAIN_SET_FMT "\n", 615 crtc_state->lane_count, 616 TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set)); 617 } else { 618 lt_dbg(intel_dp, dp_phy, 619 "8b/10b, lanes: %d, " 620 "vswing levels: " TRAIN_SET_FMT ", " 621 "pre-emphasis levels: " TRAIN_SET_FMT "\n", 622 crtc_state->lane_count, 623 TRAIN_SET_VSWING_ARGS(intel_dp->train_set), 624 TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set)); 625 } 626 627 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 628 encoder->set_signal_levels(encoder, crtc_state); 629} 630 631static bool 632intel_dp_reset_link_train(struct intel_dp *intel_dp, 633 const struct intel_crtc_state *crtc_state, 634 enum drm_dp_phy dp_phy, 635 u8 dp_train_pat) 636{ 637 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 638 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 639 return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat); 640} 641 642static bool 643intel_dp_update_link_train(struct intel_dp *intel_dp, 644 const struct intel_crtc_state *crtc_state, 645 enum drm_dp_phy dp_phy) 646{ 647 int reg = dp_phy == DP_PHY_DPRX ? 648 DP_TRAINING_LANE0_SET : 649 DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy); 650 int ret; 651 652 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 653 654 ret = drm_dp_dpcd_write(&intel_dp->aux, reg, 655 intel_dp->train_set, crtc_state->lane_count); 656 657 return ret == crtc_state->lane_count; 658} 659 660/* 128b/132b */ 661static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane) 662{ 663 return (train_set_lane & DP_TX_FFE_PRESET_VALUE_MASK) == 664 DP_TX_FFE_PRESET_VALUE_MASK; 665} 666 667/* 668 * 8b/10b 669 * 670 * FIXME: The DP spec is very confusing here, also the Link CTS spec seems to 671 * have self contradicting tests around this area. 672 * 673 * In lieu of better ideas let's just stop when we've reached the max supported 674 * vswing with its max pre-emphasis, which is either 2+1 or 3+0 depending on 675 * whether vswing level 3 is supported or not. 676 */ 677static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane) 678{ 679 u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> 680 DP_TRAIN_VOLTAGE_SWING_SHIFT; 681 u8 p = (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> 682 DP_TRAIN_PRE_EMPHASIS_SHIFT; 683 684 if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) == 0) 685 return false; 686 687 if (v + p != 3) 688 return false; 689 690 return true; 691} 692 693static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, 694 const struct intel_crtc_state *crtc_state) 695{ 696 int lane; 697 698 for (lane = 0; lane < crtc_state->lane_count; lane++) { 699 u8 train_set_lane = intel_dp->train_set[lane]; 700 701 if (intel_dp_is_uhbr(crtc_state)) { 702 if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane)) 703 return false; 704 } else { 705 if (!intel_dp_lane_max_vswing_reached(train_set_lane)) 706 return false; 707 } 708 } 709 710 return true; 711} 712 713void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr) 714{ 715 u8 link_config[2]; 716 717 link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; 718 link_config[1] = drm_dp_is_uhbr_rate(link_rate) ? 719 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; 720 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 721} 722 723static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, 724 const struct intel_crtc_state *crtc_state) 725{ 726 /* 727 * Currently, we set the MSA ignore bit based on vrr.in_range. 728 * We can't really read that out during driver load since we don't have 729 * the connector information read in yet. So if we do end up doing a 730 * modeset during initial_commit() we'll clear the MSA ignore bit. 731 * GOP likely wouldn't have set this bit so after the initial commit, 732 * if there are no modesets and we enable VRR mode seamlessly 733 * (without a full modeset), the MSA ignore bit might never get set. 734 * 735 * #TODO: Implement readout of vrr.in_range. 736 * We need fastset support for setting the MSA ignore bit in DPCD, 737 * especially on the first real commit when clearing the inherited flag. 738 */ 739 intel_dp_link_training_set_mode(intel_dp, 740 crtc_state->port_clock, crtc_state->vrr.in_range); 741} 742 743void intel_dp_link_training_set_bw(struct intel_dp *intel_dp, 744 int link_bw, int rate_select, int lane_count, 745 bool enhanced_framing) 746{ 747 if (enhanced_framing) 748 lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 749 750 if (link_bw) { 751 /* DP and eDP v1.3 and earlier link bw set method. */ 752 u8 link_config[] = { link_bw, lane_count }; 753 754 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 755 ARRAY_SIZE(link_config)); 756 } else { 757 /* 758 * eDP v1.4 and later link rate set method. 759 * 760 * eDP v1.4x sinks shall ignore DP_LINK_RATE_SET if 761 * DP_LINK_BW_SET is set. Avoid writing DP_LINK_BW_SET. 762 * 763 * eDP v1.5 sinks allow choosing either, and the last choice 764 * shall be active. 765 */ 766 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count); 767 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select); 768 } 769} 770 771/* 772 * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2 773 * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or 774 * 1.2 devices that support it, TPS2 otherwise. 775 */ 776static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, 777 const struct intel_crtc_state *crtc_state, 778 enum drm_dp_phy dp_phy) 779{ 780 struct intel_display *display = to_intel_display(intel_dp); 781 bool source_tps3, sink_tps3, source_tps4, sink_tps4; 782 783 /* UHBR+ use separate 128b/132b TPS2 */ 784 if (intel_dp_is_uhbr(crtc_state)) 785 return DP_TRAINING_PATTERN_2; 786 787 /* 788 * TPS4 support is mandatory for all downstream devices that 789 * support HBR3. There are no known eDP panels that support 790 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification. 791 * LTTPRs must support TPS4. 792 */ 793 source_tps4 = intel_dp_source_supports_tps4(display); 794 sink_tps4 = dp_phy != DP_PHY_DPRX || 795 drm_dp_tps4_supported(intel_dp->dpcd); 796 if (source_tps4 && sink_tps4) { 797 return DP_TRAINING_PATTERN_4; 798 } else if (crtc_state->port_clock == 810000) { 799 if (!source_tps4) 800 lt_dbg(intel_dp, dp_phy, 801 "8.1 Gbps link rate without source TPS4 support\n"); 802 if (!sink_tps4) 803 lt_dbg(intel_dp, dp_phy, 804 "8.1 Gbps link rate without sink TPS4 support\n"); 805 } 806 807 /* 808 * TPS3 support is mandatory for downstream devices that 809 * support HBR2. However, not all sinks follow the spec. 810 */ 811 source_tps3 = intel_dp_source_supports_tps3(display); 812 sink_tps3 = dp_phy != DP_PHY_DPRX || 813 drm_dp_tps3_supported(intel_dp->dpcd); 814 if (source_tps3 && sink_tps3) { 815 return DP_TRAINING_PATTERN_3; 816 } else if (crtc_state->port_clock >= 540000) { 817 if (!source_tps3) 818 lt_dbg(intel_dp, dp_phy, 819 ">=5.4/6.48 Gbps link rate without source TPS3 support\n"); 820 if (!sink_tps3) 821 lt_dbg(intel_dp, dp_phy, 822 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); 823 } 824 825 return DP_TRAINING_PATTERN_2; 826} 827 828static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp, 829 const struct intel_crtc_state *crtc_state, 830 u8 link_bw, u8 rate_select) 831{ 832 intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count, 833 crtc_state->enhanced_framing); 834} 835 836/* 837 * Prepare link training by configuring the link parameters. On DDI platforms 838 * also enable the port here. 839 */ 840static bool 841intel_dp_prepare_link_train(struct intel_dp *intel_dp, 842 const struct intel_crtc_state *crtc_state) 843{ 844 u8 link_bw, rate_select; 845 846 if (intel_dp->prepare_link_retrain) 847 intel_dp->prepare_link_retrain(intel_dp, crtc_state); 848 849 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, 850 &link_bw, &rate_select); 851 852 /* 853 * WaEdpLinkRateDataReload 854 * 855 * Parade PS8461E MUX (used on various TGL+ laptops) needs 856 * to snoop the link rates reported by the sink when we 857 * use LINK_RATE_SET in order to operate in jitter cleaning 858 * mode (as opposed to redriver mode). Unfortunately it 859 * loses track of the snooped link rates when powered down, 860 * so we need to make it re-snoop often. Without this high 861 * link rates are not stable. 862 */ 863 if (!link_bw) { 864 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 865 866 lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n"); 867 868 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 869 sink_rates, sizeof(sink_rates)); 870 } 871 872 if (link_bw) 873 lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n", 874 link_bw); 875 else 876 lt_dbg(intel_dp, DP_PHY_DPRX, 877 "Using LINK_RATE_SET value %02x\n", 878 rate_select); 879 /* 880 * Spec DP2.1 Section 3.5.2.16 881 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate 882 */ 883 intel_dp_update_downspread_ctrl(intel_dp, crtc_state); 884 intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw, 885 rate_select); 886 887 return true; 888} 889 890static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state, 891 const u8 old_link_status[DP_LINK_STATUS_SIZE], 892 const u8 new_link_status[DP_LINK_STATUS_SIZE]) 893{ 894 int lane; 895 896 for (lane = 0; lane < crtc_state->lane_count; lane++) { 897 u8 old, new; 898 899 if (intel_dp_is_uhbr(crtc_state)) { 900 old = drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane); 901 new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane); 902 } else { 903 old = drm_dp_get_adjust_request_voltage(old_link_status, lane) | 904 drm_dp_get_adjust_request_pre_emphasis(old_link_status, lane); 905 new = drm_dp_get_adjust_request_voltage(new_link_status, lane) | 906 drm_dp_get_adjust_request_pre_emphasis(new_link_status, lane); 907 } 908 909 if (old != new) 910 return true; 911 } 912 913 return false; 914} 915 916void 917intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy, 918 const u8 link_status[DP_LINK_STATUS_SIZE]) 919{ 920 lt_dbg(intel_dp, dp_phy, 921 "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n", 922 link_status[0], link_status[1], link_status[2], 923 link_status[3], link_status[4], link_status[5]); 924} 925 926/* 927 * Perform the link training clock recovery phase on the given DP PHY using 928 * training pattern 1. 929 */ 930static bool 931intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, 932 const struct intel_crtc_state *crtc_state, 933 enum drm_dp_phy dp_phy) 934{ 935 u8 old_link_status[DP_LINK_STATUS_SIZE] = {}; 936 int voltage_tries, cr_tries, max_cr_tries; 937 u8 link_status[DP_LINK_STATUS_SIZE]; 938 bool max_vswing_reached = false; 939 int delay_us; 940 941 delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux, 942 intel_dp->dpcd, dp_phy, 943 intel_dp_is_uhbr(crtc_state)); 944 945 /* clock recovery */ 946 if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, 947 DP_TRAINING_PATTERN_1 | 948 DP_LINK_SCRAMBLING_DISABLE)) { 949 lt_err(intel_dp, dp_phy, "Failed to enable link training\n"); 950 return false; 951 } 952 953 /* 954 * The DP 1.4 spec defines the max clock recovery retries value 955 * as 10 but for pre-DP 1.4 devices we set a very tolerant 956 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x 957 * x 5 identical voltage retries). Since the previous specs didn't 958 * define a limit and created the possibility of an infinite loop 959 * we want to prevent any sync from triggering that corner case. 960 */ 961 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 962 max_cr_tries = 10; 963 else 964 max_cr_tries = 80; 965 966 voltage_tries = 1; 967 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { 968 fsleep(delay_us); 969 970 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 971 link_status) < 0) { 972 lt_err(intel_dp, dp_phy, "Failed to get link status\n"); 973 return false; 974 } 975 976 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) { 977 lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n"); 978 return true; 979 } 980 981 if (voltage_tries == 5) { 982 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 983 lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n"); 984 return false; 985 } 986 987 if (max_vswing_reached) { 988 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 989 lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n"); 990 return false; 991 } 992 993 /* Update training set as requested by target */ 994 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 995 link_status); 996 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 997 lt_err(intel_dp, dp_phy, "Failed to update link training\n"); 998 return false; 999 } 1000 1001 if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status)) 1002 ++voltage_tries; 1003 else 1004 voltage_tries = 1; 1005 1006 memcpy(old_link_status, link_status, sizeof(link_status)); 1007 1008 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) 1009 max_vswing_reached = true; 1010 } 1011 1012 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1013 lt_err(intel_dp, dp_phy, "Failed clock recovery %d times, giving up!\n", 1014 max_cr_tries); 1015 1016 return false; 1017} 1018 1019/* 1020 * Perform the link training channel equalization phase on the given DP PHY 1021 * using one of training pattern 2, 3 or 4 depending on the source and 1022 * sink capabilities. 1023 */ 1024static bool 1025intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, 1026 const struct intel_crtc_state *crtc_state, 1027 enum drm_dp_phy dp_phy) 1028{ 1029 int tries; 1030 u32 training_pattern; 1031 u8 link_status[DP_LINK_STATUS_SIZE]; 1032 bool channel_eq = false; 1033 int delay_us; 1034 1035 delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux, 1036 intel_dp->dpcd, dp_phy, 1037 intel_dp_is_uhbr(crtc_state)); 1038 1039 training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy); 1040 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ 1041 if (training_pattern != DP_TRAINING_PATTERN_4) 1042 training_pattern |= DP_LINK_SCRAMBLING_DISABLE; 1043 1044 /* channel equalization */ 1045 if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, 1046 training_pattern)) { 1047 lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n"); 1048 return false; 1049 } 1050 1051 for (tries = 0; tries < 5; tries++) { 1052 fsleep(delay_us); 1053 1054 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 1055 link_status) < 0) { 1056 lt_err(intel_dp, dp_phy, "Failed to get link status\n"); 1057 break; 1058 } 1059 1060 /* Make sure clock is still ok */ 1061 if (!drm_dp_clock_recovery_ok(link_status, 1062 crtc_state->lane_count)) { 1063 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1064 lt_dbg(intel_dp, dp_phy, 1065 "Clock recovery check failed, cannot continue channel equalization\n"); 1066 break; 1067 } 1068 1069 if (drm_dp_channel_eq_ok(link_status, 1070 crtc_state->lane_count)) { 1071 channel_eq = true; 1072 lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n"); 1073 break; 1074 } 1075 1076 /* Update training set as requested by target */ 1077 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 1078 link_status); 1079 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 1080 lt_err(intel_dp, dp_phy, "Failed to update link training\n"); 1081 break; 1082 } 1083 } 1084 1085 /* Try 5 times, else fail and try at lower BW */ 1086 if (tries == 5) { 1087 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1088 lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n"); 1089 } 1090 1091 return channel_eq; 1092} 1093 1094static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp, 1095 enum drm_dp_phy dp_phy) 1096{ 1097 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 1098 u8 val = DP_TRAINING_PATTERN_DISABLE; 1099 1100 return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1; 1101} 1102 1103static int 1104intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp, 1105 const struct intel_crtc_state *crtc_state) 1106{ 1107 u8 sink_status; 1108 int ret; 1109 1110 ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status); 1111 if (ret != 1) { 1112 lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n"); 1113 return ret < 0 ? ret : -EIO; 1114 } 1115 1116 return sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION ? 1 : 0; 1117} 1118 1119/** 1120 * intel_dp_stop_link_train - stop link training 1121 * @intel_dp: DP struct 1122 * @crtc_state: state for CRTC attached to the encoder 1123 * 1124 * Stop the link training of the @intel_dp port, disabling the training 1125 * pattern in the sink's DPCD, and disabling the test pattern symbol 1126 * generation on the port. 1127 * 1128 * What symbols are output on the port after this point is 1129 * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern 1130 * with the pipe being disabled, on older platforms it's HW specific if/how an 1131 * idle pattern is generated, as the pipe is already enabled here for those. 1132 * 1133 * This function must be called after intel_dp_start_link_train(). 1134 */ 1135void intel_dp_stop_link_train(struct intel_dp *intel_dp, 1136 const struct intel_crtc_state *crtc_state) 1137{ 1138 struct intel_display *display = to_intel_display(intel_dp); 1139 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1140 int ret; 1141 1142 intel_dp->link.active = true; 1143 1144 intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX, 1145 DP_TRAINING_PATTERN_DISABLE); 1146 1147 if (intel_dp_is_uhbr(crtc_state)) { 1148 ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state), 1149 ret == 0, 1150 500, 500 * 1000, false); 1151 if (ret) 1152 lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n"); 1153 } 1154 1155 intel_hpd_unblock(encoder); 1156 1157 if (!display->hotplug.ignore_long_hpd && 1158 intel_dp->link.seq_train_failures < MAX_SEQ_TRAIN_FAILURES) { 1159 int delay_ms = intel_dp->link.seq_train_failures ? 0 : 2000; 1160 1161 intel_encoder_link_check_queue_work(encoder, delay_ms); 1162 } 1163} 1164 1165static bool 1166intel_dp_link_train_phy(struct intel_dp *intel_dp, 1167 const struct intel_crtc_state *crtc_state, 1168 enum drm_dp_phy dp_phy) 1169{ 1170 bool ret = false; 1171 1172 if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy)) 1173 goto out; 1174 1175 if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy)) 1176 goto out; 1177 1178 ret = true; 1179 1180out: 1181 lt_dbg(intel_dp, dp_phy, 1182 "Link Training %s at link rate = %d, lane count = %d\n", 1183 ret ? "passed" : "failed", 1184 crtc_state->port_clock, crtc_state->lane_count); 1185 1186 return ret; 1187} 1188 1189static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, 1190 int link_rate, 1191 u8 lane_count) 1192{ 1193 /* FIXME figure out what we actually want here */ 1194 const struct drm_display_mode *fixed_mode = 1195 intel_panel_preferred_fixed_mode(intel_dp->attached_connector); 1196 int mode_rate, max_rate; 1197 1198 mode_rate = intel_dp_link_required(fixed_mode->clock, 18); 1199 max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); 1200 if (mode_rate > max_rate) 1201 return false; 1202 1203 return true; 1204} 1205 1206static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp, 1207 const struct intel_crtc_state *crtc_state, 1208 int *new_link_rate, int *new_lane_count) 1209{ 1210 int link_rate; 1211 int lane_count; 1212 int i; 1213 1214 i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count); 1215 for (i--; i >= 0; i--) { 1216 intel_dp_link_config_get(intel_dp, i, &link_rate, &lane_count); 1217 1218 if ((intel_dp->link.force_rate && 1219 intel_dp->link.force_rate != link_rate) || 1220 (intel_dp->link.force_lane_count && 1221 intel_dp->link.force_lane_count != lane_count)) 1222 continue; 1223 1224 break; 1225 } 1226 1227 if (i < 0) 1228 return false; 1229 1230 *new_link_rate = link_rate; 1231 *new_lane_count = lane_count; 1232 1233 return true; 1234} 1235 1236static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) 1237{ 1238 int rate_index; 1239 int new_rate; 1240 1241 if (intel_dp->link.force_rate) 1242 return -1; 1243 1244 rate_index = intel_dp_rate_index(intel_dp->common_rates, 1245 intel_dp->num_common_rates, 1246 current_rate); 1247 1248 if (rate_index <= 0) 1249 return -1; 1250 1251 new_rate = intel_dp_common_rate(intel_dp, rate_index - 1); 1252 1253 /* TODO: Make switching from UHBR to non-UHBR rates work. */ 1254 if (drm_dp_is_uhbr_rate(current_rate) != drm_dp_is_uhbr_rate(new_rate)) 1255 return -1; 1256 1257 return new_rate; 1258} 1259 1260static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count) 1261{ 1262 if (intel_dp->link.force_lane_count) 1263 return -1; 1264 1265 if (current_lane_count == 1) 1266 return -1; 1267 1268 return current_lane_count >> 1; 1269} 1270 1271static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp, 1272 const struct intel_crtc_state *crtc_state, 1273 int *new_link_rate, int *new_lane_count) 1274{ 1275 int link_rate; 1276 int lane_count; 1277 1278 lane_count = crtc_state->lane_count; 1279 link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); 1280 if (link_rate < 0) { 1281 lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); 1282 link_rate = intel_dp_max_common_rate(intel_dp); 1283 } 1284 1285 if (lane_count < 0) 1286 return false; 1287 1288 *new_link_rate = link_rate; 1289 *new_lane_count = lane_count; 1290 1291 return true; 1292} 1293 1294static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, 1295 int *new_link_rate, int *new_lane_count) 1296{ 1297 /* TODO: Use the same fallback logic on SST as on MST. */ 1298 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 1299 return reduce_link_params_in_bw_order(intel_dp, crtc_state, 1300 new_link_rate, new_lane_count); 1301 else 1302 return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state, 1303 new_link_rate, new_lane_count); 1304} 1305 1306static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, 1307 const struct intel_crtc_state *crtc_state) 1308{ 1309 int new_link_rate; 1310 int new_lane_count; 1311 1312 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { 1313 lt_dbg(intel_dp, DP_PHY_DPRX, 1314 "Retrying Link training for eDP with max parameters\n"); 1315 intel_dp->use_max_params = true; 1316 return 0; 1317 } 1318 1319 if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count)) 1320 return -1; 1321 1322 if (intel_dp_is_edp(intel_dp) && 1323 !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) { 1324 lt_dbg(intel_dp, DP_PHY_DPRX, 1325 "Retrying Link training for eDP with same parameters\n"); 1326 return 0; 1327 } 1328 1329 lt_dbg(intel_dp, DP_PHY_DPRX, 1330 "Reducing link parameters from %dx%d to %dx%d\n", 1331 crtc_state->lane_count, crtc_state->port_clock, 1332 new_lane_count, new_link_rate); 1333 1334 intel_dp->link.max_rate = new_link_rate; 1335 intel_dp->link.max_lane_count = new_lane_count; 1336 1337 return 0; 1338} 1339 1340static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state, 1341 struct intel_dp *intel_dp, 1342 const struct intel_crtc_state *crtc_state) 1343{ 1344 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1345 1346 if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) { 1347 lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n"); 1348 return true; 1349 } 1350 1351 if (intel_dp->hobl_active) { 1352 lt_dbg(intel_dp, DP_PHY_DPRX, 1353 "Link Training failed with HOBL active, not enabling it from now on\n"); 1354 intel_dp->hobl_failed = true; 1355 } else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) { 1356 return false; 1357 } 1358 1359 /* Schedule a Hotplug Uevent to userspace to start modeset */ 1360 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 1361 1362 return true; 1363} 1364 1365/* Perform the link training on all LTTPRs and the DPRX on a link. */ 1366static bool 1367intel_dp_link_train_all_phys(struct intel_dp *intel_dp, 1368 const struct intel_crtc_state *crtc_state, 1369 int lttpr_count) 1370{ 1371 bool ret = true; 1372 int i; 1373 1374 for (i = lttpr_count - 1; i >= 0; i--) { 1375 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i); 1376 1377 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy); 1378 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy); 1379 1380 if (!ret) 1381 break; 1382 } 1383 1384 if (ret) 1385 ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX); 1386 1387 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); 1388 intel_dp->set_idle_link_train(intel_dp, crtc_state); 1389 1390 return ret; 1391} 1392 1393/* 1394 * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1) 1395 */ 1396static bool 1397intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, 1398 const struct intel_crtc_state *crtc_state) 1399{ 1400 u8 link_status[DP_LINK_STATUS_SIZE]; 1401 int delay_us; 1402 int try, max_tries = 20; 1403 unsigned long deadline; 1404 bool timeout = false; 1405 1406 /* 1407 * Reset signal levels. Start transmitting 128b/132b TPS1. 1408 * 1409 * Put DPRX and LTTPRs (if any) into intra-hop AUX mode by writing TPS1 1410 * in DP_TRAINING_PATTERN_SET. 1411 */ 1412 if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1413 DP_TRAINING_PATTERN_1)) { 1414 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n"); 1415 return false; 1416 } 1417 1418 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1419 1420 /* Read the initial TX FFE settings. */ 1421 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1422 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n"); 1423 return false; 1424 } 1425 1426 /* Update signal levels and training set as requested. */ 1427 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1428 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1429 lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n"); 1430 return false; 1431 } 1432 1433 /* Start transmitting 128b/132b TPS2. */ 1434 if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1435 DP_TRAINING_PATTERN_2)) { 1436 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n"); 1437 return false; 1438 } 1439 1440 /* Time budget for the LANEx_EQ_DONE Sequence */ 1441 deadline = jiffies + msecs_to_jiffies_timeout(450); 1442 1443 for (try = 0; try < max_tries; try++) { 1444 fsleep(delay_us); 1445 1446 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1447 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1448 return false; 1449 } 1450 1451 if (drm_dp_128b132b_link_training_failed(link_status)) { 1452 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1453 lt_err(intel_dp, DP_PHY_DPRX, 1454 "Downstream link training failure\n"); 1455 return false; 1456 } 1457 1458 if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) { 1459 lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n"); 1460 break; 1461 } 1462 1463 if (timeout) { 1464 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1465 lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n"); 1466 return false; 1467 } 1468 1469 if (time_after(jiffies, deadline)) 1470 timeout = true; /* try one last time after deadline */ 1471 1472 /* 1473 * During LT, Tx shall read AUX_RD_INTERVAL just before writing the new FFE 1474 * presets. 1475 */ 1476 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1477 1478 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1479 1480 /* Update signal levels and training set as requested. */ 1481 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1482 lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n"); 1483 return false; 1484 } 1485 } 1486 1487 if (try == max_tries) { 1488 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1489 lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n"); 1490 return false; 1491 } 1492 1493 for (;;) { 1494 if (time_after(jiffies, deadline)) 1495 timeout = true; /* try one last time after deadline */ 1496 1497 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1498 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1499 return false; 1500 } 1501 1502 if (drm_dp_128b132b_link_training_failed(link_status)) { 1503 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1504 lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n"); 1505 return false; 1506 } 1507 1508 if (drm_dp_128b132b_eq_interlane_align_done(link_status)) { 1509 lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n"); 1510 break; 1511 } 1512 1513 if (timeout) { 1514 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1515 lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n"); 1516 return false; 1517 } 1518 1519 usleep_range(2000, 3000); 1520 } 1521 1522 return true; 1523} 1524 1525/* 1526 * 128b/132b DP LANEx_CDS_DONE Sequence (DP 2.0 E11 3.5.2.16.2) 1527 */ 1528static bool 1529intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp, 1530 const struct intel_crtc_state *crtc_state, 1531 int lttpr_count) 1532{ 1533 u8 link_status[DP_LINK_STATUS_SIZE]; 1534 unsigned long deadline; 1535 1536 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 1537 DP_TRAINING_PATTERN_2_CDS) != 1) { 1538 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n"); 1539 return false; 1540 } 1541 1542 /* Time budget for the LANEx_CDS_DONE Sequence */ 1543 deadline = jiffies + msecs_to_jiffies_timeout((lttpr_count + 1) * 20); 1544 1545 for (;;) { 1546 bool timeout = false; 1547 1548 if (time_after(jiffies, deadline)) 1549 timeout = true; /* try one last time after deadline */ 1550 1551 usleep_range(2000, 3000); 1552 1553 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1554 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1555 return false; 1556 } 1557 1558 if (drm_dp_128b132b_eq_interlane_align_done(link_status) && 1559 drm_dp_128b132b_cds_interlane_align_done(link_status) && 1560 drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) { 1561 lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n"); 1562 break; 1563 } 1564 1565 if (drm_dp_128b132b_link_training_failed(link_status)) { 1566 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1567 lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n"); 1568 return false; 1569 } 1570 1571 if (timeout) { 1572 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1573 lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n"); 1574 return false; 1575 } 1576 } 1577 1578 return true; 1579} 1580 1581/* 1582 * 128b/132b link training sequence. (DP 2.0 E11 SCR on link training.) 1583 */ 1584static bool 1585intel_dp_128b132b_link_train(struct intel_dp *intel_dp, 1586 const struct intel_crtc_state *crtc_state, 1587 int lttpr_count) 1588{ 1589 bool passed = false; 1590 int ret; 1591 1592 ret = poll_timeout_us(ret = intel_dp_128b132b_intra_hop(intel_dp, crtc_state), 1593 ret == 0, 1594 500, 500 * 1000, false); 1595 if (ret) { 1596 lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n"); 1597 goto out; 1598 } 1599 1600 if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) && 1601 intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count)) 1602 passed = true; 1603 1604 lt_dbg(intel_dp, DP_PHY_DPRX, 1605 "128b/132b Link Training %s at link rate = %d, lane count = %d\n", 1606 passed ? "passed" : "failed", 1607 crtc_state->port_clock, crtc_state->lane_count); 1608 1609out: 1610 /* 1611 * Ensure that the training pattern does get set to TPS2 even in case 1612 * of a failure, as is the case at the end of a passing link training 1613 * and what is expected by the transcoder. Leaving TPS1 set (and 1614 * disabling the link train mode in DP_TP_CTL later from TPS1 directly) 1615 * would result in a stuck transcoder HW state and flip-done timeouts 1616 * later in the modeset sequence. 1617 */ 1618 if (!passed) 1619 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 1620 DP_PHY_DPRX, DP_TRAINING_PATTERN_2); 1621 1622 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); 1623 1624 return passed; 1625} 1626 1627/** 1628 * intel_dp_start_link_train - start link training 1629 * @state: Atomic state 1630 * @intel_dp: DP struct 1631 * @crtc_state: state for CRTC attached to the encoder 1632 * 1633 * Start the link training of the @intel_dp port, scheduling a fallback 1634 * retraining with reduced link rate/lane parameters if the link training 1635 * fails. 1636 * After calling this function intel_dp_stop_link_train() must be called. 1637 */ 1638void intel_dp_start_link_train(struct intel_atomic_state *state, 1639 struct intel_dp *intel_dp, 1640 const struct intel_crtc_state *crtc_state) 1641{ 1642 struct intel_display *display = to_intel_display(state); 1643 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1644 struct intel_encoder *encoder = &dig_port->base; 1645 bool passed; 1646 /* 1647 * Reinit the LTTPRs here to ensure that they are switched to 1648 * non-transparent mode. During an earlier LTTPR detection this 1649 * could've been prevented by an active link. 1650 */ 1651 int lttpr_count; 1652 1653 intel_hpd_block(encoder); 1654 1655 lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp); 1656 1657 if (lttpr_count < 0) 1658 /* Still continue with enabling the port and link training. */ 1659 lttpr_count = 0; 1660 1661 intel_dp_prepare_link_train(intel_dp, crtc_state); 1662 1663 if (intel_dp_is_uhbr(crtc_state)) 1664 passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count); 1665 else 1666 passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); 1667 1668 if (intel_dp->link.force_train_failure) { 1669 intel_dp->link.force_train_failure--; 1670 lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n"); 1671 } else if (passed) { 1672 intel_dp->link.seq_train_failures = 0; 1673 return; 1674 } 1675 1676 intel_dp->link.seq_train_failures++; 1677 1678 /* 1679 * Ignore the link failure in CI 1680 * 1681 * In fixed environments like CI, sometimes unexpected long HPDs are 1682 * generated by the displays. If ignore_long_hpd flag is set, such long 1683 * HPDs are ignored. And probably as a consequence of these ignored 1684 * long HPDs, subsequent link trainings are failed resulting into CI 1685 * execution failures. 1686 * 1687 * For test cases which rely on the link training or processing of HPDs 1688 * ignore_long_hpd flag can unset from the testcase. 1689 */ 1690 if (display->hotplug.ignore_long_hpd) { 1691 lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n"); 1692 return; 1693 } 1694 1695 if (intel_dp->link.seq_train_failures < MAX_SEQ_TRAIN_FAILURES) 1696 return; 1697 1698 if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state)) 1699 return; 1700 1701 intel_dp->link.retrain_disabled = true; 1702 1703 if (!passed) 1704 lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n"); 1705 else 1706 lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n"); 1707} 1708 1709void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, 1710 const struct intel_crtc_state *crtc_state) 1711{ 1712 /* 1713 * VIDEO_DIP_CTL register bit 31 should be set to '0' to not 1714 * disable SDP CRC. This is applicable for Display version 13. 1715 * Default value of bit 31 is '0' hence discarding the write 1716 * TODO: Corrective actions on SDP corruption yet to be defined 1717 */ 1718 if (!intel_dp_is_uhbr(crtc_state)) 1719 return; 1720 1721 /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ 1722 drm_dp_dpcd_writeb(&intel_dp->aux, 1723 DP_SDP_ERROR_DETECTION_CONFIGURATION, 1724 DP_SDP_CRC16_128B132B_EN); 1725 1726 lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n"); 1727} 1728 1729static int i915_dp_force_link_rate_show(struct seq_file *m, void *data) 1730{ 1731 struct intel_connector *connector = to_intel_connector(m->private); 1732 struct intel_display *display = to_intel_display(connector); 1733 struct intel_dp *intel_dp = intel_attached_dp(connector); 1734 int current_rate = -1; 1735 int force_rate; 1736 int err; 1737 int i; 1738 1739 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1740 if (err) 1741 return err; 1742 1743 if (intel_dp->link.active) 1744 current_rate = intel_dp->link_rate; 1745 force_rate = intel_dp->link.force_rate; 1746 1747 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1748 1749 seq_printf(m, "%sauto%s", 1750 force_rate == 0 ? "[" : "", 1751 force_rate == 0 ? "]" : ""); 1752 1753 for (i = 0; i < intel_dp->num_source_rates; i++) 1754 seq_printf(m, " %s%d%s%s", 1755 intel_dp->source_rates[i] == force_rate ? "[" : "", 1756 intel_dp->source_rates[i], 1757 intel_dp->source_rates[i] == current_rate ? "*" : "", 1758 intel_dp->source_rates[i] == force_rate ? "]" : ""); 1759 1760 seq_putc(m, '\n'); 1761 1762 return 0; 1763} 1764 1765static int parse_link_rate(struct intel_dp *intel_dp, const char __user *ubuf, size_t len) 1766{ 1767 char *kbuf; 1768 const char *p; 1769 int rate; 1770 int ret = 0; 1771 1772 kbuf = memdup_user_nul(ubuf, len); 1773 if (IS_ERR(kbuf)) 1774 return PTR_ERR(kbuf); 1775 1776 p = strim(kbuf); 1777 1778 if (!strcmp(p, "auto")) { 1779 rate = 0; 1780 } else { 1781 ret = kstrtoint(p, 0, &rate); 1782 if (ret < 0) 1783 goto out_free; 1784 1785 if (intel_dp_rate_index(intel_dp->source_rates, 1786 intel_dp->num_source_rates, 1787 rate) < 0) 1788 ret = -EINVAL; 1789 } 1790 1791out_free: 1792 kfree(kbuf); 1793 1794 return ret < 0 ? ret : rate; 1795} 1796 1797static ssize_t i915_dp_force_link_rate_write(struct file *file, 1798 const char __user *ubuf, 1799 size_t len, loff_t *offp) 1800{ 1801 struct seq_file *m = file->private_data; 1802 struct intel_connector *connector = to_intel_connector(m->private); 1803 struct intel_display *display = to_intel_display(connector); 1804 struct intel_dp *intel_dp = intel_attached_dp(connector); 1805 int rate; 1806 int err; 1807 1808 rate = parse_link_rate(intel_dp, ubuf, len); 1809 if (rate < 0) 1810 return rate; 1811 1812 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1813 if (err) 1814 return err; 1815 1816 intel_dp_reset_link_params(intel_dp); 1817 intel_dp->link.force_rate = rate; 1818 1819 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1820 1821 *offp += len; 1822 1823 return len; 1824} 1825DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_link_rate); 1826 1827static int i915_dp_force_lane_count_show(struct seq_file *m, void *data) 1828{ 1829 struct intel_connector *connector = to_intel_connector(m->private); 1830 struct intel_display *display = to_intel_display(connector); 1831 struct intel_dp *intel_dp = intel_attached_dp(connector); 1832 int current_lane_count = -1; 1833 int force_lane_count; 1834 int err; 1835 int i; 1836 1837 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1838 if (err) 1839 return err; 1840 1841 if (intel_dp->link.active) 1842 current_lane_count = intel_dp->lane_count; 1843 force_lane_count = intel_dp->link.force_lane_count; 1844 1845 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1846 1847 seq_printf(m, "%sauto%s", 1848 force_lane_count == 0 ? "[" : "", 1849 force_lane_count == 0 ? "]" : ""); 1850 1851 for (i = 1; i <= 4; i <<= 1) 1852 seq_printf(m, " %s%d%s%s", 1853 i == force_lane_count ? "[" : "", 1854 i, 1855 i == current_lane_count ? "*" : "", 1856 i == force_lane_count ? "]" : ""); 1857 1858 seq_putc(m, '\n'); 1859 1860 return 0; 1861} 1862 1863static int parse_lane_count(const char __user *ubuf, size_t len) 1864{ 1865 char *kbuf; 1866 const char *p; 1867 int lane_count; 1868 int ret = 0; 1869 1870 kbuf = memdup_user_nul(ubuf, len); 1871 if (IS_ERR(kbuf)) 1872 return PTR_ERR(kbuf); 1873 1874 p = strim(kbuf); 1875 1876 if (!strcmp(p, "auto")) { 1877 lane_count = 0; 1878 } else { 1879 ret = kstrtoint(p, 0, &lane_count); 1880 if (ret < 0) 1881 goto out_free; 1882 1883 switch (lane_count) { 1884 case 1: 1885 case 2: 1886 case 4: 1887 break; 1888 default: 1889 ret = -EINVAL; 1890 } 1891 } 1892 1893out_free: 1894 kfree(kbuf); 1895 1896 return ret < 0 ? ret : lane_count; 1897} 1898 1899static ssize_t i915_dp_force_lane_count_write(struct file *file, 1900 const char __user *ubuf, 1901 size_t len, loff_t *offp) 1902{ 1903 struct seq_file *m = file->private_data; 1904 struct intel_connector *connector = to_intel_connector(m->private); 1905 struct intel_display *display = to_intel_display(connector); 1906 struct intel_dp *intel_dp = intel_attached_dp(connector); 1907 int lane_count; 1908 int err; 1909 1910 lane_count = parse_lane_count(ubuf, len); 1911 if (lane_count < 0) 1912 return lane_count; 1913 1914 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1915 if (err) 1916 return err; 1917 1918 intel_dp_reset_link_params(intel_dp); 1919 intel_dp->link.force_lane_count = lane_count; 1920 1921 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1922 1923 *offp += len; 1924 1925 return len; 1926} 1927DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_lane_count); 1928 1929static int i915_dp_max_link_rate_show(void *data, u64 *val) 1930{ 1931 struct intel_connector *connector = to_intel_connector(data); 1932 struct intel_display *display = to_intel_display(connector); 1933 struct intel_dp *intel_dp = intel_attached_dp(connector); 1934 int err; 1935 1936 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1937 if (err) 1938 return err; 1939 1940 *val = intel_dp->link.max_rate; 1941 1942 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1943 1944 return 0; 1945} 1946DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_link_rate_fops, i915_dp_max_link_rate_show, NULL, "%llu\n"); 1947 1948static int i915_dp_max_lane_count_show(void *data, u64 *val) 1949{ 1950 struct intel_connector *connector = to_intel_connector(data); 1951 struct intel_display *display = to_intel_display(connector); 1952 struct intel_dp *intel_dp = intel_attached_dp(connector); 1953 int err; 1954 1955 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1956 if (err) 1957 return err; 1958 1959 *val = intel_dp->link.max_lane_count; 1960 1961 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1962 1963 return 0; 1964} 1965DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops, i915_dp_max_lane_count_show, NULL, "%llu\n"); 1966 1967static int i915_dp_force_link_training_failure_show(void *data, u64 *val) 1968{ 1969 struct intel_connector *connector = to_intel_connector(data); 1970 struct intel_display *display = to_intel_display(connector); 1971 struct intel_dp *intel_dp = intel_attached_dp(connector); 1972 int err; 1973 1974 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1975 if (err) 1976 return err; 1977 1978 *val = intel_dp->link.force_train_failure; 1979 1980 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1981 1982 return 0; 1983} 1984 1985static int i915_dp_force_link_training_failure_write(void *data, u64 val) 1986{ 1987 struct intel_connector *connector = to_intel_connector(data); 1988 struct intel_display *display = to_intel_display(connector); 1989 struct intel_dp *intel_dp = intel_attached_dp(connector); 1990 int err; 1991 1992 if (val > 2) 1993 return -EINVAL; 1994 1995 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 1996 if (err) 1997 return err; 1998 1999 intel_dp->link.force_train_failure = val; 2000 2001 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2002 2003 return 0; 2004} 2005DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops, 2006 i915_dp_force_link_training_failure_show, 2007 i915_dp_force_link_training_failure_write, "%llu\n"); 2008 2009static int i915_dp_force_link_retrain_show(void *data, u64 *val) 2010{ 2011 struct intel_connector *connector = to_intel_connector(data); 2012 struct intel_display *display = to_intel_display(connector); 2013 struct intel_dp *intel_dp = intel_attached_dp(connector); 2014 int err; 2015 2016 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2017 if (err) 2018 return err; 2019 2020 *val = intel_dp->link.force_retrain; 2021 2022 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2023 2024 return 0; 2025} 2026 2027static int i915_dp_force_link_retrain_write(void *data, u64 val) 2028{ 2029 struct intel_connector *connector = to_intel_connector(data); 2030 struct intel_display *display = to_intel_display(connector); 2031 struct intel_dp *intel_dp = intel_attached_dp(connector); 2032 int err; 2033 2034 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2035 if (err) 2036 return err; 2037 2038 intel_dp->link.force_retrain = val; 2039 2040 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2041 2042 intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); 2043 2044 return 0; 2045} 2046DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops, 2047 i915_dp_force_link_retrain_show, 2048 i915_dp_force_link_retrain_write, "%llu\n"); 2049 2050static int i915_dp_link_retrain_disabled_show(struct seq_file *m, void *data) 2051{ 2052 struct intel_connector *connector = to_intel_connector(m->private); 2053 struct intel_display *display = to_intel_display(connector); 2054 struct intel_dp *intel_dp = intel_attached_dp(connector); 2055 int err; 2056 2057 err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2058 if (err) 2059 return err; 2060 2061 seq_printf(m, "%s\n", str_yes_no(intel_dp->link.retrain_disabled)); 2062 2063 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2064 2065 return 0; 2066} 2067DEFINE_SHOW_ATTRIBUTE(i915_dp_link_retrain_disabled); 2068 2069void intel_dp_link_training_debugfs_add(struct intel_connector *connector) 2070{ 2071 struct dentry *root = connector->base.debugfs_entry; 2072 2073 if (connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort && 2074 connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) 2075 return; 2076 2077 debugfs_create_file("i915_dp_force_link_rate", 0644, root, 2078 connector, &i915_dp_force_link_rate_fops); 2079 2080 debugfs_create_file("i915_dp_force_lane_count", 0644, root, 2081 connector, &i915_dp_force_lane_count_fops); 2082 2083 debugfs_create_file("i915_dp_max_link_rate", 0444, root, 2084 connector, &i915_dp_max_link_rate_fops); 2085 2086 debugfs_create_file("i915_dp_max_lane_count", 0444, root, 2087 connector, &i915_dp_max_lane_count_fops); 2088 2089 debugfs_create_file("i915_dp_force_link_training_failure", 0644, root, 2090 connector, &i915_dp_force_link_training_failure_fops); 2091 2092 debugfs_create_file("i915_dp_force_link_retrain", 0644, root, 2093 connector, &i915_dp_force_link_retrain_fops); 2094 2095 debugfs_create_file("i915_dp_link_retrain_disabled", 0444, root, 2096 connector, &i915_dp_link_retrain_disabled_fops); 2097}
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