FILE
intel_dp.c
File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/i915/display/intel_dp.c
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/export.h> 29#include <linux/i2c.h> 30#include <linux/iopoll.h> 31#include <linux/log2.h> 32#include <linux/math.h> 33#include <linux/notifier.h> 34#include <linux/seq_buf.h> 35#include <linux/slab.h> 36#include <linux/sort.h> 37#include <linux/string_helpers.h> 38#include <linux/timekeeping.h> 39#include <linux/types.h> 40#include <asm/byteorder.h> 41 42#include <drm/display/drm_dp_helper.h> 43#include <drm/display/drm_dp_tunnel.h> 44#include <drm/display/drm_dsc_helper.h> 45#include <drm/display/drm_hdmi_helper.h> 46#include <drm/drm_atomic_helper.h> 47#include <drm/drm_crtc.h> 48#include <drm/drm_edid.h> 49#include <drm/drm_fixed.h> 50#include <drm/drm_print.h> 51#include <drm/drm_probe_helper.h> 52 53#include "g4x_dp.h" 54#include "intel_alpm.h" 55#include "intel_atomic.h" 56#include "intel_audio.h" 57#include "intel_backlight.h" 58#include "intel_combo_phy_regs.h" 59#include "intel_connector.h" 60#include "intel_crtc.h" 61#include "intel_crtc_state_dump.h" 62#include "intel_cx0_phy.h" 63#include "intel_ddi.h" 64#include "intel_de.h" 65#include "intel_display_driver.h" 66#include "intel_display_jiffies.h" 67#include "intel_display_utils.h" 68#include "intel_display_regs.h" 69#include "intel_display_rpm.h" 70#include "intel_display_types.h" 71#include "intel_dp.h" 72#include "intel_dp_aux.h" 73#include "intel_dp_hdcp.h" 74#include "intel_dp_link_training.h" 75#include "intel_dp_mst.h" 76#include "intel_dp_test.h" 77#include "intel_dp_tunnel.h" 78#include "intel_dpio_phy.h" 79#include "intel_dpll.h" 80#include "intel_drrs.h" 81#include "intel_encoder.h" 82#include "intel_fifo_underrun.h" 83#include "intel_hdcp.h" 84#include "intel_hdmi.h" 85#include "intel_hotplug.h" 86#include "intel_hotplug_irq.h" 87#include "intel_lspcon.h" 88#include "intel_lvds.h" 89#include "intel_modeset_lock.h" 90#include "intel_panel.h" 91#include "intel_pch_display.h" 92#include "intel_pfit.h" 93#include "intel_pps.h" 94#include "intel_psr.h" 95#include "intel_quirks.h" 96#include "intel_tc.h" 97#include "intel_vblank.h" 98#include "intel_vdsc.h" 99#include "intel_vrr.h" 100 101/* Max DSC line buffer depth supported by HW. */ 102#define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13 103 104/* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */ 105#define DP_DSC_FEC_OVERHEAD_FACTOR 1028530 106 107/* Constants for DP DSC configurations */ 108static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; 109 110/* 111 * With Single pipe configuration, HW is capable of supporting maximum of: 112 * 2 slices per line for ICL, BMG 113 * 4 slices per line for other platforms. 114 * For now consider a max of 2 slices per line, which works for all platforms. 115 * With this we can have max of 4 DSC Slices per pipe. 116 * 117 * For higher resolutions where 12 slice support is required with 118 * ultrajoiner, only then each pipe can support 3 slices. 119 * 120 * #TODO Split this better to use 4 slices/dsc engine where supported. 121 */ 122static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4}; 123 124/** 125 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) 126 * @intel_dp: DP struct 127 * 128 * If a CPU or PCH DP output is attached to an eDP panel, this function 129 * will return true, and false otherwise. 130 * 131 * This function is not safe to use prior to encoder type being set. 132 */ 133bool intel_dp_is_edp(struct intel_dp *intel_dp) 134{ 135 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 136 137 return dig_port->base.type == INTEL_OUTPUT_EDP; 138} 139 140static void intel_dp_unset_edid(struct intel_dp *intel_dp); 141 142/* Is link rate UHBR and thus 128b/132b? */ 143bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) 144{ 145 return drm_dp_is_uhbr_rate(crtc_state->port_clock); 146} 147 148/** 149 * intel_dp_link_symbol_size - get the link symbol size for a given link rate 150 * @rate: link rate in 10kbit/s units 151 * 152 * Returns the link symbol size in bits/symbol units depending on the link 153 * rate -> channel coding. 154 */ 155int intel_dp_link_symbol_size(int rate) 156{ 157 return drm_dp_is_uhbr_rate(rate) ? 32 : 10; 158} 159 160/** 161 * intel_dp_link_symbol_clock - convert link rate to link symbol clock 162 * @rate: link rate in 10kbit/s units 163 * 164 * Returns the link symbol clock frequency in kHz units depending on the 165 * link rate and channel coding. 166 */ 167int intel_dp_link_symbol_clock(int rate) 168{ 169 return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate)); 170} 171 172static int max_dprx_rate(struct intel_dp *intel_dp) 173{ 174 struct intel_display *display = to_intel_display(intel_dp); 175 int max_rate; 176 177 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 178 max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel); 179 else 180 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); 181 182 /* 183 * Some platforms + eDP panels may not reliably support HBR3 184 * due to signal integrity limitations, despite advertising it. 185 * Cap the link rate to HBR2 to avoid unstable configurations for the 186 * known machines. 187 */ 188 if (intel_dp_is_edp(intel_dp) && intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2)) 189 max_rate = min(max_rate, 540000); 190 191 return max_rate; 192} 193 194static int max_dprx_lane_count(struct intel_dp *intel_dp) 195{ 196 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 197 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel); 198 199 return drm_dp_max_lane_count(intel_dp->dpcd); 200} 201 202static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp) 203{ 204 intel_dp->sink_rates[0] = 162000; 205 intel_dp->num_sink_rates = 1; 206} 207 208/* update sink rates from dpcd */ 209static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp) 210{ 211 static const int dp_rates[] = { 212 162000, 270000, 540000, 810000 213 }; 214 int i, max_rate; 215 int max_lttpr_rate; 216 217 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { 218 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ 219 static const int quirk_rates[] = { 162000, 270000, 324000 }; 220 221 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); 222 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); 223 224 return; 225 } 226 227 /* 228 * Sink rates for 8b/10b. 229 */ 230 max_rate = max_dprx_rate(intel_dp); 231 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps); 232 if (max_lttpr_rate) 233 max_rate = min(max_rate, max_lttpr_rate); 234 235 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { 236 if (dp_rates[i] > max_rate) 237 break; 238 intel_dp->sink_rates[i] = dp_rates[i]; 239 } 240 241 /* 242 * Sink rates for 128b/132b. If set, sink should support all 8b/10b 243 * rates and 10 Gbps. 244 */ 245 if (drm_dp_128b132b_supported(intel_dp->dpcd)) { 246 u8 uhbr_rates = 0; 247 248 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3); 249 250 drm_dp_dpcd_readb(&intel_dp->aux, 251 DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates); 252 253 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) { 254 /* We have a repeater */ 255 if (intel_dp->lttpr_common_caps[0] >= 0x20 && 256 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER - 257 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] & 258 DP_PHY_REPEATER_128B132B_SUPPORTED) { 259 /* Repeater supports 128b/132b, valid UHBR rates */ 260 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES - 261 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 262 } else { 263 /* Does not support 128b/132b */ 264 uhbr_rates = 0; 265 } 266 } 267 268 if (uhbr_rates & DP_UHBR10) 269 intel_dp->sink_rates[i++] = 1000000; 270 if (uhbr_rates & DP_UHBR13_5) 271 intel_dp->sink_rates[i++] = 1350000; 272 if (uhbr_rates & DP_UHBR20) 273 intel_dp->sink_rates[i++] = 2000000; 274 } 275 276 intel_dp->num_sink_rates = i; 277} 278 279static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) 280{ 281 struct intel_display *display = to_intel_display(intel_dp); 282 struct intel_connector *connector = intel_dp->attached_connector; 283 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 284 struct intel_encoder *encoder = &intel_dig_port->base; 285 286 intel_dp_set_dpcd_sink_rates(intel_dp); 287 288 if (intel_dp->num_sink_rates) 289 return; 290 291 drm_err(display->drm, 292 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n", 293 connector->base.base.id, connector->base.name, 294 encoder->base.base.id, encoder->base.name); 295 296 intel_dp_set_default_sink_rates(intel_dp); 297} 298 299static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp) 300{ 301 intel_dp->max_sink_lane_count = 1; 302} 303 304static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp) 305{ 306 struct intel_display *display = to_intel_display(intel_dp); 307 struct intel_connector *connector = intel_dp->attached_connector; 308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 309 struct intel_encoder *encoder = &intel_dig_port->base; 310 311 intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp); 312 313 switch (intel_dp->max_sink_lane_count) { 314 case 1: 315 case 2: 316 case 4: 317 return; 318 } 319 320 drm_err(display->drm, 321 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n", 322 connector->base.base.id, connector->base.name, 323 encoder->base.base.id, encoder->base.name, 324 intel_dp->max_sink_lane_count); 325 326 intel_dp_set_default_max_sink_lane_count(intel_dp); 327} 328 329/* Get length of rates array potentially limited by max_rate. */ 330static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) 331{ 332 int i; 333 334 /* Limit results by potentially reduced max rate */ 335 for (i = 0; i < len; i++) { 336 if (rates[len - i - 1] <= max_rate) 337 return len - i; 338 } 339 340 return 0; 341} 342 343/* Get length of common rates array potentially limited by max_rate. */ 344static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, 345 int max_rate) 346{ 347 return intel_dp_rate_limit_len(intel_dp->common_rates, 348 intel_dp->num_common_rates, max_rate); 349} 350 351int intel_dp_common_rate(struct intel_dp *intel_dp, int index) 352{ 353 struct intel_display *display = to_intel_display(intel_dp); 354 355 if (drm_WARN_ON(display->drm, 356 index < 0 || index >= intel_dp->num_common_rates)) 357 return 162000; 358 359 return intel_dp->common_rates[index]; 360} 361 362/* Theoretical max between source and sink */ 363int intel_dp_max_common_rate(struct intel_dp *intel_dp) 364{ 365 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1); 366} 367 368int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) 369{ 370 int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata); 371 int max_lanes = dig_port->max_lanes; 372 373 if (vbt_max_lanes) 374 max_lanes = min(max_lanes, vbt_max_lanes); 375 376 return max_lanes; 377} 378 379/* Theoretical max between source and sink */ 380int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) 381{ 382 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 383 int source_max = intel_dp_max_source_lane_count(dig_port); 384 int sink_max = intel_dp->max_sink_lane_count; 385 int lane_max = intel_tc_port_max_lane_count(dig_port); 386 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps); 387 388 if (lttpr_max) 389 sink_max = min(sink_max, lttpr_max); 390 391 return min3(source_max, sink_max, lane_max); 392} 393 394static int forced_lane_count(struct intel_dp *intel_dp) 395{ 396 return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp)); 397} 398 399int intel_dp_max_lane_count(struct intel_dp *intel_dp) 400{ 401 int lane_count; 402 403 if (intel_dp->link.force_lane_count) 404 lane_count = forced_lane_count(intel_dp); 405 else 406 lane_count = intel_dp->link.max_lane_count; 407 408 switch (lane_count) { 409 case 1: 410 case 2: 411 case 4: 412 return lane_count; 413 default: 414 MISSING_CASE(lane_count); 415 return 1; 416 } 417} 418 419static int intel_dp_min_lane_count(struct intel_dp *intel_dp) 420{ 421 if (intel_dp->link.force_lane_count) 422 return forced_lane_count(intel_dp); 423 424 return 1; 425} 426 427/* 428 * The required data bandwidth for a mode with given pixel clock and bpp. This 429 * is the required net bandwidth independent of the data bandwidth efficiency. 430 * 431 * TODO: check if callers of this functions should use 432 * intel_dp_effective_data_rate() instead. 433 */ 434int 435intel_dp_link_required(int pixel_clock, int bpp) 436{ 437 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ 438 return DIV_ROUND_UP(pixel_clock * bpp, 8); 439} 440 441/** 442 * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead 443 * @pixel_clock: pixel clock in kHz 444 * @bpp_x16: bits per pixel .4 fixed point format 445 * @bw_overhead: BW allocation overhead in 1ppm units 446 * 447 * Return the effective pixel data rate in kB/sec units taking into account 448 * the provided SSC, FEC, DSC BW allocation overhead. 449 */ 450int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, 451 int bw_overhead) 452{ 453 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead), 454 1000000 * 16 * 8); 455} 456 457/** 458 * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params 459 * @intel_dp: Intel DP object 460 * @max_dprx_rate: Maximum data rate of the DPRX 461 * @max_dprx_lanes: Maximum lane count of the DPRX 462 * 463 * Calculate the maximum data rate for the provided link parameters taking into 464 * account any BW limitations by a DP tunnel attached to @intel_dp. 465 * 466 * Returns the maximum data rate in kBps units. 467 */ 468int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, 469 int max_dprx_rate, int max_dprx_lanes) 470{ 471 int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes); 472 473 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) 474 max_rate = min(max_rate, 475 drm_dp_tunnel_available_bw(intel_dp->tunnel)); 476 477 return max_rate; 478} 479 480bool intel_dp_has_joiner(struct intel_dp *intel_dp) 481{ 482 struct intel_display *display = to_intel_display(intel_dp); 483 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 484 struct intel_encoder *encoder = &intel_dig_port->base; 485 486 /* eDP MSO is not compatible with joiner */ 487 if (intel_dp->mso_link_count) 488 return false; 489 490 return DISPLAY_VER(display) >= 12 || 491 (DISPLAY_VER(display) == 11 && 492 encoder->port != PORT_A); 493} 494 495static int dg2_max_source_rate(struct intel_dp *intel_dp) 496{ 497 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000; 498} 499 500static int icl_max_source_rate(struct intel_dp *intel_dp) 501{ 502 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 503 504 if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp)) 505 return 540000; 506 507 return 810000; 508} 509 510static int ehl_max_source_rate(struct intel_dp *intel_dp) 511{ 512 if (intel_dp_is_edp(intel_dp)) 513 return 540000; 514 515 return 810000; 516} 517 518static int mtl_max_source_rate(struct intel_dp *intel_dp) 519{ 520 struct intel_display *display = to_intel_display(intel_dp); 521 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 522 523 if (intel_encoder_is_c10phy(encoder)) 524 return 810000; 525 526 if (DISPLAY_VERx100(display) == 1401) 527 return 1350000; 528 529 return 2000000; 530} 531 532static int vbt_max_link_rate(struct intel_dp *intel_dp) 533{ 534 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 535 int max_rate; 536 537 max_rate = intel_bios_dp_max_link_rate(encoder->devdata); 538 539 if (intel_dp_is_edp(intel_dp)) { 540 struct intel_connector *connector = intel_dp->attached_connector; 541 int edp_max_rate = connector->panel.vbt.edp.max_link_rate; 542 543 if (max_rate && edp_max_rate) 544 max_rate = min(max_rate, edp_max_rate); 545 else if (edp_max_rate) 546 max_rate = edp_max_rate; 547 } 548 549 return max_rate; 550} 551 552static void 553intel_dp_set_source_rates(struct intel_dp *intel_dp) 554{ 555 /* The values must be in increasing order */ 556 static const int bmg_rates[] = { 557 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, 558 810000, 1000000, 1350000, 559 }; 560 static const int mtl_rates[] = { 561 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000, 562 810000, 1000000, 2000000, 563 }; 564 static const int icl_rates[] = { 565 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000, 566 1000000, 1350000, 567 }; 568 static const int bxt_rates[] = { 569 162000, 216000, 243000, 270000, 324000, 432000, 540000 570 }; 571 static const int skl_rates[] = { 572 162000, 216000, 270000, 324000, 432000, 540000 573 }; 574 static const int hsw_rates[] = { 575 162000, 270000, 540000 576 }; 577 static const int g4x_rates[] = { 578 162000, 270000 579 }; 580 struct intel_display *display = to_intel_display(intel_dp); 581 const int *source_rates; 582 int size, max_rate = 0, vbt_max_rate; 583 584 /* This should only be done once */ 585 drm_WARN_ON(display->drm, 586 intel_dp->source_rates || intel_dp->num_source_rates); 587 588 if (DISPLAY_VER(display) >= 14) { 589 if (display->platform.battlemage) { 590 source_rates = bmg_rates; 591 size = ARRAY_SIZE(bmg_rates); 592 } else { 593 source_rates = mtl_rates; 594 size = ARRAY_SIZE(mtl_rates); 595 } 596 max_rate = mtl_max_source_rate(intel_dp); 597 } else if (DISPLAY_VER(display) >= 11) { 598 source_rates = icl_rates; 599 size = ARRAY_SIZE(icl_rates); 600 if (display->platform.dg2) 601 max_rate = dg2_max_source_rate(intel_dp); 602 else if (display->platform.alderlake_p || display->platform.alderlake_s || 603 display->platform.dg1 || display->platform.rocketlake) 604 max_rate = 810000; 605 else if (display->platform.jasperlake || display->platform.elkhartlake) 606 max_rate = ehl_max_source_rate(intel_dp); 607 else 608 max_rate = icl_max_source_rate(intel_dp); 609 } else if (display->platform.geminilake || display->platform.broxton) { 610 source_rates = bxt_rates; 611 size = ARRAY_SIZE(bxt_rates); 612 } else if (DISPLAY_VER(display) == 9) { 613 source_rates = skl_rates; 614 size = ARRAY_SIZE(skl_rates); 615 } else if ((display->platform.haswell && !display->platform.haswell_ulx) || 616 display->platform.broadwell) { 617 source_rates = hsw_rates; 618 size = ARRAY_SIZE(hsw_rates); 619 } else { 620 source_rates = g4x_rates; 621 size = ARRAY_SIZE(g4x_rates); 622 } 623 624 vbt_max_rate = vbt_max_link_rate(intel_dp); 625 if (max_rate && vbt_max_rate) 626 max_rate = min(max_rate, vbt_max_rate); 627 else if (vbt_max_rate) 628 max_rate = vbt_max_rate; 629 630 if (max_rate) 631 size = intel_dp_rate_limit_len(source_rates, size, max_rate); 632 633 intel_dp->source_rates = source_rates; 634 intel_dp->num_source_rates = size; 635} 636 637static int intersect_rates(const int *source_rates, int source_len, 638 const int *sink_rates, int sink_len, 639 int *common_rates) 640{ 641 int i = 0, j = 0, k = 0; 642 643 while (i < source_len && j < sink_len) { 644 if (source_rates[i] == sink_rates[j]) { 645 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) 646 return k; 647 common_rates[k] = source_rates[i]; 648 ++k; 649 ++i; 650 ++j; 651 } else if (source_rates[i] < sink_rates[j]) { 652 ++i; 653 } else { 654 ++j; 655 } 656 } 657 return k; 658} 659 660/* return index of rate in rates array, or -1 if not found */ 661int intel_dp_rate_index(const int *rates, int len, int rate) 662{ 663 int i; 664 665 for (i = 0; i < len; i++) 666 if (rate == rates[i]) 667 return i; 668 669 return -1; 670} 671 672static int intel_dp_link_config_rate(struct intel_dp *intel_dp, 673 const struct intel_dp_link_config *lc) 674{ 675 return intel_dp_common_rate(intel_dp, lc->link_rate_idx); 676} 677 678static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc) 679{ 680 return 1 << lc->lane_count_exp; 681} 682 683static int intel_dp_link_config_bw(struct intel_dp *intel_dp, 684 const struct intel_dp_link_config *lc) 685{ 686 return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc), 687 intel_dp_link_config_lane_count(lc)); 688} 689 690static int link_config_cmp_by_bw(const void *a, const void *b, const void *p) 691{ 692 struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */ 693 const struct intel_dp_link_config *lc_a = a; 694 const struct intel_dp_link_config *lc_b = b; 695 int bw_a = intel_dp_link_config_bw(intel_dp, lc_a); 696 int bw_b = intel_dp_link_config_bw(intel_dp, lc_b); 697 698 if (bw_a != bw_b) 699 return bw_a - bw_b; 700 701 return intel_dp_link_config_rate(intel_dp, lc_a) - 702 intel_dp_link_config_rate(intel_dp, lc_b); 703} 704 705static void intel_dp_link_config_init(struct intel_dp *intel_dp) 706{ 707 struct intel_display *display = to_intel_display(intel_dp); 708 struct intel_dp_link_config *lc; 709 int num_common_lane_configs; 710 int i; 711 int j; 712 713 if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp)))) 714 return; 715 716 num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1; 717 718 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs > 719 ARRAY_SIZE(intel_dp->link.configs))) 720 return; 721 722 intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs; 723 724 lc = &intel_dp->link.configs[0]; 725 for (i = 0; i < intel_dp->num_common_rates; i++) { 726 for (j = 0; j < num_common_lane_configs; j++) { 727 lc->lane_count_exp = j; 728 lc->link_rate_idx = i; 729 730 lc++; 731 } 732 } 733 734 sort_r(intel_dp->link.configs, intel_dp->link.num_configs, 735 sizeof(intel_dp->link.configs[0]), 736 link_config_cmp_by_bw, NULL, 737 intel_dp); 738} 739 740void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count) 741{ 742 struct intel_display *display = to_intel_display(intel_dp); 743 const struct intel_dp_link_config *lc; 744 745 if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs)) 746 idx = 0; 747 748 lc = &intel_dp->link.configs[idx]; 749 750 *link_rate = intel_dp_link_config_rate(intel_dp, lc); 751 *lane_count = intel_dp_link_config_lane_count(lc); 752} 753 754int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count) 755{ 756 int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates, 757 link_rate); 758 int lane_count_exp = ilog2(lane_count); 759 int i; 760 761 for (i = 0; i < intel_dp->link.num_configs; i++) { 762 const struct intel_dp_link_config *lc = &intel_dp->link.configs[i]; 763 764 if (lc->lane_count_exp == lane_count_exp && 765 lc->link_rate_idx == link_rate_idx) 766 return i; 767 } 768 769 return -1; 770} 771 772static void intel_dp_set_common_rates(struct intel_dp *intel_dp) 773{ 774 struct intel_display *display = to_intel_display(intel_dp); 775 776 drm_WARN_ON(display->drm, 777 !intel_dp->num_source_rates || !intel_dp->num_sink_rates); 778 779 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, 780 intel_dp->num_source_rates, 781 intel_dp->sink_rates, 782 intel_dp->num_sink_rates, 783 intel_dp->common_rates); 784 785 /* Paranoia, there should always be something in common. */ 786 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) { 787 intel_dp->common_rates[0] = 162000; 788 intel_dp->num_common_rates = 1; 789 } 790 791 intel_dp_link_config_init(intel_dp); 792} 793 794bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, 795 u8 lane_count) 796{ 797 /* 798 * FIXME: we need to synchronize the current link parameters with 799 * hardware readout. Currently fast link training doesn't work on 800 * boot-up. 801 */ 802 if (link_rate == 0 || 803 link_rate > intel_dp->link.max_rate) 804 return false; 805 806 if (lane_count == 0 || 807 lane_count > intel_dp_max_lane_count(intel_dp)) 808 return false; 809 810 return true; 811} 812 813u32 intel_dp_mode_to_fec_clock(u32 mode_clock) 814{ 815 return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR), 816 1000000U); 817} 818 819int intel_dp_bw_fec_overhead(bool fec_enabled) 820{ 821 /* 822 * TODO: Calculate the actual overhead for a given mode. 823 * The hard-coded 1/0.972261=2.853% overhead factor 824 * corresponds (for instance) to the 8b/10b DP FEC 2.4% + 825 * 0.453% DSC overhead. This is enough for a 3840 width mode, 826 * which has a DSC overhead of up to ~0.2%, but may not be 827 * enough for a 1024 width mode where this is ~0.8% (on a 4 828 * lane DP link, with 2 DSC slices and 8 bpp color depth). 829 */ 830 return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000; 831} 832 833static int 834small_joiner_ram_size_bits(struct intel_display *display) 835{ 836 if (DISPLAY_VER(display) >= 13) 837 return 17280 * 8; 838 else if (DISPLAY_VER(display) >= 11) 839 return 7680 * 8; 840 else 841 return 6144 * 8; 842} 843 844static u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp) 845{ 846 u32 bits_per_pixel = bpp; 847 int i; 848 849 /* Error out if the max bpp is less than smallest allowed valid bpp */ 850 if (bits_per_pixel < valid_dsc_bpp[0]) { 851 drm_dbg_kms(display->drm, "Unsupported BPP %u, min %u\n", 852 bits_per_pixel, valid_dsc_bpp[0]); 853 return 0; 854 } 855 856 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */ 857 if (DISPLAY_VER(display) >= 13) { 858 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); 859 860 /* 861 * According to BSpec, 27 is the max DSC output bpp, 862 * 8 is the min DSC output bpp. 863 * While we can still clamp higher bpp values to 27, saving bandwidth, 864 * if it is required to oompress up to bpp < 8, means we can't do 865 * that and probably means we can't fit the required mode, even with 866 * DSC enabled. 867 */ 868 if (bits_per_pixel < 8) { 869 drm_dbg_kms(display->drm, 870 "Unsupported BPP %u, min 8\n", 871 bits_per_pixel); 872 return 0; 873 } 874 bits_per_pixel = min_t(u32, bits_per_pixel, 27); 875 } else { 876 /* Find the nearest match in the array of known BPPs from VESA */ 877 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { 878 if (bits_per_pixel < valid_dsc_bpp[i + 1]) 879 break; 880 } 881 drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n", 882 bits_per_pixel, valid_dsc_bpp[i]); 883 884 bits_per_pixel = valid_dsc_bpp[i]; 885 } 886 887 return bits_per_pixel; 888} 889 890static int bigjoiner_interface_bits(struct intel_display *display) 891{ 892 return DISPLAY_VER(display) >= 14 ? 36 : 24; 893} 894 895static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock, 896 int num_joined_pipes) 897{ 898 u32 max_bpp; 899 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ 900 int ppc = 2; 901 int num_big_joiners = num_joined_pipes / 2; 902 903 max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) / 904 intel_dp_mode_to_fec_clock(mode_clock); 905 906 max_bpp *= num_big_joiners; 907 908 return max_bpp; 909 910} 911 912static u32 small_joiner_ram_max_bpp(struct intel_display *display, 913 u32 mode_hdisplay, 914 int num_joined_pipes) 915{ 916 u32 max_bpp; 917 918 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ 919 max_bpp = small_joiner_ram_size_bits(display) / mode_hdisplay; 920 921 max_bpp *= num_joined_pipes; 922 923 return max_bpp; 924} 925 926static int ultrajoiner_ram_bits(void) 927{ 928 return 4 * 72 * 512; 929} 930 931static u32 ultrajoiner_ram_max_bpp(u32 mode_hdisplay) 932{ 933 return ultrajoiner_ram_bits() / mode_hdisplay; 934} 935 936/* TODO: return a bpp_x16 value */ 937static 938u32 get_max_compressed_bpp_with_joiner(struct intel_display *display, 939 u32 mode_clock, u32 mode_hdisplay, 940 int num_joined_pipes) 941{ 942 u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes); 943 944 if (num_joined_pipes > 1) 945 max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock, 946 num_joined_pipes)); 947 if (num_joined_pipes == 4) 948 max_bpp = min(max_bpp, ultrajoiner_ram_max_bpp(mode_hdisplay)); 949 950 return max_bpp; 951} 952 953/* TODO: return a bpp_x16 value */ 954u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display, 955 u32 link_clock, u32 lane_count, 956 u32 mode_clock, u32 mode_hdisplay, 957 int num_joined_pipes, 958 enum intel_output_format output_format, 959 u32 pipe_bpp, 960 u32 timeslots) 961{ 962 u32 bits_per_pixel, joiner_max_bpp; 963 964 /* 965 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* 966 * (LinkSymbolClock)* 8 * (TimeSlots / 64) 967 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available) 968 * for MST -> TimeSlots has to be calculated, based on mode requirements 969 * 970 * Due to FEC overhead, the available bw is reduced to 97.2261%. 971 * To support the given mode: 972 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead 973 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead 974 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock 975 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) / 976 * (ModeClock / FEC Overhead) 977 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) / 978 * (ModeClock / FEC Overhead * 8) 979 */ 980 bits_per_pixel = ((link_clock * lane_count) * timeslots) / 981 (intel_dp_mode_to_fec_clock(mode_clock) * 8); 982 983 /* Bandwidth required for 420 is half, that of 444 format */ 984 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 985 bits_per_pixel *= 2; 986 987 /* 988 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum 989 * supported PPS value can be 63.9375 and with the further 990 * mention that for 420, 422 formats, bpp should be programmed double 991 * the target bpp restricting our target bpp to be 31.9375 at max. 992 */ 993 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 994 bits_per_pixel = min_t(u32, bits_per_pixel, 31); 995 996 drm_dbg_kms(display->drm, "Max link bpp is %u for %u timeslots " 997 "total bw %u pixel clock %u\n", 998 bits_per_pixel, timeslots, 999 (link_clock * lane_count * 8), 1000 intel_dp_mode_to_fec_clock(mode_clock)); 1001 1002 joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock, 1003 mode_hdisplay, num_joined_pipes); 1004 bits_per_pixel = min(bits_per_pixel, joiner_max_bpp); 1005 1006 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bits_per_pixel, pipe_bpp); 1007 1008 return bits_per_pixel; 1009} 1010 1011u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, 1012 int mode_clock, int mode_hdisplay, 1013 int num_joined_pipes) 1014{ 1015 struct intel_display *display = to_intel_display(connector); 1016 u8 min_slice_count, i; 1017 int max_slice_width; 1018 int tp_rgb_yuv444; 1019 int tp_yuv422_420; 1020 1021 /* 1022 * TODO: Use the throughput value specific to the actual RGB/YUV 1023 * format of the output. 1024 * The RGB/YUV444 throughput value should be always either equal 1025 * or smaller than the YUV422/420 value, but let's not depend on 1026 * this assumption. 1027 */ 1028 if (mode_clock > max(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444, 1029 connector->dp.dsc_branch_caps.overall_throughput.yuv422_420)) 1030 return 0; 1031 1032 if (mode_hdisplay > connector->dp.dsc_branch_caps.max_line_width) 1033 return 0; 1034 1035 /* 1036 * TODO: Pass the total pixel rate of all the streams transferred to 1037 * an MST tiled display, calculate the total slice count for all tiles 1038 * from this and the per-tile slice count from the total slice count. 1039 */ 1040 tp_rgb_yuv444 = drm_dp_dsc_sink_max_slice_throughput(connector->dp.dsc_dpcd, 1041 mode_clock, true); 1042 tp_yuv422_420 = drm_dp_dsc_sink_max_slice_throughput(connector->dp.dsc_dpcd, 1043 mode_clock, false); 1044 1045 /* 1046 * TODO: Use the throughput value specific to the actual RGB/YUV 1047 * format of the output. 1048 * For now use the smaller of these, which is ok, potentially 1049 * resulting in a higher than required minimum slice count. 1050 * The RGB/YUV444 throughput value should be always either equal 1051 * or smaller than the YUV422/420 value, but let's not depend on 1052 * this assumption. 1053 */ 1054 min_slice_count = DIV_ROUND_UP(mode_clock, min(tp_rgb_yuv444, tp_yuv422_420)); 1055 1056 /* 1057 * Due to some DSC engine BW limitations, we need to enable second 1058 * slice and VDSC engine, whenever we approach close enough to max CDCLK 1059 */ 1060 if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100)) 1061 min_slice_count = max_t(u8, min_slice_count, 2); 1062 1063 max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd); 1064 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { 1065 drm_dbg_kms(display->drm, 1066 "Unsupported slice width %d by DP DSC Sink device\n", 1067 max_slice_width); 1068 return 0; 1069 } 1070 /* Also take into account max slice width */ 1071 min_slice_count = max_t(u8, min_slice_count, 1072 DIV_ROUND_UP(mode_hdisplay, 1073 max_slice_width)); 1074 1075 /* Find the closest match to the valid slice count values */ 1076 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { 1077 u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes; 1078 1079 /* 1080 * 3 DSC Slices per pipe need 3 DSC engines, which is supported only 1081 * with Ultrajoiner only for some platforms. 1082 */ 1083 if (valid_dsc_slicecount[i] == 3 && 1084 (!HAS_DSC_3ENGINES(display) || num_joined_pipes != 4)) 1085 continue; 1086 1087 if (test_slice_count > 1088 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false)) 1089 break; 1090 1091 /* 1092 * Bigjoiner needs small joiner to be enabled. 1093 * So there should be at least 2 dsc slices per pipe, 1094 * whenever bigjoiner is enabled. 1095 */ 1096 if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2) 1097 continue; 1098 1099 if (mode_hdisplay % test_slice_count) 1100 continue; 1101 1102 if (min_slice_count <= test_slice_count) 1103 return test_slice_count; 1104 } 1105 1106 drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n", 1107 min_slice_count); 1108 return 0; 1109} 1110 1111static bool source_can_output(struct intel_dp *intel_dp, 1112 enum intel_output_format format) 1113{ 1114 struct intel_display *display = to_intel_display(intel_dp); 1115 1116 switch (format) { 1117 case INTEL_OUTPUT_FORMAT_RGB: 1118 return true; 1119 1120 case INTEL_OUTPUT_FORMAT_YCBCR444: 1121 /* 1122 * No YCbCr output support on gmch platforms. 1123 * Also, ILK doesn't seem capable of DP YCbCr output. 1124 * The displayed image is severely corrupted. SNB+ is fine. 1125 */ 1126 return !HAS_GMCH(display) && !display->platform.ironlake; 1127 1128 case INTEL_OUTPUT_FORMAT_YCBCR420: 1129 /* Platform < Gen 11 cannot output YCbCr420 format */ 1130 return DISPLAY_VER(display) >= 11; 1131 1132 default: 1133 MISSING_CASE(format); 1134 return false; 1135 } 1136} 1137 1138static bool 1139dfp_can_convert_from_rgb(struct intel_dp *intel_dp, 1140 enum intel_output_format sink_format) 1141{ 1142 if (!drm_dp_is_branch(intel_dp->dpcd)) 1143 return false; 1144 1145 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1146 return intel_dp->dfp.rgb_to_ycbcr; 1147 1148 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1149 return intel_dp->dfp.rgb_to_ycbcr && 1150 intel_dp->dfp.ycbcr_444_to_420; 1151 1152 return false; 1153} 1154 1155static bool 1156dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp, 1157 enum intel_output_format sink_format) 1158{ 1159 if (!drm_dp_is_branch(intel_dp->dpcd)) 1160 return false; 1161 1162 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1163 return intel_dp->dfp.ycbcr_444_to_420; 1164 1165 return false; 1166} 1167 1168static bool 1169dfp_can_convert(struct intel_dp *intel_dp, 1170 enum intel_output_format output_format, 1171 enum intel_output_format sink_format) 1172{ 1173 switch (output_format) { 1174 case INTEL_OUTPUT_FORMAT_RGB: 1175 return dfp_can_convert_from_rgb(intel_dp, sink_format); 1176 case INTEL_OUTPUT_FORMAT_YCBCR444: 1177 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format); 1178 default: 1179 MISSING_CASE(output_format); 1180 return false; 1181 } 1182 1183 return false; 1184} 1185 1186static enum intel_output_format 1187intel_dp_output_format(struct intel_connector *connector, 1188 enum intel_output_format sink_format) 1189{ 1190 struct intel_display *display = to_intel_display(connector); 1191 struct intel_dp *intel_dp = intel_attached_dp(connector); 1192 enum intel_output_format force_dsc_output_format = 1193 intel_dp->force_dsc_output_format; 1194 enum intel_output_format output_format; 1195 if (force_dsc_output_format) { 1196 if (source_can_output(intel_dp, force_dsc_output_format) && 1197 (!drm_dp_is_branch(intel_dp->dpcd) || 1198 sink_format != force_dsc_output_format || 1199 dfp_can_convert(intel_dp, force_dsc_output_format, sink_format))) 1200 return force_dsc_output_format; 1201 1202 drm_dbg_kms(display->drm, "Cannot force DSC output format\n"); 1203 } 1204 1205 if (sink_format == INTEL_OUTPUT_FORMAT_RGB || 1206 dfp_can_convert_from_rgb(intel_dp, sink_format)) 1207 output_format = INTEL_OUTPUT_FORMAT_RGB; 1208 1209 else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 1210 dfp_can_convert_from_ycbcr444(intel_dp, sink_format)) 1211 output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 1212 1213 else 1214 output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 1215 1216 drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format)); 1217 1218 return output_format; 1219} 1220 1221int intel_dp_min_bpp(enum intel_output_format output_format) 1222{ 1223 if (output_format == INTEL_OUTPUT_FORMAT_RGB) 1224 return intel_display_min_pipe_bpp(); 1225 else 1226 return 8 * 3; 1227} 1228 1229int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) 1230{ 1231 /* 1232 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output 1233 * format of the number of bytes per pixel will be half the number 1234 * of bytes of RGB pixel. 1235 */ 1236 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1237 bpp /= 2; 1238 1239 return bpp; 1240} 1241 1242static enum intel_output_format 1243intel_dp_sink_format(struct intel_connector *connector, 1244 const struct drm_display_mode *mode) 1245{ 1246 const struct drm_display_info *info = &connector->base.display_info; 1247 1248 if (drm_mode_is_420_only(info, mode)) 1249 return INTEL_OUTPUT_FORMAT_YCBCR420; 1250 1251 return INTEL_OUTPUT_FORMAT_RGB; 1252} 1253 1254static int 1255intel_dp_mode_min_output_bpp(struct intel_connector *connector, 1256 const struct drm_display_mode *mode) 1257{ 1258 enum intel_output_format output_format, sink_format; 1259 1260 sink_format = intel_dp_sink_format(connector, mode); 1261 1262 output_format = intel_dp_output_format(connector, sink_format); 1263 1264 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); 1265} 1266 1267static bool intel_dp_hdisplay_bad(struct intel_display *display, 1268 int hdisplay) 1269{ 1270 /* 1271 * Older platforms don't like hdisplay==4096 with DP. 1272 * 1273 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline 1274 * and frame counter increment), but we don't get vblank interrupts, 1275 * and the pipe underruns immediately. The link also doesn't seem 1276 * to get trained properly. 1277 * 1278 * On CHV the vblank interrupts don't seem to disappear but 1279 * otherwise the symptoms are similar. 1280 * 1281 * TODO: confirm the behaviour on HSW+ 1282 */ 1283 return hdisplay == 4096 && !HAS_DDI(display); 1284} 1285 1286static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp) 1287{ 1288 struct intel_connector *connector = intel_dp->attached_connector; 1289 const struct drm_display_info *info = &connector->base.display_info; 1290 int max_tmds_clock = intel_dp->dfp.max_tmds_clock; 1291 1292 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */ 1293 if (max_tmds_clock && info->max_tmds_clock) 1294 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); 1295 1296 return max_tmds_clock; 1297} 1298 1299static enum drm_mode_status 1300intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, 1301 int clock, int bpc, 1302 enum intel_output_format sink_format, 1303 bool respect_downstream_limits) 1304{ 1305 int tmds_clock, min_tmds_clock, max_tmds_clock; 1306 1307 if (!respect_downstream_limits) 1308 return MODE_OK; 1309 1310 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1311 1312 min_tmds_clock = intel_dp->dfp.min_tmds_clock; 1313 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp); 1314 1315 if (min_tmds_clock && tmds_clock < min_tmds_clock) 1316 return MODE_CLOCK_LOW; 1317 1318 if (max_tmds_clock && tmds_clock > max_tmds_clock) 1319 return MODE_CLOCK_HIGH; 1320 1321 return MODE_OK; 1322} 1323 1324static enum drm_mode_status 1325intel_dp_mode_valid_downstream(struct intel_connector *connector, 1326 const struct drm_display_mode *mode, 1327 int target_clock) 1328{ 1329 struct intel_dp *intel_dp = intel_attached_dp(connector); 1330 const struct drm_display_info *info = &connector->base.display_info; 1331 enum drm_mode_status status; 1332 enum intel_output_format sink_format; 1333 1334 /* If PCON supports FRL MODE, check FRL bandwidth constraints */ 1335 if (intel_dp->dfp.pcon_max_frl_bw) { 1336 int target_bw; 1337 int max_frl_bw; 1338 int bpp = intel_dp_mode_min_output_bpp(connector, mode); 1339 1340 target_bw = bpp * target_clock; 1341 1342 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 1343 1344 /* converting bw from Gbps to Kbps*/ 1345 max_frl_bw = max_frl_bw * 1000000; 1346 1347 if (target_bw > max_frl_bw) 1348 return MODE_CLOCK_HIGH; 1349 1350 return MODE_OK; 1351 } 1352 1353 if (intel_dp->dfp.max_dotclock && 1354 target_clock > intel_dp->dfp.max_dotclock) 1355 return MODE_CLOCK_HIGH; 1356 1357 sink_format = intel_dp_sink_format(connector, mode); 1358 1359 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ 1360 status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 1361 8, sink_format, true); 1362 1363 if (status != MODE_OK) { 1364 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 1365 !connector->base.ycbcr_420_allowed || 1366 !drm_mode_is_420_also(info, mode)) 1367 return status; 1368 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 1369 status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 1370 8, sink_format, true); 1371 if (status != MODE_OK) 1372 return status; 1373 } 1374 1375 return MODE_OK; 1376} 1377 1378static 1379bool intel_dp_needs_joiner(struct intel_dp *intel_dp, 1380 struct intel_connector *connector, 1381 int hdisplay, int clock, 1382 int num_joined_pipes) 1383{ 1384 struct intel_display *display = to_intel_display(intel_dp); 1385 int hdisplay_limit; 1386 1387 if (!intel_dp_has_joiner(intel_dp)) 1388 return false; 1389 1390 num_joined_pipes /= 2; 1391 1392 hdisplay_limit = DISPLAY_VER(display) >= 30 ? 6144 : 5120; 1393 1394 return clock > num_joined_pipes * display->cdclk.max_dotclk_freq || 1395 hdisplay > num_joined_pipes * hdisplay_limit; 1396} 1397 1398int intel_dp_num_joined_pipes(struct intel_dp *intel_dp, 1399 struct intel_connector *connector, 1400 int hdisplay, int clock) 1401{ 1402 struct intel_display *display = to_intel_display(intel_dp); 1403 1404 if (connector->force_joined_pipes) 1405 return connector->force_joined_pipes; 1406 1407 if (HAS_ULTRAJOINER(display) && 1408 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 4)) 1409 return 4; 1410 1411 if ((HAS_BIGJOINER(display) || HAS_UNCOMPRESSED_JOINER(display)) && 1412 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 2)) 1413 return 2; 1414 1415 return 1; 1416} 1417 1418bool intel_dp_has_dsc(const struct intel_connector *connector) 1419{ 1420 struct intel_display *display = to_intel_display(connector); 1421 1422 if (!HAS_DSC(display)) 1423 return false; 1424 1425 if (connector->mst.dp && !HAS_DSC_MST(display)) 1426 return false; 1427 1428 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP && 1429 connector->panel.vbt.edp.dsc_disable) 1430 return false; 1431 1432 if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) 1433 return false; 1434 1435 return true; 1436} 1437 1438static enum drm_mode_status 1439intel_dp_mode_valid(struct drm_connector *_connector, 1440 const struct drm_display_mode *mode) 1441{ 1442 struct intel_display *display = to_intel_display(_connector->dev); 1443 struct intel_connector *connector = to_intel_connector(_connector); 1444 struct intel_dp *intel_dp = intel_attached_dp(connector); 1445 enum intel_output_format sink_format, output_format; 1446 const struct drm_display_mode *fixed_mode; 1447 int target_clock = mode->clock; 1448 int max_rate, mode_rate, max_lanes, max_link_clock; 1449 int max_dotclk = display->cdclk.max_dotclk_freq; 1450 u16 dsc_max_compressed_bpp = 0; 1451 u8 dsc_slice_count = 0; 1452 enum drm_mode_status status; 1453 bool dsc = false; 1454 int num_joined_pipes; 1455 1456 status = intel_cpu_transcoder_mode_valid(display, mode); 1457 if (status != MODE_OK) 1458 return status; 1459 1460 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1461 return MODE_H_ILLEGAL; 1462 1463 if (mode->clock < 10000) 1464 return MODE_CLOCK_LOW; 1465 1466 fixed_mode = intel_panel_fixed_mode(connector, mode); 1467 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 1468 status = intel_panel_mode_valid(connector, mode); 1469 if (status != MODE_OK) 1470 return status; 1471 1472 target_clock = fixed_mode->clock; 1473 } 1474 1475 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector, 1476 mode->hdisplay, target_clock); 1477 max_dotclk *= num_joined_pipes; 1478 1479 sink_format = intel_dp_sink_format(connector, mode); 1480 output_format = intel_dp_output_format(connector, sink_format); 1481 1482 status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes); 1483 if (status != MODE_OK) 1484 return status; 1485 1486 if (target_clock > max_dotclk) 1487 return MODE_CLOCK_HIGH; 1488 1489 if (intel_dp_hdisplay_bad(display, mode->hdisplay)) 1490 return MODE_H_ILLEGAL; 1491 1492 max_link_clock = intel_dp_max_link_rate(intel_dp); 1493 max_lanes = intel_dp_max_lane_count(intel_dp); 1494 1495 max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); 1496 1497 mode_rate = intel_dp_link_required(target_clock, 1498 intel_dp_mode_min_output_bpp(connector, mode)); 1499 1500 if (intel_dp_has_dsc(connector)) { 1501 int pipe_bpp; 1502 1503 /* 1504 * TBD pass the connector BPC, 1505 * for now U8_MAX so that max BPC on that platform would be picked 1506 */ 1507 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); 1508 1509 /* 1510 * Output bpp is stored in 6.4 format so right shift by 4 to get the 1511 * integer value since we support only integer values of bpp. 1512 */ 1513 if (intel_dp_is_edp(intel_dp)) { 1514 dsc_max_compressed_bpp = 1515 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4; 1516 dsc_slice_count = 1517 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, 1518 true); 1519 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { 1520 dsc_max_compressed_bpp = 1521 intel_dp_dsc_get_max_compressed_bpp(display, 1522 max_link_clock, 1523 max_lanes, 1524 target_clock, 1525 mode->hdisplay, 1526 num_joined_pipes, 1527 output_format, 1528 pipe_bpp, 64); 1529 dsc_slice_count = 1530 intel_dp_dsc_get_slice_count(connector, 1531 target_clock, 1532 mode->hdisplay, 1533 num_joined_pipes); 1534 } 1535 1536 dsc = dsc_max_compressed_bpp && dsc_slice_count; 1537 } 1538 1539 if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) 1540 return MODE_CLOCK_HIGH; 1541 1542 if (mode_rate > max_rate && !dsc) 1543 return MODE_CLOCK_HIGH; 1544 1545 status = intel_dp_mode_valid_downstream(connector, mode, target_clock); 1546 if (status != MODE_OK) 1547 return status; 1548 1549 return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes); 1550} 1551 1552bool intel_dp_source_supports_tps3(struct intel_display *display) 1553{ 1554 return DISPLAY_VER(display) >= 9 || 1555 display->platform.broadwell || display->platform.haswell; 1556} 1557 1558bool intel_dp_source_supports_tps4(struct intel_display *display) 1559{ 1560 return DISPLAY_VER(display) >= 10; 1561} 1562 1563static void seq_buf_print_array(struct seq_buf *s, const int *array, int nelem) 1564{ 1565 int i; 1566 1567 for (i = 0; i < nelem; i++) 1568 seq_buf_printf(s, "%s%d", i ? ", " : "", array[i]); 1569} 1570 1571static void intel_dp_print_rates(struct intel_dp *intel_dp) 1572{ 1573 struct intel_display *display = to_intel_display(intel_dp); 1574 DECLARE_SEQ_BUF(s, 128); /* FIXME: too big for stack? */ 1575 1576 if (!drm_debug_enabled(DRM_UT_KMS)) 1577 return; 1578 1579 seq_buf_print_array(&s, intel_dp->source_rates, intel_dp->num_source_rates); 1580 drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s)); 1581 1582 seq_buf_clear(&s); 1583 seq_buf_print_array(&s, intel_dp->sink_rates, intel_dp->num_sink_rates); 1584 drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s)); 1585 1586 seq_buf_clear(&s); 1587 seq_buf_print_array(&s, intel_dp->common_rates, intel_dp->num_common_rates); 1588 drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s)); 1589} 1590 1591static int forced_link_rate(struct intel_dp *intel_dp) 1592{ 1593 int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate); 1594 1595 if (len == 0) 1596 return intel_dp_common_rate(intel_dp, 0); 1597 1598 return intel_dp_common_rate(intel_dp, len - 1); 1599} 1600 1601int 1602intel_dp_max_link_rate(struct intel_dp *intel_dp) 1603{ 1604 int len; 1605 1606 if (intel_dp->link.force_rate) 1607 return forced_link_rate(intel_dp); 1608 1609 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate); 1610 1611 return intel_dp_common_rate(intel_dp, len - 1); 1612} 1613 1614static int 1615intel_dp_min_link_rate(struct intel_dp *intel_dp) 1616{ 1617 if (intel_dp->link.force_rate) 1618 return forced_link_rate(intel_dp); 1619 1620 return intel_dp_common_rate(intel_dp, 0); 1621} 1622 1623int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) 1624{ 1625 struct intel_display *display = to_intel_display(intel_dp); 1626 int i = intel_dp_rate_index(intel_dp->sink_rates, 1627 intel_dp->num_sink_rates, rate); 1628 1629 if (drm_WARN_ON(display->drm, i < 0)) 1630 i = 0; 1631 1632 return i; 1633} 1634 1635void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 1636 u8 *link_bw, u8 *rate_select) 1637{ 1638 struct intel_display *display = to_intel_display(intel_dp); 1639 1640 /* FIXME g4x can't generate an exact 2.7GHz with the 96MHz non-SSC refclk */ 1641 if (display->platform.g4x && port_clock == 268800) 1642 port_clock = 270000; 1643 1644 /* eDP 1.4 rate select method. */ 1645 if (intel_dp->use_rate_select) { 1646 *link_bw = 0; 1647 *rate_select = 1648 intel_dp_rate_select(intel_dp, port_clock); 1649 } else { 1650 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); 1651 *rate_select = 0; 1652 } 1653} 1654 1655bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp) 1656{ 1657 struct intel_connector *connector = intel_dp->attached_connector; 1658 1659 return connector->base.display_info.is_hdmi; 1660} 1661 1662static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, 1663 const struct intel_crtc_state *pipe_config) 1664{ 1665 struct intel_display *display = to_intel_display(intel_dp); 1666 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1667 1668 if (DISPLAY_VER(display) >= 12) 1669 return true; 1670 1671 if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A && 1672 !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) 1673 return true; 1674 1675 return false; 1676} 1677 1678bool intel_dp_supports_fec(struct intel_dp *intel_dp, 1679 const struct intel_connector *connector, 1680 const struct intel_crtc_state *pipe_config) 1681{ 1682 return intel_dp_source_supports_fec(intel_dp, pipe_config) && 1683 drm_dp_sink_supports_fec(connector->dp.fec_capability); 1684} 1685 1686bool intel_dp_supports_dsc(struct intel_dp *intel_dp, 1687 const struct intel_connector *connector, 1688 const struct intel_crtc_state *crtc_state) 1689{ 1690 if (!intel_dp_has_dsc(connector)) 1691 return false; 1692 1693 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && 1694 !intel_dp_supports_fec(intel_dp, connector, crtc_state)) 1695 return false; 1696 1697 return intel_dsc_source_support(crtc_state); 1698} 1699 1700static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, 1701 const struct intel_crtc_state *crtc_state, 1702 int bpc, bool respect_downstream_limits) 1703{ 1704 int clock = crtc_state->hw.adjusted_mode.crtc_clock; 1705 1706 /* 1707 * Current bpc could already be below 8bpc due to 1708 * FDI bandwidth constraints or other limits. 1709 * HDMI minimum is 8bpc however. 1710 */ 1711 bpc = max(bpc, 8); 1712 1713 /* 1714 * We will never exceed downstream TMDS clock limits while 1715 * attempting deep color. If the user insists on forcing an 1716 * out of spec mode they will have to be satisfied with 8bpc. 1717 */ 1718 if (!respect_downstream_limits) 1719 bpc = 8; 1720 1721 for (; bpc >= 8; bpc -= 2) { 1722 if (intel_hdmi_bpc_possible(crtc_state, bpc, 1723 intel_dp_has_hdmi_sink(intel_dp)) && 1724 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format, 1725 respect_downstream_limits) == MODE_OK) 1726 return bpc; 1727 } 1728 1729 return -EINVAL; 1730} 1731 1732static int intel_dp_max_bpp(struct intel_dp *intel_dp, 1733 const struct intel_crtc_state *crtc_state, 1734 bool respect_downstream_limits) 1735{ 1736 struct intel_display *display = to_intel_display(intel_dp); 1737 struct intel_connector *connector = intel_dp->attached_connector; 1738 int bpp, bpc; 1739 1740 bpc = crtc_state->pipe_bpp / 3; 1741 1742 if (intel_dp->dfp.max_bpc) 1743 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); 1744 1745 if (intel_dp->dfp.min_tmds_clock) { 1746 int max_hdmi_bpc; 1747 1748 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc, 1749 respect_downstream_limits); 1750 if (max_hdmi_bpc < 0) 1751 return 0; 1752 1753 bpc = min(bpc, max_hdmi_bpc); 1754 } 1755 1756 bpp = bpc * 3; 1757 if (intel_dp_is_edp(intel_dp)) { 1758 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1759 if (connector->base.display_info.bpc == 0 && 1760 connector->panel.vbt.edp.bpp && 1761 connector->panel.vbt.edp.bpp < bpp) { 1762 drm_dbg_kms(display->drm, 1763 "clamping bpp for eDP panel to BIOS-provided %i\n", 1764 connector->panel.vbt.edp.bpp); 1765 bpp = connector->panel.vbt.edp.bpp; 1766 } 1767 } 1768 1769 return bpp; 1770} 1771 1772static bool has_seamless_m_n(struct intel_connector *connector) 1773{ 1774 struct intel_display *display = to_intel_display(connector); 1775 1776 /* 1777 * Seamless M/N reprogramming only implemented 1778 * for BDW+ double buffered M/N registers so far. 1779 */ 1780 return HAS_DOUBLE_BUFFERED_M_N(display) && 1781 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 1782} 1783 1784static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state, 1785 const struct drm_connector_state *conn_state) 1786{ 1787 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1788 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1789 1790 /* FIXME a bit of a mess wrt clock vs. crtc_clock */ 1791 if (has_seamless_m_n(connector)) 1792 return intel_panel_highest_mode(connector, adjusted_mode)->clock; 1793 else 1794 return adjusted_mode->crtc_clock; 1795} 1796 1797/* Optimize link config in order: max bpp, min clock, min lanes */ 1798static int 1799intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, 1800 struct intel_crtc_state *pipe_config, 1801 const struct drm_connector_state *conn_state, 1802 const struct link_config_limits *limits) 1803{ 1804 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); 1805 int mode_rate, link_rate, link_avail; 1806 1807 for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 1808 bpp >= fxp_q4_to_int(limits->link.min_bpp_x16); 1809 bpp -= 2 * 3) { 1810 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); 1811 1812 mode_rate = intel_dp_link_required(clock, link_bpp); 1813 1814 for (i = 0; i < intel_dp->num_common_rates; i++) { 1815 link_rate = intel_dp_common_rate(intel_dp, i); 1816 if (link_rate < limits->min_rate || 1817 link_rate > limits->max_rate) 1818 continue; 1819 1820 for (lane_count = limits->min_lane_count; 1821 lane_count <= limits->max_lane_count; 1822 lane_count <<= 1) { 1823 link_avail = intel_dp_max_link_data_rate(intel_dp, 1824 link_rate, 1825 lane_count); 1826 1827 1828 if (mode_rate <= link_avail) { 1829 pipe_config->lane_count = lane_count; 1830 pipe_config->pipe_bpp = bpp; 1831 pipe_config->port_clock = link_rate; 1832 1833 return 0; 1834 } 1835 } 1836 } 1837 } 1838 1839 return -EINVAL; 1840} 1841 1842int intel_dp_dsc_max_src_input_bpc(struct intel_display *display) 1843{ 1844 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ 1845 if (DISPLAY_VER(display) >= 12) 1846 return 12; 1847 if (DISPLAY_VER(display) == 11) 1848 return 10; 1849 1850 return intel_dp_dsc_min_src_input_bpc(); 1851} 1852 1853int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, 1854 u8 max_req_bpc) 1855{ 1856 struct intel_display *display = to_intel_display(connector); 1857 int i, num_bpc; 1858 u8 dsc_bpc[3] = {}; 1859 int dsc_max_bpc; 1860 1861 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display); 1862 1863 if (!dsc_max_bpc) 1864 return dsc_max_bpc; 1865 1866 dsc_max_bpc = min(dsc_max_bpc, max_req_bpc); 1867 1868 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, 1869 dsc_bpc); 1870 for (i = 0; i < num_bpc; i++) { 1871 if (dsc_max_bpc >= dsc_bpc[i]) 1872 return dsc_bpc[i] * 3; 1873 } 1874 1875 return 0; 1876} 1877 1878static int intel_dp_source_dsc_version_minor(struct intel_display *display) 1879{ 1880 return DISPLAY_VER(display) >= 14 ? 2 : 1; 1881} 1882 1883static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 1884{ 1885 return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >> 1886 DP_DSC_MINOR_SHIFT; 1887} 1888 1889static int intel_dp_get_slice_height(int vactive) 1890{ 1891 int slice_height; 1892 1893 /* 1894 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108 1895 * lines is an optimal slice height, but any size can be used as long as 1896 * vertical active integer multiple and maximum vertical slice count 1897 * requirements are met. 1898 */ 1899 for (slice_height = 108; slice_height <= vactive; slice_height += 2) 1900 if (vactive % slice_height == 0) 1901 return slice_height; 1902 1903 /* 1904 * Highly unlikely we reach here as most of the resolutions will end up 1905 * finding appropriate slice_height in above loop but returning 1906 * slice_height as 2 here as it should work with all resolutions. 1907 */ 1908 return 2; 1909} 1910 1911static int intel_dp_dsc_compute_params(const struct intel_connector *connector, 1912 struct intel_crtc_state *crtc_state) 1913{ 1914 struct intel_display *display = to_intel_display(connector); 1915 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1916 int ret; 1917 1918 /* 1919 * RC_MODEL_SIZE is currently a constant across all configurations. 1920 * 1921 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and 1922 * DP_DSC_RC_BUF_SIZE for this. 1923 */ 1924 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1925 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1926 1927 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height); 1928 1929 ret = intel_dsc_compute_params(crtc_state); 1930 if (ret) 1931 return ret; 1932 1933 vdsc_cfg->dsc_version_major = 1934 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & 1935 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; 1936 vdsc_cfg->dsc_version_minor = 1937 min(intel_dp_source_dsc_version_minor(display), 1938 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)); 1939 if (vdsc_cfg->convert_rgb) 1940 vdsc_cfg->convert_rgb = 1941 connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & 1942 DP_DSC_RGB; 1943 1944 vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH, 1945 drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd)); 1946 if (!vdsc_cfg->line_buf_depth) { 1947 drm_dbg_kms(display->drm, 1948 "DSC Sink Line Buffer Depth invalid\n"); 1949 return -EINVAL; 1950 } 1951 1952 vdsc_cfg->block_pred_enable = 1953 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & 1954 DP_DSC_BLK_PREDICTION_IS_SUPPORTED; 1955 1956 return drm_dsc_compute_rc_parameters(vdsc_cfg); 1957} 1958 1959static bool intel_dp_dsc_supports_format(const struct intel_connector *connector, 1960 enum intel_output_format output_format) 1961{ 1962 struct intel_display *display = to_intel_display(connector); 1963 u8 sink_dsc_format; 1964 1965 switch (output_format) { 1966 case INTEL_OUTPUT_FORMAT_RGB: 1967 sink_dsc_format = DP_DSC_RGB; 1968 break; 1969 case INTEL_OUTPUT_FORMAT_YCBCR444: 1970 sink_dsc_format = DP_DSC_YCbCr444; 1971 break; 1972 case INTEL_OUTPUT_FORMAT_YCBCR420: 1973 if (min(intel_dp_source_dsc_version_minor(display), 1974 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2) 1975 return false; 1976 sink_dsc_format = DP_DSC_YCbCr420_Native; 1977 break; 1978 default: 1979 return false; 1980 } 1981 1982 return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format); 1983} 1984 1985static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 link_clock, 1986 u32 lane_count, u32 mode_clock, 1987 enum intel_output_format output_format, 1988 int timeslots) 1989{ 1990 u32 available_bw, required_bw; 1991 1992 available_bw = (link_clock * lane_count * timeslots * 16) / 8; 1993 required_bw = dsc_bpp_x16 * (intel_dp_mode_to_fec_clock(mode_clock)); 1994 1995 return available_bw > required_bw; 1996} 1997 1998static int dsc_compute_link_config(struct intel_dp *intel_dp, 1999 struct intel_crtc_state *pipe_config, 2000 struct drm_connector_state *conn_state, 2001 const struct link_config_limits *limits, 2002 int dsc_bpp_x16, 2003 int timeslots) 2004{ 2005 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2006 int link_rate, lane_count; 2007 int i; 2008 2009 for (i = 0; i < intel_dp->num_common_rates; i++) { 2010 link_rate = intel_dp_common_rate(intel_dp, i); 2011 if (link_rate < limits->min_rate || link_rate > limits->max_rate) 2012 continue; 2013 2014 for (lane_count = limits->min_lane_count; 2015 lane_count <= limits->max_lane_count; 2016 lane_count <<= 1) { 2017 2018 /* 2019 * FIXME: intel_dp_mtp_tu_compute_config() requires 2020 * ->lane_count and ->port_clock set before we know 2021 * they'll work. If we end up failing altogether, 2022 * they'll remain in crtc state. This shouldn't matter, 2023 * as we'd then bail out from compute config, but it's 2024 * just ugly. 2025 */ 2026 pipe_config->lane_count = lane_count; 2027 pipe_config->port_clock = link_rate; 2028 2029 if (drm_dp_is_uhbr_rate(link_rate)) { 2030 int ret; 2031 2032 ret = intel_dp_mtp_tu_compute_config(intel_dp, 2033 pipe_config, 2034 conn_state, 2035 dsc_bpp_x16, 2036 dsc_bpp_x16, 2037 0, true); 2038 if (ret) 2039 continue; 2040 } else { 2041 if (!is_bw_sufficient_for_dsc_config(dsc_bpp_x16, link_rate, 2042 lane_count, adjusted_mode->clock, 2043 pipe_config->output_format, 2044 timeslots)) 2045 continue; 2046 } 2047 2048 return 0; 2049 } 2050 } 2051 2052 return -EINVAL; 2053} 2054 2055static 2056u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector, 2057 const struct intel_crtc_state *pipe_config, 2058 int bpc) 2059{ 2060 u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd); 2061 2062 if (max_bppx16) 2063 return max_bppx16; 2064 /* 2065 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate 2066 * values as given in spec Table 2-157 DP v2.0 2067 */ 2068 switch (pipe_config->output_format) { 2069 case INTEL_OUTPUT_FORMAT_RGB: 2070 case INTEL_OUTPUT_FORMAT_YCBCR444: 2071 return (3 * bpc) << 4; 2072 case INTEL_OUTPUT_FORMAT_YCBCR420: 2073 return (3 * (bpc / 2)) << 4; 2074 default: 2075 MISSING_CASE(pipe_config->output_format); 2076 break; 2077 } 2078 2079 return 0; 2080} 2081 2082int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config) 2083{ 2084 /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */ 2085 switch (pipe_config->output_format) { 2086 case INTEL_OUTPUT_FORMAT_RGB: 2087 case INTEL_OUTPUT_FORMAT_YCBCR444: 2088 return 8; 2089 case INTEL_OUTPUT_FORMAT_YCBCR420: 2090 return 6; 2091 default: 2092 MISSING_CASE(pipe_config->output_format); 2093 break; 2094 } 2095 2096 return 0; 2097} 2098 2099int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, 2100 const struct intel_crtc_state *pipe_config, 2101 int bpc) 2102{ 2103 return intel_dp_dsc_max_sink_compressed_bppx16(connector, 2104 pipe_config, bpc) >> 4; 2105} 2106 2107int intel_dp_dsc_min_src_compressed_bpp(void) 2108{ 2109 /* Min Compressed bpp supported by source is 8 */ 2110 return 8; 2111} 2112 2113static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) 2114{ 2115 struct intel_display *display = to_intel_display(intel_dp); 2116 2117 /* 2118 * Forcing DSC and using the platform's max compressed bpp is seen to cause 2119 * underruns. Since DSC isn't needed in these cases, limit the 2120 * max compressed bpp to 18, which is a safe value across platforms with different 2121 * pipe bpps. 2122 */ 2123 if (intel_dp->force_dsc_en) 2124 return 18; 2125 2126 /* 2127 * Max Compressed bpp for Gen 13+ is 27bpp. 2128 * For earlier platform is 23bpp. (Bspec:49259). 2129 */ 2130 if (DISPLAY_VER(display) < 13) 2131 return 23; 2132 else 2133 return 27; 2134} 2135 2136/* 2137 * Note: for pre-13 display you still need to check the validity of each step. 2138 */ 2139int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) 2140{ 2141 struct intel_display *display = to_intel_display(connector); 2142 u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); 2143 2144 if (DISPLAY_VER(display) < 14 || !incr) 2145 return fxp_q4_from_int(1); 2146 2147 if (connector->mst.dp && 2148 !connector->link.force_bpp_x16 && !connector->mst.dp->force_dsc_fractional_bpp_en) 2149 return fxp_q4_from_int(1); 2150 2151 /* fxp q4 */ 2152 return fxp_q4_from_int(1) / incr; 2153} 2154 2155/* 2156 * Note: for bpp_x16 to be valid it must be also within the source/sink's 2157 * min..max bpp capability range. 2158 */ 2159bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16) 2160{ 2161 struct intel_display *display = to_intel_display(intel_dp); 2162 int i; 2163 2164 if (DISPLAY_VER(display) >= 13) { 2165 if (intel_dp->force_dsc_fractional_bpp_en && !fxp_q4_to_frac(bpp_x16)) 2166 return false; 2167 2168 return true; 2169 } 2170 2171 if (fxp_q4_to_frac(bpp_x16)) 2172 return false; 2173 2174 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { 2175 if (fxp_q4_to_int(bpp_x16) == valid_dsc_bpp[i]) 2176 return true; 2177 } 2178 2179 return false; 2180} 2181 2182/* 2183 * Find the max compressed BPP we can find a link configuration for. The BPPs to 2184 * try depend on the source (platform) and sink. 2185 */ 2186static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, 2187 struct intel_crtc_state *pipe_config, 2188 struct drm_connector_state *conn_state, 2189 const struct link_config_limits *limits, 2190 int pipe_bpp, 2191 int timeslots) 2192{ 2193 struct intel_display *display = to_intel_display(intel_dp); 2194 const struct intel_connector *connector = to_intel_connector(conn_state->connector); 2195 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2196 int output_bpp; 2197 int min_bpp_x16, max_bpp_x16, bpp_step_x16; 2198 int dsc_joiner_max_bpp; 2199 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); 2200 int bpp_x16; 2201 int ret; 2202 2203 dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock, 2204 adjusted_mode->hdisplay, 2205 num_joined_pipes); 2206 max_bpp_x16 = min(fxp_q4_from_int(dsc_joiner_max_bpp), limits->link.max_bpp_x16); 2207 2208 bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); 2209 2210 /* Compressed BPP should be less than the Input DSC bpp */ 2211 output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); 2212 max_bpp_x16 = min(max_bpp_x16, fxp_q4_from_int(output_bpp) - bpp_step_x16); 2213 2214 drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16)); 2215 min_bpp_x16 = round_up(limits->link.min_bpp_x16, bpp_step_x16); 2216 max_bpp_x16 = round_down(max_bpp_x16, bpp_step_x16); 2217 2218 for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) { 2219 if (!intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16)) 2220 continue; 2221 2222 ret = dsc_compute_link_config(intel_dp, 2223 pipe_config, 2224 conn_state, 2225 limits, 2226 bpp_x16, 2227 timeslots); 2228 if (ret == 0) { 2229 pipe_config->dsc.compressed_bpp_x16 = bpp_x16; 2230 if (intel_dp->force_dsc_fractional_bpp_en && 2231 fxp_q4_to_frac(bpp_x16)) 2232 drm_dbg_kms(display->drm, 2233 "Forcing DSC fractional bpp\n"); 2234 2235 return 0; 2236 } 2237 } 2238 2239 return -EINVAL; 2240} 2241 2242int intel_dp_dsc_min_src_input_bpc(void) 2243{ 2244 /* Min DSC Input BPC for ICL+ is 8 */ 2245 return 8; 2246} 2247 2248static 2249bool is_dsc_pipe_bpp_sufficient(const struct link_config_limits *limits, 2250 int pipe_bpp) 2251{ 2252 return pipe_bpp >= limits->pipe.min_bpp && 2253 pipe_bpp <= limits->pipe.max_bpp; 2254} 2255 2256static 2257int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp, 2258 const struct link_config_limits *limits) 2259{ 2260 struct intel_display *display = to_intel_display(intel_dp); 2261 int forced_bpp; 2262 2263 if (!intel_dp->force_dsc_bpc) 2264 return 0; 2265 2266 forced_bpp = intel_dp->force_dsc_bpc * 3; 2267 2268 if (is_dsc_pipe_bpp_sufficient(limits, forced_bpp)) { 2269 drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n", 2270 intel_dp->force_dsc_bpc); 2271 return forced_bpp; 2272 } 2273 2274 drm_dbg_kms(display->drm, 2275 "Cannot force DSC BPC:%d, due to DSC BPC limits\n", 2276 intel_dp->force_dsc_bpc); 2277 2278 return 0; 2279} 2280 2281static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 2282 struct intel_crtc_state *pipe_config, 2283 struct drm_connector_state *conn_state, 2284 const struct link_config_limits *limits, 2285 int timeslots) 2286{ 2287 const struct intel_connector *connector = 2288 to_intel_connector(conn_state->connector); 2289 u8 dsc_bpc[3] = {}; 2290 int forced_bpp, pipe_bpp; 2291 int num_bpc, i, ret; 2292 2293 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits); 2294 2295 if (forced_bpp) { 2296 ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state, 2297 limits, forced_bpp, timeslots); 2298 if (ret == 0) { 2299 pipe_config->pipe_bpp = forced_bpp; 2300 return 0; 2301 } 2302 } 2303 2304 /* 2305 * Get the maximum DSC bpc that will be supported by any valid 2306 * link configuration and compressed bpp. 2307 */ 2308 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc); 2309 for (i = 0; i < num_bpc; i++) { 2310 pipe_bpp = dsc_bpc[i] * 3; 2311 if (pipe_bpp < limits->pipe.min_bpp || pipe_bpp > limits->pipe.max_bpp) 2312 continue; 2313 2314 ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state, 2315 limits, pipe_bpp, timeslots); 2316 if (ret == 0) { 2317 pipe_config->pipe_bpp = pipe_bpp; 2318 return 0; 2319 } 2320 } 2321 2322 return -EINVAL; 2323} 2324 2325static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, 2326 struct intel_crtc_state *pipe_config, 2327 struct drm_connector_state *conn_state, 2328 const struct link_config_limits *limits) 2329{ 2330 struct intel_display *display = to_intel_display(intel_dp); 2331 struct intel_connector *connector = 2332 to_intel_connector(conn_state->connector); 2333 int pipe_bpp, forced_bpp; 2334 int dsc_min_bpp; 2335 int dsc_max_bpp; 2336 2337 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits); 2338 2339 if (forced_bpp) { 2340 pipe_bpp = forced_bpp; 2341 } else { 2342 int max_bpc = limits->pipe.max_bpp / 3; 2343 2344 /* For eDP use max bpp that can be supported with DSC. */ 2345 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc); 2346 if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) { 2347 drm_dbg_kms(display->drm, 2348 "Computed BPC is not in DSC BPC limits\n"); 2349 return -EINVAL; 2350 } 2351 } 2352 pipe_config->port_clock = limits->max_rate; 2353 pipe_config->lane_count = limits->max_lane_count; 2354 2355 dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16); 2356 2357 dsc_max_bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 2358 2359 /* Compressed BPP should be less than the Input DSC bpp */ 2360 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); 2361 2362 pipe_config->dsc.compressed_bpp_x16 = 2363 fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp)); 2364 2365 pipe_config->pipe_bpp = pipe_bpp; 2366 2367 return 0; 2368} 2369 2370/* 2371 * Return whether FEC must be enabled for 8b10b SST or MST links. On 128b132b 2372 * links FEC is always enabled implicitly by the HW, so this function returns 2373 * false for that case. 2374 */ 2375bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state, 2376 bool dsc_enabled_on_crtc) 2377{ 2378 if (intel_dp_is_uhbr(crtc_state)) 2379 return false; 2380 2381 /* 2382 * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional. 2383 * Since, FEC is a bandwidth overhead, continue to not enable it for 2384 * eDP. Until, there is a good reason to do so. 2385 */ 2386 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2387 return false; 2388 2389 return dsc_enabled_on_crtc || intel_dsc_enabled_on_link(crtc_state); 2390} 2391 2392int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 2393 struct intel_crtc_state *pipe_config, 2394 struct drm_connector_state *conn_state, 2395 const struct link_config_limits *limits, 2396 int timeslots) 2397{ 2398 struct intel_display *display = to_intel_display(intel_dp); 2399 const struct intel_connector *connector = 2400 to_intel_connector(conn_state->connector); 2401 const struct drm_display_mode *adjusted_mode = 2402 &pipe_config->hw.adjusted_mode; 2403 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); 2404 bool is_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST); 2405 int ret; 2406 2407 /* 2408 * FIXME: set the FEC enabled state once pipe_config->port_clock is 2409 * already known, so the UHBR/non-UHBR mode can be determined. 2410 */ 2411 pipe_config->fec_enable = intel_dp_needs_8b10b_fec(pipe_config, true); 2412 2413 if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format)) 2414 return -EINVAL; 2415 2416 /* 2417 * Link parameters, pipe bpp and compressed bpp have already been 2418 * figured out for DP MST DSC. 2419 */ 2420 if (!is_mst) { 2421 if (intel_dp_is_edp(intel_dp)) 2422 ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config, 2423 conn_state, limits); 2424 else 2425 ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config, 2426 conn_state, limits, timeslots); 2427 if (ret) { 2428 drm_dbg_kms(display->drm, 2429 "No Valid pipe bpp for given mode ret = %d\n", ret); 2430 return ret; 2431 } 2432 } 2433 2434 /* Calculate Slice count */ 2435 if (intel_dp_is_edp(intel_dp)) { 2436 pipe_config->dsc.slice_count = 2437 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, 2438 true); 2439 if (!pipe_config->dsc.slice_count) { 2440 drm_dbg_kms(display->drm, 2441 "Unsupported Slice Count %d\n", 2442 pipe_config->dsc.slice_count); 2443 return -EINVAL; 2444 } 2445 } else { 2446 u8 dsc_dp_slice_count; 2447 2448 dsc_dp_slice_count = 2449 intel_dp_dsc_get_slice_count(connector, 2450 adjusted_mode->crtc_clock, 2451 adjusted_mode->crtc_hdisplay, 2452 num_joined_pipes); 2453 if (!dsc_dp_slice_count) { 2454 drm_dbg_kms(display->drm, 2455 "Compressed Slice Count not supported\n"); 2456 return -EINVAL; 2457 } 2458 2459 pipe_config->dsc.slice_count = dsc_dp_slice_count; 2460 } 2461 /* 2462 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate 2463 * is greater than the maximum Cdclock and if slice count is even 2464 * then we need to use 2 VDSC instances. 2465 * In case of Ultrajoiner along with 12 slices we need to use 3 2466 * VDSC instances. 2467 */ 2468 if (pipe_config->joiner_pipes && num_joined_pipes == 4 && 2469 pipe_config->dsc.slice_count == 12) 2470 pipe_config->dsc.num_streams = 3; 2471 else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) 2472 pipe_config->dsc.num_streams = 2; 2473 else 2474 pipe_config->dsc.num_streams = 1; 2475 2476 ret = intel_dp_dsc_compute_params(connector, pipe_config); 2477 if (ret < 0) { 2478 drm_dbg_kms(display->drm, 2479 "Cannot compute valid DSC parameters for Input Bpp = %d" 2480 "Compressed BPP = " FXP_Q4_FMT "\n", 2481 pipe_config->pipe_bpp, 2482 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16)); 2483 return ret; 2484 } 2485 2486 intel_dsc_enable_on_crtc(pipe_config); 2487 2488 drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d " 2489 "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n", 2490 pipe_config->pipe_bpp, 2491 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2492 pipe_config->dsc.slice_count); 2493 2494 return 0; 2495} 2496 2497static int 2498dsc_throughput_quirk_max_bpp_x16(const struct intel_connector *connector, 2499 const struct intel_crtc_state *crtc_state) 2500{ 2501 const struct drm_display_mode *adjusted_mode = 2502 &crtc_state->hw.adjusted_mode; 2503 2504 if (!connector->dp.dsc_throughput_quirk) 2505 return INT_MAX; 2506 2507 /* 2508 * Synaptics Panamera branch devices have a problem decompressing a 2509 * stream with a compressed link-bpp higher than 12, if the pixel 2510 * clock is higher than ~50 % of the maximum overall throughput 2511 * reported by the branch device. Work around this by limiting the 2512 * maximum link bpp for such pixel clocks. 2513 * 2514 * TODO: Use the throughput value specific to the actual RGB/YUV 2515 * format of the output, after determining the pixel clock limit for 2516 * YUV modes. For now use the smaller of the throughput values, which 2517 * may result in limiting the link-bpp value already at a lower than 2518 * required mode clock in case of native YUV422/420 output formats. 2519 * The RGB/YUV444 throughput value should be always either equal or 2520 * smaller than the YUV422/420 value, but let's not depend on this 2521 * assumption. 2522 */ 2523 if (adjusted_mode->crtc_clock < 2524 min(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444, 2525 connector->dp.dsc_branch_caps.overall_throughput.yuv422_420) / 2) 2526 return INT_MAX; 2527 2528 return fxp_q4_from_int(12); 2529} 2530 2531/* 2532 * Calculate the output link min, max bpp values in limits based on the pipe bpp 2533 * range, crtc_state and dsc mode. Return true on success. 2534 */ 2535static bool 2536intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, 2537 const struct intel_connector *connector, 2538 const struct intel_crtc_state *crtc_state, 2539 bool dsc, 2540 struct link_config_limits *limits) 2541{ 2542 struct intel_display *display = to_intel_display(intel_dp); 2543 const struct drm_display_mode *adjusted_mode = 2544 &crtc_state->hw.adjusted_mode; 2545 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2546 const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2547 int max_link_bpp_x16; 2548 2549 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16, 2550 fxp_q4_from_int(limits->pipe.max_bpp)); 2551 2552 if (!dsc) { 2553 max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3)); 2554 2555 if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp)) 2556 return false; 2557 2558 limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp); 2559 } else { 2560 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; 2561 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; 2562 int throughput_max_bpp_x16; 2563 2564 dsc_src_min_bpp = intel_dp_dsc_min_src_compressed_bpp(); 2565 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state); 2566 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); 2567 limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp); 2568 2569 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); 2570 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, 2571 crtc_state, 2572 limits->pipe.max_bpp / 3); 2573 dsc_max_bpp = dsc_sink_max_bpp ? 2574 min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; 2575 2576 max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp)); 2577 2578 throughput_max_bpp_x16 = dsc_throughput_quirk_max_bpp_x16(connector, crtc_state); 2579 throughput_max_bpp_x16 = clamp(throughput_max_bpp_x16, 2580 limits->link.min_bpp_x16, max_link_bpp_x16); 2581 if (throughput_max_bpp_x16 < max_link_bpp_x16) { 2582 max_link_bpp_x16 = throughput_max_bpp_x16; 2583 2584 drm_dbg_kms(display->drm, 2585 "[CRTC:%d:%s][CONNECTOR:%d:%s] Decreasing link max bpp to " FXP_Q4_FMT " due to DSC throughput quirk\n", 2586 crtc->base.base.id, crtc->base.name, 2587 connector->base.base.id, connector->base.name, 2588 FXP_Q4_ARGS(max_link_bpp_x16)); 2589 } 2590 } 2591 2592 limits->link.max_bpp_x16 = max_link_bpp_x16; 2593 2594 drm_dbg_kms(display->drm, 2595 "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n", 2596 encoder->base.base.id, encoder->base.name, 2597 crtc->base.base.id, crtc->base.name, 2598 adjusted_mode->crtc_clock, 2599 str_on_off(dsc), 2600 limits->max_lane_count, 2601 limits->max_rate, 2602 limits->pipe.max_bpp, 2603 FXP_Q4_ARGS(limits->link.max_bpp_x16)); 2604 2605 return true; 2606} 2607 2608static bool 2609intel_dp_dsc_compute_pipe_bpp_limits(struct intel_connector *connector, 2610 struct link_config_limits *limits) 2611{ 2612 struct intel_display *display = to_intel_display(connector); 2613 const struct link_config_limits orig_limits = *limits; 2614 int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(); 2615 int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display); 2616 2617 limits->pipe.min_bpp = max(limits->pipe.min_bpp, dsc_min_bpc * 3); 2618 limits->pipe.max_bpp = min(limits->pipe.max_bpp, dsc_max_bpc * 3); 2619 2620 if (limits->pipe.min_bpp <= 0 || 2621 limits->pipe.min_bpp > limits->pipe.max_bpp) { 2622 drm_dbg_kms(display->drm, 2623 "[CONNECTOR:%d:%s] Invalid DSC src/sink input BPP (src:%d-%d pipe:%d-%d)\n", 2624 connector->base.base.id, connector->base.name, 2625 dsc_min_bpc * 3, dsc_max_bpc * 3, 2626 orig_limits.pipe.min_bpp, orig_limits.pipe.max_bpp); 2627 2628 return false; 2629 } 2630 2631 return true; 2632} 2633 2634bool 2635intel_dp_compute_config_limits(struct intel_dp *intel_dp, 2636 struct drm_connector_state *conn_state, 2637 struct intel_crtc_state *crtc_state, 2638 bool respect_downstream_limits, 2639 bool dsc, 2640 struct link_config_limits *limits) 2641{ 2642 struct intel_display *display = to_intel_display(intel_dp); 2643 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2644 struct intel_connector *connector = 2645 to_intel_connector(conn_state->connector); 2646 2647 limits->min_rate = intel_dp_min_link_rate(intel_dp); 2648 limits->max_rate = intel_dp_max_link_rate(intel_dp); 2649 2650 limits->min_rate = min(limits->min_rate, limits->max_rate); 2651 2652 limits->min_lane_count = intel_dp_min_lane_count(intel_dp); 2653 limits->max_lane_count = intel_dp_max_lane_count(intel_dp); 2654 2655 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format); 2656 if (is_mst) { 2657 /* 2658 * FIXME: If all the streams can't fit into the link with their 2659 * current pipe_bpp we should reduce pipe_bpp across the board 2660 * until things start to fit. Until then we limit to <= 8bpc 2661 * since that's what was hardcoded for all MST streams 2662 * previously. This hack should be removed once we have the 2663 * proper retry logic in place. 2664 */ 2665 limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24); 2666 } else { 2667 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state, 2668 respect_downstream_limits); 2669 } 2670 2671 if (!dsc && intel_dp_in_hdr_mode(conn_state)) { 2672 if (intel_dp_supports_dsc(intel_dp, connector, crtc_state) && 2673 limits->pipe.max_bpp >= 30) 2674 limits->pipe.min_bpp = max(limits->pipe.min_bpp, 30); 2675 else 2676 drm_dbg_kms(display->drm, 2677 "[CONNECTOR:%d:%s] Can't force 30 bpp for HDR (pipe bpp: %d-%d DSC-support: %s)\n", 2678 connector->base.base.id, connector->base.name, 2679 limits->pipe.min_bpp, limits->pipe.max_bpp, 2680 str_yes_no(intel_dp_supports_dsc(intel_dp, connector, 2681 crtc_state))); 2682 } 2683 2684 if (dsc && !intel_dp_dsc_compute_pipe_bpp_limits(connector, limits)) 2685 return false; 2686 2687 if (is_mst || intel_dp->use_max_params) { 2688 /* 2689 * For MST we always configure max link bw - the spec doesn't 2690 * seem to suggest we should do otherwise. 2691 * 2692 * Use the maximum clock and number of lanes the eDP panel 2693 * advertizes being capable of in case the initial fast 2694 * optimal params failed us. The panels are generally 2695 * designed to support only a single clock and lane 2696 * configuration, and typically on older panels these 2697 * values correspond to the native resolution of the panel. 2698 */ 2699 limits->min_lane_count = limits->max_lane_count; 2700 limits->min_rate = limits->max_rate; 2701 } 2702 2703 intel_dp_test_compute_config(intel_dp, crtc_state, limits); 2704 2705 return intel_dp_compute_config_link_bpp_limits(intel_dp, 2706 connector, 2707 crtc_state, 2708 dsc, 2709 limits); 2710} 2711 2712int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state) 2713{ 2714 const struct drm_display_mode *adjusted_mode = 2715 &crtc_state->hw.adjusted_mode; 2716 int bpp = crtc_state->dsc.compression_enable ? 2717 fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) : 2718 crtc_state->pipe_bpp; 2719 2720 return intel_dp_link_required(adjusted_mode->crtc_clock, bpp); 2721} 2722 2723bool intel_dp_joiner_needs_dsc(struct intel_display *display, 2724 int num_joined_pipes) 2725{ 2726 /* 2727 * Pipe joiner needs compression up to display 12 due to bandwidth 2728 * limitation. DG2 onwards pipe joiner can be enabled without 2729 * compression. 2730 * Ultrajoiner always needs compression. 2731 */ 2732 return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) || 2733 num_joined_pipes == 4; 2734} 2735 2736static int 2737intel_dp_compute_link_config(struct intel_encoder *encoder, 2738 struct intel_crtc_state *pipe_config, 2739 struct drm_connector_state *conn_state, 2740 bool respect_downstream_limits) 2741{ 2742 struct intel_display *display = to_intel_display(encoder); 2743 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2744 struct intel_connector *connector = 2745 to_intel_connector(conn_state->connector); 2746 const struct drm_display_mode *adjusted_mode = 2747 &pipe_config->hw.adjusted_mode; 2748 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2749 struct link_config_limits limits; 2750 bool dsc_needed, joiner_needs_dsc; 2751 int num_joined_pipes; 2752 int ret = 0; 2753 2754 if (pipe_config->fec_enable && 2755 !intel_dp_supports_fec(intel_dp, connector, pipe_config)) 2756 return -EINVAL; 2757 2758 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector, 2759 adjusted_mode->crtc_hdisplay, 2760 adjusted_mode->crtc_clock); 2761 if (num_joined_pipes > 1) 2762 pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe); 2763 2764 joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes); 2765 2766 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en || 2767 !intel_dp_compute_config_limits(intel_dp, conn_state, pipe_config, 2768 respect_downstream_limits, 2769 false, 2770 &limits); 2771 2772 if (!dsc_needed) { 2773 /* 2774 * Optimize for slow and wide for everything, because there are some 2775 * eDP 1.3 and 1.4 panels don't work well with fast and narrow. 2776 */ 2777 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, 2778 conn_state, &limits); 2779 if (!ret && intel_dp_is_uhbr(pipe_config)) 2780 ret = intel_dp_mtp_tu_compute_config(intel_dp, 2781 pipe_config, 2782 conn_state, 2783 fxp_q4_from_int(pipe_config->pipe_bpp), 2784 fxp_q4_from_int(pipe_config->pipe_bpp), 2785 0, false); 2786 if (ret) 2787 dsc_needed = true; 2788 } 2789 2790 if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) { 2791 drm_dbg_kms(display->drm, "DSC required but not available\n"); 2792 return -EINVAL; 2793 } 2794 2795 if (dsc_needed) { 2796 drm_dbg_kms(display->drm, 2797 "Try DSC (fallback=%s, joiner=%s, force=%s)\n", 2798 str_yes_no(ret), str_yes_no(joiner_needs_dsc), 2799 str_yes_no(intel_dp->force_dsc_en)); 2800 2801 if (!intel_dp_compute_config_limits(intel_dp, conn_state, pipe_config, 2802 respect_downstream_limits, 2803 true, 2804 &limits)) 2805 return -EINVAL; 2806 2807 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, 2808 conn_state, &limits, 64); 2809 if (ret < 0) 2810 return ret; 2811 } 2812 2813 drm_dbg_kms(display->drm, 2814 "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " HDR %s link rate required %d available %d\n", 2815 pipe_config->lane_count, pipe_config->port_clock, 2816 pipe_config->pipe_bpp, 2817 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16), 2818 str_yes_no(intel_dp_in_hdr_mode(conn_state)), 2819 intel_dp_config_required_rate(pipe_config), 2820 intel_dp_max_link_data_rate(intel_dp, 2821 pipe_config->port_clock, 2822 pipe_config->lane_count)); 2823 2824 return 0; 2825} 2826 2827bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 2828 const struct drm_connector_state *conn_state) 2829{ 2830 const struct intel_digital_connector_state *intel_conn_state = 2831 to_intel_digital_connector_state(conn_state); 2832 const struct drm_display_mode *adjusted_mode = 2833 &crtc_state->hw.adjusted_mode; 2834 2835 /* 2836 * Our YCbCr output is always limited range. 2837 * crtc_state->limited_color_range only applies to RGB, 2838 * and it must never be set for YCbCr or we risk setting 2839 * some conflicting bits in TRANSCONF which will mess up 2840 * the colors on the monitor. 2841 */ 2842 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2843 return false; 2844 2845 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2846 /* 2847 * See: 2848 * CEA-861-E - 5.1 Default Encoding Parameters 2849 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 2850 */ 2851 return crtc_state->pipe_bpp != 18 && 2852 drm_default_rgb_quant_range(adjusted_mode) == 2853 HDMI_QUANTIZATION_RANGE_LIMITED; 2854 } else { 2855 return intel_conn_state->broadcast_rgb == 2856 INTEL_BROADCAST_RGB_LIMITED; 2857 } 2858} 2859 2860static bool intel_dp_port_has_audio(struct intel_display *display, enum port port) 2861{ 2862 if (display->platform.g4x) 2863 return false; 2864 if (DISPLAY_VER(display) < 12 && port == PORT_A) 2865 return false; 2866 2867 return true; 2868} 2869 2870static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state, 2871 const struct drm_connector_state *conn_state, 2872 struct drm_dp_vsc_sdp *vsc) 2873{ 2874 struct intel_display *display = to_intel_display(crtc_state); 2875 2876 if (crtc_state->has_panel_replay) { 2877 /* 2878 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 2879 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel 2880 * Encoding/Colorimetry Format indication. 2881 */ 2882 vsc->revision = 0x7; 2883 } else { 2884 /* 2885 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 2886 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ 2887 * Colorimetry Format indication. 2888 */ 2889 vsc->revision = 0x5; 2890 } 2891 2892 vsc->length = 0x13; 2893 2894 /* DP 1.4a spec, Table 2-120 */ 2895 switch (crtc_state->output_format) { 2896 case INTEL_OUTPUT_FORMAT_YCBCR444: 2897 vsc->pixelformat = DP_PIXELFORMAT_YUV444; 2898 break; 2899 case INTEL_OUTPUT_FORMAT_YCBCR420: 2900 vsc->pixelformat = DP_PIXELFORMAT_YUV420; 2901 break; 2902 case INTEL_OUTPUT_FORMAT_RGB: 2903 default: 2904 vsc->pixelformat = DP_PIXELFORMAT_RGB; 2905 } 2906 2907 switch (conn_state->colorspace) { 2908 case DRM_MODE_COLORIMETRY_BT709_YCC: 2909 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2910 break; 2911 case DRM_MODE_COLORIMETRY_XVYCC_601: 2912 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; 2913 break; 2914 case DRM_MODE_COLORIMETRY_XVYCC_709: 2915 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; 2916 break; 2917 case DRM_MODE_COLORIMETRY_SYCC_601: 2918 vsc->colorimetry = DP_COLORIMETRY_SYCC_601; 2919 break; 2920 case DRM_MODE_COLORIMETRY_OPYCC_601: 2921 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; 2922 break; 2923 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 2924 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; 2925 break; 2926 case DRM_MODE_COLORIMETRY_BT2020_RGB: 2927 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; 2928 break; 2929 case DRM_MODE_COLORIMETRY_BT2020_YCC: 2930 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; 2931 break; 2932 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 2933 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 2934 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; 2935 break; 2936 default: 2937 /* 2938 * RGB->YCBCR color conversion uses the BT.709 2939 * color space. 2940 */ 2941 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2942 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 2943 else 2944 vsc->colorimetry = DP_COLORIMETRY_DEFAULT; 2945 break; 2946 } 2947 2948 vsc->bpc = crtc_state->pipe_bpp / 3; 2949 2950 /* only RGB pixelformat supports 6 bpc */ 2951 drm_WARN_ON(display->drm, 2952 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); 2953 2954 /* all YCbCr are always limited range */ 2955 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; 2956 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; 2957} 2958 2959static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, 2960 struct intel_crtc_state *crtc_state) 2961{ 2962 struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp; 2963 const struct drm_display_mode *adjusted_mode = 2964 &crtc_state->hw.adjusted_mode; 2965 2966 if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported) 2967 return; 2968 2969 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); 2970 2971 as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; 2972 as_sdp->length = 0x9; 2973 as_sdp->duration_incr_ms = 0; 2974 as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state); 2975 2976 if (crtc_state->cmrr.enable) { 2977 as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED; 2978 as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode); 2979 as_sdp->target_rr_divider = true; 2980 } else { 2981 as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL; 2982 as_sdp->target_rr = 0; 2983 } 2984} 2985 2986static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, 2987 struct intel_crtc_state *crtc_state, 2988 const struct drm_connector_state *conn_state) 2989{ 2990 struct drm_dp_vsc_sdp *vsc; 2991 2992 if ((!intel_dp->colorimetry_support || 2993 !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) && 2994 !crtc_state->has_psr) 2995 return; 2996 2997 vsc = &crtc_state->infoframes.vsc; 2998 2999 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 3000 vsc->sdp_type = DP_SDP_VSC; 3001 3002 /* Needs colorimetry */ 3003 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { 3004 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, 3005 vsc); 3006 } else if (crtc_state->has_panel_replay) { 3007 /* 3008 * [Panel Replay without colorimetry info] 3009 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 3010 * VSC SDP supporting 3D stereo + Panel Replay. 3011 */ 3012 vsc->revision = 0x6; 3013 vsc->length = 0x10; 3014 } else if (crtc_state->has_sel_update) { 3015 /* 3016 * [PSR2 without colorimetry] 3017 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 3018 * 3D stereo + PSR/PSR2 + Y-coordinate. 3019 */ 3020 vsc->revision = 0x4; 3021 vsc->length = 0xe; 3022 } else { 3023 /* 3024 * [PSR1] 3025 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 3026 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or 3027 * higher). 3028 */ 3029 vsc->revision = 0x2; 3030 vsc->length = 0x8; 3031 } 3032} 3033 3034bool 3035intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state) 3036{ 3037 struct hdr_output_metadata *hdr_metadata; 3038 3039 if (!conn_state->hdr_output_metadata) 3040 return false; 3041 3042 hdr_metadata = conn_state->hdr_output_metadata->data; 3043 3044 return hdr_metadata->hdmi_metadata_type1.eotf == HDMI_EOTF_SMPTE_ST2084; 3045} 3046 3047static void 3048intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, 3049 struct intel_crtc_state *crtc_state, 3050 const struct drm_connector_state *conn_state) 3051{ 3052 struct intel_display *display = to_intel_display(intel_dp); 3053 int ret; 3054 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; 3055 3056 if (!conn_state->hdr_output_metadata) 3057 return; 3058 3059 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state); 3060 3061 if (ret) { 3062 drm_dbg_kms(display->drm, 3063 "couldn't set HDR metadata in infoframe\n"); 3064 return; 3065 } 3066 3067 crtc_state->infoframes.enable |= 3068 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); 3069} 3070 3071static bool can_enable_drrs(struct intel_connector *connector, 3072 const struct intel_crtc_state *pipe_config, 3073 const struct drm_display_mode *downclock_mode) 3074{ 3075 struct intel_display *display = to_intel_display(connector); 3076 3077 if (pipe_config->vrr.enable) 3078 return false; 3079 3080 /* 3081 * DRRS and PSR can't be enable together, so giving preference to PSR 3082 * as it allows more power-savings by complete shutting down display, 3083 * so to guarantee this, intel_drrs_compute_config() must be called 3084 * after intel_psr_compute_config(). 3085 */ 3086 if (pipe_config->has_psr) 3087 return false; 3088 3089 /* FIXME missing FDI M2/N2 etc. */ 3090 if (pipe_config->has_pch_encoder) 3091 return false; 3092 3093 if (!intel_cpu_transcoder_has_drrs(display, pipe_config->cpu_transcoder)) 3094 return false; 3095 3096 return downclock_mode && 3097 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 3098} 3099 3100static void 3101intel_dp_drrs_compute_config(struct intel_connector *connector, 3102 struct intel_crtc_state *pipe_config, 3103 int link_bpp_x16) 3104{ 3105 struct intel_display *display = to_intel_display(connector); 3106 const struct drm_display_mode *downclock_mode = 3107 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); 3108 int pixel_clock; 3109 3110 /* 3111 * FIXME all joined pipes share the same transcoder. 3112 * Need to account for that when updating M/N live. 3113 */ 3114 if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes) 3115 pipe_config->update_m_n = true; 3116 3117 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { 3118 if (intel_cpu_transcoder_has_m2_n2(display, pipe_config->cpu_transcoder)) 3119 intel_zero_m_n(&pipe_config->dp_m2_n2); 3120 return; 3121 } 3122 3123 if (display->platform.ironlake || display->platform.sandybridge || 3124 display->platform.ivybridge) 3125 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay; 3126 3127 pipe_config->has_drrs = true; 3128 3129 pixel_clock = downclock_mode->clock; 3130 if (pipe_config->splitter.enable) 3131 pixel_clock /= pipe_config->splitter.link_count; 3132 3133 intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock, 3134 pipe_config->port_clock, 3135 intel_dp_bw_fec_overhead(pipe_config->fec_enable), 3136 &pipe_config->dp_m2_n2); 3137 3138 /* FIXME: abstract this better */ 3139 if (pipe_config->splitter.enable) 3140 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 3141} 3142 3143static bool intel_dp_has_audio(struct intel_encoder *encoder, 3144 const struct drm_connector_state *conn_state) 3145{ 3146 struct intel_display *display = to_intel_display(encoder); 3147 const struct intel_digital_connector_state *intel_conn_state = 3148 to_intel_digital_connector_state(conn_state); 3149 struct intel_connector *connector = 3150 to_intel_connector(conn_state->connector); 3151 3152 if (!intel_dp_port_has_audio(display, encoder->port)) 3153 return false; 3154 3155 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 3156 return connector->base.display_info.has_audio; 3157 else 3158 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 3159} 3160 3161static int 3162intel_dp_compute_output_format(struct intel_encoder *encoder, 3163 struct intel_crtc_state *crtc_state, 3164 struct drm_connector_state *conn_state, 3165 bool respect_downstream_limits) 3166{ 3167 struct intel_display *display = to_intel_display(encoder); 3168 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3169 struct intel_connector *connector = intel_dp->attached_connector; 3170 const struct drm_display_info *info = &connector->base.display_info; 3171 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3172 bool ycbcr_420_only; 3173 int ret; 3174 3175 ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 3176 3177 if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) { 3178 drm_dbg_kms(display->drm, 3179 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 3180 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 3181 } else { 3182 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode); 3183 } 3184 3185 crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format); 3186 3187 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, 3188 respect_downstream_limits); 3189 if (ret) { 3190 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3191 !connector->base.ycbcr_420_allowed || 3192 !drm_mode_is_420_also(info, adjusted_mode)) 3193 return ret; 3194 3195 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 3196 crtc_state->output_format = intel_dp_output_format(connector, 3197 crtc_state->sink_format); 3198 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, 3199 respect_downstream_limits); 3200 } 3201 3202 return ret; 3203} 3204 3205void 3206intel_dp_audio_compute_config(struct intel_encoder *encoder, 3207 struct intel_crtc_state *pipe_config, 3208 struct drm_connector_state *conn_state) 3209{ 3210 pipe_config->has_audio = 3211 intel_dp_has_audio(encoder, conn_state) && 3212 intel_audio_compute_config(encoder, pipe_config, conn_state); 3213 3214 pipe_config->sdp_split_enable = pipe_config->has_audio && 3215 intel_dp_is_uhbr(pipe_config); 3216} 3217 3218void 3219intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, 3220 struct intel_encoder *encoder, 3221 const struct intel_crtc_state *crtc_state) 3222{ 3223 struct intel_connector *connector; 3224 struct intel_digital_connector_state *conn_state; 3225 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3226 int i; 3227 3228 if (intel_dp->needs_modeset_retry) 3229 return; 3230 3231 intel_dp->needs_modeset_retry = true; 3232 3233 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3234 intel_connector_queue_modeset_retry_work(intel_dp->attached_connector); 3235 3236 return; 3237 } 3238 3239 for_each_new_intel_connector_in_state(state, connector, conn_state, i) { 3240 if (!conn_state->base.crtc) 3241 continue; 3242 3243 if (connector->mst.dp == intel_dp) 3244 intel_connector_queue_modeset_retry_work(connector); 3245 } 3246} 3247 3248int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state, 3249 const struct drm_connector_state *conn_state) 3250{ 3251 struct intel_display *display = to_intel_display(crtc_state); 3252 const struct drm_display_mode *adjusted_mode = 3253 &crtc_state->hw.adjusted_mode; 3254 struct intel_connector *connector = to_intel_connector(conn_state->connector); 3255 int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8; 3256 /* 3257 * min symbol cycles is 3(BS,VBID, BE) for 128b/132b and 3258 * 5(BS, VBID, MVID, MAUD, BE) for 8b/10b 3259 */ 3260 int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5; 3261 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3262 int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state); 3263 int min_hblank; 3264 int max_lane_count = 4; 3265 int hactive_sym_cycles, htotal_sym_cycles; 3266 int dsc_slices = 0; 3267 int link_bpp_x16; 3268 3269 if (DISPLAY_VER(display) < 30) 3270 return 0; 3271 3272 /* MIN_HBLANK should be set only for 8b/10b MST or for 128b/132b SST/MST */ 3273 if (!is_mst && !intel_dp_is_uhbr(crtc_state)) 3274 return 0; 3275 3276 if (crtc_state->dsc.compression_enable) { 3277 dsc_slices = intel_dp_dsc_get_slice_count(connector, 3278 adjusted_mode->crtc_clock, 3279 adjusted_mode->crtc_hdisplay, 3280 num_joined_pipes); 3281 if (!dsc_slices) { 3282 drm_dbg(display->drm, "failed to calculate dsc slice count\n"); 3283 return -EINVAL; 3284 } 3285 } 3286 3287 if (crtc_state->dsc.compression_enable) 3288 link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16; 3289 else 3290 link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format, 3291 crtc_state->pipe_bpp)); 3292 3293 /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */ 3294 hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count, 3295 adjusted_mode->hdisplay, 3296 dsc_slices, 3297 link_bpp_x16, 3298 symbol_size, is_mst); 3299 htotal_sym_cycles = adjusted_mode->htotal * hactive_sym_cycles / 3300 adjusted_mode->hdisplay; 3301 3302 min_hblank = htotal_sym_cycles - hactive_sym_cycles; 3303 /* minimum Hblank calculation: https://groups.vesa.org/wg/DP/document/20494 */ 3304 min_hblank = max(min_hblank, min_sym_cycles); 3305 3306 /* 3307 * adjust the BlankingStart/BlankingEnd framing control from 3308 * the calculated value 3309 */ 3310 min_hblank = min_hblank - 2; 3311 3312 /* 3313 * min_hblank formula is undergoing a change, to avoid underrun use the 3314 * recomended value in spec to compare with the calculated one and use the 3315 * minimum value 3316 */ 3317 if (intel_dp_is_uhbr(crtc_state)) { 3318 /* 3319 * Note: Bspec requires a min_hblank of 2 for YCBCR420 3320 * with compressed bpp 6, but the minimum compressed bpp 3321 * supported by the driver is 8. 3322 */ 3323 drm_WARN_ON(display->drm, 3324 (crtc_state->dsc.compression_enable && 3325 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 3326 crtc_state->dsc.compressed_bpp_x16 < fxp_q4_from_int(8))); 3327 min_hblank = min(3, min_hblank); 3328 } else { 3329 min_hblank = min(10, min_hblank); 3330 } 3331 3332 crtc_state->min_hblank = min_hblank; 3333 3334 return 0; 3335} 3336 3337int 3338intel_dp_compute_config(struct intel_encoder *encoder, 3339 struct intel_crtc_state *pipe_config, 3340 struct drm_connector_state *conn_state) 3341{ 3342 struct intel_display *display = to_intel_display(encoder); 3343 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); 3344 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 3345 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3346 const struct drm_display_mode *fixed_mode; 3347 struct intel_connector *connector = intel_dp->attached_connector; 3348 int ret = 0, link_bpp_x16; 3349 3350 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode); 3351 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 3352 ret = intel_panel_compute_config(connector, adjusted_mode); 3353 if (ret) 3354 return ret; 3355 } 3356 3357 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 3358 return -EINVAL; 3359 3360 if (!connector->base.interlace_allowed && 3361 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 3362 return -EINVAL; 3363 3364 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 3365 return -EINVAL; 3366 3367 if (intel_dp_hdisplay_bad(display, adjusted_mode->crtc_hdisplay)) 3368 return -EINVAL; 3369 3370 /* 3371 * Try to respect downstream TMDS clock limits first, if 3372 * that fails assume the user might know something we don't. 3373 */ 3374 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true); 3375 if (ret) 3376 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false); 3377 if (ret) 3378 return ret; 3379 3380 if ((intel_dp_is_edp(intel_dp) && fixed_mode) || 3381 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3382 ret = intel_pfit_compute_config(pipe_config, conn_state); 3383 if (ret) 3384 return ret; 3385 } 3386 3387 pipe_config->limited_color_range = 3388 intel_dp_limited_color_range(pipe_config, conn_state); 3389 3390 if (intel_dp_is_uhbr(pipe_config)) { 3391 /* 128b/132b SST also needs this */ 3392 pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder; 3393 } else { 3394 pipe_config->enhanced_framing = 3395 drm_dp_enhanced_frame_cap(intel_dp->dpcd); 3396 } 3397 3398 if (pipe_config->dsc.compression_enable) 3399 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16; 3400 else 3401 link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format, 3402 pipe_config->pipe_bpp)); 3403 3404 if (intel_dp->mso_link_count) { 3405 int n = intel_dp->mso_link_count; 3406 int overlap = intel_dp->mso_pixel_overlap; 3407 3408 pipe_config->splitter.enable = true; 3409 pipe_config->splitter.link_count = n; 3410 pipe_config->splitter.pixel_overlap = overlap; 3411 3412 drm_dbg_kms(display->drm, 3413 "MSO link count %d, pixel overlap %d\n", 3414 n, overlap); 3415 3416 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap; 3417 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap; 3418 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap; 3419 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap; 3420 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap; 3421 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap; 3422 adjusted_mode->crtc_clock /= n; 3423 } 3424 3425 intel_dp_audio_compute_config(encoder, pipe_config, conn_state); 3426 3427 if (!intel_dp_is_uhbr(pipe_config)) { 3428 intel_link_compute_m_n(link_bpp_x16, 3429 pipe_config->lane_count, 3430 adjusted_mode->crtc_clock, 3431 pipe_config->port_clock, 3432 intel_dp_bw_fec_overhead(pipe_config->fec_enable), 3433 &pipe_config->dp_m_n); 3434 } 3435 3436 ret = intel_dp_compute_min_hblank(pipe_config, conn_state); 3437 if (ret) 3438 return ret; 3439 3440 /* FIXME: abstract this better */ 3441 if (pipe_config->splitter.enable) 3442 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count; 3443 3444 intel_vrr_compute_config(pipe_config, conn_state); 3445 intel_dp_compute_as_sdp(intel_dp, pipe_config); 3446 intel_psr_compute_config(intel_dp, pipe_config, conn_state); 3447 intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state); 3448 intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); 3449 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); 3450 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); 3451 3452 return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector, 3453 pipe_config); 3454} 3455 3456void intel_dp_set_link_params(struct intel_dp *intel_dp, 3457 int link_rate, int lane_count) 3458{ 3459 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 3460 intel_dp->link.active = false; 3461 intel_dp->needs_modeset_retry = false; 3462 intel_dp->link_rate = link_rate; 3463 intel_dp->lane_count = lane_count; 3464} 3465 3466void intel_dp_reset_link_params(struct intel_dp *intel_dp) 3467{ 3468 intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); 3469 intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); 3470 intel_dp->link.mst_probed_lane_count = 0; 3471 intel_dp->link.mst_probed_rate = 0; 3472 intel_dp->link.retrain_disabled = false; 3473 intel_dp->link.seq_train_failures = 0; 3474} 3475 3476/* Enable backlight PWM and backlight PP control. */ 3477void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 3478 const struct drm_connector_state *conn_state) 3479{ 3480 struct intel_display *display = to_intel_display(crtc_state); 3481 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); 3482 3483 if (!intel_dp_is_edp(intel_dp)) 3484 return; 3485 3486 drm_dbg_kms(display->drm, "\n"); 3487 3488 intel_backlight_enable(crtc_state, conn_state); 3489 intel_pps_backlight_on(intel_dp); 3490} 3491 3492/* Disable backlight PP control and backlight PWM. */ 3493void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) 3494{ 3495 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); 3496 struct intel_display *display = to_intel_display(intel_dp); 3497 3498 if (!intel_dp_is_edp(intel_dp)) 3499 return; 3500 3501 drm_dbg_kms(display->drm, "\n"); 3502 3503 intel_pps_backlight_off(intel_dp); 3504 intel_backlight_disable(old_conn_state); 3505} 3506 3507static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) 3508{ 3509 /* 3510 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus 3511 * be capable of signalling downstream hpd with a long pulse. 3512 * Whether or not that means D3 is safe to use is not clear, 3513 * but let's assume so until proven otherwise. 3514 * 3515 * FIXME should really check all downstream ports... 3516 */ 3517 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && 3518 drm_dp_is_branch(intel_dp->dpcd) && 3519 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; 3520} 3521 3522static int 3523write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set) 3524{ 3525 int err; 3526 u8 val; 3527 3528 err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val); 3529 if (err < 0) 3530 return err; 3531 3532 if (set) 3533 val |= flag; 3534 else 3535 val &= ~flag; 3536 3537 return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val); 3538} 3539 3540static void 3541intel_dp_sink_set_dsc_decompression(struct intel_connector *connector, 3542 bool enable) 3543{ 3544 struct intel_display *display = to_intel_display(connector); 3545 3546 if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux, 3547 DP_DECOMPRESSION_EN, enable) < 0) 3548 drm_dbg_kms(display->drm, 3549 "Failed to %s sink decompression state\n", 3550 str_enable_disable(enable)); 3551} 3552 3553static void 3554intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector, 3555 bool enable) 3556{ 3557 struct intel_display *display = to_intel_display(connector); 3558 struct drm_dp_aux *aux = connector->mst.port ? 3559 connector->mst.port->passthrough_aux : NULL; 3560 3561 if (!aux) 3562 return; 3563 3564 if (write_dsc_decompression_flag(aux, 3565 DP_DSC_PASSTHROUGH_EN, enable) < 0) 3566 drm_dbg_kms(display->drm, 3567 "Failed to %s sink compression passthrough state\n", 3568 str_enable_disable(enable)); 3569} 3570 3571static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state, 3572 const struct intel_connector *connector, 3573 bool for_get_ref) 3574{ 3575 struct intel_display *display = to_intel_display(state); 3576 struct drm_connector *_connector_iter; 3577 struct drm_connector_state *old_conn_state; 3578 struct drm_connector_state *new_conn_state; 3579 int ref_count = 0; 3580 int i; 3581 3582 /* 3583 * On SST the decompression AUX device won't be shared, each connector 3584 * uses for this its own AUX targeting the sink device. 3585 */ 3586 if (!connector->mst.dp) 3587 return connector->dp.dsc_decompression_enabled ? 1 : 0; 3588 3589 for_each_oldnew_connector_in_state(&state->base, _connector_iter, 3590 old_conn_state, new_conn_state, i) { 3591 const struct intel_connector * 3592 connector_iter = to_intel_connector(_connector_iter); 3593 3594 if (connector_iter->mst.dp != connector->mst.dp) 3595 continue; 3596 3597 if (!connector_iter->dp.dsc_decompression_enabled) 3598 continue; 3599 3600 drm_WARN_ON(display->drm, 3601 (for_get_ref && !new_conn_state->crtc) || 3602 (!for_get_ref && !old_conn_state->crtc)); 3603 3604 if (connector_iter->dp.dsc_decompression_aux == 3605 connector->dp.dsc_decompression_aux) 3606 ref_count++; 3607 } 3608 3609 return ref_count; 3610} 3611 3612static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state, 3613 struct intel_connector *connector) 3614{ 3615 bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0; 3616 3617 connector->dp.dsc_decompression_enabled = true; 3618 3619 return ret; 3620} 3621 3622static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state, 3623 struct intel_connector *connector) 3624{ 3625 connector->dp.dsc_decompression_enabled = false; 3626 3627 return intel_dp_dsc_aux_ref_count(state, connector, false) == 0; 3628} 3629 3630/** 3631 * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device 3632 * @state: atomic state 3633 * @connector: connector to enable the decompression for 3634 * @new_crtc_state: new state for the CRTC driving @connector 3635 * 3636 * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD 3637 * register of the appropriate sink/branch device. On SST this is always the 3638 * sink device, whereas on MST based on each device's DSC capabilities it's 3639 * either the last branch device (enabling decompression in it) or both the 3640 * last branch device (enabling passthrough in it) and the sink device 3641 * (enabling decompression in it). 3642 */ 3643void intel_dp_sink_enable_decompression(struct intel_atomic_state *state, 3644 struct intel_connector *connector, 3645 const struct intel_crtc_state *new_crtc_state) 3646{ 3647 struct intel_display *display = to_intel_display(state); 3648 3649 if (!new_crtc_state->dsc.compression_enable) 3650 return; 3651 3652 if (drm_WARN_ON(display->drm, 3653 !connector->dp.dsc_decompression_aux || 3654 connector->dp.dsc_decompression_enabled)) 3655 return; 3656 3657 if (!intel_dp_dsc_aux_get_ref(state, connector)) 3658 return; 3659 3660 intel_dp_sink_set_dsc_passthrough(connector, true); 3661 intel_dp_sink_set_dsc_decompression(connector, true); 3662} 3663 3664/** 3665 * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device 3666 * @state: atomic state 3667 * @connector: connector to disable the decompression for 3668 * @old_crtc_state: old state for the CRTC driving @connector 3669 * 3670 * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD 3671 * register of the appropriate sink/branch device, corresponding to the 3672 * sequence in intel_dp_sink_enable_decompression(). 3673 */ 3674void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, 3675 struct intel_connector *connector, 3676 const struct intel_crtc_state *old_crtc_state) 3677{ 3678 struct intel_display *display = to_intel_display(state); 3679 3680 if (!old_crtc_state->dsc.compression_enable) 3681 return; 3682 3683 if (drm_WARN_ON(display->drm, 3684 !connector->dp.dsc_decompression_aux || 3685 !connector->dp.dsc_decompression_enabled)) 3686 return; 3687 3688 if (!intel_dp_dsc_aux_put_ref(state, connector)) 3689 return; 3690 3691 intel_dp_sink_set_dsc_decompression(connector, false); 3692 intel_dp_sink_set_dsc_passthrough(connector, false); 3693} 3694 3695static void 3696intel_dp_init_source_oui(struct intel_dp *intel_dp) 3697{ 3698 struct intel_display *display = to_intel_display(intel_dp); 3699 u8 oui[] = { 0x00, 0xaa, 0x01 }; 3700 u8 buf[3] = {}; 3701 3702 if (READ_ONCE(intel_dp->oui_valid)) 3703 return; 3704 3705 WRITE_ONCE(intel_dp->oui_valid, true); 3706 3707 /* 3708 * During driver init, we want to be careful and avoid changing the source OUI if it's 3709 * already set to what we want, so as to avoid clearing any state by accident 3710 */ 3711 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) 3712 drm_dbg_kms(display->drm, "Failed to read source OUI\n"); 3713 3714 if (memcmp(oui, buf, sizeof(oui)) == 0) { 3715 /* Assume the OUI was written now. */ 3716 intel_dp->last_oui_write = jiffies; 3717 return; 3718 } 3719 3720 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) { 3721 drm_dbg_kms(display->drm, "Failed to write source OUI\n"); 3722 WRITE_ONCE(intel_dp->oui_valid, false); 3723 } 3724 3725 intel_dp->last_oui_write = jiffies; 3726} 3727 3728void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp) 3729{ 3730 WRITE_ONCE(intel_dp->oui_valid, false); 3731} 3732 3733void intel_dp_wait_source_oui(struct intel_dp *intel_dp) 3734{ 3735 struct intel_display *display = to_intel_display(intel_dp); 3736 struct intel_connector *connector = intel_dp->attached_connector; 3737 3738 drm_dbg_kms(display->drm, 3739 "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n", 3740 connector->base.base.id, connector->base.name, 3741 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 3742 3743 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 3744 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout); 3745} 3746 3747/* If the device supports it, try to set the power state appropriately */ 3748void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) 3749{ 3750 struct intel_display *display = to_intel_display(intel_dp); 3751 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3752 int ret, i; 3753 3754 /* Should have a valid DPCD by this point */ 3755 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 3756 return; 3757 3758 if (mode != DP_SET_POWER_D0) { 3759 if (downstream_hpd_needs_d0(intel_dp)) 3760 return; 3761 3762 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3763 } else { 3764 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3765 3766 intel_lspcon_resume(dig_port); 3767 3768 /* Write the source OUI as early as possible */ 3769 intel_dp_init_source_oui(intel_dp); 3770 3771 /* 3772 * When turning on, we need to retry for 1ms to give the sink 3773 * time to wake up. 3774 */ 3775 for (i = 0; i < 3; i++) { 3776 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 3777 if (ret == 1) 3778 break; 3779 msleep(1); 3780 } 3781 3782 if (ret == 1 && intel_lspcon_active(dig_port)) 3783 intel_lspcon_wait_pcon_mode(dig_port); 3784 } 3785 3786 if (ret != 1) 3787 drm_dbg_kms(display->drm, 3788 "[ENCODER:%d:%s] Set power to %s failed\n", 3789 encoder->base.base.id, encoder->base.name, 3790 mode == DP_SET_POWER_D0 ? "D0" : "D3"); 3791} 3792 3793static bool 3794intel_dp_get_dpcd(struct intel_dp *intel_dp); 3795 3796/** 3797 * intel_dp_sync_state - sync the encoder state during init/resume 3798 * @encoder: intel encoder to sync 3799 * @crtc_state: state for the CRTC connected to the encoder 3800 * 3801 * Sync any state stored in the encoder wrt. HW state during driver init 3802 * and system resume. 3803 */ 3804void intel_dp_sync_state(struct intel_encoder *encoder, 3805 const struct intel_crtc_state *crtc_state) 3806{ 3807 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3808 bool dpcd_updated = false; 3809 3810 /* 3811 * Don't clobber DPCD if it's been already read out during output 3812 * setup (eDP) or detect. 3813 */ 3814 if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) { 3815 intel_dp_get_dpcd(intel_dp); 3816 dpcd_updated = true; 3817 } 3818 3819 intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); 3820 3821 if (crtc_state) { 3822 intel_dp_reset_link_params(intel_dp); 3823 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count); 3824 intel_dp->link.active = true; 3825 } 3826} 3827 3828bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, 3829 struct intel_crtc_state *crtc_state) 3830{ 3831 struct intel_display *display = to_intel_display(encoder); 3832 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3833 bool fastset = true; 3834 3835 /* 3836 * If BIOS has set an unsupported or non-standard link rate for some 3837 * reason force an encoder recompute and full modeset. 3838 */ 3839 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates, 3840 crtc_state->port_clock) < 0) { 3841 drm_dbg_kms(display->drm, 3842 "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n", 3843 encoder->base.base.id, encoder->base.name); 3844 crtc_state->uapi.connectors_changed = true; 3845 fastset = false; 3846 } 3847 3848 /* 3849 * FIXME hack to force full modeset when DSC is being used. 3850 * 3851 * As long as we do not have full state readout and config comparison 3852 * of crtc_state->dsc, we have no way to ensure reliable fastset. 3853 * Remove once we have readout for DSC. 3854 */ 3855 if (crtc_state->dsc.compression_enable) { 3856 drm_dbg_kms(display->drm, 3857 "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n", 3858 encoder->base.base.id, encoder->base.name); 3859 crtc_state->uapi.mode_changed = true; 3860 fastset = false; 3861 } 3862 3863 if (CAN_PANEL_REPLAY(intel_dp)) { 3864 drm_dbg_kms(display->drm, 3865 "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n", 3866 encoder->base.base.id, encoder->base.name); 3867 crtc_state->uapi.mode_changed = true; 3868 fastset = false; 3869 } 3870 3871 return fastset; 3872} 3873 3874static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) 3875{ 3876 struct intel_display *display = to_intel_display(intel_dp); 3877 3878 /* Clear the cached register set to avoid using stale values */ 3879 3880 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); 3881 3882 if (!drm_dp_is_branch(intel_dp->dpcd)) 3883 return; 3884 3885 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, 3886 intel_dp->pcon_dsc_dpcd, 3887 sizeof(intel_dp->pcon_dsc_dpcd)) < 0) 3888 drm_err(display->drm, "Failed to read DPCD register 0x%x\n", 3889 DP_PCON_DSC_ENCODER); 3890 3891 drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n", 3892 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd); 3893} 3894 3895static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) 3896{ 3897 static const int bw_gbps[] = {9, 18, 24, 32, 40, 48}; 3898 int i; 3899 3900 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) { 3901 if (frl_bw_mask & (1 << i)) 3902 return bw_gbps[i]; 3903 } 3904 return 0; 3905} 3906 3907static int intel_dp_pcon_set_frl_mask(int max_frl) 3908{ 3909 switch (max_frl) { 3910 case 48: 3911 return DP_PCON_FRL_BW_MASK_48GBPS; 3912 case 40: 3913 return DP_PCON_FRL_BW_MASK_40GBPS; 3914 case 32: 3915 return DP_PCON_FRL_BW_MASK_32GBPS; 3916 case 24: 3917 return DP_PCON_FRL_BW_MASK_24GBPS; 3918 case 18: 3919 return DP_PCON_FRL_BW_MASK_18GBPS; 3920 case 9: 3921 return DP_PCON_FRL_BW_MASK_9GBPS; 3922 } 3923 3924 return 0; 3925} 3926 3927static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) 3928{ 3929 struct intel_connector *connector = intel_dp->attached_connector; 3930 const struct drm_display_info *info = &connector->base.display_info; 3931 int max_frl_rate; 3932 int max_lanes, rate_per_lane; 3933 int max_dsc_lanes, dsc_rate_per_lane; 3934 3935 max_lanes = info->hdmi.max_lanes; 3936 rate_per_lane = info->hdmi.max_frl_rate_per_lane; 3937 max_frl_rate = max_lanes * rate_per_lane; 3938 3939 if (info->hdmi.dsc_cap.v_1p2) { 3940 max_dsc_lanes = info->hdmi.dsc_cap.max_lanes; 3941 dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane; 3942 if (max_dsc_lanes && dsc_rate_per_lane) 3943 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane); 3944 } 3945 3946 return max_frl_rate; 3947} 3948 3949static bool 3950intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp, 3951 u8 max_frl_bw_mask, u8 *frl_trained_mask) 3952{ 3953 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) && 3954 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL && 3955 *frl_trained_mask >= max_frl_bw_mask) 3956 return true; 3957 3958 return false; 3959} 3960 3961static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) 3962{ 3963 struct intel_display *display = to_intel_display(intel_dp); 3964#define TIMEOUT_FRL_READY_MS 500 3965#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 3966 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret; 3967 u8 max_frl_bw_mask = 0, frl_trained_mask; 3968 bool is_active; 3969 3970 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 3971 drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw); 3972 3973 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp); 3974 drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n", 3975 max_edid_frl_bw); 3976 3977 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw); 3978 3979 if (max_frl_bw <= 0) 3980 return -EINVAL; 3981 3982 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); 3983 drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask); 3984 3985 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask)) 3986 goto frl_trained; 3987 3988 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false); 3989 if (ret < 0) 3990 return ret; 3991 /* Wait for PCON to be FRL Ready */ 3992 ret = poll_timeout_us(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux), 3993 is_active, 3994 1000, TIMEOUT_FRL_READY_MS * 1000, false); 3995 if (ret) 3996 return ret; 3997 3998 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, 3999 DP_PCON_ENABLE_SEQUENTIAL_LINK); 4000 if (ret < 0) 4001 return ret; 4002 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, 4003 DP_PCON_FRL_LINK_TRAIN_NORMAL); 4004 if (ret < 0) 4005 return ret; 4006 ret = drm_dp_pcon_frl_enable(&intel_dp->aux); 4007 if (ret < 0) 4008 return ret; 4009 /* 4010 * Wait for FRL to be completed 4011 * Check if the HDMI Link is up and active. 4012 */ 4013 ret = poll_timeout_us(is_active = intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask), 4014 is_active, 4015 1000, TIMEOUT_HDMI_LINK_ACTIVE_MS * 1000, false); 4016 if (ret) 4017 return ret; 4018 4019frl_trained: 4020 drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask); 4021 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask); 4022 intel_dp->frl.is_trained = true; 4023 drm_dbg(display->drm, "FRL trained with : %d Gbps\n", 4024 intel_dp->frl.trained_rate_gbps); 4025 4026 return 0; 4027} 4028 4029static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp) 4030{ 4031 if (drm_dp_is_branch(intel_dp->dpcd) && 4032 intel_dp_has_hdmi_sink(intel_dp) && 4033 intel_dp_hdmi_sink_max_frl(intel_dp) > 0) 4034 return true; 4035 4036 return false; 4037} 4038 4039static 4040int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp) 4041{ 4042 int ret; 4043 u8 buf = 0; 4044 4045 /* Set PCON source control mode */ 4046 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE; 4047 4048 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 4049 if (ret < 0) 4050 return ret; 4051 4052 /* Set HDMI LINK ENABLE */ 4053 buf |= DP_PCON_ENABLE_HDMI_LINK; 4054 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 4055 if (ret < 0) 4056 return ret; 4057 4058 return 0; 4059} 4060 4061void intel_dp_check_frl_training(struct intel_dp *intel_dp) 4062{ 4063 struct intel_display *display = to_intel_display(intel_dp); 4064 4065 /* 4066 * Always go for FRL training if: 4067 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7) 4068 * -sink is HDMI2.1 4069 */ 4070 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) || 4071 !intel_dp_is_hdmi_2_1_sink(intel_dp) || 4072 intel_dp->frl.is_trained) 4073 return; 4074 4075 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) { 4076 int ret, mode; 4077 4078 drm_dbg(display->drm, 4079 "Couldn't set FRL mode, continuing with TMDS mode\n"); 4080 ret = intel_dp_pcon_set_tmds_mode(intel_dp); 4081 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL); 4082 4083 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS) 4084 drm_dbg(display->drm, 4085 "Issue with PCON, cannot set TMDS mode\n"); 4086 } else { 4087 drm_dbg(display->drm, "FRL training Completed\n"); 4088 } 4089} 4090 4091static int 4092intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state) 4093{ 4094 int vactive = crtc_state->hw.adjusted_mode.vdisplay; 4095 4096 return intel_hdmi_dsc_get_slice_height(vactive); 4097} 4098 4099static int 4100intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp, 4101 const struct intel_crtc_state *crtc_state) 4102{ 4103 struct intel_connector *connector = intel_dp->attached_connector; 4104 const struct drm_display_info *info = &connector->base.display_info; 4105 int hdmi_throughput = info->hdmi.dsc_cap.clk_per_slice; 4106 int hdmi_max_slices = info->hdmi.dsc_cap.max_slices; 4107 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd); 4108 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd); 4109 4110 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices, 4111 pcon_max_slice_width, 4112 hdmi_max_slices, hdmi_throughput); 4113} 4114 4115static int 4116intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp, 4117 const struct intel_crtc_state *crtc_state, 4118 int num_slices, int slice_width) 4119{ 4120 struct intel_connector *connector = intel_dp->attached_connector; 4121 const struct drm_display_info *info = &connector->base.display_info; 4122 int output_format = crtc_state->output_format; 4123 bool hdmi_all_bpp = info->hdmi.dsc_cap.all_bpp; 4124 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd); 4125 int hdmi_max_chunk_bytes = 4126 info->hdmi.dsc_cap.total_chunk_kbytes * 1024; 4127 4128 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width, 4129 num_slices, output_format, hdmi_all_bpp, 4130 hdmi_max_chunk_bytes); 4131} 4132 4133void 4134intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, 4135 const struct intel_crtc_state *crtc_state) 4136{ 4137 struct intel_display *display = to_intel_display(intel_dp); 4138 struct intel_connector *connector = intel_dp->attached_connector; 4139 const struct drm_display_info *info; 4140 u8 pps_param[6]; 4141 int slice_height; 4142 int slice_width; 4143 int num_slices; 4144 int bits_per_pixel; 4145 int ret; 4146 bool hdmi_is_dsc_1_2; 4147 4148 if (!intel_dp_is_hdmi_2_1_sink(intel_dp)) 4149 return; 4150 4151 if (!connector) 4152 return; 4153 4154 info = &connector->base.display_info; 4155 4156 hdmi_is_dsc_1_2 = info->hdmi.dsc_cap.v_1p2; 4157 4158 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) || 4159 !hdmi_is_dsc_1_2) 4160 return; 4161 4162 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state); 4163 if (!slice_height) 4164 return; 4165 4166 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state); 4167 if (!num_slices) 4168 return; 4169 4170 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, 4171 num_slices); 4172 4173 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state, 4174 num_slices, slice_width); 4175 if (!bits_per_pixel) 4176 return; 4177 4178 pps_param[0] = slice_height & 0xFF; 4179 pps_param[1] = slice_height >> 8; 4180 pps_param[2] = slice_width & 0xFF; 4181 pps_param[3] = slice_width >> 8; 4182 pps_param[4] = bits_per_pixel & 0xFF; 4183 pps_param[5] = (bits_per_pixel >> 8) & 0x3; 4184 4185 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param); 4186 if (ret < 0) 4187 drm_dbg_kms(display->drm, "Failed to set pcon DSC\n"); 4188} 4189 4190void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, 4191 const struct intel_crtc_state *crtc_state) 4192{ 4193 struct intel_display *display = to_intel_display(intel_dp); 4194 bool ycbcr444_to_420 = false; 4195 bool rgb_to_ycbcr = false; 4196 u8 tmp; 4197 4198 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) 4199 return; 4200 4201 if (!drm_dp_is_branch(intel_dp->dpcd)) 4202 return; 4203 4204 tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0; 4205 4206 if (drm_dp_dpcd_writeb(&intel_dp->aux, 4207 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1) 4208 drm_dbg_kms(display->drm, 4209 "Failed to %s protocol converter HDMI mode\n", 4210 str_enable_disable(intel_dp_has_hdmi_sink(intel_dp))); 4211 4212 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 4213 switch (crtc_state->output_format) { 4214 case INTEL_OUTPUT_FORMAT_YCBCR420: 4215 break; 4216 case INTEL_OUTPUT_FORMAT_YCBCR444: 4217 ycbcr444_to_420 = true; 4218 break; 4219 case INTEL_OUTPUT_FORMAT_RGB: 4220 rgb_to_ycbcr = true; 4221 ycbcr444_to_420 = true; 4222 break; 4223 default: 4224 MISSING_CASE(crtc_state->output_format); 4225 break; 4226 } 4227 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) { 4228 switch (crtc_state->output_format) { 4229 case INTEL_OUTPUT_FORMAT_YCBCR444: 4230 break; 4231 case INTEL_OUTPUT_FORMAT_RGB: 4232 rgb_to_ycbcr = true; 4233 break; 4234 default: 4235 MISSING_CASE(crtc_state->output_format); 4236 break; 4237 } 4238 } 4239 4240 tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; 4241 4242 if (drm_dp_dpcd_writeb(&intel_dp->aux, 4243 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) 4244 drm_dbg_kms(display->drm, 4245 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n", 4246 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420)); 4247 4248 tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0; 4249 4250 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) 4251 drm_dbg_kms(display->drm, 4252 "Failed to %s protocol converter RGB->YCbCr conversion mode\n", 4253 str_enable_disable(tmp)); 4254} 4255 4256static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) 4257{ 4258 u8 dprx = 0; 4259 4260 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 4261 &dprx) != 1) 4262 return false; 4263 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; 4264} 4265 4266static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, 4267 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 4268{ 4269 if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd, 4270 DP_DSC_RECEIVER_CAP_SIZE) < 0) { 4271 drm_err(aux->drm_dev, 4272 "Failed to read DPCD register 0x%x\n", 4273 DP_DSC_SUPPORT); 4274 return; 4275 } 4276 4277 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n", 4278 DP_DSC_RECEIVER_CAP_SIZE, 4279 dsc_dpcd); 4280} 4281 4282static void init_dsc_overall_throughput_limits(struct intel_connector *connector, bool is_branch) 4283{ 4284 u8 branch_caps[DP_DSC_BRANCH_CAP_SIZE]; 4285 int line_width; 4286 4287 connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 = INT_MAX; 4288 connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 = INT_MAX; 4289 connector->dp.dsc_branch_caps.max_line_width = INT_MAX; 4290 4291 if (!is_branch) 4292 return; 4293 4294 if (drm_dp_dpcd_read_data(connector->dp.dsc_decompression_aux, 4295 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, branch_caps, 4296 sizeof(branch_caps)) != 0) 4297 return; 4298 4299 connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 = 4300 drm_dp_dsc_branch_max_overall_throughput(branch_caps, true) ? : INT_MAX; 4301 4302 connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 = 4303 drm_dp_dsc_branch_max_overall_throughput(branch_caps, false) ? : INT_MAX; 4304 4305 line_width = drm_dp_dsc_branch_max_line_width(branch_caps); 4306 connector->dp.dsc_branch_caps.max_line_width = line_width > 0 ? line_width : INT_MAX; 4307} 4308 4309void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, 4310 const struct drm_dp_desc *desc, bool is_branch, 4311 struct intel_connector *connector) 4312{ 4313 struct intel_display *display = to_intel_display(connector); 4314 4315 /* 4316 * Clear the cached register set to avoid using stale values 4317 * for the sinks that do not support DSC. 4318 */ 4319 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); 4320 4321 /* Clear fec_capable to avoid using stale values */ 4322 connector->dp.fec_capability = 0; 4323 4324 memset(&connector->dp.dsc_branch_caps, 0, sizeof(connector->dp.dsc_branch_caps)); 4325 connector->dp.dsc_throughput_quirk = false; 4326 4327 if (dpcd_rev < DP_DPCD_REV_14) 4328 return; 4329 4330 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, 4331 connector->dp.dsc_dpcd); 4332 4333 if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY, 4334 &connector->dp.fec_capability) < 0) { 4335 drm_err(display->drm, "Failed to read FEC DPCD register\n"); 4336 return; 4337 } 4338 4339 drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n", 4340 connector->dp.fec_capability); 4341 4342 if (!(connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)) 4343 return; 4344 4345 init_dsc_overall_throughput_limits(connector, is_branch); 4346 4347 /* 4348 * TODO: Move the HW rev check as well to the DRM core quirk table if 4349 * that's required after clarifying the list of affected devices. 4350 */ 4351 if (drm_dp_has_quirk(desc, DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) && 4352 desc->ident.hw_rev == 0x10) 4353 connector->dp.dsc_throughput_quirk = true; 4354} 4355 4356static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector) 4357{ 4358 if (edp_dpcd_rev < DP_EDP_14) 4359 return; 4360 4361 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd); 4362 4363 if (connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED) 4364 init_dsc_overall_throughput_limits(connector, false); 4365} 4366 4367static void 4368intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) 4369{ 4370 struct intel_display *display = to_intel_display(intel_dp); 4371 4372 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ 4373 if (!HAS_DSC(display)) 4374 return; 4375 4376 if (intel_dp_is_edp(intel_dp)) 4377 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], 4378 connector); 4379 else 4380 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], 4381 &intel_dp->desc, drm_dp_is_branch(intel_dp->dpcd), 4382 connector); 4383} 4384 4385static void intel_edp_mso_mode_fixup(struct intel_connector *connector, 4386 struct drm_display_mode *mode) 4387{ 4388 struct intel_display *display = to_intel_display(connector); 4389 struct intel_dp *intel_dp = intel_attached_dp(connector); 4390 int n = intel_dp->mso_link_count; 4391 int overlap = intel_dp->mso_pixel_overlap; 4392 4393 if (!mode || !n) 4394 return; 4395 4396 mode->hdisplay = (mode->hdisplay - overlap) * n; 4397 mode->hsync_start = (mode->hsync_start - overlap) * n; 4398 mode->hsync_end = (mode->hsync_end - overlap) * n; 4399 mode->htotal = (mode->htotal - overlap) * n; 4400 mode->clock *= n; 4401 4402 drm_mode_set_name(mode); 4403 4404 drm_dbg_kms(display->drm, 4405 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n", 4406 connector->base.base.id, connector->base.name, 4407 DRM_MODE_ARG(mode)); 4408} 4409 4410void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp) 4411{ 4412 struct intel_display *display = to_intel_display(encoder); 4413 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4414 struct intel_connector *connector = intel_dp->attached_connector; 4415 4416 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) { 4417 /* 4418 * This is a big fat ugly hack. 4419 * 4420 * Some machines in UEFI boot mode provide us a VBT that has 18 4421 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4422 * unknown we fail to light up. Yet the same BIOS boots up with 4423 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4424 * max, not what it tells us to use. 4425 * 4426 * Note: This will still be broken if the eDP panel is not lit 4427 * up by the BIOS, and thus we can't get the mode at module 4428 * load. 4429 */ 4430 drm_dbg_kms(display->drm, 4431 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4432 pipe_bpp, connector->panel.vbt.edp.bpp); 4433 connector->panel.vbt.edp.bpp = pipe_bpp; 4434 } 4435} 4436 4437static void intel_edp_mso_init(struct intel_dp *intel_dp) 4438{ 4439 struct intel_display *display = to_intel_display(intel_dp); 4440 struct intel_connector *connector = intel_dp->attached_connector; 4441 struct drm_display_info *info = &connector->base.display_info; 4442 u8 mso; 4443 4444 if (intel_dp->edp_dpcd[0] < DP_EDP_14) 4445 return; 4446 4447 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) { 4448 drm_err(display->drm, "Failed to read MSO cap\n"); 4449 return; 4450 } 4451 4452 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */ 4453 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK; 4454 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) { 4455 drm_err(display->drm, "Invalid MSO link count cap %u\n", mso); 4456 mso = 0; 4457 } 4458 4459 if (mso) { 4460 drm_dbg_kms(display->drm, 4461 "Sink MSO %ux%u configuration, pixel overlap %u\n", 4462 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso, 4463 info->mso_pixel_overlap); 4464 if (!HAS_MSO(display)) { 4465 drm_err(display->drm, 4466 "No source MSO support, disabling\n"); 4467 mso = 0; 4468 } 4469 } 4470 4471 intel_dp->mso_link_count = mso; 4472 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0; 4473} 4474 4475static void 4476intel_edp_set_data_override_rates(struct intel_dp *intel_dp) 4477{ 4478 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4479 int *sink_rates = intel_dp->sink_rates; 4480 int i, count = 0; 4481 4482 for (i = 0; i < intel_dp->num_sink_rates; i++) { 4483 if (intel_bios_encoder_reject_edp_rate(encoder->devdata, 4484 intel_dp->sink_rates[i])) 4485 continue; 4486 4487 sink_rates[count++] = intel_dp->sink_rates[i]; 4488 } 4489 intel_dp->num_sink_rates = count; 4490} 4491 4492static void 4493intel_edp_set_sink_rates(struct intel_dp *intel_dp) 4494{ 4495 struct intel_display *display = to_intel_display(intel_dp); 4496 4497 intel_dp->num_sink_rates = 0; 4498 4499 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { 4500 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 4501 int i; 4502 4503 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 4504 sink_rates, sizeof(sink_rates)); 4505 4506 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 4507 int rate; 4508 4509 /* Value read multiplied by 200kHz gives the per-lane 4510 * link rate in kHz. The source rates are, however, 4511 * stored in terms of LS_Clk kHz. The full conversion 4512 * back to symbols is 4513 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) 4514 */ 4515 rate = le16_to_cpu(sink_rates[i]) * 200 / 10; 4516 4517 if (rate == 0) 4518 break; 4519 4520 /* 4521 * Some platforms cannot reliably drive HBR3 rates due to PHY limitations, 4522 * even if the sink advertises support. Reject any sink rates above HBR2 on 4523 * the known machines for stable output. 4524 */ 4525 if (rate > 540000 && 4526 intel_has_quirk(display, QUIRK_EDP_LIMIT_RATE_HBR2)) 4527 break; 4528 4529 intel_dp->sink_rates[i] = rate; 4530 } 4531 intel_dp->num_sink_rates = i; 4532 } 4533 4534 /* 4535 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, 4536 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. 4537 */ 4538 if (intel_dp->num_sink_rates) 4539 intel_dp->use_rate_select = true; 4540 else 4541 intel_dp_set_sink_rates(intel_dp); 4542 4543 intel_edp_set_data_override_rates(intel_dp); 4544} 4545 4546static bool 4547intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 4548{ 4549 struct intel_display *display = to_intel_display(intel_dp); 4550 int ret; 4551 4552 /* this function is meant to be called only once */ 4553 drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); 4554 4555 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) 4556 return false; 4557 4558 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4559 drm_dp_is_branch(intel_dp->dpcd)); 4560 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident); 4561 4562 intel_dp->colorimetry_support = 4563 intel_dp_get_colorimetry_status(intel_dp); 4564 4565 /* 4566 * Read the eDP display control registers. 4567 * 4568 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in 4569 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it 4570 * set, but require eDP 1.4+ detection (e.g. for supported link rates 4571 * method). The display control registers should read zero if they're 4572 * not supported anyway. 4573 */ 4574 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 4575 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == 4576 sizeof(intel_dp->edp_dpcd)) { 4577 drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n", 4578 (int)sizeof(intel_dp->edp_dpcd), 4579 intel_dp->edp_dpcd); 4580 4581 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14; 4582 } 4583 4584 /* 4585 * If needed, program our source OUI so we can make various Intel-specific AUX services 4586 * available (such as HDR backlight controls) 4587 */ 4588 intel_dp_init_source_oui(intel_dp); 4589 4590 /* Read the ALPM DPCD caps */ 4591 ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, 4592 &intel_dp->alpm_dpcd); 4593 if (ret < 0) 4594 return false; 4595 4596 /* 4597 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks 4598 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] 4599 */ 4600 intel_psr_init_dpcd(intel_dp); 4601 4602 intel_edp_set_sink_rates(intel_dp); 4603 intel_dp_set_max_sink_lane_count(intel_dp); 4604 4605 /* Read the eDP DSC DPCD registers */ 4606 intel_dp_detect_dsc_caps(intel_dp, connector); 4607 4608 return true; 4609} 4610 4611static bool 4612intel_dp_has_sink_count(struct intel_dp *intel_dp) 4613{ 4614 if (!intel_dp->attached_connector) 4615 return false; 4616 4617 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base, 4618 intel_dp->dpcd, 4619 &intel_dp->desc); 4620} 4621 4622void intel_dp_update_sink_caps(struct intel_dp *intel_dp) 4623{ 4624 intel_dp_set_sink_rates(intel_dp); 4625 intel_dp_set_max_sink_lane_count(intel_dp); 4626 intel_dp_set_common_rates(intel_dp); 4627} 4628 4629static bool 4630intel_dp_get_dpcd(struct intel_dp *intel_dp) 4631{ 4632 int ret; 4633 4634 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0) 4635 return false; 4636 4637 /* 4638 * Don't clobber cached eDP rates. Also skip re-reading 4639 * the OUI/ID since we know it won't change. 4640 */ 4641 if (!intel_dp_is_edp(intel_dp)) { 4642 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4643 drm_dp_is_branch(intel_dp->dpcd)); 4644 4645 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident); 4646 4647 intel_dp->colorimetry_support = 4648 intel_dp_get_colorimetry_status(intel_dp); 4649 4650 intel_dp_update_sink_caps(intel_dp); 4651 } 4652 4653 if (intel_dp_has_sink_count(intel_dp)) { 4654 ret = drm_dp_read_sink_count(&intel_dp->aux); 4655 if (ret < 0) 4656 return false; 4657 4658 /* 4659 * Sink count can change between short pulse hpd hence 4660 * a member variable in intel_dp will track any changes 4661 * between short pulse interrupts. 4662 */ 4663 intel_dp->sink_count = ret; 4664 4665 /* 4666 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that 4667 * a dongle is present but no display. Unless we require to know 4668 * if a dongle is present or not, we don't need to update 4669 * downstream port information. So, an early return here saves 4670 * time from performing other operations which are not required. 4671 */ 4672 if (!intel_dp->sink_count) 4673 return false; 4674 } 4675 4676 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, 4677 intel_dp->downstream_ports) == 0; 4678} 4679 4680static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode) 4681{ 4682 if (mst_mode == DRM_DP_MST) 4683 return "MST"; 4684 else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG) 4685 return "SST w/ sideband messaging"; 4686 else 4687 return "SST"; 4688} 4689 4690static enum drm_dp_mst_mode 4691intel_dp_mst_mode_choose(struct intel_dp *intel_dp, 4692 enum drm_dp_mst_mode sink_mst_mode) 4693{ 4694 struct intel_display *display = to_intel_display(intel_dp); 4695 4696 if (!display->params.enable_dp_mst) 4697 return DRM_DP_SST; 4698 4699 if (!intel_dp_mst_source_support(intel_dp)) 4700 return DRM_DP_SST; 4701 4702 if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG && 4703 !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B)) 4704 return DRM_DP_SST; 4705 4706 return sink_mst_mode; 4707} 4708 4709static enum drm_dp_mst_mode 4710intel_dp_mst_detect(struct intel_dp *intel_dp) 4711{ 4712 struct intel_display *display = to_intel_display(intel_dp); 4713 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4714 enum drm_dp_mst_mode sink_mst_mode; 4715 enum drm_dp_mst_mode mst_detect; 4716 4717 sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); 4718 4719 mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode); 4720 4721 drm_dbg_kms(display->drm, 4722 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n", 4723 encoder->base.base.id, encoder->base.name, 4724 str_yes_no(intel_dp_mst_source_support(intel_dp)), 4725 intel_dp_mst_mode_str(sink_mst_mode), 4726 str_yes_no(display->params.enable_dp_mst), 4727 intel_dp_mst_mode_str(mst_detect)); 4728 4729 return mst_detect; 4730} 4731 4732static void 4733intel_dp_mst_configure(struct intel_dp *intel_dp) 4734{ 4735 if (!intel_dp_mst_source_support(intel_dp)) 4736 return; 4737 4738 intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST; 4739 4740 if (intel_dp->is_mst) 4741 intel_dp_mst_prepare_probe(intel_dp); 4742 4743 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst); 4744 4745 /* Avoid stale info on the next detect cycle. */ 4746 intel_dp->mst_detect = DRM_DP_SST; 4747} 4748 4749static void 4750intel_dp_mst_disconnect(struct intel_dp *intel_dp) 4751{ 4752 struct intel_display *display = to_intel_display(intel_dp); 4753 4754 if (!intel_dp->is_mst) 4755 return; 4756 4757 drm_dbg_kms(display->drm, 4758 "MST device may have disappeared %d vs %d\n", 4759 intel_dp->is_mst, intel_dp->mst.mgr.mst_state); 4760 intel_dp->is_mst = false; 4761 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst); 4762} 4763 4764static bool 4765intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi) 4766{ 4767 struct intel_display *display = to_intel_display(intel_dp); 4768 4769 /* 4770 * Display WA for HSD #13013007775: mtl/arl/lnl 4771 * Read the sink count and link service IRQ registers in separate 4772 * transactions to prevent disconnecting the sink on a TBT link 4773 * inadvertently. 4774 */ 4775 if (IS_DISPLAY_VER(display, 14, 20) && !display->platform.battlemage) { 4776 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 3) != 3) 4777 return false; 4778 4779 /* DP_SINK_COUNT_ESI + 3 == DP_LINK_SERVICE_IRQ_VECTOR_ESI0 */ 4780 return drm_dp_dpcd_readb(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0, 4781 &esi[3]) == 1; 4782 } 4783 4784 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4; 4785} 4786 4787static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4]) 4788{ 4789 int retry; 4790 4791 for (retry = 0; retry < 3; retry++) { 4792 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1, 4793 &esi[1], 3) == 3) 4794 return true; 4795 } 4796 4797 return false; 4798} 4799 4800bool 4801intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, 4802 const struct drm_connector_state *conn_state) 4803{ 4804 /* 4805 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 4806 * of Color Encoding Format and Content Color Gamut], in order to 4807 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. 4808 */ 4809 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 4810 return true; 4811 4812 switch (conn_state->colorspace) { 4813 case DRM_MODE_COLORIMETRY_SYCC_601: 4814 case DRM_MODE_COLORIMETRY_OPYCC_601: 4815 case DRM_MODE_COLORIMETRY_BT2020_YCC: 4816 case DRM_MODE_COLORIMETRY_BT2020_RGB: 4817 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 4818 return true; 4819 default: 4820 break; 4821 } 4822 4823 return false; 4824} 4825 4826static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, 4827 struct dp_sdp *sdp, size_t size) 4828{ 4829 size_t length = sizeof(struct dp_sdp); 4830 4831 if (size < length) 4832 return -ENOSPC; 4833 4834 memset(sdp, 0, size); 4835 4836 /* Prepare AS (Adaptive Sync) SDP Header */ 4837 sdp->sdp_header.HB0 = 0; 4838 sdp->sdp_header.HB1 = as_sdp->sdp_type; 4839 sdp->sdp_header.HB2 = 0x02; 4840 sdp->sdp_header.HB3 = as_sdp->length; 4841 4842 /* Fill AS (Adaptive Sync) SDP Payload */ 4843 sdp->db[0] = as_sdp->mode; 4844 sdp->db[1] = as_sdp->vtotal & 0xFF; 4845 sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF; 4846 sdp->db[3] = as_sdp->target_rr & 0xFF; 4847 sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; 4848 4849 if (as_sdp->target_rr_divider) 4850 sdp->db[4] |= 0x20; 4851 4852 return length; 4853} 4854 4855static ssize_t 4856intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display *display, 4857 const struct hdmi_drm_infoframe *drm_infoframe, 4858 struct dp_sdp *sdp, 4859 size_t size) 4860{ 4861 size_t length = sizeof(struct dp_sdp); 4862 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE; 4863 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE]; 4864 ssize_t len; 4865 4866 if (size < length) 4867 return -ENOSPC; 4868 4869 memset(sdp, 0, size); 4870 4871 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf)); 4872 if (len < 0) { 4873 drm_dbg_kms(display->drm, 4874 "buffer size is smaller than hdr metadata infoframe\n"); 4875 return -ENOSPC; 4876 } 4877 4878 if (len != infoframe_size) { 4879 drm_dbg_kms(display->drm, "wrong static hdr metadata size\n"); 4880 return -ENOSPC; 4881 } 4882 4883 /* 4884 * Set up the infoframe sdp packet for HDR static metadata. 4885 * Prepare VSC Header for SU as per DP 1.4a spec, 4886 * Table 2-100 and Table 2-101 4887 */ 4888 4889 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ 4890 sdp->sdp_header.HB0 = 0; 4891 /* 4892 * Packet Type 80h + Non-audio INFOFRAME Type value 4893 * HDMI_INFOFRAME_TYPE_DRM: 0x87 4894 * - 80h + Non-audio INFOFRAME Type value 4895 * - InfoFrame Type: 0x07 4896 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] 4897 */ 4898 sdp->sdp_header.HB1 = drm_infoframe->type; 4899 /* 4900 * Least Significant Eight Bits of (Data Byte Count – 1) 4901 * infoframe_size - 1 4902 */ 4903 sdp->sdp_header.HB2 = 0x1D; 4904 /* INFOFRAME SDP Version Number */ 4905 sdp->sdp_header.HB3 = (0x13 << 2); 4906 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 4907 sdp->db[0] = drm_infoframe->version; 4908 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 4909 sdp->db[1] = drm_infoframe->length; 4910 /* 4911 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after 4912 * HDMI_INFOFRAME_HEADER_SIZE 4913 */ 4914 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2); 4915 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], 4916 HDMI_DRM_INFOFRAME_SIZE); 4917 4918 /* 4919 * Size of DP infoframe sdp packet for HDR static metadata consists of 4920 * - DP SDP Header(struct dp_sdp_header): 4 bytes 4921 * - Two Data Blocks: 2 bytes 4922 * CTA Header Byte2 (INFOFRAME Version Number) 4923 * CTA Header Byte3 (Length of INFOFRAME) 4924 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes 4925 * 4926 * Prior to GEN11's GMP register size is identical to DP HDR static metadata 4927 * infoframe size. But GEN11+ has larger than that size, write_infoframe 4928 * will pad rest of the size. 4929 */ 4930 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; 4931} 4932 4933static void intel_write_dp_sdp(struct intel_encoder *encoder, 4934 const struct intel_crtc_state *crtc_state, 4935 unsigned int type) 4936{ 4937 struct intel_display *display = to_intel_display(encoder); 4938 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4939 struct dp_sdp sdp = {}; 4940 ssize_t len; 4941 4942 if ((crtc_state->infoframes.enable & 4943 intel_hdmi_infoframe_enable(type)) == 0) 4944 return; 4945 4946 switch (type) { 4947 case DP_SDP_VSC: 4948 len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp); 4949 break; 4950 case HDMI_PACKET_TYPE_GAMUT_METADATA: 4951 len = intel_dp_hdr_metadata_infoframe_sdp_pack(display, 4952 &crtc_state->infoframes.drm.drm, 4953 &sdp, sizeof(sdp)); 4954 break; 4955 case DP_SDP_ADAPTIVE_SYNC: 4956 len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp, 4957 sizeof(sdp)); 4958 break; 4959 default: 4960 MISSING_CASE(type); 4961 return; 4962 } 4963 4964 if (drm_WARN_ON(display->drm, len < 0)) 4965 return; 4966 4967 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); 4968} 4969 4970void intel_dp_set_infoframes(struct intel_encoder *encoder, 4971 bool enable, 4972 const struct intel_crtc_state *crtc_state, 4973 const struct drm_connector_state *conn_state) 4974{ 4975 struct intel_display *display = to_intel_display(encoder); 4976 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder); 4977 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 4978 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | 4979 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; 4980 4981 if (HAS_AS_SDP(display)) 4982 dip_enable |= VIDEO_DIP_ENABLE_AS_ADL; 4983 4984 u32 val = intel_de_read(display, reg) & ~dip_enable; 4985 4986 /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */ 4987 if (!enable && HAS_DSC(display)) 4988 val &= ~VDIP_ENABLE_PPS; 4989 4990 /* 4991 * This routine disables VSC DIP if the function is called 4992 * to disable SDP or if it does not have PSR 4993 */ 4994 if (!enable || !crtc_state->has_psr) 4995 val &= ~VIDEO_DIP_ENABLE_VSC_HSW; 4996 4997 intel_de_write(display, reg, val); 4998 intel_de_posting_read(display, reg); 4999 5000 if (!enable) 5001 return; 5002 5003 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); 5004 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC); 5005 5006 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); 5007} 5008 5009static 5010int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, 5011 const void *buffer, size_t size) 5012{ 5013 const struct dp_sdp *sdp = buffer; 5014 5015 if (size < sizeof(struct dp_sdp)) 5016 return -EINVAL; 5017 5018 memset(as_sdp, 0, sizeof(*as_sdp)); 5019 5020 if (sdp->sdp_header.HB0 != 0) 5021 return -EINVAL; 5022 5023 if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC) 5024 return -EINVAL; 5025 5026 if (sdp->sdp_header.HB2 != 0x02) 5027 return -EINVAL; 5028 5029 if ((sdp->sdp_header.HB3 & 0x3F) != 9) 5030 return -EINVAL; 5031 5032 as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH; 5033 as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; 5034 as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; 5035 as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); 5036 as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false; 5037 5038 return 0; 5039} 5040 5041static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, 5042 const void *buffer, size_t size) 5043{ 5044 const struct dp_sdp *sdp = buffer; 5045 5046 if (size < sizeof(struct dp_sdp)) 5047 return -EINVAL; 5048 5049 memset(vsc, 0, sizeof(*vsc)); 5050 5051 if (sdp->sdp_header.HB0 != 0) 5052 return -EINVAL; 5053 5054 if (sdp->sdp_header.HB1 != DP_SDP_VSC) 5055 return -EINVAL; 5056 5057 vsc->sdp_type = sdp->sdp_header.HB1; 5058 vsc->revision = sdp->sdp_header.HB2; 5059 vsc->length = sdp->sdp_header.HB3; 5060 5061 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || 5062 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) || 5063 (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) { 5064 /* 5065 * - HB2 = 0x2, HB3 = 0x8 5066 * VSC SDP supporting 3D stereo + PSR 5067 * - HB2 = 0x4, HB3 = 0xe 5068 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of 5069 * first scan line of the SU region (applies to eDP v1.4b 5070 * and higher). 5071 * - HB2 = 0x6, HB3 = 0x10 5072 * VSC SDP supporting 3D stereo + Panel Replay. 5073 */ 5074 return 0; 5075 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { 5076 /* 5077 * - HB2 = 0x5, HB3 = 0x13 5078 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry 5079 * Format. 5080 */ 5081 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf; 5082 vsc->colorimetry = sdp->db[16] & 0xf; 5083 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1; 5084 5085 switch (sdp->db[17] & 0x7) { 5086 case 0x0: 5087 vsc->bpc = 6; 5088 break; 5089 case 0x1: 5090 vsc->bpc = 8; 5091 break; 5092 case 0x2: 5093 vsc->bpc = 10; 5094 break; 5095 case 0x3: 5096 vsc->bpc = 12; 5097 break; 5098 case 0x4: 5099 vsc->bpc = 16; 5100 break; 5101 default: 5102 MISSING_CASE(sdp->db[17] & 0x7); 5103 return -EINVAL; 5104 } 5105 5106 vsc->content_type = sdp->db[18] & 0x7; 5107 } else { 5108 return -EINVAL; 5109 } 5110 5111 return 0; 5112} 5113 5114static void 5115intel_read_dp_as_sdp(struct intel_encoder *encoder, 5116 struct intel_crtc_state *crtc_state, 5117 struct drm_dp_as_sdp *as_sdp) 5118{ 5119 struct intel_display *display = to_intel_display(encoder); 5120 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5121 unsigned int type = DP_SDP_ADAPTIVE_SYNC; 5122 struct dp_sdp sdp = {}; 5123 int ret; 5124 5125 if ((crtc_state->infoframes.enable & 5126 intel_hdmi_infoframe_enable(type)) == 0) 5127 return; 5128 5129 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 5130 sizeof(sdp)); 5131 5132 ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp)); 5133 if (ret) 5134 drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n"); 5135} 5136 5137static int 5138intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, 5139 const void *buffer, size_t size) 5140{ 5141 int ret; 5142 5143 const struct dp_sdp *sdp = buffer; 5144 5145 if (size < sizeof(struct dp_sdp)) 5146 return -EINVAL; 5147 5148 if (sdp->sdp_header.HB0 != 0) 5149 return -EINVAL; 5150 5151 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM) 5152 return -EINVAL; 5153 5154 /* 5155 * Least Significant Eight Bits of (Data Byte Count – 1) 5156 * 1Dh (i.e., Data Byte Count = 30 bytes). 5157 */ 5158 if (sdp->sdp_header.HB2 != 0x1D) 5159 return -EINVAL; 5160 5161 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */ 5162 if ((sdp->sdp_header.HB3 & 0x3) != 0) 5163 return -EINVAL; 5164 5165 /* INFOFRAME SDP Version Number */ 5166 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13) 5167 return -EINVAL; 5168 5169 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 5170 if (sdp->db[0] != 1) 5171 return -EINVAL; 5172 5173 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 5174 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE) 5175 return -EINVAL; 5176 5177 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2], 5178 HDMI_DRM_INFOFRAME_SIZE); 5179 5180 return ret; 5181} 5182 5183static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, 5184 struct intel_crtc_state *crtc_state, 5185 struct drm_dp_vsc_sdp *vsc) 5186{ 5187 struct intel_display *display = to_intel_display(encoder); 5188 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5189 unsigned int type = DP_SDP_VSC; 5190 struct dp_sdp sdp = {}; 5191 int ret; 5192 5193 if ((crtc_state->infoframes.enable & 5194 intel_hdmi_infoframe_enable(type)) == 0) 5195 return; 5196 5197 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); 5198 5199 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); 5200 5201 if (ret) 5202 drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n"); 5203} 5204 5205static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, 5206 struct intel_crtc_state *crtc_state, 5207 struct hdmi_drm_infoframe *drm_infoframe) 5208{ 5209 struct intel_display *display = to_intel_display(encoder); 5210 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5211 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; 5212 struct dp_sdp sdp = {}; 5213 int ret; 5214 5215 if ((crtc_state->infoframes.enable & 5216 intel_hdmi_infoframe_enable(type)) == 0) 5217 return; 5218 5219 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 5220 sizeof(sdp)); 5221 5222 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, 5223 sizeof(sdp)); 5224 5225 if (ret) 5226 drm_dbg_kms(display->drm, 5227 "Failed to unpack DP HDR Metadata Infoframe SDP\n"); 5228} 5229 5230void intel_read_dp_sdp(struct intel_encoder *encoder, 5231 struct intel_crtc_state *crtc_state, 5232 unsigned int type) 5233{ 5234 switch (type) { 5235 case DP_SDP_VSC: 5236 intel_read_dp_vsc_sdp(encoder, crtc_state, 5237 &crtc_state->infoframes.vsc); 5238 break; 5239 case HDMI_PACKET_TYPE_GAMUT_METADATA: 5240 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, 5241 &crtc_state->infoframes.drm.drm); 5242 break; 5243 case DP_SDP_ADAPTIVE_SYNC: 5244 intel_read_dp_as_sdp(encoder, crtc_state, 5245 &crtc_state->infoframes.as_sdp); 5246 break; 5247 default: 5248 MISSING_CASE(type); 5249 break; 5250 } 5251} 5252 5253static bool intel_dp_link_ok(struct intel_dp *intel_dp, 5254 u8 link_status[DP_LINK_STATUS_SIZE]) 5255{ 5256 struct intel_display *display = to_intel_display(intel_dp); 5257 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 5258 bool uhbr = intel_dp->link_rate >= 1000000; 5259 bool ok; 5260 5261 if (uhbr) 5262 ok = drm_dp_128b132b_lane_channel_eq_done(link_status, 5263 intel_dp->lane_count); 5264 else 5265 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); 5266 5267 if (ok) 5268 return true; 5269 5270 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 5271 drm_dbg_kms(display->drm, 5272 "[ENCODER:%d:%s] %s link not ok, retraining\n", 5273 encoder->base.base.id, encoder->base.name, 5274 uhbr ? "128b/132b" : "8b/10b"); 5275 5276 return false; 5277} 5278 5279static void 5280intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack) 5281{ 5282 bool handled = false; 5283 5284 drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst.mgr, esi, ack, &handled); 5285 5286 if (esi[1] & DP_CP_IRQ) { 5287 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 5288 ack[1] |= DP_CP_IRQ; 5289 } 5290} 5291 5292static bool intel_dp_mst_link_status(struct intel_dp *intel_dp) 5293{ 5294 struct intel_display *display = to_intel_display(intel_dp); 5295 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 5296 u8 link_status[DP_LINK_STATUS_SIZE] = {}; 5297 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2; 5298 5299 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status, 5300 esi_link_status_size) != esi_link_status_size) { 5301 drm_err(display->drm, 5302 "[ENCODER:%d:%s] Failed to read link status\n", 5303 encoder->base.base.id, encoder->base.name); 5304 return false; 5305 } 5306 5307 return intel_dp_link_ok(intel_dp, link_status); 5308} 5309 5310/** 5311 * intel_dp_check_mst_status - service any pending MST interrupts, check link status 5312 * @intel_dp: Intel DP struct 5313 * 5314 * Read any pending MST interrupts, call MST core to handle these and ack the 5315 * interrupts. Check if the main and AUX link state is ok. 5316 * 5317 * Returns: 5318 * - %true if pending interrupts were serviced (or no interrupts were 5319 * pending) w/o detecting an error condition. 5320 * - %false if an error condition - like AUX failure or a loss of link - is 5321 * detected, or another condition - like a DP tunnel BW state change - needs 5322 * servicing from the hotplug work. 5323 */ 5324static bool 5325intel_dp_check_mst_status(struct intel_dp *intel_dp) 5326{ 5327 struct intel_display *display = to_intel_display(intel_dp); 5328 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5329 struct intel_encoder *encoder = &dig_port->base; 5330 bool link_ok = true; 5331 bool reprobe_needed = false; 5332 5333 for (;;) { 5334 u8 esi[4] = {}; 5335 u8 ack[4] = {}; 5336 5337 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { 5338 drm_dbg_kms(display->drm, 5339 "failed to get ESI - device may have failed\n"); 5340 link_ok = false; 5341 5342 break; 5343 } 5344 5345 drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi); 5346 5347 if (intel_dp_mst_active_streams(intel_dp) > 0 && link_ok && 5348 esi[3] & LINK_STATUS_CHANGED) { 5349 if (!intel_dp_mst_link_status(intel_dp)) 5350 link_ok = false; 5351 ack[3] |= LINK_STATUS_CHANGED; 5352 } 5353 5354 intel_dp_mst_hpd_irq(intel_dp, esi, ack); 5355 5356 if (esi[3] & DP_TUNNELING_IRQ) { 5357 if (drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr, 5358 &intel_dp->aux)) 5359 reprobe_needed = true; 5360 ack[3] |= DP_TUNNELING_IRQ; 5361 } 5362 5363 if (mem_is_zero(ack, sizeof(ack))) 5364 break; 5365 5366 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack)) 5367 drm_dbg_kms(display->drm, "Failed to ack ESI\n"); 5368 5369 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY)) 5370 drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst.mgr); 5371 } 5372 5373 if (!link_ok || intel_dp->link.force_retrain) 5374 intel_encoder_link_check_queue_work(encoder, 0); 5375 5376 return !reprobe_needed; 5377} 5378 5379static void 5380intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) 5381{ 5382 bool is_active; 5383 u8 buf = 0; 5384 5385 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux); 5386 if (intel_dp->frl.is_trained && !is_active) { 5387 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0) 5388 return; 5389 5390 buf &= ~DP_PCON_ENABLE_HDMI_LINK; 5391 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0) 5392 return; 5393 5394 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base); 5395 5396 intel_dp->frl.is_trained = false; 5397 5398 /* Restart FRL training or fall back to TMDS mode */ 5399 intel_dp_check_frl_training(intel_dp); 5400 } 5401} 5402 5403static bool 5404intel_dp_needs_link_retrain(struct intel_dp *intel_dp) 5405{ 5406 u8 link_status[DP_LINK_STATUS_SIZE]; 5407 5408 if (!intel_dp->link.active) 5409 return false; 5410 5411 /* 5412 * While PSR source HW is enabled, it will control main-link sending 5413 * frames, enabling and disabling it so trying to do a retrain will fail 5414 * as the link would or not be on or it could mix training patterns 5415 * and frame data at the same time causing retrain to fail. 5416 * Also when exiting PSR, HW will retrain the link anyways fixing 5417 * any link status error. 5418 */ 5419 if (intel_psr_enabled(intel_dp)) 5420 return false; 5421 5422 if (intel_dp->link.force_retrain) 5423 return true; 5424 5425 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 5426 link_status) < 0) 5427 return false; 5428 5429 /* 5430 * Validate the cached values of intel_dp->link_rate and 5431 * intel_dp->lane_count before attempting to retrain. 5432 * 5433 * FIXME would be nice to user the crtc state here, but since 5434 * we need to call this from the short HPD handler that seems 5435 * a bit hard. 5436 */ 5437 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, 5438 intel_dp->lane_count)) 5439 return false; 5440 5441 if (intel_dp->link.retrain_disabled) 5442 return false; 5443 5444 if (intel_dp->link.seq_train_failures) 5445 return true; 5446 5447 /* Retrain if link not ok */ 5448 return !intel_dp_link_ok(intel_dp, link_status) && 5449 !intel_psr_link_ok(intel_dp); 5450} 5451 5452bool intel_dp_has_connector(struct intel_dp *intel_dp, 5453 const struct drm_connector_state *conn_state) 5454{ 5455 struct intel_display *display = to_intel_display(intel_dp); 5456 struct intel_encoder *encoder; 5457 enum pipe pipe; 5458 5459 if (!conn_state->best_encoder) 5460 return false; 5461 5462 /* SST */ 5463 encoder = &dp_to_dig_port(intel_dp)->base; 5464 if (conn_state->best_encoder == &encoder->base) 5465 return true; 5466 5467 /* MST */ 5468 for_each_pipe(display, pipe) { 5469 encoder = &intel_dp->mst.stream_encoders[pipe]->base; 5470 if (conn_state->best_encoder == &encoder->base) 5471 return true; 5472 } 5473 5474 return false; 5475} 5476 5477static void wait_for_connector_hw_done(const struct drm_connector_state *conn_state) 5478{ 5479 struct intel_connector *connector = to_intel_connector(conn_state->connector); 5480 struct intel_display *display = to_intel_display(connector); 5481 5482 drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex); 5483 5484 if (!conn_state->commit) 5485 return; 5486 5487 drm_WARN_ON(display->drm, 5488 !wait_for_completion_timeout(&conn_state->commit->hw_done, 5489 msecs_to_jiffies(5000))); 5490} 5491 5492int intel_dp_get_active_pipes(struct intel_dp *intel_dp, 5493 struct drm_modeset_acquire_ctx *ctx, 5494 u8 *pipe_mask) 5495{ 5496 struct intel_display *display = to_intel_display(intel_dp); 5497 struct drm_connector_list_iter conn_iter; 5498 struct intel_connector *connector; 5499 int ret = 0; 5500 5501 *pipe_mask = 0; 5502 5503 drm_connector_list_iter_begin(display->drm, &conn_iter); 5504 for_each_intel_connector_iter(connector, &conn_iter) { 5505 struct drm_connector_state *conn_state = 5506 connector->base.state; 5507 struct intel_crtc_state *crtc_state; 5508 struct intel_crtc *crtc; 5509 5510 if (!intel_dp_has_connector(intel_dp, conn_state)) 5511 continue; 5512 5513 crtc = to_intel_crtc(conn_state->crtc); 5514 if (!crtc) 5515 continue; 5516 5517 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 5518 if (ret) 5519 break; 5520 5521 crtc_state = to_intel_crtc_state(crtc->base.state); 5522 5523 drm_WARN_ON(display->drm, 5524 !intel_crtc_has_dp_encoder(crtc_state)); 5525 5526 if (!crtc_state->hw.active) 5527 continue; 5528 5529 wait_for_connector_hw_done(conn_state); 5530 5531 *pipe_mask |= BIT(crtc->pipe); 5532 } 5533 drm_connector_list_iter_end(&conn_iter); 5534 5535 return ret; 5536} 5537 5538void intel_dp_flush_connector_commits(struct intel_connector *connector) 5539{ 5540 wait_for_connector_hw_done(connector->base.state); 5541} 5542 5543static bool intel_dp_is_connected(struct intel_dp *intel_dp) 5544{ 5545 struct intel_connector *connector = intel_dp->attached_connector; 5546 5547 return connector->base.status == connector_status_connected || 5548 intel_dp->is_mst; 5549} 5550 5551static int intel_dp_retrain_link(struct intel_encoder *encoder, 5552 struct drm_modeset_acquire_ctx *ctx) 5553{ 5554 struct intel_display *display = to_intel_display(encoder); 5555 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5556 u8 pipe_mask; 5557 int ret; 5558 5559 if (!intel_dp_is_connected(intel_dp)) 5560 return 0; 5561 5562 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 5563 ctx); 5564 if (ret) 5565 return ret; 5566 5567 if (!intel_dp_needs_link_retrain(intel_dp)) 5568 return 0; 5569 5570 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask); 5571 if (ret) 5572 return ret; 5573 5574 if (pipe_mask == 0) 5575 return 0; 5576 5577 if (!intel_dp_needs_link_retrain(intel_dp)) 5578 return 0; 5579 5580 drm_dbg_kms(display->drm, 5581 "[ENCODER:%d:%s] retraining link (forced %s)\n", 5582 encoder->base.base.id, encoder->base.name, 5583 str_yes_no(intel_dp->link.force_retrain)); 5584 5585 ret = intel_modeset_commit_pipes(display, pipe_mask, ctx); 5586 if (ret == -EDEADLK) 5587 return ret; 5588 5589 intel_dp->link.force_retrain = false; 5590 5591 if (ret) 5592 drm_dbg_kms(display->drm, 5593 "[ENCODER:%d:%s] link retraining failed: %pe\n", 5594 encoder->base.base.id, encoder->base.name, 5595 ERR_PTR(ret)); 5596 5597 return ret; 5598} 5599 5600void intel_dp_link_check(struct intel_encoder *encoder) 5601{ 5602 struct drm_modeset_acquire_ctx ctx; 5603 int ret; 5604 5605 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 5606 ret = intel_dp_retrain_link(encoder, &ctx); 5607} 5608 5609void intel_dp_check_link_state(struct intel_dp *intel_dp) 5610{ 5611 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5612 struct intel_encoder *encoder = &dig_port->base; 5613 5614 if (!intel_dp_is_connected(intel_dp)) 5615 return; 5616 5617 if (!intel_dp_needs_link_retrain(intel_dp)) 5618 return; 5619 5620 intel_encoder_link_check_queue_work(encoder, 0); 5621} 5622 5623static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp) 5624{ 5625 struct intel_display *display = to_intel_display(intel_dp); 5626 u8 val; 5627 5628 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 5629 return; 5630 5631 if (drm_dp_dpcd_readb(&intel_dp->aux, 5632 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val) 5633 return; 5634 5635 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); 5636 5637 if (val & DP_AUTOMATED_TEST_REQUEST) 5638 intel_dp_test_request(intel_dp); 5639 5640 if (val & DP_CP_IRQ) 5641 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 5642 5643 if (val & DP_SINK_SPECIFIC_IRQ) 5644 drm_dbg_kms(display->drm, "Sink specific irq unhandled\n"); 5645} 5646 5647static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp) 5648{ 5649 struct intel_display *display = to_intel_display(intel_dp); 5650 bool reprobe_needed = false; 5651 u8 val; 5652 5653 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 5654 return false; 5655 5656 if (drm_dp_dpcd_readb(&intel_dp->aux, 5657 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) 5658 return false; 5659 5660 if ((val & DP_TUNNELING_IRQ) && 5661 drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr, 5662 &intel_dp->aux)) 5663 reprobe_needed = true; 5664 5665 if (drm_dp_dpcd_writeb(&intel_dp->aux, 5666 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) 5667 return reprobe_needed; 5668 5669 if (val & HDMI_LINK_STATUS_CHANGED) 5670 intel_dp_handle_hdmi_link_status_change(intel_dp); 5671 5672 return reprobe_needed; 5673} 5674 5675/* 5676 * According to DP spec 5677 * 5.1.2: 5678 * 1. Read DPCD 5679 * 2. Configure link according to Receiver Capabilities 5680 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 5681 * 4. Check link status on receipt of hot-plug interrupt 5682 * 5683 * intel_dp_short_pulse - handles short pulse interrupts 5684 * when full detection is not required. 5685 * Returns %true if short pulse is handled and full detection 5686 * is NOT required and %false otherwise. 5687 */ 5688static bool 5689intel_dp_short_pulse(struct intel_dp *intel_dp) 5690{ 5691 u8 old_sink_count = intel_dp->sink_count; 5692 bool reprobe_needed = false; 5693 bool ret; 5694 5695 intel_dp_test_reset(intel_dp); 5696 5697 /* 5698 * Now read the DPCD to see if it's actually running 5699 * If the current value of sink count doesn't match with 5700 * the value that was stored earlier or dpcd read failed 5701 * we need to do full detection 5702 */ 5703 ret = intel_dp_get_dpcd(intel_dp); 5704 5705 if ((old_sink_count != intel_dp->sink_count) || !ret) { 5706 /* No need to proceed if we are going to do full detect */ 5707 return false; 5708 } 5709 5710 intel_dp_check_device_service_irq(intel_dp); 5711 reprobe_needed = intel_dp_check_link_service_irq(intel_dp); 5712 5713 /* Handle CEC interrupts, if any */ 5714 drm_dp_cec_irq(&intel_dp->aux); 5715 5716 intel_dp_check_link_state(intel_dp); 5717 5718 intel_psr_short_pulse(intel_dp); 5719 5720 if (intel_alpm_get_error(intel_dp)) { 5721 intel_alpm_disable(intel_dp); 5722 intel_dp->alpm.sink_alpm_error = true; 5723 } 5724 5725 if (intel_dp_test_short_pulse(intel_dp)) 5726 reprobe_needed = true; 5727 5728 return !reprobe_needed; 5729} 5730 5731/* XXX this is probably wrong for multiple downstream ports */ 5732static enum drm_connector_status 5733intel_dp_detect_dpcd(struct intel_dp *intel_dp) 5734{ 5735 struct intel_display *display = to_intel_display(intel_dp); 5736 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5737 u8 *dpcd = intel_dp->dpcd; 5738 u8 type; 5739 5740 if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp))) 5741 return connector_status_connected; 5742 5743 intel_lspcon_resume(dig_port); 5744 5745 if (!intel_dp_get_dpcd(intel_dp)) 5746 return connector_status_disconnected; 5747 5748 intel_dp->mst_detect = intel_dp_mst_detect(intel_dp); 5749 5750 /* if there's no downstream port, we're done */ 5751 if (!drm_dp_is_branch(dpcd)) 5752 return connector_status_connected; 5753 5754 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 5755 if (intel_dp_has_sink_count(intel_dp) && 5756 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 5757 return intel_dp->sink_count ? 5758 connector_status_connected : connector_status_disconnected; 5759 } 5760 5761 if (intel_dp->mst_detect == DRM_DP_MST) 5762 return connector_status_connected; 5763 5764 /* If no HPD, poke DDC gently */ 5765 if (drm_probe_ddc(&intel_dp->aux.ddc)) 5766 return connector_status_connected; 5767 5768 /* Well we tried, say unknown for unreliable port types */ 5769 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 5770 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 5771 if (type == DP_DS_PORT_TYPE_VGA || 5772 type == DP_DS_PORT_TYPE_NON_EDID) 5773 return connector_status_unknown; 5774 } else { 5775 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 5776 DP_DWN_STRM_PORT_TYPE_MASK; 5777 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 5778 type == DP_DWN_STRM_PORT_TYPE_OTHER) 5779 return connector_status_unknown; 5780 } 5781 5782 /* Anything else is out of spec, warn and ignore */ 5783 drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n"); 5784 return connector_status_disconnected; 5785} 5786 5787static enum drm_connector_status 5788edp_detect(struct intel_dp *intel_dp) 5789{ 5790 return connector_status_connected; 5791} 5792 5793void intel_digital_port_lock(struct intel_encoder *encoder) 5794{ 5795 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5796 5797 if (dig_port->lock) 5798 dig_port->lock(dig_port); 5799} 5800 5801void intel_digital_port_unlock(struct intel_encoder *encoder) 5802{ 5803 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5804 5805 if (dig_port->unlock) 5806 dig_port->unlock(dig_port); 5807} 5808 5809/* 5810 * intel_digital_port_connected_locked - is the specified port connected? 5811 * @encoder: intel_encoder 5812 * 5813 * In cases where there's a connector physically connected but it can't be used 5814 * by our hardware we also return false, since the rest of the driver should 5815 * pretty much treat the port as disconnected. This is relevant for type-C 5816 * (starting on ICL) where there's ownership involved. 5817 * 5818 * The caller must hold the lock acquired by calling intel_digital_port_lock() 5819 * when calling this function. 5820 * 5821 * Return %true if port is connected, %false otherwise. 5822 */ 5823bool intel_digital_port_connected_locked(struct intel_encoder *encoder) 5824{ 5825 struct intel_display *display = to_intel_display(encoder); 5826 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5827 bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port); 5828 bool is_connected = false; 5829 intel_wakeref_t wakeref; 5830 5831 with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { 5832 poll_timeout_us(is_connected = dig_port->connected(encoder), 5833 is_connected || is_glitch_free, 5834 30, 4000, false); 5835 } 5836 5837 return is_connected; 5838} 5839 5840bool intel_digital_port_connected(struct intel_encoder *encoder) 5841{ 5842 bool ret; 5843 5844 intel_digital_port_lock(encoder); 5845 ret = intel_digital_port_connected_locked(encoder); 5846 intel_digital_port_unlock(encoder); 5847 5848 return ret; 5849} 5850 5851static const struct drm_edid * 5852intel_dp_get_edid(struct intel_dp *intel_dp) 5853{ 5854 struct intel_connector *connector = intel_dp->attached_connector; 5855 const struct drm_edid *fixed_edid = connector->panel.fixed_edid; 5856 5857 /* Use panel fixed edid if we have one */ 5858 if (fixed_edid) { 5859 /* invalid edid */ 5860 if (IS_ERR(fixed_edid)) 5861 return NULL; 5862 5863 return drm_edid_dup(fixed_edid); 5864 } 5865 5866 return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc); 5867} 5868 5869static void 5870intel_dp_update_dfp(struct intel_dp *intel_dp, 5871 const struct drm_edid *drm_edid) 5872{ 5873 struct intel_display *display = to_intel_display(intel_dp); 5874 struct intel_connector *connector = intel_dp->attached_connector; 5875 5876 intel_dp->dfp.max_bpc = 5877 drm_dp_downstream_max_bpc(intel_dp->dpcd, 5878 intel_dp->downstream_ports, drm_edid); 5879 5880 intel_dp->dfp.max_dotclock = 5881 drm_dp_downstream_max_dotclock(intel_dp->dpcd, 5882 intel_dp->downstream_ports); 5883 5884 intel_dp->dfp.min_tmds_clock = 5885 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, 5886 intel_dp->downstream_ports, 5887 drm_edid); 5888 intel_dp->dfp.max_tmds_clock = 5889 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, 5890 intel_dp->downstream_ports, 5891 drm_edid); 5892 5893 intel_dp->dfp.pcon_max_frl_bw = 5894 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, 5895 intel_dp->downstream_ports); 5896 5897 drm_dbg_kms(display->drm, 5898 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n", 5899 connector->base.base.id, connector->base.name, 5900 intel_dp->dfp.max_bpc, 5901 intel_dp->dfp.max_dotclock, 5902 intel_dp->dfp.min_tmds_clock, 5903 intel_dp->dfp.max_tmds_clock, 5904 intel_dp->dfp.pcon_max_frl_bw); 5905 5906 intel_dp_get_pcon_dsc_cap(intel_dp); 5907} 5908 5909static bool 5910intel_dp_can_ycbcr420(struct intel_dp *intel_dp) 5911{ 5912 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) && 5913 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough)) 5914 return true; 5915 5916 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) && 5917 dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 5918 return true; 5919 5920 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) && 5921 dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) 5922 return true; 5923 5924 return false; 5925} 5926 5927static void 5928intel_dp_update_420(struct intel_dp *intel_dp) 5929{ 5930 struct intel_display *display = to_intel_display(intel_dp); 5931 struct intel_connector *connector = intel_dp->attached_connector; 5932 5933 intel_dp->dfp.ycbcr420_passthrough = 5934 drm_dp_downstream_420_passthrough(intel_dp->dpcd, 5935 intel_dp->downstream_ports); 5936 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ 5937 intel_dp->dfp.ycbcr_444_to_420 = 5938 intel_lspcon_active(dp_to_dig_port(intel_dp)) || 5939 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, 5940 intel_dp->downstream_ports); 5941 intel_dp->dfp.rgb_to_ycbcr = 5942 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, 5943 intel_dp->downstream_ports, 5944 DP_DS_HDMI_BT709_RGB_YCBCR_CONV); 5945 5946 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp); 5947 5948 drm_dbg_kms(display->drm, 5949 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n", 5950 connector->base.base.id, connector->base.name, 5951 str_yes_no(intel_dp->dfp.rgb_to_ycbcr), 5952 str_yes_no(connector->base.ycbcr_420_allowed), 5953 str_yes_no(intel_dp->dfp.ycbcr_444_to_420)); 5954} 5955 5956static void 5957intel_dp_set_edid(struct intel_dp *intel_dp) 5958{ 5959 struct intel_display *display = to_intel_display(intel_dp); 5960 struct intel_connector *connector = intel_dp->attached_connector; 5961 const struct drm_edid *drm_edid; 5962 bool vrr_capable; 5963 5964 intel_dp_unset_edid(intel_dp); 5965 drm_edid = intel_dp_get_edid(intel_dp); 5966 connector->detect_edid = drm_edid; 5967 5968 /* Below we depend on display info having been updated */ 5969 drm_edid_connector_update(&connector->base, drm_edid); 5970 5971 vrr_capable = intel_vrr_is_capable(connector); 5972 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n", 5973 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable)); 5974 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable); 5975 5976 intel_dp_update_dfp(intel_dp, drm_edid); 5977 intel_dp_update_420(intel_dp); 5978 5979 drm_dp_cec_attach(&intel_dp->aux, 5980 connector->base.display_info.source_physical_address); 5981} 5982 5983static void 5984intel_dp_unset_edid(struct intel_dp *intel_dp) 5985{ 5986 struct intel_connector *connector = intel_dp->attached_connector; 5987 5988 drm_dp_cec_unset_edid(&intel_dp->aux); 5989 drm_edid_free(connector->detect_edid); 5990 connector->detect_edid = NULL; 5991 5992 intel_dp->dfp.max_bpc = 0; 5993 intel_dp->dfp.max_dotclock = 0; 5994 intel_dp->dfp.min_tmds_clock = 0; 5995 intel_dp->dfp.max_tmds_clock = 0; 5996 5997 intel_dp->dfp.pcon_max_frl_bw = 0; 5998 5999 intel_dp->dfp.ycbcr_444_to_420 = false; 6000 connector->base.ycbcr_420_allowed = false; 6001 6002 drm_connector_set_vrr_capable_property(&connector->base, 6003 false); 6004} 6005 6006static void 6007intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) 6008{ 6009 struct intel_display *display = to_intel_display(intel_dp); 6010 6011 intel_dp->as_sdp_supported = HAS_AS_SDP(display) && 6012 drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd); 6013} 6014 6015static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external) 6016{ 6017 struct intel_connector *connector = intel_dp->attached_connector; 6018 6019 if (intel_dp_is_edp(intel_dp)) 6020 return false; 6021 6022 if (force_on_external) 6023 return true; 6024 6025 if (intel_dp->is_mst) 6026 return false; 6027 6028 return drm_edid_has_quirk(&connector->base, DRM_EDID_QUIRK_DP_DPCD_PROBE); 6029} 6030 6031void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external) 6032{ 6033 drm_dp_dpcd_set_probe(&intel_dp->aux, 6034 intel_dp_needs_dpcd_probe(intel_dp, force_on_external)); 6035} 6036 6037static int 6038intel_dp_detect(struct drm_connector *_connector, 6039 struct drm_modeset_acquire_ctx *ctx, 6040 bool force) 6041{ 6042 struct intel_display *display = to_intel_display(_connector->dev); 6043 struct intel_connector *connector = to_intel_connector(_connector); 6044 struct intel_dp *intel_dp = intel_attached_dp(connector); 6045 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 6046 struct intel_encoder *encoder = &dig_port->base; 6047 enum drm_connector_status status; 6048 int ret; 6049 6050 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 6051 connector->base.base.id, connector->base.name); 6052 drm_WARN_ON(display->drm, 6053 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 6054 6055 if (!intel_display_device_enabled(display)) 6056 return connector_status_disconnected; 6057 6058 if (!intel_display_driver_check_access(display)) 6059 return connector->base.status; 6060 6061 intel_dp_flush_connector_commits(connector); 6062 6063 intel_pps_vdd_on(intel_dp); 6064 6065 /* Can't disconnect eDP */ 6066 if (intel_dp_is_edp(intel_dp)) 6067 status = edp_detect(intel_dp); 6068 else if (intel_digital_port_connected(encoder)) 6069 status = intel_dp_detect_dpcd(intel_dp); 6070 else 6071 status = connector_status_disconnected; 6072 6073 if (status != connector_status_disconnected && 6074 !intel_dp_mst_verify_dpcd_state(intel_dp)) 6075 /* 6076 * This requires retrying detection for instance to re-enable 6077 * the MST mode that got reset via a long HPD pulse. The retry 6078 * will happen either via the hotplug handler's retry logic, 6079 * ensured by setting the connector here to SST/disconnected, 6080 * or via a userspace connector probing in response to the 6081 * hotplug uevent sent when removing the MST connectors. 6082 */ 6083 status = connector_status_disconnected; 6084 6085 if (status == connector_status_disconnected) { 6086 intel_dp_test_reset(intel_dp); 6087 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); 6088 intel_dp->psr.sink_panel_replay_support = false; 6089 intel_dp->psr.sink_panel_replay_su_support = false; 6090 intel_dp->psr.sink_panel_replay_dsc_support = 6091 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED; 6092 6093 intel_dp_mst_disconnect(intel_dp); 6094 6095 intel_dp_tunnel_disconnect(intel_dp); 6096 6097 goto out_unset_edid; 6098 } 6099 6100 intel_dp_init_source_oui(intel_dp); 6101 6102 ret = intel_dp_tunnel_detect(intel_dp, ctx); 6103 if (ret == -EDEADLK) { 6104 status = ret; 6105 6106 goto out_vdd_off; 6107 } 6108 6109 if (ret == 1) 6110 connector->base.epoch_counter++; 6111 6112 if (!intel_dp_is_edp(intel_dp)) 6113 intel_psr_init_dpcd(intel_dp); 6114 6115 intel_dp_detect_dsc_caps(intel_dp, connector); 6116 6117 intel_dp_detect_sdp_caps(intel_dp); 6118 6119 if (intel_dp->reset_link_params) { 6120 intel_dp_reset_link_params(intel_dp); 6121 intel_dp->reset_link_params = false; 6122 } 6123 6124 intel_dp_mst_configure(intel_dp); 6125 6126 intel_dp_print_rates(intel_dp); 6127 6128 if (intel_dp->is_mst) { 6129 /* 6130 * If we are in MST mode then this connector 6131 * won't appear connected or have anything 6132 * with EDID on it 6133 */ 6134 status = connector_status_disconnected; 6135 goto out_unset_edid; 6136 } 6137 6138 /* 6139 * Some external monitors do not signal loss of link synchronization 6140 * with an IRQ_HPD, so force a link status check. 6141 * 6142 * TODO: this probably became redundant, so remove it: the link state 6143 * is rechecked/recovered now after modesets, where the loss of 6144 * synchronization tends to occur. 6145 */ 6146 if (!intel_dp_is_edp(intel_dp)) 6147 intel_dp_check_link_state(intel_dp); 6148 6149 /* 6150 * Clearing NACK and defer counts to get their exact values 6151 * while reading EDID which are required by Compliance tests 6152 * 4.2.2.4 and 4.2.2.5 6153 */ 6154 intel_dp->aux.i2c_nack_count = 0; 6155 intel_dp->aux.i2c_defer_count = 0; 6156 6157 intel_dp_set_edid(intel_dp); 6158 if (intel_dp_is_edp(intel_dp) || connector->detect_edid) 6159 status = connector_status_connected; 6160 6161 intel_dp_check_device_service_irq(intel_dp); 6162 6163out_unset_edid: 6164 if (status != connector_status_connected && !intel_dp->is_mst) 6165 intel_dp_unset_edid(intel_dp); 6166 6167 intel_dp_dpcd_set_probe(intel_dp, false); 6168 6169 if (!intel_dp_is_edp(intel_dp)) 6170 drm_dp_set_subconnector_property(&connector->base, 6171 status, 6172 intel_dp->dpcd, 6173 intel_dp->downstream_ports); 6174out_vdd_off: 6175 intel_pps_vdd_off(intel_dp); 6176 6177 return status; 6178} 6179 6180static void 6181intel_dp_force(struct drm_connector *_connector) 6182{ 6183 struct intel_connector *connector = to_intel_connector(_connector); 6184 struct intel_display *display = to_intel_display(connector); 6185 struct intel_dp *intel_dp = intel_attached_dp(connector); 6186 6187 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 6188 connector->base.base.id, connector->base.name); 6189 6190 if (!intel_display_driver_check_access(display)) 6191 return; 6192 6193 intel_dp_unset_edid(intel_dp); 6194 6195 if (connector->base.status != connector_status_connected) 6196 return; 6197 6198 intel_dp_set_edid(intel_dp); 6199 6200 intel_dp_dpcd_set_probe(intel_dp, false); 6201} 6202 6203static int intel_dp_get_modes(struct drm_connector *_connector) 6204{ 6205 struct intel_display *display = to_intel_display(_connector->dev); 6206 struct intel_connector *connector = to_intel_connector(_connector); 6207 struct intel_dp *intel_dp = intel_attached_dp(connector); 6208 int num_modes; 6209 6210 /* drm_edid_connector_update() done in ->detect() or ->force() */ 6211 num_modes = drm_edid_connector_add_modes(&connector->base); 6212 6213 /* Also add fixed mode, which may or may not be present in EDID */ 6214 if (intel_dp_is_edp(intel_dp)) 6215 num_modes += intel_panel_get_modes(connector); 6216 6217 if (num_modes) 6218 return num_modes; 6219 6220 if (!connector->detect_edid) { 6221 struct drm_display_mode *mode; 6222 6223 mode = drm_dp_downstream_mode(display->drm, 6224 intel_dp->dpcd, 6225 intel_dp->downstream_ports); 6226 if (mode) { 6227 drm_mode_probed_add(&connector->base, mode); 6228 num_modes++; 6229 } 6230 } 6231 6232 return num_modes; 6233} 6234 6235static int 6236intel_dp_connector_register(struct drm_connector *_connector) 6237{ 6238 struct intel_connector *connector = to_intel_connector(_connector); 6239 struct intel_display *display = to_intel_display(connector); 6240 struct intel_dp *intel_dp = intel_attached_dp(connector); 6241 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 6242 int ret; 6243 6244 ret = intel_connector_register(&connector->base); 6245 if (ret) 6246 return ret; 6247 6248 drm_dbg_kms(display->drm, "registering %s bus for %s\n", 6249 intel_dp->aux.name, connector->base.kdev->kobj.name); 6250 6251 intel_dp->aux.dev = connector->base.kdev; 6252 ret = drm_dp_aux_register(&intel_dp->aux); 6253 if (!ret) 6254 drm_dp_cec_register_connector(&intel_dp->aux, &connector->base); 6255 6256 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata)) 6257 return ret; 6258 6259 /* 6260 * ToDo: Clean this up to handle lspcon init and resume more 6261 * efficiently and streamlined. 6262 */ 6263 if (intel_lspcon_init(dig_port)) { 6264 if (intel_lspcon_detect_hdr_capability(dig_port)) 6265 drm_connector_attach_hdr_output_metadata_property(&connector->base); 6266 } 6267 6268 return ret; 6269} 6270 6271static void 6272intel_dp_connector_unregister(struct drm_connector *_connector) 6273{ 6274 struct intel_connector *connector = to_intel_connector(_connector); 6275 struct intel_dp *intel_dp = intel_attached_dp(connector); 6276 6277 drm_dp_cec_unregister_connector(&intel_dp->aux); 6278 drm_dp_aux_unregister(&intel_dp->aux); 6279 intel_connector_unregister(&connector->base); 6280} 6281 6282void intel_dp_connector_sync_state(struct intel_connector *connector, 6283 const struct intel_crtc_state *crtc_state) 6284{ 6285 struct intel_display *display = to_intel_display(connector); 6286 6287 if (crtc_state && crtc_state->dsc.compression_enable) { 6288 drm_WARN_ON(display->drm, 6289 !connector->dp.dsc_decompression_aux); 6290 connector->dp.dsc_decompression_enabled = true; 6291 } else { 6292 connector->dp.dsc_decompression_enabled = false; 6293 } 6294} 6295 6296void intel_dp_encoder_flush_work(struct drm_encoder *_encoder) 6297{ 6298 struct intel_encoder *encoder = to_intel_encoder(_encoder); 6299 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 6300 struct intel_dp *intel_dp = &dig_port->dp; 6301 6302 intel_encoder_link_check_flush_work(encoder); 6303 6304 intel_dp_mst_encoder_cleanup(dig_port); 6305 6306 intel_dp_tunnel_destroy(intel_dp); 6307 6308 intel_pps_vdd_off_sync(intel_dp); 6309 6310 /* 6311 * Ensure power off delay is respected on module remove, so that we can 6312 * reduce delays at driver probe. See pps_init_timestamps(). 6313 */ 6314 intel_pps_wait_power_cycle(intel_dp); 6315 6316 intel_dp_aux_fini(intel_dp); 6317} 6318 6319void intel_dp_encoder_suspend(struct intel_encoder *encoder) 6320{ 6321 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 6322 6323 intel_pps_vdd_off_sync(intel_dp); 6324 6325 intel_dp_tunnel_suspend(intel_dp); 6326} 6327 6328void intel_dp_encoder_shutdown(struct intel_encoder *encoder) 6329{ 6330 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 6331 6332 intel_pps_wait_power_cycle(intel_dp); 6333} 6334 6335static int intel_modeset_tile_group(struct intel_atomic_state *state, 6336 int tile_group_id) 6337{ 6338 struct intel_display *display = to_intel_display(state); 6339 struct drm_connector_list_iter conn_iter; 6340 struct intel_connector *connector; 6341 int ret = 0; 6342 6343 drm_connector_list_iter_begin(display->drm, &conn_iter); 6344 for_each_intel_connector_iter(connector, &conn_iter) { 6345 struct drm_connector_state *conn_state; 6346 struct intel_crtc_state *crtc_state; 6347 struct intel_crtc *crtc; 6348 6349 if (!connector->base.has_tile || 6350 connector->base.tile_group->id != tile_group_id) 6351 continue; 6352 6353 conn_state = drm_atomic_get_connector_state(&state->base, 6354 &connector->base); 6355 if (IS_ERR(conn_state)) { 6356 ret = PTR_ERR(conn_state); 6357 break; 6358 } 6359 6360 crtc = to_intel_crtc(conn_state->crtc); 6361 6362 if (!crtc) 6363 continue; 6364 6365 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6366 crtc_state->uapi.mode_changed = true; 6367 6368 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 6369 if (ret) 6370 break; 6371 } 6372 drm_connector_list_iter_end(&conn_iter); 6373 6374 return ret; 6375} 6376 6377static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders) 6378{ 6379 struct intel_display *display = to_intel_display(state); 6380 struct intel_crtc *crtc; 6381 6382 if (transcoders == 0) 6383 return 0; 6384 6385 for_each_intel_crtc(display->drm, crtc) { 6386 struct intel_crtc_state *crtc_state; 6387 int ret; 6388 6389 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6390 if (IS_ERR(crtc_state)) 6391 return PTR_ERR(crtc_state); 6392 6393 if (!crtc_state->hw.enable) 6394 continue; 6395 6396 if (!(transcoders & BIT(crtc_state->cpu_transcoder))) 6397 continue; 6398 6399 crtc_state->uapi.mode_changed = true; 6400 6401 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6402 if (ret) 6403 return ret; 6404 6405 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 6406 if (ret) 6407 return ret; 6408 6409 transcoders &= ~BIT(crtc_state->cpu_transcoder); 6410 } 6411 6412 drm_WARN_ON(display->drm, transcoders != 0); 6413 6414 return 0; 6415} 6416 6417static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, 6418 struct drm_connector *_connector) 6419{ 6420 struct intel_connector *connector = to_intel_connector(_connector); 6421 const struct drm_connector_state *old_conn_state = 6422 drm_atomic_get_old_connector_state(&state->base, &connector->base); 6423 const struct intel_crtc_state *old_crtc_state; 6424 struct intel_crtc *crtc; 6425 u8 transcoders; 6426 6427 crtc = to_intel_crtc(old_conn_state->crtc); 6428 if (!crtc) 6429 return 0; 6430 6431 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6432 6433 if (!old_crtc_state->hw.active) 6434 return 0; 6435 6436 transcoders = old_crtc_state->sync_mode_slaves_mask; 6437 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) 6438 transcoders |= BIT(old_crtc_state->master_transcoder); 6439 6440 return intel_modeset_affected_transcoders(state, 6441 transcoders); 6442} 6443 6444static int intel_dp_connector_atomic_check(struct drm_connector *_connector, 6445 struct drm_atomic_state *_state) 6446{ 6447 struct intel_connector *connector = to_intel_connector(_connector); 6448 struct intel_display *display = to_intel_display(connector); 6449 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6450 struct drm_connector_state *conn_state = 6451 drm_atomic_get_new_connector_state(_state, &connector->base); 6452 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); 6453 int ret; 6454 6455 ret = intel_digital_connector_atomic_check(&connector->base, &state->base); 6456 if (ret) 6457 return ret; 6458 6459 if (intel_dp_mst_source_support(intel_dp)) { 6460 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst.mgr); 6461 if (ret) 6462 return ret; 6463 } 6464 6465 if (!intel_connector_needs_modeset(state, &connector->base)) 6466 return 0; 6467 6468 ret = intel_dp_tunnel_atomic_check_state(state, 6469 intel_dp, 6470 connector); 6471 if (ret) 6472 return ret; 6473 6474 /* 6475 * We don't enable port sync on BDW due to missing w/as and 6476 * due to not having adjusted the modeset sequence appropriately. 6477 */ 6478 if (DISPLAY_VER(display) < 9) 6479 return 0; 6480 6481 if (connector->base.has_tile) { 6482 ret = intel_modeset_tile_group(state, connector->base.tile_group->id); 6483 if (ret) 6484 return ret; 6485 } 6486 6487 return intel_modeset_synced_crtcs(state, &connector->base); 6488} 6489 6490static void intel_dp_oob_hotplug_event(struct drm_connector *_connector, 6491 enum drm_connector_status hpd_state) 6492{ 6493 struct intel_connector *connector = to_intel_connector(_connector); 6494 struct intel_display *display = to_intel_display(connector); 6495 struct intel_encoder *encoder = intel_attached_encoder(connector); 6496 bool hpd_high = hpd_state == connector_status_connected; 6497 unsigned int hpd_pin = encoder->hpd_pin; 6498 bool need_work = false; 6499 6500 spin_lock_irq(&display->irq.lock); 6501 if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) { 6502 display->hotplug.event_bits |= BIT(hpd_pin); 6503 6504 __assign_bit(hpd_pin, 6505 &display->hotplug.oob_hotplug_last_state, 6506 hpd_high); 6507 need_work = true; 6508 } 6509 spin_unlock_irq(&display->irq.lock); 6510 6511 if (need_work) 6512 intel_hpd_schedule_detection(display); 6513} 6514 6515static const struct drm_connector_funcs intel_dp_connector_funcs = { 6516 .force = intel_dp_force, 6517 .fill_modes = drm_helper_probe_single_connector_modes, 6518 .atomic_get_property = intel_digital_connector_atomic_get_property, 6519 .atomic_set_property = intel_digital_connector_atomic_set_property, 6520 .late_register = intel_dp_connector_register, 6521 .early_unregister = intel_dp_connector_unregister, 6522 .destroy = intel_connector_destroy, 6523 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6524 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 6525 .oob_hotplug_event = intel_dp_oob_hotplug_event, 6526}; 6527 6528static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 6529 .detect_ctx = intel_dp_detect, 6530 .get_modes = intel_dp_get_modes, 6531 .mode_valid = intel_dp_mode_valid, 6532 .atomic_check = intel_dp_connector_atomic_check, 6533}; 6534 6535enum irqreturn 6536intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) 6537{ 6538 struct intel_display *display = to_intel_display(dig_port); 6539 struct intel_dp *intel_dp = &dig_port->dp; 6540 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 6541 6542 if (dig_port->base.type == INTEL_OUTPUT_EDP && 6543 (long_hpd || 6544 intel_display_rpm_suspended(display) || 6545 !intel_pps_have_panel_power_or_vdd(intel_dp))) { 6546 /* 6547 * vdd off can generate a long/short pulse on eDP which 6548 * would require vdd on to handle it, and thus we 6549 * would end up in an endless cycle of 6550 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..." 6551 */ 6552 drm_dbg_kms(display->drm, 6553 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", 6554 long_hpd ? "long" : "short", 6555 dig_port->base.base.base.id, 6556 dig_port->base.base.name); 6557 return IRQ_HANDLED; 6558 } 6559 6560 drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", 6561 dig_port->base.base.base.id, 6562 dig_port->base.base.name, 6563 long_hpd ? "long" : "short"); 6564 6565 /* 6566 * TBT DP tunnels require the GFX driver to read out the DPRX caps in 6567 * response to long HPD pulses. The DP hotplug handler does that, 6568 * however the hotplug handler may be blocked by another 6569 * connector's/encoder's hotplug handler. Since the TBT CM may not 6570 * complete the DP tunnel BW request for the latter connector/encoder 6571 * waiting for this encoder's DPRX read, perform a dummy read here. 6572 */ 6573 if (long_hpd) { 6574 intel_dp_dpcd_set_probe(intel_dp, true); 6575 6576 intel_dp_read_dprx_caps(intel_dp, dpcd); 6577 6578 intel_dp->reset_link_params = true; 6579 intel_dp_invalidate_source_oui(intel_dp); 6580 6581 return IRQ_NONE; 6582 } 6583 6584 if (intel_dp->is_mst) { 6585 if (!intel_dp_check_mst_status(intel_dp)) 6586 return IRQ_NONE; 6587 } else if (!intel_dp_short_pulse(intel_dp)) { 6588 return IRQ_NONE; 6589 } 6590 6591 return IRQ_HANDLED; 6592} 6593 6594static bool _intel_dp_is_port_edp(struct intel_display *display, 6595 const struct intel_bios_encoder_data *devdata, 6596 enum port port) 6597{ 6598 /* 6599 * eDP not supported on g4x. so bail out early just 6600 * for a bit extra safety in case the VBT is bonkers. 6601 */ 6602 if (DISPLAY_VER(display) < 5) 6603 return false; 6604 6605 if (DISPLAY_VER(display) < 9 && port == PORT_A) 6606 return true; 6607 6608 return devdata && intel_bios_encoder_supports_edp(devdata); 6609} 6610 6611bool intel_dp_is_port_edp(struct intel_display *display, enum port port) 6612{ 6613 const struct intel_bios_encoder_data *devdata = 6614 intel_bios_encoder_data_lookup(display, port); 6615 6616 return _intel_dp_is_port_edp(display, devdata, port); 6617} 6618 6619bool 6620intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder) 6621{ 6622 struct intel_display *display = to_intel_display(encoder); 6623 enum port port = encoder->port; 6624 6625 if (intel_bios_encoder_is_lspcon(encoder->devdata)) 6626 return false; 6627 6628 if (DISPLAY_VER(display) >= 11) 6629 return true; 6630 6631 if (port == PORT_A) 6632 return false; 6633 6634 if (display->platform.haswell || display->platform.broadwell || 6635 DISPLAY_VER(display) >= 9) 6636 return true; 6637 6638 return false; 6639} 6640 6641static void 6642intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *_connector) 6643{ 6644 struct intel_connector *connector = to_intel_connector(_connector); 6645 struct intel_display *display = to_intel_display(intel_dp); 6646 enum port port = dp_to_dig_port(intel_dp)->base.port; 6647 6648 if (!intel_dp_is_edp(intel_dp)) 6649 drm_connector_attach_dp_subconnector_property(&connector->base); 6650 6651 if (!display->platform.g4x && port != PORT_A) 6652 intel_attach_force_audio_property(&connector->base); 6653 6654 intel_attach_broadcast_rgb_property(&connector->base); 6655 if (HAS_GMCH(display)) 6656 drm_connector_attach_max_bpc_property(&connector->base, 6, 10); 6657 else if (DISPLAY_VER(display) >= 5) 6658 drm_connector_attach_max_bpc_property(&connector->base, 6, 12); 6659 6660 /* Register HDMI colorspace for case of lspcon */ 6661 if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) { 6662 drm_connector_attach_content_type_property(&connector->base); 6663 intel_attach_hdmi_colorspace_property(&connector->base); 6664 } else { 6665 intel_attach_dp_colorspace_property(&connector->base); 6666 } 6667 6668 if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base)) 6669 drm_connector_attach_hdr_output_metadata_property(&connector->base); 6670 6671 if (HAS_VRR(display)) 6672 drm_connector_attach_vrr_capable_property(&connector->base); 6673} 6674 6675static void 6676intel_edp_add_properties(struct intel_dp *intel_dp) 6677{ 6678 struct intel_display *display = to_intel_display(intel_dp); 6679 struct intel_connector *connector = intel_dp->attached_connector; 6680 const struct drm_display_mode *fixed_mode = 6681 intel_panel_preferred_fixed_mode(connector); 6682 6683 intel_attach_scaling_mode_property(&connector->base); 6684 6685 drm_connector_set_panel_orientation_with_quirk(&connector->base, 6686 display->vbt.orientation, 6687 fixed_mode->hdisplay, 6688 fixed_mode->vdisplay); 6689} 6690 6691static void intel_edp_backlight_setup(struct intel_dp *intel_dp, 6692 struct intel_connector *connector) 6693{ 6694 struct intel_display *display = to_intel_display(intel_dp); 6695 enum pipe pipe = INVALID_PIPE; 6696 6697 if (display->platform.valleyview || display->platform.cherryview) 6698 pipe = vlv_pps_backlight_initial_pipe(intel_dp); 6699 6700 intel_backlight_setup(connector, pipe); 6701} 6702 6703static bool intel_edp_init_connector(struct intel_dp *intel_dp, 6704 struct intel_connector *connector) 6705{ 6706 struct intel_display *display = to_intel_display(intel_dp); 6707 struct drm_display_mode *fixed_mode; 6708 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 6709 bool has_dpcd; 6710 const struct drm_edid *drm_edid; 6711 6712 if (!intel_dp_is_edp(intel_dp)) 6713 return true; 6714 6715 /* 6716 * On IBX/CPT we may get here with LVDS already registered. Since the 6717 * driver uses the only internal power sequencer available for both 6718 * eDP and LVDS bail out early in this case to prevent interfering 6719 * with an already powered-on LVDS power sequencer. 6720 */ 6721 if (intel_get_lvds_encoder(display)) { 6722 drm_WARN_ON(display->drm, 6723 !(HAS_PCH_IBX(display) || HAS_PCH_CPT(display))); 6724 drm_info(display->drm, 6725 "LVDS was detected, not registering eDP\n"); 6726 6727 return false; 6728 } 6729 6730 intel_bios_init_panel_early(display, &connector->panel, 6731 encoder->devdata); 6732 6733 if (!intel_pps_init(intel_dp)) { 6734 drm_info(display->drm, 6735 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n", 6736 encoder->base.base.id, encoder->base.name); 6737 /* 6738 * The BIOS may have still enabled VDD on the PPS even 6739 * though it's unusable. Make sure we turn it back off 6740 * and to release the power domain references/etc. 6741 */ 6742 goto out_vdd_off; 6743 } 6744 6745 /* 6746 * Enable HPD sense for live status check. 6747 * intel_hpd_irq_setup() will turn it off again 6748 * if it's no longer needed later. 6749 * 6750 * The DPCD probe below will make sure VDD is on. 6751 */ 6752 intel_hpd_enable_detection(encoder); 6753 6754 intel_alpm_init(intel_dp); 6755 6756 /* Cache DPCD and EDID for edp. */ 6757 has_dpcd = intel_edp_init_dpcd(intel_dp, connector); 6758 6759 if (!has_dpcd) { 6760 /* if this fails, presume the device is a ghost */ 6761 drm_info(display->drm, 6762 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n", 6763 encoder->base.base.id, encoder->base.name); 6764 goto out_vdd_off; 6765 } 6766 6767 /* 6768 * VBT and straps are liars. Also check HPD as that seems 6769 * to be the most reliable piece of information available. 6770 * 6771 * ... expect on devices that forgot to hook HPD up for eDP 6772 * (eg. Acer Chromebook C710), so we'll check it only if multiple 6773 * ports are attempting to use the same AUX CH, according to VBT. 6774 */ 6775 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) { 6776 /* 6777 * If this fails, presume the DPCD answer came 6778 * from some other port using the same AUX CH. 6779 * 6780 * FIXME maybe cleaner to check this before the 6781 * DPCD read? Would need sort out the VDD handling... 6782 */ 6783 if (!intel_digital_port_connected(encoder)) { 6784 drm_info(display->drm, 6785 "[ENCODER:%d:%s] HPD is down, disabling eDP\n", 6786 encoder->base.base.id, encoder->base.name); 6787 goto out_vdd_off; 6788 } 6789 6790 /* 6791 * Unfortunately even the HPD based detection fails on 6792 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall 6793 * back to checking for a VGA branch device. Only do this 6794 * on known affected platforms to minimize false positives. 6795 */ 6796 if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) && 6797 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) == 6798 DP_DWN_STRM_PORT_TYPE_ANALOG) { 6799 drm_info(display->drm, 6800 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n", 6801 encoder->base.base.id, encoder->base.name); 6802 goto out_vdd_off; 6803 } 6804 } 6805 6806 mutex_lock(&display->drm->mode_config.mutex); 6807 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc); 6808 if (!drm_edid) { 6809 /* Fallback to EDID from ACPI OpRegion, if any */ 6810 drm_edid = intel_opregion_get_edid(connector); 6811 if (drm_edid) 6812 drm_dbg_kms(display->drm, 6813 "[CONNECTOR:%d:%s] Using OpRegion EDID\n", 6814 connector->base.base.id, connector->base.name); 6815 } 6816 if (drm_edid) { 6817 if (drm_edid_connector_update(&connector->base, drm_edid) || 6818 !drm_edid_connector_add_modes(&connector->base)) { 6819 drm_edid_connector_update(&connector->base, NULL); 6820 drm_edid_free(drm_edid); 6821 drm_edid = ERR_PTR(-EINVAL); 6822 } 6823 } else { 6824 drm_edid = ERR_PTR(-ENOENT); 6825 } 6826 6827 intel_bios_init_panel_late(display, &connector->panel, encoder->devdata, 6828 IS_ERR(drm_edid) ? NULL : drm_edid); 6829 6830 intel_panel_add_edid_fixed_modes(connector, true); 6831 6832 /* MSO requires information from the EDID */ 6833 intel_edp_mso_init(intel_dp); 6834 6835 /* multiply the mode clock and horizontal timings for MSO */ 6836 list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) 6837 intel_edp_mso_mode_fixup(connector, fixed_mode); 6838 6839 /* fallback to VBT if available for eDP */ 6840 if (!intel_panel_preferred_fixed_mode(connector)) 6841 intel_panel_add_vbt_lfp_fixed_mode(connector); 6842 6843 mutex_unlock(&display->drm->mode_config.mutex); 6844 6845 if (!intel_panel_preferred_fixed_mode(connector)) { 6846 drm_info(display->drm, 6847 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n", 6848 encoder->base.base.id, encoder->base.name); 6849 goto out_vdd_off; 6850 } 6851 6852 intel_panel_init(connector, drm_edid); 6853 6854 intel_edp_backlight_setup(intel_dp, connector); 6855 6856 intel_edp_add_properties(intel_dp); 6857 6858 intel_pps_init_late(intel_dp); 6859 6860 return true; 6861 6862out_vdd_off: 6863 intel_pps_vdd_off_sync(intel_dp); 6864 intel_bios_fini_panel(&connector->panel); 6865 6866 return false; 6867} 6868 6869bool 6870intel_dp_init_connector(struct intel_digital_port *dig_port, 6871 struct intel_connector *connector) 6872{ 6873 struct intel_display *display = to_intel_display(dig_port); 6874 struct intel_dp *intel_dp = &dig_port->dp; 6875 struct intel_encoder *encoder = &dig_port->base; 6876 struct drm_device *dev = encoder->base.dev; 6877 enum port port = encoder->port; 6878 int type; 6879 6880 if (drm_WARN(dev, dig_port->max_lanes < 1, 6881 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", 6882 dig_port->max_lanes, encoder->base.base.id, 6883 encoder->base.name)) 6884 return false; 6885 6886 intel_dp->reset_link_params = true; 6887 6888 /* Preserve the current hw state. */ 6889 intel_dp->DP = intel_de_read(display, intel_dp->output_reg); 6890 intel_dp->attached_connector = connector; 6891 6892 if (_intel_dp_is_port_edp(display, encoder->devdata, port)) { 6893 /* 6894 * Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30, 6895 * although in theory it could work on TypeC legacy ports. 6896 */ 6897 drm_WARN_ON(dev, intel_encoder_is_tc(encoder) && 6898 DISPLAY_VER(display) < 30); 6899 type = DRM_MODE_CONNECTOR_eDP; 6900 encoder->type = INTEL_OUTPUT_EDP; 6901 6902 /* eDP only on port B and/or C on vlv/chv */ 6903 if (drm_WARN_ON(dev, (display->platform.valleyview || 6904 display->platform.cherryview) && 6905 port != PORT_B && port != PORT_C)) 6906 return false; 6907 } else { 6908 type = DRM_MODE_CONNECTOR_DisplayPort; 6909 } 6910 6911 intel_dp_set_default_sink_rates(intel_dp); 6912 intel_dp_set_default_max_sink_lane_count(intel_dp); 6913 6914 if (display->platform.valleyview || display->platform.cherryview) 6915 vlv_pps_pipe_init(intel_dp); 6916 6917 intel_dp_aux_init(intel_dp); 6918 connector->dp.dsc_decompression_aux = &intel_dp->aux; 6919 6920 drm_dbg_kms(display->drm, 6921 "Adding %s connector on [ENCODER:%d:%s]\n", 6922 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 6923 encoder->base.base.id, encoder->base.name); 6924 6925 drm_connector_init_with_ddc(dev, &connector->base, &intel_dp_connector_funcs, 6926 type, &intel_dp->aux.ddc); 6927 drm_connector_helper_add(&connector->base, &intel_dp_connector_helper_funcs); 6928 6929 if (!HAS_GMCH(display) && DISPLAY_VER(display) < 12) 6930 connector->base.interlace_allowed = true; 6931 6932 if (type != DRM_MODE_CONNECTOR_eDP) 6933 connector->polled = DRM_CONNECTOR_POLL_HPD; 6934 connector->base.polled = connector->polled; 6935 6936 intel_connector_attach_encoder(connector, encoder); 6937 6938 if (HAS_DDI(display)) 6939 connector->get_hw_state = intel_ddi_connector_get_hw_state; 6940 else 6941 connector->get_hw_state = intel_connector_get_hw_state; 6942 connector->sync_state = intel_dp_connector_sync_state; 6943 6944 if (!intel_edp_init_connector(intel_dp, connector)) { 6945 intel_dp_aux_fini(intel_dp); 6946 goto fail; 6947 } 6948 6949 intel_dp_set_source_rates(intel_dp); 6950 intel_dp_set_common_rates(intel_dp); 6951 intel_dp_reset_link_params(intel_dp); 6952 6953 /* init MST on ports that can support it */ 6954 intel_dp_mst_encoder_init(dig_port, connector->base.base.id); 6955 6956 intel_dp_add_properties(intel_dp, &connector->base); 6957 6958 if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) { 6959 int ret = intel_dp_hdcp_init(dig_port, connector); 6960 if (ret) 6961 drm_dbg_kms(display->drm, 6962 "HDCP init failed, skipping.\n"); 6963 } 6964 6965 intel_dp->frl.is_trained = false; 6966 intel_dp->frl.trained_rate_gbps = 0; 6967 6968 intel_psr_init(intel_dp); 6969 6970 return true; 6971 6972fail: 6973 intel_display_power_flush_work(display); 6974 drm_connector_cleanup(&connector->base); 6975 6976 return false; 6977} 6978 6979void intel_dp_mst_suspend(struct intel_display *display) 6980{ 6981 struct intel_encoder *encoder; 6982 6983 if (!HAS_DISPLAY(display)) 6984 return; 6985 6986 for_each_intel_encoder(display->drm, encoder) { 6987 struct intel_dp *intel_dp; 6988 6989 if (encoder->type != INTEL_OUTPUT_DDI) 6990 continue; 6991 6992 intel_dp = enc_to_intel_dp(encoder); 6993 6994 if (!intel_dp_mst_source_support(intel_dp)) 6995 continue; 6996 6997 if (intel_dp->is_mst) 6998 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst.mgr); 6999 } 7000} 7001 7002void intel_dp_mst_resume(struct intel_display *display) 7003{ 7004 struct intel_encoder *encoder; 7005 7006 if (!HAS_DISPLAY(display)) 7007 return; 7008 7009 for_each_intel_encoder(display->drm, encoder) { 7010 struct intel_dp *intel_dp; 7011 int ret; 7012 7013 if (encoder->type != INTEL_OUTPUT_DDI) 7014 continue; 7015 7016 intel_dp = enc_to_intel_dp(encoder); 7017 7018 if (!intel_dp_mst_source_support(intel_dp)) 7019 continue; 7020 7021 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst.mgr, true); 7022 if (ret) { 7023 intel_dp->is_mst = false; 7024 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, false); 7025 } 7026 } 7027} 7028 7029static 7030int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state) 7031{ 7032 struct intel_display *display = to_intel_display(crtc_state); 7033 int guardband = intel_crtc_vblank_length(crtc_state); 7034 int min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, false); 7035 7036 if (guardband < min_sdp_guardband) { 7037 drm_dbg_kms(display->drm, "guardband %d < min sdp guardband %d\n", 7038 guardband, min_sdp_guardband); 7039 return -EINVAL; 7040 } 7041 7042 return 0; 7043} 7044 7045int intel_dp_compute_config_late(struct intel_encoder *encoder, 7046 struct intel_crtc_state *crtc_state, 7047 struct drm_connector_state *conn_state) 7048{ 7049 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 7050 int ret; 7051 7052 intel_psr_compute_config_late(intel_dp, crtc_state); 7053 7054 ret = intel_dp_sdp_compute_config_late(crtc_state); 7055 if (ret) 7056 return ret; 7057 7058 return 0; 7059} 7060 7061static 7062int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 type) 7063{ 7064 switch (type) { 7065 case DP_SDP_VSC_EXT_VESA: 7066 case DP_SDP_VSC_EXT_CEA: 7067 return 10; 7068 case HDMI_PACKET_TYPE_GAMUT_METADATA: 7069 return 8; 7070 case DP_SDP_PPS: 7071 return 7; 7072 case DP_SDP_ADAPTIVE_SYNC: 7073 return crtc_state->vrr.vsync_start + 1; 7074 default: 7075 break; 7076 } 7077 7078 return 0; 7079} 7080 7081int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state, 7082 bool assume_all_enabled) 7083{ 7084 struct intel_display *display = to_intel_display(crtc_state); 7085 int sdp_guardband = 0; 7086 7087 if (assume_all_enabled || 7088 crtc_state->infoframes.enable & 7089 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 7090 sdp_guardband = max(sdp_guardband, 7091 intel_dp_get_lines_for_sdp(crtc_state, 7092 HDMI_PACKET_TYPE_GAMUT_METADATA)); 7093 7094 if (assume_all_enabled || 7095 crtc_state->dsc.compression_enable) 7096 sdp_guardband = max(sdp_guardband, 7097 intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_PPS)); 7098 7099 if ((assume_all_enabled && HAS_AS_SDP(display)) || 7100 crtc_state->infoframes.enable & intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)) 7101 sdp_guardband = max(sdp_guardband, 7102 intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_ADAPTIVE_SYNC)); 7103 7104 return sdp_guardband; 7105}
~/
Read-only file preview.