intel_dkl_phy_regs.h

  1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2022 Intel Corporation
  4 */
  5
  6#ifndef __INTEL_DKL_PHY_REGS__
  7#define __INTEL_DKL_PHY_REGS__
  8
  9#include <linux/types.h>
 10
 11#include "intel_display_reg_defs.h"
 12
 13struct intel_dkl_phy_reg {
 14	u32 reg:24;
 15	u32 bank_idx:4;
 16};
 17
 18#define _DKL_PHY1_BASE					0x168000
 19#define _DKL_PHY2_BASE					0x169000
 20#define _DKL_PHY3_BASE					0x16A000
 21#define _DKL_PHY4_BASE					0x16B000
 22#define _DKL_PHY5_BASE					0x16C000
 23#define _DKL_PHY6_BASE					0x16D000
 24
 25#define DKL_REG_TC_PORT(__reg) \
 26	(TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - _DKL_PHY1_BASE))
 27
 28/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
 29#define DKL_REG_MMIO(__reg)				_MMIO((__reg).reg)
 30
 31#define _DKL_REG_PHY_BASE(tc_port)			_PORT(tc_port, \
 32							      _DKL_PHY1_BASE, \
 33							      _DKL_PHY2_BASE)
 34
 35#define _DKL_BANK_SHIFT					12
 36#define _DKL_REG_BANK_OFFSET(phy_offset) \
 37	((phy_offset) & ((1 << _DKL_BANK_SHIFT) - 1))
 38#define _DKL_REG_BANK_IDX(phy_offset) \
 39	(((phy_offset) >> _DKL_BANK_SHIFT) & 0xf)
 40
 41#define _DKL_REG(tc_port, phy_offset)	\
 42	((const struct intel_dkl_phy_reg) { \
 43		.reg = _DKL_REG_PHY_BASE(tc_port) + \
 44		       _DKL_REG_BANK_OFFSET(phy_offset), \
 45		.bank_idx = _DKL_REG_BANK_IDX(phy_offset), \
 46	})
 47
 48#define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \
 49	_DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs)))
 50
 51#define _DKL_PCS_DW5_LN0				0x0014
 52#define _DKL_PCS_DW5_LN1				0x1014
 53#define DKL_PCS_DW5(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
 54								    _DKL_PCS_DW5_LN0, \
 55								    _DKL_PCS_DW5_LN1)
 56#define   DKL_PCS_DW5_CORE_SOFTRESET			REG_BIT(11)
 57
 58#define _DKL_PLL_DIV0					0x2200
 59#define DKL_PLL_DIV0(tc_port)				_DKL_REG(tc_port, \
 60								 _DKL_PLL_DIV0)
 61#define   DKL_PLL_DIV0_AFC_STARTUP_MASK			REG_GENMASK(27, 25)
 62#define   DKL_PLL_DIV0_AFC_STARTUP(val)			REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val))
 63#define   DKL_PLL_DIV0_INTEG_COEFF(x)			((x) << 16)
 64#define   DKL_PLL_DIV0_INTEG_COEFF_MASK			(0x1F << 16)
 65#define   DKL_PLL_DIV0_PROP_COEFF(x)			((x) << 12)
 66#define   DKL_PLL_DIV0_PROP_COEFF_MASK			(0xF << 12)
 67#define   DKL_PLL_DIV0_FBPREDIV_SHIFT			(8)
 68#define   DKL_PLL_DIV0_FBPREDIV(x)			((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT)
 69#define   DKL_PLL_DIV0_FBPREDIV_MASK			(0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
 70#define   DKL_PLL_DIV0_FBDIV_INT(x)			((x) << 0)
 71#define   DKL_PLL_DIV0_FBDIV_INT_MASK			(0xFF << 0)
 72#define   DKL_PLL_DIV0_MASK				(DKL_PLL_DIV0_INTEG_COEFF_MASK | \
 73							 DKL_PLL_DIV0_PROP_COEFF_MASK | \
 74							 DKL_PLL_DIV0_FBPREDIV_MASK | \
 75							 DKL_PLL_DIV0_FBDIV_INT_MASK)
 76
 77#define _DKL_PLL_DIV1					0x2204
 78#define DKL_PLL_DIV1(tc_port)				_DKL_REG(tc_port, \
 79								 _DKL_PLL_DIV1)
 80#define   DKL_PLL_DIV1_IREF_TRIM(x)			((x) << 16)
 81#define   DKL_PLL_DIV1_IREF_TRIM_MASK			(0x1F << 16)
 82#define   DKL_PLL_DIV1_TDC_TARGET_CNT(x)		((x) << 0)
 83#define   DKL_PLL_DIV1_TDC_TARGET_CNT_MASK		(0xFF << 0)
 84
 85#define _DKL_PLL_SSC					0x2210
 86#define DKL_PLL_SSC(tc_port)				_DKL_REG(tc_port, \
 87								 _DKL_PLL_SSC)
 88#define   DKL_PLL_SSC_IREF_NDIV_RATIO(x)		((x) << 29)
 89#define   DKL_PLL_SSC_IREF_NDIV_RATIO_MASK		(0x7 << 29)
 90#define   DKL_PLL_SSC_STEP_LEN(x)			((x) << 16)
 91#define   DKL_PLL_SSC_STEP_LEN_MASK			(0xFF << 16)
 92#define   DKL_PLL_SSC_STEP_NUM(x)			((x) << 11)
 93#define   DKL_PLL_SSC_STEP_NUM_MASK			(0x7 << 11)
 94#define   DKL_PLL_SSC_EN				(1 << 9)
 95
 96#define _DKL_PLL_BIAS					0x2214
 97#define DKL_PLL_BIAS(tc_port)				_DKL_REG(tc_port, \
 98								 _DKL_PLL_BIAS)
 99#define   DKL_PLL_BIAS_FRAC_EN_H			(1 << 30)
100#define   DKL_PLL_BIAS_FBDIV_SHIFT			(8)
101#define   DKL_PLL_BIAS_FBDIV_FRAC(x)			((x) << DKL_PLL_BIAS_FBDIV_SHIFT)
102#define   DKL_PLL_BIAS_FBDIV_FRAC_MASK			(0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
103
104#define _DKL_PLL_TDC_COLDST_BIAS			0x2218
105#define DKL_PLL_TDC_COLDST_BIAS(tc_port)		_DKL_REG(tc_port, \
106								 _DKL_PLL_TDC_COLDST_BIAS)
107#define   DKL_PLL_TDC_SSC_STEP_SIZE(x)			((x) << 8)
108#define   DKL_PLL_TDC_SSC_STEP_SIZE_MASK		(0xFF << 8)
109#define   DKL_PLL_TDC_FEED_FWD_GAIN(x)			((x) << 0)
110#define   DKL_PLL_TDC_FEED_FWD_GAIN_MASK		(0xFF << 0)
111
112#define _DKL_REFCLKIN_CTL				0x212C
113#define DKL_REFCLKIN_CTL(tc_port)			_DKL_REG(tc_port, \
114								 _DKL_REFCLKIN_CTL)
115/* Bits are the same as MG_REFCLKIN_CTL */
116
117#define _DKL_CLKTOP2_HSCLKCTL				0x20D4
118#define DKL_CLKTOP2_HSCLKCTL(rc_port)			_DKL_REG(tc_port, \
119								 _DKL_CLKTOP2_HSCLKCTL)
120/* Bits are the same as MG_CLKTOP2_HSCLKCTL */
121
122#define _DKL_CLKTOP2_CORECLKCTL1			0x20D8
123#define DKL_CLKTOP2_CORECLKCTL1(tc_port)		_DKL_REG(tc_port, \
124								 _DKL_CLKTOP2_CORECLKCTL1)
125/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */
126
127#define _DKL_TX_DPCNTL0_LN0				0x02C0
128#define _DKL_TX_DPCNTL0_LN1				0x12C0
129#define DKL_TX_DPCNTL0(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
130								    _DKL_TX_DPCNTL0_LN0, \
131								    _DKL_TX_DPCNTL0_LN1)
132#define  DKL_TX_PRESHOOT_COEFF(x)			((x) << 13)
133#define  DKL_TX_PRESHOOT_COEFF_MASK			(0x1f << 13)
134#define  DKL_TX_DE_EMPHASIS_COEFF(x)			((x) << 8)
135#define  DKL_TX_DE_EMPAHSIS_COEFF_MASK			(0x1f << 8)
136#define  DKL_TX_VSWING_CONTROL(x)			((x) << 0)
137#define  DKL_TX_VSWING_CONTROL_MASK			(0x7 << 0)
138
139#define _DKL_TX_DPCNTL1_LN0				0x02C4
140#define _DKL_TX_DPCNTL1_LN1				0x12C4
141#define DKL_TX_DPCNTL1(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
142								    _DKL_TX_DPCNTL1_LN0, \
143								    _DKL_TX_DPCNTL1_LN1)
144/* Bits are the same as DKL_TX_DPCNTRL0 */
145
146#define _DKL_TX_DPCNTL2_LN0				0x02C8
147#define _DKL_TX_DPCNTL2_LN1				0x12C8
148#define DKL_TX_DPCNTL2(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
149								    _DKL_TX_DPCNTL2_LN0, \
150								    _DKL_TX_DPCNTL2_LN1)
151#define  DKL_TX_DP20BITMODE				REG_BIT(2)
152#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK	REG_GENMASK(4, 3)
153#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val)	REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))
154#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK	REG_GENMASK(6, 5)
155#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val)	REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))
156#define  LOADGEN_SHARING_PMD_DISABLE			REG_BIT(12)
157
158#define _DKL_TX_FW_CALIB_LN0				0x02F8
159#define _DKL_TX_FW_CALIB_LN1				0x12F8
160#define DKL_TX_FW_CALIB(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
161								    _DKL_TX_FW_CALIB_LN0, \
162								    _DKL_TX_FW_CALIB_LN1)
163#define  DKL_TX_CFG_DISABLE_WAIT_INIT			(1 << 7)
164
165#define _DKL_TX_PMD_LANE_SUS_LN0			0x0D00
166#define _DKL_TX_PMD_LANE_SUS_LN1			0x1D00
167#define DKL_TX_PMD_LANE_SUS(tc_port, ln)		_DKL_REG_LN(tc_port, ln, \
168								    _DKL_TX_PMD_LANE_SUS_LN0, \
169								    _DKL_TX_PMD_LANE_SUS_LN1)
170
171#define _DKL_TX_DW17_LN0				0x0DC4
172#define _DKL_TX_DW17_LN1				0x1DC4
173#define DKL_TX_DW17(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
174								    _DKL_TX_DW17_LN0, \
175								    _DKL_TX_DW17_LN1)
176
177#define _DKL_TX_DW18_LN0				0x0DC8
178#define _DKL_TX_DW18_LN1				0x1DC8
179#define DKL_TX_DW18(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
180								    _DKL_TX_DW18_LN0, \
181								    _DKL_TX_DW18_LN1)
182
183#define _DKL_DP_MODE_LN0				0x00A0
184#define _DKL_DP_MODE_LN1				0x10A0
185#define DKL_DP_MODE(tc_port, ln)			_DKL_REG_LN(tc_port, ln, \
186								    _DKL_DP_MODE_LN0, \
187								    _DKL_DP_MODE_LN1)
188
189#define _DKL_CMN_UC_DW27				0x236C
190#define DKL_CMN_UC_DW_27(tc_port)			_DKL_REG(tc_port, \
191								 _DKL_CMN_UC_DW27)
192#define  DKL_CMN_UC_DW27_UC_HEALTH			(0x1 << 15)
193
194/*
195 * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than
196 * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0
197 * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address
198 * bits that point the 4KB window into the full PHY register space.
199 */
200#define _HIP_INDEX_REG0					0x1010A0
201#define _HIP_INDEX_REG1					0x1010A4
202#define HIP_INDEX_REG(tc_port)				_MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \
203							      : _HIP_INDEX_REG1)
204#define _HIP_INDEX_SHIFT(tc_port)			(8 * ((tc_port) % 4))
205#define HIP_INDEX_VAL(tc_port, val)			((val) << _HIP_INDEX_SHIFT(tc_port))
206
207#endif /* __INTEL_DKL_PHY_REGS__ */