intel_display.c

   1/*
   2 * Copyright © 2006-2007 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21 * DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors:
  24 *	Eric Anholt <eric@anholt.net>
  25 */
  26
  27#include <linux/dma-resv.h>
  28#include <linux/i2c.h>
  29#include <linux/input.h>
  30#include <linux/kernel.h>
  31#include <linux/module.h>
  32#include <linux/slab.h>
  33#include <linux/string_helpers.h>
  34
  35#include <drm/display/drm_dp_helper.h>
  36#include <drm/display/drm_dp_tunnel.h>
  37#include <drm/drm_atomic.h>
  38#include <drm/drm_atomic_helper.h>
  39#include <drm/drm_atomic_uapi.h>
  40#include <drm/drm_damage_helper.h>
  41#include <drm/drm_edid.h>
  42#include <drm/drm_fixed.h>
  43#include <drm/drm_fourcc.h>
  44#include <drm/drm_print.h>
  45#include <drm/drm_probe_helper.h>
  46#include <drm/drm_rect.h>
  47#include <drm/drm_vblank.h>
  48
  49#include "g4x_dp.h"
  50#include "g4x_hdmi.h"
  51#include "hsw_ips.h"
  52#include "i915_config.h"
  53#include "i915_drv.h"
  54#include "i915_reg.h"
  55#include "i9xx_plane.h"
  56#include "i9xx_plane_regs.h"
  57#include "i9xx_wm.h"
  58#include "intel_alpm.h"
  59#include "intel_atomic.h"
  60#include "intel_audio.h"
  61#include "intel_bo.h"
  62#include "intel_bw.h"
  63#include "intel_casf.h"
  64#include "intel_cdclk.h"
  65#include "intel_clock_gating.h"
  66#include "intel_color.h"
  67#include "intel_crt.h"
  68#include "intel_crtc.h"
  69#include "intel_crtc_state_dump.h"
  70#include "intel_cursor.h"
  71#include "intel_cursor_regs.h"
  72#include "intel_cx0_phy.h"
  73#include "intel_ddi.h"
  74#include "intel_de.h"
  75#include "intel_display_driver.h"
  76#include "intel_display_power.h"
  77#include "intel_display_regs.h"
  78#include "intel_display_rpm.h"
  79#include "intel_display_types.h"
  80#include "intel_display_utils.h"
  81#include "intel_display_wa.h"
  82#include "intel_dmc.h"
  83#include "intel_dp.h"
  84#include "intel_dp_link_training.h"
  85#include "intel_dp_mst.h"
  86#include "intel_dp_tunnel.h"
  87#include "intel_dpll.h"
  88#include "intel_dpll_mgr.h"
  89#include "intel_dpt.h"
  90#include "intel_dpt_common.h"
  91#include "intel_drrs.h"
  92#include "intel_dsb.h"
  93#include "intel_dsi.h"
  94#include "intel_dvo.h"
  95#include "intel_fb.h"
  96#include "intel_fbc.h"
  97#include "intel_fdi.h"
  98#include "intel_fifo_underrun.h"
  99#include "intel_flipq.h"
 100#include "intel_frontbuffer.h"
 101#include "intel_hdmi.h"
 102#include "intel_hotplug.h"
 103#include "intel_link_bw.h"
 104#include "intel_lt_phy.h"
 105#include "intel_lvds.h"
 106#include "intel_lvds_regs.h"
 107#include "intel_modeset_setup.h"
 108#include "intel_modeset_verify.h"
 109#include "intel_overlay.h"
 110#include "intel_panel.h"
 111#include "intel_pch_display.h"
 112#include "intel_pch_refclk.h"
 113#include "intel_pfit.h"
 114#include "intel_pipe_crc.h"
 115#include "intel_plane.h"
 116#include "intel_plane_initial.h"
 117#include "intel_pmdemand.h"
 118#include "intel_pps.h"
 119#include "intel_psr.h"
 120#include "intel_psr_regs.h"
 121#include "intel_sdvo.h"
 122#include "intel_snps_phy.h"
 123#include "intel_tc.h"
 124#include "intel_tdf.h"
 125#include "intel_tv.h"
 126#include "intel_vblank.h"
 127#include "intel_vdsc.h"
 128#include "intel_vdsc_regs.h"
 129#include "intel_vga.h"
 130#include "intel_vrr.h"
 131#include "intel_wm.h"
 132#include "skl_scaler.h"
 133#include "skl_universal_plane.h"
 134#include "skl_watermark.h"
 135#include "vlv_dsi.h"
 136#include "vlv_dsi_pll.h"
 137#include "vlv_dsi_regs.h"
 138
 139static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 140static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 141static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 142static void bdw_set_pipe_misc(struct intel_dsb *dsb,
 143			      const struct intel_crtc_state *crtc_state);
 144
 145static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
 146{
 147	return (crtc_state->active_planes &
 148		~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
 149}
 150
 151/* WA Display #0827: Gen9:all */
 152static void
 153skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable)
 154{
 155	intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),
 156		     DUPS1_GATING_DIS | DUPS2_GATING_DIS,
 157		     enable ? DUPS1_GATING_DIS | DUPS2_GATING_DIS : 0);
 158}
 159
 160/* Wa_2006604312:icl,ehl */
 161static void
 162icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe,
 163		       bool enable)
 164{
 165	intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),
 166		     DPFR_GATING_DIS,
 167		     enable ? DPFR_GATING_DIS : 0);
 168}
 169
 170/* Wa_1604331009:icl,jsl,ehl */
 171static void
 172icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe,
 173		       bool enable)
 174{
 175	intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),
 176		     CURSOR_GATING_DIS,
 177		     enable ? CURSOR_GATING_DIS : 0);
 178}
 179
 180static bool
 181is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 182{
 183	return crtc_state->master_transcoder != INVALID_TRANSCODER;
 184}
 185
 186bool
 187is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 188{
 189	return crtc_state->sync_mode_slaves_mask != 0;
 190}
 191
 192bool
 193is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 194{
 195	return is_trans_port_sync_master(crtc_state) ||
 196		is_trans_port_sync_slave(crtc_state);
 197}
 198
 199static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state)
 200{
 201	return ffs(crtc_state->joiner_pipes) - 1;
 202}
 203
 204/*
 205 * The following helper functions, despite being named for bigjoiner,
 206 * are applicable to both bigjoiner and uncompressed joiner configurations.
 207 */
 208static bool is_bigjoiner(const struct intel_crtc_state *crtc_state)
 209{
 210	return hweight8(crtc_state->joiner_pipes) >= 2;
 211}
 212
 213static u8 bigjoiner_primary_pipes(const struct intel_crtc_state *crtc_state)
 214{
 215	if (!is_bigjoiner(crtc_state))
 216		return 0;
 217
 218	return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state));
 219}
 220
 221static unsigned int bigjoiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
 222{
 223	if (!is_bigjoiner(crtc_state))
 224		return 0;
 225
 226	return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state));
 227}
 228
 229bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state)
 230{
 231	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 232
 233	if (!is_bigjoiner(crtc_state))
 234		return false;
 235
 236	return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state);
 237}
 238
 239bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state)
 240{
 241	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 242
 243	if (!is_bigjoiner(crtc_state))
 244		return false;
 245
 246	return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state);
 247}
 248
 249u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state)
 250{
 251	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 252
 253	if (!is_bigjoiner(crtc_state))
 254		return BIT(crtc->pipe);
 255
 256	return bigjoiner_primary_pipes(crtc_state);
 257}
 258
 259u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state)
 260{
 261	return bigjoiner_secondary_pipes(crtc_state);
 262}
 263
 264bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state)
 265{
 266	return intel_crtc_num_joined_pipes(crtc_state) >= 4;
 267}
 268
 269static u8 ultrajoiner_primary_pipes(const struct intel_crtc_state *crtc_state)
 270{
 271	if (!intel_crtc_is_ultrajoiner(crtc_state))
 272		return 0;
 273
 274	return crtc_state->joiner_pipes & (0b00010001 << joiner_primary_pipe(crtc_state));
 275}
 276
 277bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state)
 278{
 279	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 280
 281	return intel_crtc_is_ultrajoiner(crtc_state) &&
 282	       BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state);
 283}
 284
 285/*
 286 * The ultrajoiner enable bit doesn't seem to follow primary/secondary logic or
 287 * any other logic, so lets just add helper function to
 288 * at least hide this hassle..
 289 */
 290static u8 ultrajoiner_enable_pipes(const struct intel_crtc_state *crtc_state)
 291{
 292	if (!intel_crtc_is_ultrajoiner(crtc_state))
 293		return 0;
 294
 295	return crtc_state->joiner_pipes & (0b01110111 << joiner_primary_pipe(crtc_state));
 296}
 297
 298bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state)
 299{
 300	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 301
 302	return intel_crtc_is_ultrajoiner(crtc_state) &&
 303	       BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state);
 304}
 305
 306u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
 307{
 308	if (crtc_state->joiner_pipes)
 309		return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state));
 310	else
 311		return 0;
 312}
 313
 314bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state)
 315{
 316	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 317
 318	return crtc_state->joiner_pipes &&
 319		crtc->pipe != joiner_primary_pipe(crtc_state);
 320}
 321
 322bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)
 323{
 324	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 325
 326	return crtc_state->joiner_pipes &&
 327		crtc->pipe == joiner_primary_pipe(crtc_state);
 328}
 329
 330int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state)
 331{
 332	return hweight8(intel_crtc_joined_pipe_mask(crtc_state));
 333}
 334
 335u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state)
 336{
 337	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 338
 339	return BIT(crtc->pipe) | crtc_state->joiner_pipes;
 340}
 341
 342struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state)
 343{
 344	struct intel_display *display = to_intel_display(crtc_state);
 345
 346	if (intel_crtc_is_joiner_secondary(crtc_state))
 347		return intel_crtc_for_pipe(display, joiner_primary_pipe(crtc_state));
 348	else
 349		return to_intel_crtc(crtc_state->uapi.crtc);
 350}
 351
 352static void
 353intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 354{
 355	struct intel_display *display = to_intel_display(old_crtc_state);
 356	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 357
 358	if (DISPLAY_VER(display) >= 4) {
 359		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 360
 361		/* Wait for the Pipe State to go off */
 362		if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, cpu_transcoder),
 363					       TRANSCONF_STATE_ENABLE, 100))
 364			drm_WARN(display->drm, 1, "pipe_off wait timed out\n");
 365	} else {
 366		intel_wait_for_pipe_scanline_stopped(crtc);
 367	}
 368}
 369
 370void assert_transcoder(struct intel_display *display,
 371		       enum transcoder cpu_transcoder, bool state)
 372{
 373	bool cur_state;
 374	enum intel_display_power_domain power_domain;
 375	intel_wakeref_t wakeref;
 376
 377	/* we keep both pipes enabled on 830 */
 378	if (display->platform.i830)
 379		state = true;
 380
 381	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 382	wakeref = intel_display_power_get_if_enabled(display, power_domain);
 383	if (wakeref) {
 384		u32 val = intel_de_read(display,
 385					TRANSCONF(display, cpu_transcoder));
 386		cur_state = !!(val & TRANSCONF_ENABLE);
 387
 388		intel_display_power_put(display, power_domain, wakeref);
 389	} else {
 390		cur_state = false;
 391	}
 392
 393	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
 394				 "transcoder %s assertion failure (expected %s, current %s)\n",
 395				 transcoder_name(cpu_transcoder), str_on_off(state),
 396				 str_on_off(cur_state));
 397}
 398
 399static void assert_plane(struct intel_plane *plane, bool state)
 400{
 401	struct intel_display *display = to_intel_display(plane->base.dev);
 402	enum pipe pipe;
 403	bool cur_state;
 404
 405	cur_state = plane->get_hw_state(plane, &pipe);
 406
 407	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
 408				 "%s assertion failure (expected %s, current %s)\n",
 409				 plane->base.name, str_on_off(state),
 410				 str_on_off(cur_state));
 411}
 412
 413#define assert_plane_enabled(p) assert_plane(p, true)
 414#define assert_plane_disabled(p) assert_plane(p, false)
 415
 416static void assert_planes_disabled(struct intel_crtc *crtc)
 417{
 418	struct intel_display *display = to_intel_display(crtc);
 419	struct intel_plane *plane;
 420
 421	for_each_intel_plane_on_crtc(display->drm, crtc, plane)
 422		assert_plane_disabled(plane);
 423}
 424
 425void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 426{
 427	struct intel_display *display = to_intel_display(new_crtc_state);
 428	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 429	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 430	enum pipe pipe = crtc->pipe;
 431	u32 val;
 432
 433	drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe));
 434
 435	assert_planes_disabled(crtc);
 436
 437	/*
 438	 * A pipe without a PLL won't actually be able to drive bits from
 439	 * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
 440	 * need the check.
 441	 */
 442	if (HAS_GMCH(display)) {
 443		if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 444			assert_dsi_pll_enabled(display);
 445		else
 446			assert_pll_enabled(display, pipe);
 447	} else {
 448		if (new_crtc_state->has_pch_encoder) {
 449			/* if driving the PCH, we need FDI enabled */
 450			assert_fdi_rx_pll_enabled(display,
 451						  intel_crtc_pch_transcoder(crtc));
 452			assert_fdi_tx_pll_enabled(display,
 453						  (enum pipe) cpu_transcoder);
 454		}
 455		/* FIXME: assert CPU port conditions for SNB+ */
 456	}
 457
 458	/* Wa_22012358565:adl-p */
 459	if (DISPLAY_VER(display) == 13)
 460		intel_de_rmw(display, PIPE_ARB_CTL(display, pipe),
 461			     0, PIPE_ARB_USE_PROG_SLOTS);
 462
 463	if (DISPLAY_VER(display) >= 14) {
 464		u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
 465		u32 set = 0;
 466
 467		if (DISPLAY_VER(display) == 14)
 468			set |= DP_FEC_BS_JITTER_WA;
 469
 470		intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
 471			     clear, set);
 472	}
 473
 474	val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
 475	if (val & TRANSCONF_ENABLE) {
 476		/* we keep both pipes enabled on 830 */
 477		drm_WARN_ON(display->drm, !display->platform.i830);
 478		return;
 479	}
 480
 481	/* Wa_1409098942:adlp+ */
 482	if (DISPLAY_VER(display) >= 13 &&
 483	    new_crtc_state->dsc.compression_enable) {
 484		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
 485		val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
 486				      TRANSCONF_PIXEL_COUNT_SCALING_X4);
 487	}
 488
 489	intel_de_write(display, TRANSCONF(display, cpu_transcoder),
 490		       val | TRANSCONF_ENABLE);
 491	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
 492
 493	/*
 494	 * Until the pipe starts PIPEDSL reads will return a stale value,
 495	 * which causes an apparent vblank timestamp jump when PIPEDSL
 496	 * resets to its proper value. That also messes up the frame count
 497	 * when it's derived from the timestamps. So let's wait for the
 498	 * pipe to start properly before we call drm_crtc_vblank_on()
 499	 */
 500	if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
 501		intel_wait_for_pipe_scanline_moving(crtc);
 502}
 503
 504void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
 505{
 506	struct intel_display *display = to_intel_display(old_crtc_state);
 507	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 508	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 509	enum pipe pipe = crtc->pipe;
 510	u32 val;
 511
 512	drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe));
 513
 514	/*
 515	 * Make sure planes won't keep trying to pump pixels to us,
 516	 * or we might hang the display.
 517	 */
 518	assert_planes_disabled(crtc);
 519
 520	val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
 521	if ((val & TRANSCONF_ENABLE) == 0)
 522		return;
 523
 524	/*
 525	 * Double wide has implications for planes
 526	 * so best keep it disabled when not needed.
 527	 */
 528	if (old_crtc_state->double_wide)
 529		val &= ~TRANSCONF_DOUBLE_WIDE;
 530
 531	/* Don't disable pipe or pipe PLLs if needed */
 532	if (!display->platform.i830)
 533		val &= ~TRANSCONF_ENABLE;
 534
 535	/* Wa_1409098942:adlp+ */
 536	if (DISPLAY_VER(display) >= 13 &&
 537	    old_crtc_state->dsc.compression_enable)
 538		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
 539
 540	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
 541
 542	if (DISPLAY_VER(display) >= 12)
 543		intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
 544			     FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 545
 546	if ((val & TRANSCONF_ENABLE) == 0)
 547		intel_wait_for_pipe_off(old_crtc_state);
 548}
 549
 550u32 intel_plane_fb_max_stride(struct intel_display *display,
 551			      const struct drm_format_info *info,
 552			      u64 modifier)
 553{
 554	struct intel_crtc *crtc;
 555	struct intel_plane *plane;
 556
 557	/*
 558	 * We assume the primary plane for pipe A has
 559	 * the highest stride limits of them all,
 560	 * if in case pipe A is disabled, use the first pipe from pipe_mask.
 561	 */
 562	crtc = intel_first_crtc(display);
 563	if (!crtc)
 564		return 0;
 565
 566	plane = to_intel_plane(crtc->base.primary);
 567
 568	return plane->max_stride(plane, info, modifier,
 569				 DRM_MODE_ROTATE_0);
 570}
 571
 572u32 intel_dumb_fb_max_stride(struct drm_device *drm,
 573			     u32 pixel_format, u64 modifier)
 574{
 575	struct intel_display *display = to_intel_display(drm);
 576
 577	if (!HAS_DISPLAY(display))
 578		return 0;
 579
 580	return intel_plane_fb_max_stride(display,
 581					 drm_get_format_info(drm, pixel_format, modifier),
 582					 modifier);
 583}
 584
 585void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 586			     struct intel_plane_state *plane_state,
 587			     bool visible)
 588{
 589	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 590
 591	plane_state->uapi.visible = visible;
 592
 593	if (visible)
 594		crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
 595	else
 596		crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
 597}
 598
 599void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
 600{
 601	struct intel_display *display = to_intel_display(crtc_state);
 602	struct drm_plane *plane;
 603
 604	/*
 605	 * Active_planes aliases if multiple "primary" or cursor planes
 606	 * have been used on the same (or wrong) pipe. plane_mask uses
 607	 * unique ids, hence we can use that to reconstruct active_planes.
 608	 */
 609	crtc_state->enabled_planes = 0;
 610	crtc_state->active_planes = 0;
 611
 612	drm_for_each_plane_mask(plane, display->drm,
 613				crtc_state->uapi.plane_mask) {
 614		crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
 615		crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
 616	}
 617}
 618
 619void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 620				  struct intel_plane *plane)
 621{
 622	struct intel_display *display = to_intel_display(crtc);
 623	struct intel_crtc_state *crtc_state =
 624		to_intel_crtc_state(crtc->base.state);
 625	struct intel_plane_state *plane_state =
 626		to_intel_plane_state(plane->base.state);
 627
 628	drm_dbg_kms(display->drm,
 629		    "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
 630		    plane->base.base.id, plane->base.name,
 631		    crtc->base.base.id, crtc->base.name);
 632
 633	intel_plane_set_invisible(crtc_state, plane_state);
 634	intel_set_plane_visible(crtc_state, plane_state, false);
 635	intel_plane_fixup_bitmasks(crtc_state);
 636
 637	skl_wm_plane_disable_noatomic(crtc, plane);
 638
 639	if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
 640	    hsw_ips_disable(crtc_state)) {
 641		crtc_state->ips_enabled = false;
 642		intel_plane_initial_vblank_wait(crtc);
 643	}
 644
 645	/*
 646	 * Vblank time updates from the shadow to live plane control register
 647	 * are blocked if the memory self-refresh mode is active at that
 648	 * moment. So to make sure the plane gets truly disabled, disable
 649	 * first the self-refresh mode. The self-refresh enable bit in turn
 650	 * will be checked/applied by the HW only at the next frame start
 651	 * event which is after the vblank start event, so we need to have a
 652	 * wait-for-vblank between disabling the plane and the pipe.
 653	 */
 654	if (HAS_GMCH(display) &&
 655	    intel_set_memory_cxsr(display, false))
 656		intel_plane_initial_vblank_wait(crtc);
 657
 658	/*
 659	 * Gen2 reports pipe underruns whenever all planes are disabled.
 660	 * So disable underrun reporting before all the planes get disabled.
 661	 */
 662	if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes)
 663		intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false);
 664
 665	intel_plane_disable_arm(NULL, plane, crtc_state);
 666	intel_plane_initial_vblank_wait(crtc);
 667}
 668
 669unsigned int
 670intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
 671{
 672	int x = 0, y = 0;
 673
 674	intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
 675					  plane_state->view.color_plane[0].offset, 0);
 676
 677	return y;
 678}
 679
 680static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
 681{
 682	struct intel_display *display = to_intel_display(crtc_state);
 683	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 684	enum pipe pipe = crtc->pipe;
 685	u32 tmp;
 686
 687	tmp = intel_de_read(display, PIPE_CHICKEN(pipe));
 688
 689	/*
 690	 * Display WA #1153: icl
 691	 * enable hardware to bypass the alpha math
 692	 * and rounding for per-pixel values 00 and 0xff
 693	 */
 694	tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
 695	/*
 696	 * Display WA # 1605353570: icl
 697	 * Set the pixel rounding bit to 1 for allowing
 698	 * passthrough of Frame buffer pixels unmodified
 699	 * across pipe
 700	 */
 701	tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
 702
 703	/*
 704	 * Underrun recovery must always be disabled on display 13+.
 705	 * DG2 chicken bit meaning is inverted compared to other platforms.
 706	 */
 707	if (display->platform.dg2)
 708		tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
 709	else if ((DISPLAY_VER(display) >= 13) && (DISPLAY_VER(display) < 30))
 710		tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
 711
 712	/* Wa_14010547955:dg2 */
 713	if (display->platform.dg2)
 714		tmp |= DG2_RENDER_CCSTAG_4_3_EN;
 715
 716	intel_de_write(display, PIPE_CHICKEN(pipe), tmp);
 717}
 718
 719bool intel_has_pending_fb_unpin(struct intel_display *display)
 720{
 721	struct drm_crtc *crtc;
 722	bool cleanup_done;
 723
 724	drm_for_each_crtc(crtc, display->drm) {
 725		struct drm_crtc_commit *commit;
 726		spin_lock(&crtc->commit_lock);
 727		commit = list_first_entry_or_null(&crtc->commit_list,
 728						  struct drm_crtc_commit, commit_entry);
 729		cleanup_done = commit ?
 730			try_wait_for_completion(&commit->cleanup_done) : true;
 731		spin_unlock(&crtc->commit_lock);
 732
 733		if (cleanup_done)
 734			continue;
 735
 736		intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
 737
 738		return true;
 739	}
 740
 741	return false;
 742}
 743
 744/*
 745 * Finds the encoder associated with the given CRTC. This can only be
 746 * used when we know that the CRTC isn't feeding multiple encoders!
 747 */
 748struct intel_encoder *
 749intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 750			   const struct intel_crtc_state *crtc_state)
 751{
 752	const struct drm_connector_state *connector_state;
 753	const struct drm_connector *connector;
 754	struct intel_encoder *encoder = NULL;
 755	struct intel_crtc *primary_crtc;
 756	int num_encoders = 0;
 757	int i;
 758
 759	primary_crtc = intel_primary_crtc(crtc_state);
 760
 761	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
 762		if (connector_state->crtc != &primary_crtc->base)
 763			continue;
 764
 765		encoder = to_intel_encoder(connector_state->best_encoder);
 766		num_encoders++;
 767	}
 768
 769	drm_WARN(state->base.dev, num_encoders != 1,
 770		 "%d encoders for pipe %c\n",
 771		 num_encoders, pipe_name(primary_crtc->pipe));
 772
 773	return encoder;
 774}
 775
 776static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
 777{
 778	if (crtc->overlay)
 779		(void) intel_overlay_switch_off(crtc->overlay);
 780
 781	/* Let userspace switch the overlay on again. In most cases userspace
 782	 * has to recompute where to put it anyway.
 783	 */
 784}
 785
 786static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
 787{
 788	struct intel_display *display = to_intel_display(crtc_state);
 789
 790	if (!crtc_state->nv12_planes)
 791		return false;
 792
 793	/* WA Display #0827: Gen9:all */
 794	if (DISPLAY_VER(display) == 9)
 795		return true;
 796
 797	return false;
 798}
 799
 800static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
 801{
 802	struct intel_display *display = to_intel_display(crtc_state);
 803
 804	/* Wa_2006604312:icl,ehl */
 805	if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11)
 806		return true;
 807
 808	return false;
 809}
 810
 811static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
 812{
 813	struct intel_display *display = to_intel_display(crtc_state);
 814
 815	/* Wa_1604331009:icl,jsl,ehl */
 816	if (is_hdr_mode(crtc_state) &&
 817	    crtc_state->active_planes & BIT(PLANE_CURSOR) &&
 818	    DISPLAY_VER(display) == 11)
 819		return true;
 820
 821	return false;
 822}
 823
 824static void intel_async_flip_vtd_wa(struct intel_display *display,
 825				    enum pipe pipe, bool enable)
 826{
 827	if (DISPLAY_VER(display) == 9) {
 828		/*
 829		 * "Plane N stretch max must be programmed to 11b (x1)
 830		 *  when Async flips are enabled on that plane."
 831		 */
 832		intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),
 833			     SKL_PLANE1_STRETCH_MAX_MASK,
 834			     enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
 835	} else {
 836		/* Also needed on HSW/BDW albeit undocumented */
 837		intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),
 838			     HSW_PRI_STRETCH_MAX_MASK,
 839			     enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
 840	}
 841}
 842
 843static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
 844{
 845	struct intel_display *display = to_intel_display(crtc_state);
 846
 847	return crtc_state->uapi.async_flip && intel_display_vtd_active(display) &&
 848		(DISPLAY_VER(display) == 9 || display->platform.broadwell ||
 849		 display->platform.haswell);
 850}
 851
 852static void intel_encoders_audio_enable(struct intel_atomic_state *state,
 853					struct intel_crtc *crtc)
 854{
 855	const struct intel_crtc_state *crtc_state =
 856		intel_atomic_get_new_crtc_state(state, crtc);
 857	const struct drm_connector_state *conn_state;
 858	struct drm_connector *conn;
 859	int i;
 860
 861	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
 862		struct intel_encoder *encoder =
 863			to_intel_encoder(conn_state->best_encoder);
 864
 865		if (conn_state->crtc != &crtc->base)
 866			continue;
 867
 868		if (encoder->audio_enable)
 869			encoder->audio_enable(encoder, crtc_state, conn_state);
 870	}
 871}
 872
 873static void intel_encoders_audio_disable(struct intel_atomic_state *state,
 874					 struct intel_crtc *crtc)
 875{
 876	const struct intel_crtc_state *old_crtc_state =
 877		intel_atomic_get_old_crtc_state(state, crtc);
 878	const struct drm_connector_state *old_conn_state;
 879	struct drm_connector *conn;
 880	int i;
 881
 882	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
 883		struct intel_encoder *encoder =
 884			to_intel_encoder(old_conn_state->best_encoder);
 885
 886		if (old_conn_state->crtc != &crtc->base)
 887			continue;
 888
 889		if (encoder->audio_disable)
 890			encoder->audio_disable(encoder, old_crtc_state, old_conn_state);
 891	}
 892}
 893
 894#define is_enabling(feature, old_crtc_state, new_crtc_state) \
 895	((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
 896	 (new_crtc_state)->feature)
 897#define is_disabling(feature, old_crtc_state, new_crtc_state) \
 898	((old_crtc_state)->feature && \
 899	 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
 900
 901static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
 902			    const struct intel_crtc_state *new_crtc_state)
 903{
 904	if (!new_crtc_state->hw.active)
 905		return false;
 906
 907	return is_enabling(active_planes, old_crtc_state, new_crtc_state);
 908}
 909
 910static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
 911			     const struct intel_crtc_state *new_crtc_state)
 912{
 913	if (!old_crtc_state->hw.active)
 914		return false;
 915
 916	return is_disabling(active_planes, old_crtc_state, new_crtc_state);
 917}
 918
 919static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 920			       const struct intel_crtc_state *new_crtc_state)
 921{
 922	return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||
 923		old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
 924		old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
 925		old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
 926		old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full ||
 927		old_crtc_state->vrr.vsync_start != new_crtc_state->vrr.vsync_start ||
 928		old_crtc_state->vrr.vsync_end != new_crtc_state->vrr.vsync_end;
 929}
 930
 931static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 932				const struct intel_crtc_state *new_crtc_state)
 933{
 934	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
 935		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
 936}
 937
 938static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
 939				    struct intel_crtc *crtc)
 940{
 941	const struct intel_crtc_state *old_crtc_state =
 942		intel_atomic_get_old_crtc_state(state, crtc);
 943	const struct intel_crtc_state *new_crtc_state =
 944		intel_atomic_get_new_crtc_state(state, crtc);
 945
 946	if (!new_crtc_state->hw.active)
 947		return false;
 948
 949	return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
 950		(new_crtc_state->vrr.enable &&
 951		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
 952		  vrr_params_changed(old_crtc_state, new_crtc_state)));
 953}
 954
 955bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
 956			      struct intel_crtc *crtc)
 957{
 958	const struct intel_crtc_state *old_crtc_state =
 959		intel_atomic_get_old_crtc_state(state, crtc);
 960	const struct intel_crtc_state *new_crtc_state =
 961		intel_atomic_get_new_crtc_state(state, crtc);
 962
 963	if (!old_crtc_state->hw.active)
 964		return false;
 965
 966	return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
 967		(old_crtc_state->vrr.enable &&
 968		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
 969		  vrr_params_changed(old_crtc_state, new_crtc_state)));
 970}
 971
 972static bool audio_enabling(const struct intel_crtc_state *old_crtc_state,
 973			   const struct intel_crtc_state *new_crtc_state)
 974{
 975	if (!new_crtc_state->hw.active)
 976		return false;
 977
 978	return is_enabling(has_audio, old_crtc_state, new_crtc_state) ||
 979		(new_crtc_state->has_audio &&
 980		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);
 981}
 982
 983static bool audio_disabling(const struct intel_crtc_state *old_crtc_state,
 984			    const struct intel_crtc_state *new_crtc_state)
 985{
 986	if (!old_crtc_state->hw.active)
 987		return false;
 988
 989	return is_disabling(has_audio, old_crtc_state, new_crtc_state) ||
 990		(old_crtc_state->has_audio &&
 991		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);
 992}
 993
 994static bool intel_casf_enabling(const struct intel_crtc_state *new_crtc_state,
 995				const struct intel_crtc_state *old_crtc_state)
 996{
 997	if (!new_crtc_state->hw.active)
 998		return false;
 999
1000	return is_enabling(hw.casf_params.casf_enable, old_crtc_state, new_crtc_state);
1001}
1002
1003static bool intel_casf_disabling(const struct intel_crtc_state *old_crtc_state,
1004				 const struct intel_crtc_state *new_crtc_state)
1005{
1006	if (!new_crtc_state->hw.active)
1007		return false;
1008
1009	return is_disabling(hw.casf_params.casf_enable, old_crtc_state, new_crtc_state);
1010}
1011
1012#undef is_disabling
1013#undef is_enabling
1014
1015static void intel_post_plane_update(struct intel_atomic_state *state,
1016				    struct intel_crtc *crtc)
1017{
1018	struct intel_display *display = to_intel_display(state);
1019	const struct intel_crtc_state *old_crtc_state =
1020		intel_atomic_get_old_crtc_state(state, crtc);
1021	const struct intel_crtc_state *new_crtc_state =
1022		intel_atomic_get_new_crtc_state(state, crtc);
1023	enum pipe pipe = crtc->pipe;
1024
1025	intel_frontbuffer_flip(display, new_crtc_state->fb_bits);
1026
1027	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
1028		intel_update_watermarks(display);
1029
1030	intel_fbc_post_update(state, crtc);
1031
1032	if (needs_async_flip_vtd_wa(old_crtc_state) &&
1033	    !needs_async_flip_vtd_wa(new_crtc_state))
1034		intel_async_flip_vtd_wa(display, pipe, false);
1035
1036	if (needs_nv12_wa(old_crtc_state) &&
1037	    !needs_nv12_wa(new_crtc_state))
1038		skl_wa_827(display, pipe, false);
1039
1040	if (needs_scalerclk_wa(old_crtc_state) &&
1041	    !needs_scalerclk_wa(new_crtc_state))
1042		icl_wa_scalerclkgating(display, pipe, false);
1043
1044	if (needs_cursorclk_wa(old_crtc_state) &&
1045	    !needs_cursorclk_wa(new_crtc_state))
1046		icl_wa_cursorclkgating(display, pipe, false);
1047
1048	if (intel_crtc_needs_color_update(new_crtc_state))
1049		intel_color_post_update(new_crtc_state);
1050
1051	if (audio_enabling(old_crtc_state, new_crtc_state))
1052		intel_encoders_audio_enable(state, crtc);
1053
1054	if (intel_display_wa(display, 14011503117)) {
1055		if (old_crtc_state->pch_pfit.enabled != new_crtc_state->pch_pfit.enabled)
1056			adl_scaler_ecc_unmask(new_crtc_state);
1057	}
1058
1059	intel_alpm_post_plane_update(state, crtc);
1060
1061	intel_psr_post_plane_update(state, crtc);
1062}
1063
1064static void intel_post_plane_update_after_readout(struct intel_atomic_state *state,
1065						  struct intel_crtc *crtc)
1066{
1067	const struct intel_crtc_state *new_crtc_state =
1068		intel_atomic_get_new_crtc_state(state, crtc);
1069
1070	/* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
1071	hsw_ips_post_update(state, crtc);
1072
1073	/*
1074	 * Activate DRRS after state readout to avoid
1075	 * dp_m_n vs. dp_m2_n2 confusion on BDW+.
1076	 */
1077	intel_drrs_activate(new_crtc_state);
1078}
1079
1080static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
1081					struct intel_crtc *crtc)
1082{
1083	const struct intel_crtc_state *crtc_state =
1084		intel_atomic_get_new_crtc_state(state, crtc);
1085	u8 update_planes = crtc_state->update_planes;
1086	const struct intel_plane_state __maybe_unused *plane_state;
1087	struct intel_plane *plane;
1088	int i;
1089
1090	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1091		if (plane->pipe == crtc->pipe &&
1092		    update_planes & BIT(plane->id))
1093			plane->enable_flip_done(plane);
1094	}
1095}
1096
1097static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
1098					 struct intel_crtc *crtc)
1099{
1100	const struct intel_crtc_state *crtc_state =
1101		intel_atomic_get_new_crtc_state(state, crtc);
1102	u8 update_planes = crtc_state->update_planes;
1103	const struct intel_plane_state __maybe_unused *plane_state;
1104	struct intel_plane *plane;
1105	int i;
1106
1107	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1108		if (plane->pipe == crtc->pipe &&
1109		    update_planes & BIT(plane->id))
1110			plane->disable_flip_done(plane);
1111	}
1112}
1113
1114static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1115					     struct intel_crtc *crtc)
1116{
1117	const struct intel_crtc_state *old_crtc_state =
1118		intel_atomic_get_old_crtc_state(state, crtc);
1119	const struct intel_crtc_state *new_crtc_state =
1120		intel_atomic_get_new_crtc_state(state, crtc);
1121	u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
1122				       ~new_crtc_state->async_flip_planes;
1123	const struct intel_plane_state *old_plane_state;
1124	struct intel_plane *plane;
1125	bool need_vbl_wait = false;
1126	int i;
1127
1128	for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1129		if (plane->need_async_flip_toggle_wa &&
1130		    plane->pipe == crtc->pipe &&
1131		    disable_async_flip_planes & BIT(plane->id)) {
1132			/*
1133			 * Apart from the async flip bit we want to
1134			 * preserve the old state for the plane.
1135			 */
1136			intel_plane_async_flip(NULL, plane,
1137					       old_crtc_state, old_plane_state, false);
1138			need_vbl_wait = true;
1139		}
1140	}
1141
1142	if (need_vbl_wait)
1143		intel_crtc_wait_for_next_vblank(crtc);
1144}
1145
1146static void intel_pre_plane_update(struct intel_atomic_state *state,
1147				   struct intel_crtc *crtc)
1148{
1149	struct intel_display *display = to_intel_display(state);
1150	const struct intel_crtc_state *old_crtc_state =
1151		intel_atomic_get_old_crtc_state(state, crtc);
1152	const struct intel_crtc_state *new_crtc_state =
1153		intel_atomic_get_new_crtc_state(state, crtc);
1154	enum pipe pipe = crtc->pipe;
1155
1156	intel_alpm_pre_plane_update(state, crtc);
1157	intel_psr_pre_plane_update(state, crtc);
1158
1159	if (intel_crtc_vrr_disabling(state, crtc)) {
1160		intel_vrr_disable(old_crtc_state);
1161		intel_crtc_update_active_timings(old_crtc_state, false);
1162	}
1163
1164	if (audio_disabling(old_crtc_state, new_crtc_state))
1165		intel_encoders_audio_disable(state, crtc);
1166
1167	if (intel_casf_disabling(old_crtc_state, new_crtc_state))
1168		intel_casf_disable(new_crtc_state);
1169
1170	intel_drrs_deactivate(old_crtc_state);
1171
1172	if (hsw_ips_pre_update(state, crtc))
1173		intel_crtc_wait_for_next_vblank(crtc);
1174
1175	if (intel_fbc_pre_update(state, crtc))
1176		intel_crtc_wait_for_next_vblank(crtc);
1177
1178	if (!needs_async_flip_vtd_wa(old_crtc_state) &&
1179	    needs_async_flip_vtd_wa(new_crtc_state))
1180		intel_async_flip_vtd_wa(display, pipe, true);
1181
1182	/* Display WA 827 */
1183	if (!needs_nv12_wa(old_crtc_state) &&
1184	    needs_nv12_wa(new_crtc_state))
1185		skl_wa_827(display, pipe, true);
1186
1187	/* Wa_2006604312:icl,ehl */
1188	if (!needs_scalerclk_wa(old_crtc_state) &&
1189	    needs_scalerclk_wa(new_crtc_state))
1190		icl_wa_scalerclkgating(display, pipe, true);
1191
1192	/* Wa_1604331009:icl,jsl,ehl */
1193	if (!needs_cursorclk_wa(old_crtc_state) &&
1194	    needs_cursorclk_wa(new_crtc_state))
1195		icl_wa_cursorclkgating(display, pipe, true);
1196
1197	/*
1198	 * Vblank time updates from the shadow to live plane control register
1199	 * are blocked if the memory self-refresh mode is active at that
1200	 * moment. So to make sure the plane gets truly disabled, disable
1201	 * first the self-refresh mode. The self-refresh enable bit in turn
1202	 * will be checked/applied by the HW only at the next frame start
1203	 * event which is after the vblank start event, so we need to have a
1204	 * wait-for-vblank between disabling the plane and the pipe.
1205	 */
1206	if (HAS_GMCH(display) && old_crtc_state->hw.active &&
1207	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, false))
1208		intel_crtc_wait_for_next_vblank(crtc);
1209
1210	/*
1211	 * IVB workaround: must disable low power watermarks for at least
1212	 * one frame before enabling scaling.  LP watermarks can be re-enabled
1213	 * when scaling is disabled.
1214	 *
1215	 * WaCxSRDisabledForSpriteScaling:ivb
1216	 */
1217	if (!HAS_GMCH(display) && old_crtc_state->hw.active &&
1218	    new_crtc_state->disable_cxsr && ilk_disable_cxsr(display))
1219		intel_crtc_wait_for_next_vblank(crtc);
1220
1221	/*
1222	 * If we're doing a modeset we don't need to do any
1223	 * pre-vblank watermark programming here.
1224	 */
1225	if (!intel_crtc_needs_modeset(new_crtc_state)) {
1226		/*
1227		 * For platforms that support atomic watermarks, program the
1228		 * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
1229		 * will be the intermediate values that are safe for both pre- and
1230		 * post- vblank; when vblank happens, the 'active' values will be set
1231		 * to the final 'target' values and we'll do this again to get the
1232		 * optimal watermarks.  For gen9+ platforms, the values we program here
1233		 * will be the final target values which will get automatically latched
1234		 * at vblank time; no further programming will be necessary.
1235		 *
1236		 * If a platform hasn't been transitioned to atomic watermarks yet,
1237		 * we'll continue to update watermarks the old way, if flags tell
1238		 * us to.
1239		 */
1240		if (!intel_initial_watermarks(state, crtc))
1241			if (new_crtc_state->update_wm_pre)
1242				intel_update_watermarks(display);
1243	}
1244
1245	/*
1246	 * Gen2 reports pipe underruns whenever all planes are disabled.
1247	 * So disable underrun reporting before all the planes get disabled.
1248	 *
1249	 * We do this after .initial_watermarks() so that we have a
1250	 * chance of catching underruns with the intermediate watermarks
1251	 * vs. the old plane configuration.
1252	 */
1253	if (DISPLAY_VER(display) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1254		intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
1255
1256	/*
1257	 * WA for platforms where async address update enable bit
1258	 * is double buffered and only latched at start of vblank.
1259	 */
1260	if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)
1261		intel_crtc_async_flip_disable_wa(state, crtc);
1262}
1263
1264static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1265				      struct intel_crtc *crtc)
1266{
1267	struct intel_display *display = to_intel_display(state);
1268	const struct intel_crtc_state *new_crtc_state =
1269		intel_atomic_get_new_crtc_state(state, crtc);
1270	unsigned int update_mask = new_crtc_state->update_planes;
1271	const struct intel_plane_state *old_plane_state;
1272	struct intel_plane *plane;
1273	unsigned fb_bits = 0;
1274	int i;
1275
1276	intel_crtc_dpms_overlay_disable(crtc);
1277
1278	for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1279		if (crtc->pipe != plane->pipe ||
1280		    !(update_mask & BIT(plane->id)))
1281			continue;
1282
1283		intel_plane_disable_arm(NULL, plane, new_crtc_state);
1284
1285		if (old_plane_state->uapi.visible)
1286			fb_bits |= plane->frontbuffer_bit;
1287	}
1288
1289	intel_frontbuffer_flip(display, fb_bits);
1290}
1291
1292static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1293{
1294	struct intel_display *display = to_intel_display(state);
1295	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1296	struct intel_crtc *crtc;
1297	int i;
1298
1299	/*
1300	 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1301	 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1302	 */
1303	if (display->dpll.mgr) {
1304		for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1305			if (intel_crtc_needs_modeset(new_crtc_state))
1306				continue;
1307
1308			new_crtc_state->intel_dpll = old_crtc_state->intel_dpll;
1309			new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1310		}
1311	}
1312}
1313
1314static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1315					  struct intel_crtc *crtc)
1316{
1317	const struct intel_crtc_state *crtc_state =
1318		intel_atomic_get_new_crtc_state(state, crtc);
1319	const struct drm_connector_state *conn_state;
1320	struct drm_connector *conn;
1321	int i;
1322
1323	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1324		struct intel_encoder *encoder =
1325			to_intel_encoder(conn_state->best_encoder);
1326
1327		if (conn_state->crtc != &crtc->base)
1328			continue;
1329
1330		if (encoder->pre_pll_enable)
1331			encoder->pre_pll_enable(state, encoder,
1332						crtc_state, conn_state);
1333	}
1334}
1335
1336static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1337				      struct intel_crtc *crtc)
1338{
1339	const struct intel_crtc_state *crtc_state =
1340		intel_atomic_get_new_crtc_state(state, crtc);
1341	const struct drm_connector_state *conn_state;
1342	struct drm_connector *conn;
1343	int i;
1344
1345	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1346		struct intel_encoder *encoder =
1347			to_intel_encoder(conn_state->best_encoder);
1348
1349		if (conn_state->crtc != &crtc->base)
1350			continue;
1351
1352		if (encoder->pre_enable)
1353			encoder->pre_enable(state, encoder,
1354					    crtc_state, conn_state);
1355	}
1356}
1357
1358static void intel_encoders_enable(struct intel_atomic_state *state,
1359				  struct intel_crtc *crtc)
1360{
1361	const struct intel_crtc_state *crtc_state =
1362		intel_atomic_get_new_crtc_state(state, crtc);
1363	const struct drm_connector_state *conn_state;
1364	struct drm_connector *conn;
1365	int i;
1366
1367	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1368		struct intel_encoder *encoder =
1369			to_intel_encoder(conn_state->best_encoder);
1370
1371		if (conn_state->crtc != &crtc->base)
1372			continue;
1373
1374		if (encoder->enable)
1375			encoder->enable(state, encoder,
1376					crtc_state, conn_state);
1377		intel_opregion_notify_encoder(encoder, true);
1378	}
1379}
1380
1381static void intel_encoders_disable(struct intel_atomic_state *state,
1382				   struct intel_crtc *crtc)
1383{
1384	const struct intel_crtc_state *old_crtc_state =
1385		intel_atomic_get_old_crtc_state(state, crtc);
1386	const struct drm_connector_state *old_conn_state;
1387	struct drm_connector *conn;
1388	int i;
1389
1390	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1391		struct intel_encoder *encoder =
1392			to_intel_encoder(old_conn_state->best_encoder);
1393
1394		if (old_conn_state->crtc != &crtc->base)
1395			continue;
1396
1397		intel_opregion_notify_encoder(encoder, false);
1398		if (encoder->disable)
1399			encoder->disable(state, encoder,
1400					 old_crtc_state, old_conn_state);
1401	}
1402}
1403
1404static void intel_encoders_post_disable(struct intel_atomic_state *state,
1405					struct intel_crtc *crtc)
1406{
1407	const struct intel_crtc_state *old_crtc_state =
1408		intel_atomic_get_old_crtc_state(state, crtc);
1409	const struct drm_connector_state *old_conn_state;
1410	struct drm_connector *conn;
1411	int i;
1412
1413	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1414		struct intel_encoder *encoder =
1415			to_intel_encoder(old_conn_state->best_encoder);
1416
1417		if (old_conn_state->crtc != &crtc->base)
1418			continue;
1419
1420		if (encoder->post_disable)
1421			encoder->post_disable(state, encoder,
1422					      old_crtc_state, old_conn_state);
1423	}
1424}
1425
1426static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1427					    struct intel_crtc *crtc)
1428{
1429	const struct intel_crtc_state *old_crtc_state =
1430		intel_atomic_get_old_crtc_state(state, crtc);
1431	const struct drm_connector_state *old_conn_state;
1432	struct drm_connector *conn;
1433	int i;
1434
1435	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1436		struct intel_encoder *encoder =
1437			to_intel_encoder(old_conn_state->best_encoder);
1438
1439		if (old_conn_state->crtc != &crtc->base)
1440			continue;
1441
1442		if (encoder->post_pll_disable)
1443			encoder->post_pll_disable(state, encoder,
1444						  old_crtc_state, old_conn_state);
1445	}
1446}
1447
1448static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1449				       struct intel_crtc *crtc)
1450{
1451	const struct intel_crtc_state *crtc_state =
1452		intel_atomic_get_new_crtc_state(state, crtc);
1453	const struct drm_connector_state *conn_state;
1454	struct drm_connector *conn;
1455	int i;
1456
1457	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1458		struct intel_encoder *encoder =
1459			to_intel_encoder(conn_state->best_encoder);
1460
1461		if (conn_state->crtc != &crtc->base)
1462			continue;
1463
1464		if (encoder->update_pipe)
1465			encoder->update_pipe(state, encoder,
1466					     crtc_state, conn_state);
1467	}
1468}
1469
1470static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1471{
1472	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1473	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1474
1475	if (crtc_state->has_pch_encoder) {
1476		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1477					       &crtc_state->fdi_m_n);
1478	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
1479		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1480					       &crtc_state->dp_m_n);
1481		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1482					       &crtc_state->dp_m2_n2);
1483	}
1484
1485	intel_set_transcoder_timings(crtc_state);
1486
1487	ilk_set_pipeconf(crtc_state);
1488}
1489
1490static void ilk_crtc_enable(struct intel_atomic_state *state,
1491			    struct intel_crtc *crtc)
1492{
1493	struct intel_display *display = to_intel_display(crtc);
1494	const struct intel_crtc_state *new_crtc_state =
1495		intel_atomic_get_new_crtc_state(state, crtc);
1496	enum pipe pipe = crtc->pipe;
1497
1498	if (drm_WARN_ON(display->drm, crtc->active))
1499		return;
1500
1501	/*
1502	 * Sometimes spurious CPU pipe underruns happen during FDI
1503	 * training, at least with VGA+HDMI cloning. Suppress them.
1504	 *
1505	 * On ILK we get an occasional spurious CPU pipe underruns
1506	 * between eDP port A enable and vdd enable. Also PCH port
1507	 * enable seems to result in the occasional CPU pipe underrun.
1508	 *
1509	 * Spurious PCH underruns also occur during PCH enabling.
1510	 */
1511	intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
1512	intel_set_pch_fifo_underrun_reporting(display, pipe, false);
1513
1514	ilk_configure_cpu_transcoder(new_crtc_state);
1515
1516	intel_set_pipe_src_size(new_crtc_state);
1517
1518	crtc->active = true;
1519
1520	intel_encoders_pre_enable(state, crtc);
1521
1522	if (new_crtc_state->has_pch_encoder) {
1523		ilk_pch_pre_enable(state, crtc);
1524	} else {
1525		assert_fdi_tx_disabled(display, pipe);
1526		assert_fdi_rx_disabled(display, pipe);
1527	}
1528
1529	ilk_pfit_enable(new_crtc_state);
1530
1531	/*
1532	 * On ILK+ LUT must be loaded before the pipe is running but with
1533	 * clocks enabled
1534	 */
1535	intel_color_modeset(new_crtc_state);
1536
1537	intel_initial_watermarks(state, crtc);
1538	intel_enable_transcoder(new_crtc_state);
1539
1540	if (new_crtc_state->has_pch_encoder)
1541		ilk_pch_enable(state, crtc);
1542
1543	intel_crtc_vblank_on(new_crtc_state);
1544
1545	intel_encoders_enable(state, crtc);
1546
1547	if (HAS_PCH_CPT(display))
1548		intel_wait_for_pipe_scanline_moving(crtc);
1549
1550	/*
1551	 * Must wait for vblank to avoid spurious PCH FIFO underruns.
1552	 * And a second vblank wait is needed at least on ILK with
1553	 * some interlaced HDMI modes. Let's do the double wait always
1554	 * in case there are more corner cases we don't know about.
1555	 */
1556	if (new_crtc_state->has_pch_encoder) {
1557		intel_crtc_wait_for_next_vblank(crtc);
1558		intel_crtc_wait_for_next_vblank(crtc);
1559	}
1560	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
1561	intel_set_pch_fifo_underrun_reporting(display, pipe, true);
1562}
1563
1564/* Display WA #1180: WaDisableScalarClockGating: glk */
1565static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state)
1566{
1567	struct intel_display *display = to_intel_display(crtc_state);
1568
1569	return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled;
1570}
1571
1572static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable)
1573{
1574	struct intel_display *display = to_intel_display(crtc);
1575	u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1576
1577	intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe),
1578		     mask, enable ? mask : 0);
1579}
1580
1581static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1582{
1583	struct intel_display *display = to_intel_display(crtc_state);
1584	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1585
1586	intel_de_write(display, WM_LINETIME(crtc->pipe),
1587		       HSW_LINETIME(crtc_state->linetime) |
1588		       HSW_IPS_LINETIME(crtc_state->ips_linetime));
1589}
1590
1591static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1592{
1593	struct intel_display *display = to_intel_display(crtc_state);
1594
1595	intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder),
1596		     HSW_FRAME_START_DELAY_MASK,
1597		     HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
1598}
1599
1600static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1601{
1602	struct intel_display *display = to_intel_display(crtc_state);
1603	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1604	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1605
1606	if (crtc_state->has_pch_encoder) {
1607		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1608					       &crtc_state->fdi_m_n);
1609	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
1610		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1611					       &crtc_state->dp_m_n);
1612		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1613					       &crtc_state->dp_m2_n2);
1614	}
1615
1616	intel_set_transcoder_timings(crtc_state);
1617
1618	if (cpu_transcoder != TRANSCODER_EDP)
1619		intel_de_write(display, TRANS_MULT(display, cpu_transcoder),
1620			       crtc_state->pixel_multiplier - 1);
1621
1622	hsw_set_frame_start_delay(crtc_state);
1623
1624	hsw_set_transconf(crtc_state);
1625}
1626
1627static void hsw_crtc_enable(struct intel_atomic_state *state,
1628			    struct intel_crtc *crtc)
1629{
1630	struct intel_display *display = to_intel_display(state);
1631	const struct intel_crtc_state *new_crtc_state =
1632		intel_atomic_get_new_crtc_state(state, crtc);
1633	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1634	struct intel_crtc *pipe_crtc;
1635	int i;
1636
1637	if (drm_WARN_ON(display->drm, crtc->active))
1638		return;
1639	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1640		const struct intel_crtc_state *new_pipe_crtc_state =
1641			intel_atomic_get_new_crtc_state(state, pipe_crtc);
1642
1643		intel_dmc_enable_pipe(new_pipe_crtc_state);
1644	}
1645
1646	intel_encoders_pre_pll_enable(state, crtc);
1647
1648	if (new_crtc_state->intel_dpll)
1649		intel_dpll_enable(new_crtc_state);
1650
1651	intel_encoders_pre_enable(state, crtc);
1652
1653	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1654		const struct intel_crtc_state *pipe_crtc_state =
1655			intel_atomic_get_new_crtc_state(state, pipe_crtc);
1656
1657		intel_dsc_enable(pipe_crtc_state);
1658
1659		if (HAS_UNCOMPRESSED_JOINER(display))
1660			intel_uncompressed_joiner_enable(pipe_crtc_state);
1661
1662		intel_set_pipe_src_size(pipe_crtc_state);
1663
1664		if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)
1665			bdw_set_pipe_misc(NULL, pipe_crtc_state);
1666	}
1667
1668	if (!transcoder_is_dsi(cpu_transcoder))
1669		hsw_configure_cpu_transcoder(new_crtc_state);
1670
1671	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1672		const struct intel_crtc_state *pipe_crtc_state =
1673			intel_atomic_get_new_crtc_state(state, pipe_crtc);
1674
1675		pipe_crtc->active = true;
1676
1677		if (glk_need_scaler_clock_gating_wa(pipe_crtc_state))
1678			glk_pipe_scaler_clock_gating_wa(pipe_crtc, true);
1679
1680		if (DISPLAY_VER(display) >= 9)
1681			skl_pfit_enable(pipe_crtc_state);
1682		else
1683			ilk_pfit_enable(pipe_crtc_state);
1684
1685		/*
1686		 * On ILK+ LUT must be loaded before the pipe is running but with
1687		 * clocks enabled
1688		 */
1689		intel_color_modeset(pipe_crtc_state);
1690
1691		hsw_set_linetime_wm(pipe_crtc_state);
1692
1693		if (DISPLAY_VER(display) >= 11)
1694			icl_set_pipe_chicken(pipe_crtc_state);
1695
1696		intel_initial_watermarks(state, pipe_crtc);
1697	}
1698
1699	intel_encoders_enable(state, crtc);
1700
1701	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1702		const struct intel_crtc_state *pipe_crtc_state =
1703			intel_atomic_get_new_crtc_state(state, pipe_crtc);
1704		enum pipe hsw_workaround_pipe;
1705
1706		if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) {
1707			intel_crtc_wait_for_next_vblank(pipe_crtc);
1708			glk_pipe_scaler_clock_gating_wa(pipe_crtc, false);
1709		}
1710
1711		/*
1712		 * If we change the relative order between pipe/planes
1713		 * enabling, we need to change the workaround.
1714		 */
1715		hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe;
1716		if (display->platform.haswell && hsw_workaround_pipe != INVALID_PIPE) {
1717			struct intel_crtc *wa_crtc =
1718				intel_crtc_for_pipe(display, hsw_workaround_pipe);
1719
1720			intel_crtc_wait_for_next_vblank(wa_crtc);
1721			intel_crtc_wait_for_next_vblank(wa_crtc);
1722		}
1723	}
1724}
1725
1726static void ilk_crtc_disable(struct intel_atomic_state *state,
1727			     struct intel_crtc *crtc)
1728{
1729	struct intel_display *display = to_intel_display(crtc);
1730	const struct intel_crtc_state *old_crtc_state =
1731		intel_atomic_get_old_crtc_state(state, crtc);
1732	enum pipe pipe = crtc->pipe;
1733
1734	/*
1735	 * Sometimes spurious CPU pipe underruns happen when the
1736	 * pipe is already disabled, but FDI RX/TX is still enabled.
1737	 * Happens at least with VGA+HDMI cloning. Suppress them.
1738	 */
1739	intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
1740	intel_set_pch_fifo_underrun_reporting(display, pipe, false);
1741
1742	intel_encoders_disable(state, crtc);
1743
1744	intel_crtc_vblank_off(old_crtc_state);
1745
1746	intel_disable_transcoder(old_crtc_state);
1747
1748	ilk_pfit_disable(old_crtc_state);
1749
1750	if (old_crtc_state->has_pch_encoder)
1751		ilk_pch_disable(state, crtc);
1752
1753	intel_encoders_post_disable(state, crtc);
1754
1755	if (old_crtc_state->has_pch_encoder)
1756		ilk_pch_post_disable(state, crtc);
1757
1758	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
1759	intel_set_pch_fifo_underrun_reporting(display, pipe, true);
1760}
1761
1762static void hsw_crtc_disable(struct intel_atomic_state *state,
1763			     struct intel_crtc *crtc)
1764{
1765	struct intel_display *display = to_intel_display(state);
1766	const struct intel_crtc_state *old_crtc_state =
1767		intel_atomic_get_old_crtc_state(state, crtc);
1768	struct intel_crtc *pipe_crtc;
1769	int i;
1770
1771	/*
1772	 * FIXME collapse everything to one hook.
1773	 * Need care with mst->ddi interactions.
1774	 */
1775	intel_encoders_disable(state, crtc);
1776	intel_encoders_post_disable(state, crtc);
1777
1778	intel_dpll_disable(old_crtc_state);
1779
1780	intel_encoders_post_pll_disable(state, crtc);
1781
1782	for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
1783		const struct intel_crtc_state *old_pipe_crtc_state =
1784			intel_atomic_get_old_crtc_state(state, pipe_crtc);
1785
1786		intel_dmc_disable_pipe(old_pipe_crtc_state);
1787	}
1788}
1789
1790/* Prefer intel_encoder_is_combo() */
1791bool intel_phy_is_combo(struct intel_display *display, enum phy phy)
1792{
1793	if (phy == PHY_NONE)
1794		return false;
1795	else if (display->platform.alderlake_s)
1796		return phy <= PHY_E;
1797	else if (display->platform.dg1 || display->platform.rocketlake)
1798		return phy <= PHY_D;
1799	else if (display->platform.jasperlake || display->platform.elkhartlake)
1800		return phy <= PHY_C;
1801	else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12))
1802		return phy <= PHY_B;
1803	else
1804		/*
1805		 * DG2 outputs labelled as "combo PHY" in the bspec use
1806		 * SNPS PHYs with completely different programming,
1807		 * hence we always return false here.
1808		 */
1809		return false;
1810}
1811
1812/* Prefer intel_encoder_is_tc() */
1813bool intel_phy_is_tc(struct intel_display *display, enum phy phy)
1814{
1815	/*
1816	 * Discrete GPU phy's are not attached to FIA's to support TC
1817	 * subsystem Legacy or non-legacy, and only support native DP/HDMI
1818	 */
1819	if (display->platform.dgfx)
1820		return false;
1821
1822	if (DISPLAY_VER(display) >= 13)
1823		return phy >= PHY_F && phy <= PHY_I;
1824	else if (display->platform.tigerlake)
1825		return phy >= PHY_D && phy <= PHY_I;
1826	else if (display->platform.icelake)
1827		return phy >= PHY_C && phy <= PHY_F;
1828
1829	return false;
1830}
1831
1832/* Prefer intel_encoder_is_snps() */
1833bool intel_phy_is_snps(struct intel_display *display, enum phy phy)
1834{
1835	/*
1836	 * For DG2, and for DG2 only, all four "combo" ports and the TC1 port
1837	 * (PHY E) use Synopsis PHYs. See intel_phy_is_tc().
1838	 */
1839	return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E;
1840}
1841
1842/* Prefer intel_encoder_to_phy() */
1843enum phy intel_port_to_phy(struct intel_display *display, enum port port)
1844{
1845	if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD)
1846		return PHY_D + port - PORT_D_XELPD;
1847	else if (DISPLAY_VER(display) >= 13 && port >= PORT_TC1)
1848		return PHY_F + port - PORT_TC1;
1849	else if (display->platform.alderlake_s && port >= PORT_TC1)
1850		return PHY_B + port - PORT_TC1;
1851	else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1)
1852		return PHY_C + port - PORT_TC1;
1853	else if ((display->platform.jasperlake || display->platform.elkhartlake) &&
1854		 port == PORT_D)
1855		return PHY_A;
1856
1857	return PHY_A + port - PORT_A;
1858}
1859
1860/* Prefer intel_encoder_to_tc() */
1861enum tc_port intel_port_to_tc(struct intel_display *display, enum port port)
1862{
1863	if (!intel_phy_is_tc(display, intel_port_to_phy(display, port)))
1864		return TC_PORT_NONE;
1865
1866	if (DISPLAY_VER(display) >= 12)
1867		return TC_PORT_1 + port - PORT_TC1;
1868	else
1869		return TC_PORT_1 + port - PORT_C;
1870}
1871
1872enum phy intel_encoder_to_phy(struct intel_encoder *encoder)
1873{
1874	struct intel_display *display = to_intel_display(encoder);
1875
1876	return intel_port_to_phy(display, encoder->port);
1877}
1878
1879bool intel_encoder_is_combo(struct intel_encoder *encoder)
1880{
1881	struct intel_display *display = to_intel_display(encoder);
1882
1883	return intel_phy_is_combo(display, intel_encoder_to_phy(encoder));
1884}
1885
1886bool intel_encoder_is_snps(struct intel_encoder *encoder)
1887{
1888	struct intel_display *display = to_intel_display(encoder);
1889
1890	return intel_phy_is_snps(display, intel_encoder_to_phy(encoder));
1891}
1892
1893bool intel_encoder_is_tc(struct intel_encoder *encoder)
1894{
1895	struct intel_display *display = to_intel_display(encoder);
1896
1897	return intel_phy_is_tc(display, intel_encoder_to_phy(encoder));
1898}
1899
1900enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder)
1901{
1902	struct intel_display *display = to_intel_display(encoder);
1903
1904	return intel_port_to_tc(display, encoder->port);
1905}
1906
1907enum intel_display_power_domain
1908intel_aux_power_domain(struct intel_digital_port *dig_port)
1909{
1910	struct intel_display *display = to_intel_display(dig_port);
1911
1912	if (intel_tc_port_in_tbt_alt_mode(dig_port))
1913		return intel_display_power_tbt_aux_domain(display, dig_port->aux_ch);
1914
1915	return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);
1916}
1917
1918static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1919				   struct intel_power_domain_mask *mask)
1920{
1921	struct intel_display *display = to_intel_display(crtc_state);
1922	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1923	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1924	struct drm_encoder *encoder;
1925	enum pipe pipe = crtc->pipe;
1926
1927	bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
1928
1929	if (!crtc_state->hw.active)
1930		return;
1931
1932	set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
1933	set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
1934	if (crtc_state->pch_pfit.enabled ||
1935	    crtc_state->pch_pfit.force_thru)
1936		set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
1937
1938	drm_for_each_encoder_mask(encoder, display->drm,
1939				  crtc_state->uapi.encoder_mask) {
1940		struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1941
1942		set_bit(intel_encoder->power_domain, mask->bits);
1943	}
1944
1945	if (HAS_DDI(display) && crtc_state->has_audio)
1946		set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
1947
1948	if (crtc_state->intel_dpll)
1949		set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
1950
1951	if (crtc_state->dsc.compression_enable)
1952		set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
1953}
1954
1955void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1956					  struct intel_power_domain_mask *old_domains)
1957{
1958	struct intel_display *display = to_intel_display(crtc_state);
1959	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1960	enum intel_display_power_domain domain;
1961	struct intel_power_domain_mask domains, new_domains;
1962
1963	get_crtc_power_domains(crtc_state, &domains);
1964
1965	bitmap_andnot(new_domains.bits,
1966		      domains.bits,
1967		      crtc->enabled_power_domains.mask.bits,
1968		      POWER_DOMAIN_NUM);
1969	bitmap_andnot(old_domains->bits,
1970		      crtc->enabled_power_domains.mask.bits,
1971		      domains.bits,
1972		      POWER_DOMAIN_NUM);
1973
1974	for_each_power_domain(domain, &new_domains)
1975		intel_display_power_get_in_set(display,
1976					       &crtc->enabled_power_domains,
1977					       domain);
1978}
1979
1980void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
1981					  struct intel_power_domain_mask *domains)
1982{
1983	struct intel_display *display = to_intel_display(crtc);
1984
1985	intel_display_power_put_mask_in_set(display,
1986					    &crtc->enabled_power_domains,
1987					    domains);
1988}
1989
1990static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1991{
1992	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1993	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1994
1995	if (intel_crtc_has_dp_encoder(crtc_state)) {
1996		intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1997					       &crtc_state->dp_m_n);
1998		intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1999					       &crtc_state->dp_m2_n2);
2000	}
2001
2002	intel_set_transcoder_timings(crtc_state);
2003
2004	i9xx_set_pipeconf(crtc_state);
2005}
2006
2007static void valleyview_crtc_enable(struct intel_atomic_state *state,
2008				   struct intel_crtc *crtc)
2009{
2010	struct intel_display *display = to_intel_display(crtc);
2011	const struct intel_crtc_state *new_crtc_state =
2012		intel_atomic_get_new_crtc_state(state, crtc);
2013	enum pipe pipe = crtc->pipe;
2014
2015	if (drm_WARN_ON(display->drm, crtc->active))
2016		return;
2017
2018	i9xx_configure_cpu_transcoder(new_crtc_state);
2019
2020	intel_set_pipe_src_size(new_crtc_state);
2021
2022	intel_de_write(display, VLV_PIPE_MSA_MISC(display, pipe), 0);
2023
2024	if (display->platform.cherryview && pipe == PIPE_B) {
2025		intel_de_write(display, CHV_BLEND(display, pipe),
2026			       CHV_BLEND_LEGACY);
2027		intel_de_write(display, CHV_CANVAS(display, pipe), 0);
2028	}
2029
2030	crtc->active = true;
2031
2032	intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
2033
2034	intel_encoders_pre_pll_enable(state, crtc);
2035
2036	if (display->platform.cherryview)
2037		chv_enable_pll(new_crtc_state);
2038	else
2039		vlv_enable_pll(new_crtc_state);
2040
2041	intel_encoders_pre_enable(state, crtc);
2042
2043	i9xx_pfit_enable(new_crtc_state);
2044
2045	intel_color_modeset(new_crtc_state);
2046
2047	intel_initial_watermarks(state, crtc);
2048	intel_enable_transcoder(new_crtc_state);
2049
2050	intel_crtc_vblank_on(new_crtc_state);
2051
2052	intel_encoders_enable(state, crtc);
2053}
2054
2055static void i9xx_crtc_enable(struct intel_atomic_state *state,
2056			     struct intel_crtc *crtc)
2057{
2058	struct intel_display *display = to_intel_display(crtc);
2059	const struct intel_crtc_state *new_crtc_state =
2060		intel_atomic_get_new_crtc_state(state, crtc);
2061	enum pipe pipe = crtc->pipe;
2062
2063	if (drm_WARN_ON(display->drm, crtc->active))
2064		return;
2065
2066	i9xx_configure_cpu_transcoder(new_crtc_state);
2067
2068	intel_set_pipe_src_size(new_crtc_state);
2069
2070	crtc->active = true;
2071
2072	if (DISPLAY_VER(display) != 2)
2073		intel_set_cpu_fifo_underrun_reporting(display, pipe, true);
2074
2075	intel_encoders_pre_enable(state, crtc);
2076
2077	i9xx_enable_pll(new_crtc_state);
2078
2079	i9xx_pfit_enable(new_crtc_state);
2080
2081	intel_color_modeset(new_crtc_state);
2082
2083	if (!intel_initial_watermarks(state, crtc))
2084		intel_update_watermarks(display);
2085	intel_enable_transcoder(new_crtc_state);
2086
2087	intel_crtc_vblank_on(new_crtc_state);
2088
2089	intel_encoders_enable(state, crtc);
2090
2091	/* prevents spurious underruns */
2092	if (DISPLAY_VER(display) == 2)
2093		intel_crtc_wait_for_next_vblank(crtc);
2094}
2095
2096static void i9xx_crtc_disable(struct intel_atomic_state *state,
2097			      struct intel_crtc *crtc)
2098{
2099	struct intel_display *display = to_intel_display(state);
2100	struct intel_crtc_state *old_crtc_state =
2101		intel_atomic_get_old_crtc_state(state, crtc);
2102	enum pipe pipe = crtc->pipe;
2103
2104	/*
2105	 * On gen2 planes are double buffered but the pipe isn't, so we must
2106	 * wait for planes to fully turn off before disabling the pipe.
2107	 */
2108	if (DISPLAY_VER(display) == 2)
2109		intel_crtc_wait_for_next_vblank(crtc);
2110
2111	intel_encoders_disable(state, crtc);
2112
2113	intel_crtc_vblank_off(old_crtc_state);
2114
2115	intel_disable_transcoder(old_crtc_state);
2116
2117	i9xx_pfit_disable(old_crtc_state);
2118
2119	intel_encoders_post_disable(state, crtc);
2120
2121	if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2122		if (display->platform.cherryview)
2123			chv_disable_pll(display, pipe);
2124		else if (display->platform.valleyview)
2125			vlv_disable_pll(display, pipe);
2126		else
2127			i9xx_disable_pll(old_crtc_state);
2128	}
2129
2130	intel_encoders_post_pll_disable(state, crtc);
2131
2132	if (DISPLAY_VER(display) != 2)
2133		intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
2134
2135	if (!display->funcs.wm->initial_watermarks)
2136		intel_update_watermarks(display);
2137
2138	/* clock the pipe down to 640x480@60 to potentially save power */
2139	if (display->platform.i830)
2140		i830_enable_pipe(display, pipe);
2141}
2142
2143void intel_encoder_destroy(struct drm_encoder *encoder)
2144{
2145	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2146
2147	drm_encoder_cleanup(encoder);
2148	kfree(intel_encoder);
2149}
2150
2151static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2152{
2153	struct intel_display *display = to_intel_display(crtc);
2154
2155	/* GDG double wide on either pipe, otherwise pipe A only */
2156	return HAS_DOUBLE_WIDE(display) &&
2157		(crtc->pipe == PIPE_A || display->platform.i915g);
2158}
2159
2160static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2161{
2162	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2163	struct drm_rect src;
2164
2165	/*
2166	 * We only use IF-ID interlacing. If we ever use
2167	 * PF-ID we'll need to adjust the pixel_rate here.
2168	 */
2169
2170	if (!crtc_state->pch_pfit.enabled)
2171		return pixel_rate;
2172
2173	drm_rect_init(&src, 0, 0,
2174		      drm_rect_width(&crtc_state->pipe_src) << 16,
2175		      drm_rect_height(&crtc_state->pipe_src) << 16);
2176
2177	return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
2178				   pixel_rate);
2179}
2180
2181static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2182					 const struct drm_display_mode *timings)
2183{
2184	mode->hdisplay = timings->crtc_hdisplay;
2185	mode->htotal = timings->crtc_htotal;
2186	mode->hsync_start = timings->crtc_hsync_start;
2187	mode->hsync_end = timings->crtc_hsync_end;
2188
2189	mode->vdisplay = timings->crtc_vdisplay;
2190	mode->vtotal = timings->crtc_vtotal;
2191	mode->vsync_start = timings->crtc_vsync_start;
2192	mode->vsync_end = timings->crtc_vsync_end;
2193
2194	mode->flags = timings->flags;
2195	mode->type = DRM_MODE_TYPE_DRIVER;
2196
2197	mode->clock = timings->crtc_clock;
2198
2199	drm_mode_set_name(mode);
2200}
2201
2202static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2203{
2204	struct intel_display *display = to_intel_display(crtc_state);
2205
2206	if (HAS_GMCH(display))
2207		/* FIXME calculate proper pipe pixel rate for GMCH pfit */
2208		crtc_state->pixel_rate =
2209			crtc_state->hw.pipe_mode.crtc_clock;
2210	else
2211		crtc_state->pixel_rate =
2212			ilk_pipe_pixel_rate(crtc_state);
2213}
2214
2215static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2216					struct drm_display_mode *mode)
2217{
2218	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
2219
2220	if (num_pipes == 1)
2221		return;
2222
2223	mode->crtc_clock /= num_pipes;
2224	mode->crtc_hdisplay /= num_pipes;
2225	mode->crtc_hblank_start /= num_pipes;
2226	mode->crtc_hblank_end /= num_pipes;
2227	mode->crtc_hsync_start /= num_pipes;
2228	mode->crtc_hsync_end /= num_pipes;
2229	mode->crtc_htotal /= num_pipes;
2230}
2231
2232static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2233					  struct drm_display_mode *mode)
2234{
2235	int overlap = crtc_state->splitter.pixel_overlap;
2236	int n = crtc_state->splitter.link_count;
2237
2238	if (!crtc_state->splitter.enable)
2239		return;
2240
2241	/*
2242	 * eDP MSO uses segment timings from EDID for transcoder
2243	 * timings, but full mode for everything else.
2244	 *
2245	 * h_full = (h_segment - pixel_overlap) * link_count
2246	 */
2247	mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2248	mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2249	mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2250	mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2251	mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2252	mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2253	mode->crtc_clock *= n;
2254}
2255
2256static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2257{
2258	struct drm_display_mode *mode = &crtc_state->hw.mode;
2259	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2260	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2261
2262	/*
2263	 * Start with the adjusted_mode crtc timings, which
2264	 * have been filled with the transcoder timings.
2265	 */
2266	drm_mode_copy(pipe_mode, adjusted_mode);
2267
2268	/* Expand MSO per-segment transcoder timings to full */
2269	intel_splitter_adjust_timings(crtc_state, pipe_mode);
2270
2271	/*
2272	 * We want the full numbers in adjusted_mode normal timings,
2273	 * adjusted_mode crtc timings are left with the raw transcoder
2274	 * timings.
2275	 */
2276	intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2277
2278	/* Populate the "user" mode with full numbers */
2279	drm_mode_copy(mode, pipe_mode);
2280	intel_mode_from_crtc_timings(mode, mode);
2281	mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2282		intel_crtc_num_joined_pipes(crtc_state);
2283	mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2284
2285	/* Derive per-pipe timings in case joiner is used */
2286	intel_joiner_adjust_timings(crtc_state, pipe_mode);
2287	intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2288
2289	intel_crtc_compute_pixel_rate(crtc_state);
2290}
2291
2292void intel_encoder_get_config(struct intel_encoder *encoder,
2293			      struct intel_crtc_state *crtc_state)
2294{
2295	encoder->get_config(encoder, crtc_state);
2296
2297	intel_crtc_readout_derived_state(crtc_state);
2298}
2299
2300static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2301{
2302	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
2303	int width, height;
2304
2305	if (num_pipes == 1)
2306		return;
2307
2308	width = drm_rect_width(&crtc_state->pipe_src);
2309	height = drm_rect_height(&crtc_state->pipe_src);
2310
2311	drm_rect_init(&crtc_state->pipe_src, 0, 0,
2312		      width / num_pipes, height);
2313}
2314
2315static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2316{
2317	struct intel_display *display = to_intel_display(crtc_state);
2318	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2319
2320	intel_joiner_compute_pipe_src(crtc_state);
2321
2322	/*
2323	 * Pipe horizontal size must be even in:
2324	 * - DVO ganged mode
2325	 * - LVDS dual channel mode
2326	 * - Double wide pipe
2327	 */
2328	if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2329		if (crtc_state->double_wide) {
2330			drm_dbg_kms(display->drm,
2331				    "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2332				    crtc->base.base.id, crtc->base.name);
2333			return -EINVAL;
2334		}
2335
2336		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
2337		    intel_is_dual_link_lvds(display)) {
2338			drm_dbg_kms(display->drm,
2339				    "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2340				    crtc->base.base.id, crtc->base.name);
2341			return -EINVAL;
2342		}
2343	}
2344
2345	return 0;
2346}
2347
2348static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2349{
2350	struct intel_display *display = to_intel_display(crtc_state);
2351	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2352	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2353	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2354	int clock_limit = display->cdclk.max_dotclk_freq;
2355
2356	/*
2357	 * Start with the adjusted_mode crtc timings, which
2358	 * have been filled with the transcoder timings.
2359	 */
2360	drm_mode_copy(pipe_mode, adjusted_mode);
2361
2362	/* Expand MSO per-segment transcoder timings to full */
2363	intel_splitter_adjust_timings(crtc_state, pipe_mode);
2364
2365	/* Derive per-pipe timings in case joiner is used */
2366	intel_joiner_adjust_timings(crtc_state, pipe_mode);
2367	intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2368
2369	if (DISPLAY_VER(display) < 4) {
2370		clock_limit = display->cdclk.max_cdclk_freq * 9 / 10;
2371
2372		/*
2373		 * Enable double wide mode when the dot clock
2374		 * is > 90% of the (display) core speed.
2375		 */
2376		if (intel_crtc_supports_double_wide(crtc) &&
2377		    pipe_mode->crtc_clock > clock_limit) {
2378			clock_limit = display->cdclk.max_dotclk_freq;
2379			crtc_state->double_wide = true;
2380		}
2381	}
2382
2383	if (pipe_mode->crtc_clock > clock_limit) {
2384		drm_dbg_kms(display->drm,
2385			    "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2386			    crtc->base.base.id, crtc->base.name,
2387			    pipe_mode->crtc_clock, clock_limit,
2388			    str_yes_no(crtc_state->double_wide));
2389		return -EINVAL;
2390	}
2391
2392	return 0;
2393}
2394
2395static int intel_crtc_set_context_latency(struct intel_crtc_state *crtc_state)
2396{
2397	struct intel_display *display = to_intel_display(crtc_state);
2398	int set_context_latency = 0;
2399
2400	if (!HAS_DSB(display))
2401		return 0;
2402
2403	set_context_latency = max(set_context_latency,
2404				  intel_psr_min_set_context_latency(crtc_state));
2405
2406	return set_context_latency;
2407}
2408
2409static int intel_crtc_compute_set_context_latency(struct intel_atomic_state *state,
2410						  struct intel_crtc *crtc)
2411{
2412	struct intel_display *display = to_intel_display(state);
2413	struct intel_crtc_state *crtc_state =
2414		intel_atomic_get_new_crtc_state(state, crtc);
2415	struct drm_display_mode *adjusted_mode =
2416		&crtc_state->hw.adjusted_mode;
2417	int set_context_latency, max_vblank_delay;
2418
2419	set_context_latency = intel_crtc_set_context_latency(crtc_state);
2420
2421	max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1;
2422
2423	if (set_context_latency > max_vblank_delay) {
2424		drm_dbg_kms(display->drm, "[CRTC:%d:%s] set context latency (%d) exceeds max (%d)\n",
2425			    crtc->base.base.id, crtc->base.name,
2426			    set_context_latency,
2427			    max_vblank_delay);
2428		return -EINVAL;
2429	}
2430
2431	crtc_state->set_context_latency = set_context_latency;
2432	adjusted_mode->crtc_vblank_start += set_context_latency;
2433
2434	return 0;
2435}
2436
2437static int intel_crtc_compute_config(struct intel_atomic_state *state,
2438				     struct intel_crtc *crtc)
2439{
2440	struct intel_crtc_state *crtc_state =
2441		intel_atomic_get_new_crtc_state(state, crtc);
2442	int ret;
2443
2444	ret = intel_dpll_crtc_compute_clock(state, crtc);
2445	if (ret)
2446		return ret;
2447
2448	ret = intel_crtc_compute_set_context_latency(state, crtc);
2449	if (ret)
2450		return ret;
2451
2452	ret = intel_crtc_compute_pipe_src(crtc_state);
2453	if (ret)
2454		return ret;
2455
2456	ret = intel_crtc_compute_pipe_mode(crtc_state);
2457	if (ret)
2458		return ret;
2459
2460	intel_crtc_compute_pixel_rate(crtc_state);
2461
2462	if (crtc_state->has_pch_encoder)
2463		return ilk_fdi_compute_config(crtc, crtc_state);
2464
2465	intel_vrr_compute_guardband(crtc_state);
2466
2467	return 0;
2468}
2469
2470static void
2471intel_reduce_m_n_ratio(u32 *num, u32 *den)
2472{
2473	while (*num > DATA_LINK_M_N_MASK ||
2474	       *den > DATA_LINK_M_N_MASK) {
2475		*num >>= 1;
2476		*den >>= 1;
2477	}
2478}
2479
2480static void compute_m_n(u32 *ret_m, u32 *ret_n,
2481			u32 m, u32 n, u32 constant_n)
2482{
2483	if (constant_n)
2484		*ret_n = constant_n;
2485	else
2486		*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2487
2488	*ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2489	intel_reduce_m_n_ratio(ret_m, ret_n);
2490}
2491
2492void
2493intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
2494		       int pixel_clock, int link_clock,
2495		       int bw_overhead,
2496		       struct intel_link_m_n *m_n)
2497{
2498	u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
2499	u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16,
2500						  bw_overhead);
2501	u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes);
2502
2503	/*
2504	 * Windows/BIOS uses fixed M/N values always. Follow suit.
2505	 *
2506	 * Also several DP dongles in particular seem to be fussy
2507	 * about too large link M/N values. Presumably the 20bit
2508	 * value used by Windows/BIOS is acceptable to everyone.
2509	 */
2510	m_n->tu = 64;
2511	compute_m_n(&m_n->data_m, &m_n->data_n,
2512		    data_m, data_n,
2513		    0x8000000);
2514
2515	compute_m_n(&m_n->link_m, &m_n->link_n,
2516		    pixel_clock, link_symbol_clock,
2517		    0x80000);
2518}
2519
2520void intel_panel_sanitize_ssc(struct intel_display *display)
2521{
2522	/*
2523	 * There may be no VBT; and if the BIOS enabled SSC we can
2524	 * just keep using it to avoid unnecessary flicker.  Whereas if the
2525	 * BIOS isn't using it, don't assume it will work even if the VBT
2526	 * indicates as much.
2527	 */
2528	if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) {
2529		bool bios_lvds_use_ssc = intel_de_read(display,
2530						       PCH_DREF_CONTROL) &
2531			DREF_SSC1_ENABLE;
2532
2533		if (display->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2534			drm_dbg_kms(display->drm,
2535				    "SSC %s by BIOS, overriding VBT which says %s\n",
2536				    str_enabled_disabled(bios_lvds_use_ssc),
2537				    str_enabled_disabled(display->vbt.lvds_use_ssc));
2538			display->vbt.lvds_use_ssc = bios_lvds_use_ssc;
2539		}
2540	}
2541}
2542
2543void intel_zero_m_n(struct intel_link_m_n *m_n)
2544{
2545	/* corresponds to 0 register value */
2546	memset(m_n, 0, sizeof(*m_n));
2547	m_n->tu = 1;
2548}
2549
2550void intel_set_m_n(struct intel_display *display,
2551		   const struct intel_link_m_n *m_n,
2552		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2553		   i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2554{
2555	intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2556	intel_de_write(display, data_n_reg, m_n->data_n);
2557	intel_de_write(display, link_m_reg, m_n->link_m);
2558	/*
2559	 * On BDW+ writing LINK_N arms the double buffered update
2560	 * of all the M/N registers, so it must be written last.
2561	 */
2562	intel_de_write(display, link_n_reg, m_n->link_n);
2563}
2564
2565bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
2566				    enum transcoder transcoder)
2567{
2568	if (display->platform.haswell)
2569		return transcoder == TRANSCODER_EDP;
2570
2571	return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;
2572}
2573
2574void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2575				    enum transcoder transcoder,
2576				    const struct intel_link_m_n *m_n)
2577{
2578	struct intel_display *display = to_intel_display(crtc);
2579	enum pipe pipe = crtc->pipe;
2580
2581	if (DISPLAY_VER(display) >= 5)
2582		intel_set_m_n(display, m_n,
2583			      PIPE_DATA_M1(display, transcoder),
2584			      PIPE_DATA_N1(display, transcoder),
2585			      PIPE_LINK_M1(display, transcoder),
2586			      PIPE_LINK_N1(display, transcoder));
2587	else
2588		intel_set_m_n(display, m_n,
2589			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2590			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2591}
2592
2593void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2594				    enum transcoder transcoder,
2595				    const struct intel_link_m_n *m_n)
2596{
2597	struct intel_display *display = to_intel_display(crtc);
2598
2599	if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))
2600		return;
2601
2602	intel_set_m_n(display, m_n,
2603		      PIPE_DATA_M2(display, transcoder),
2604		      PIPE_DATA_N2(display, transcoder),
2605		      PIPE_LINK_M2(display, transcoder),
2606		      PIPE_LINK_N2(display, transcoder));
2607}
2608
2609static bool
2610transcoder_has_vrr(const struct intel_crtc_state *crtc_state)
2611{
2612	struct intel_display *display = to_intel_display(crtc_state);
2613	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2614
2615	return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder);
2616}
2617
2618static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2619{
2620	struct intel_display *display = to_intel_display(crtc_state);
2621	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2622	enum pipe pipe = crtc->pipe;
2623	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2624	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2625	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2626	int vsyncshift = 0;
2627
2628	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
2629
2630	/* We need to be careful not to changed the adjusted mode, for otherwise
2631	 * the hw state checker will get angry at the mismatch. */
2632	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2633	crtc_vtotal = adjusted_mode->crtc_vtotal;
2634	crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2635	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2636
2637	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2638		/* the chip adds 2 halflines automatically */
2639		crtc_vtotal -= 1;
2640		crtc_vblank_end -= 1;
2641
2642		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2643			vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2644		else
2645			vsyncshift = adjusted_mode->crtc_hsync_start -
2646				adjusted_mode->crtc_htotal / 2;
2647		if (vsyncshift < 0)
2648			vsyncshift += adjusted_mode->crtc_htotal;
2649	}
2650
2651	/*
2652	 * VBLANK_START no longer works on ADL+, instead we must use
2653	 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
2654	 */
2655	if (DISPLAY_VER(display) >= 13) {
2656		intel_de_write(display,
2657			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
2658			       crtc_state->set_context_latency);
2659
2660		/*
2661		 * VBLANK_START not used by hw, just clear it
2662		 * to make it stand out in register dumps.
2663		 */
2664		crtc_vblank_start = 1;
2665	} else if (DISPLAY_VER(display) == 12) {
2666		/* VBLANK_START - VACTIVE defines SCL on TGL */
2667		crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;
2668	}
2669
2670	if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35)
2671		intel_de_write(display,
2672			       TRANS_VSYNCSHIFT(display, cpu_transcoder),
2673			       vsyncshift);
2674
2675	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
2676		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
2677		       HTOTAL(adjusted_mode->crtc_htotal - 1));
2678	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
2679		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
2680		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
2681	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
2682		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
2683		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
2684
2685	/*
2686	 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
2687	 * bits are not required. Since the support for these bits is going to
2688	 * be deprecated in upcoming platforms, avoid writing these bits for the
2689	 * platforms that do not use legacy Timing Generator.
2690	 */
2691	if (intel_vrr_always_use_vrr_tg(display))
2692		crtc_vtotal = 1;
2693
2694	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
2695		       VACTIVE(crtc_vdisplay - 1) |
2696		       VTOTAL(crtc_vtotal - 1));
2697	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
2698		       VBLANK_START(crtc_vblank_start - 1) |
2699		       VBLANK_END(crtc_vblank_end - 1));
2700	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
2701		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
2702		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
2703
2704	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2705	 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2706	 * documented on the DDI_FUNC_CTL register description, EDP Input Select
2707	 * bits. */
2708	if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP &&
2709	    (pipe == PIPE_B || pipe == PIPE_C))
2710		intel_de_write(display, TRANS_VTOTAL(display, pipe),
2711			       VACTIVE(crtc_vdisplay - 1) |
2712			       VTOTAL(crtc_vtotal - 1));
2713
2714	if (DISPLAY_VER(display) >= 30) {
2715		/*
2716		 * Address issues for resolutions with high refresh rate that
2717		 * have small Hblank, specifically where Hblank is smaller than
2718		 * one MTP. Simulations indicate this will address the
2719		 * jitter issues that currently causes BS to be immediately
2720		 * followed by BE which DPRX devices are unable to handle.
2721		 * https://groups.vesa.org/wg/DP/document/20494
2722		 */
2723		intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
2724			       crtc_state->min_hblank);
2725	}
2726}
2727
2728static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
2729{
2730	struct intel_display *display = to_intel_display(crtc_state);
2731	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2732	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2733	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2734
2735	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
2736
2737	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2738	crtc_vtotal = adjusted_mode->crtc_vtotal;
2739	crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2740	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2741
2742	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2743		/* the chip adds 2 halflines automatically */
2744		crtc_vtotal -= 1;
2745		crtc_vblank_end -= 1;
2746	}
2747
2748	if (DISPLAY_VER(display) >= 13) {
2749		intel_de_write(display,
2750			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
2751			       crtc_state->set_context_latency);
2752
2753		/*
2754		 * VBLANK_START not used by hw, just clear it
2755		 * to make it stand out in register dumps.
2756		 */
2757		crtc_vblank_start = 1;
2758	} else if (DISPLAY_VER(display) == 12) {
2759		/* VBLANK_START - VACTIVE defines SCL on TGL */
2760		crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;
2761	}
2762
2763	/*
2764	 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
2765	 * But let's write it anyway to keep the state checker happy.
2766	 */
2767	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
2768		       VBLANK_START(crtc_vblank_start - 1) |
2769		       VBLANK_END(crtc_vblank_end - 1));
2770	/*
2771	 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
2772	 * bits are not required. Since the support for these bits is going to
2773	 * be deprecated in upcoming platforms, avoid writing these bits for the
2774	 * platforms that do not use legacy Timing Generator.
2775	 */
2776	if (intel_vrr_always_use_vrr_tg(display))
2777		crtc_vtotal = 1;
2778
2779	/*
2780	 * The double buffer latch point for TRANS_VTOTAL
2781	 * is the transcoder's undelayed vblank.
2782	 */
2783	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
2784		       VACTIVE(crtc_vdisplay - 1) |
2785		       VTOTAL(crtc_vtotal - 1));
2786
2787	intel_vrr_set_fixed_rr_timings(crtc_state);
2788	intel_vrr_transcoder_enable(crtc_state);
2789}
2790
2791static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2792{
2793	struct intel_display *display = to_intel_display(crtc_state);
2794	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2795	int width = drm_rect_width(&crtc_state->pipe_src);
2796	int height = drm_rect_height(&crtc_state->pipe_src);
2797	enum pipe pipe = crtc->pipe;
2798
2799	/* pipesrc controls the size that is scaled from, which should
2800	 * always be the user's requested size.
2801	 */
2802	intel_de_write(display, PIPESRC(display, pipe),
2803		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2804}
2805
2806static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2807{
2808	struct intel_display *display = to_intel_display(crtc_state);
2809	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2810
2811	if (DISPLAY_VER(display) == 2 || DISPLAY_VER(display) >= 35)
2812		return false;
2813
2814	if (DISPLAY_VER(display) >= 9 ||
2815	    display->platform.broadwell || display->platform.haswell)
2816		return intel_de_read(display,
2817				     TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2818	else
2819		return intel_de_read(display,
2820				     TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2821}
2822
2823static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2824					 struct intel_crtc_state *pipe_config)
2825{
2826	struct intel_display *display = to_intel_display(crtc);
2827	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2828	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2829	u32 tmp;
2830
2831	tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder));
2832	adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
2833	adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
2834
2835	if (!transcoder_is_dsi(cpu_transcoder)) {
2836		tmp = intel_de_read(display,
2837				    TRANS_HBLANK(display, cpu_transcoder));
2838		adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
2839		adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
2840	}
2841
2842	tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder));
2843	adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
2844	adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
2845
2846	tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));
2847	adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
2848	adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
2849
2850	/* FIXME TGL+ DSI transcoders have this! */
2851	if (!transcoder_is_dsi(cpu_transcoder)) {
2852		tmp = intel_de_read(display,
2853				    TRANS_VBLANK(display, cpu_transcoder));
2854		adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
2855		adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
2856	}
2857	tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder));
2858	adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
2859	adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
2860
2861	if (intel_pipe_is_interlaced(pipe_config)) {
2862		adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
2863		adjusted_mode->crtc_vtotal += 1;
2864		adjusted_mode->crtc_vblank_end += 1;
2865	}
2866
2867	if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) {
2868		pipe_config->set_context_latency =
2869			intel_de_read(display,
2870				      TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder));
2871		adjusted_mode->crtc_vblank_start =
2872			adjusted_mode->crtc_vdisplay +
2873			pipe_config->set_context_latency;
2874	} else if (DISPLAY_VER(display) == 12) {
2875		/*
2876		 * TGL doesn't have a dedicated register for SCL.
2877		 * Instead, the hardware derives SCL from the difference between
2878		 * TRANS_VBLANK.vblank_start and TRANS_VTOTAL.vactive.
2879		 * To reflect the HW behaviour, readout the value for SCL as
2880		 * Vblank start - Vactive.
2881		 */
2882		pipe_config->set_context_latency =
2883			adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
2884	}
2885
2886	if (DISPLAY_VER(display) >= 30)
2887		pipe_config->min_hblank = intel_de_read(display,
2888							DP_MIN_HBLANK_CTL(cpu_transcoder));
2889}
2890
2891static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2892{
2893	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2894	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
2895	enum pipe primary_pipe, pipe = crtc->pipe;
2896	int width;
2897
2898	if (num_pipes == 1)
2899		return;
2900
2901	primary_pipe = joiner_primary_pipe(crtc_state);
2902	width = drm_rect_width(&crtc_state->pipe_src);
2903
2904	drm_rect_translate_to(&crtc_state->pipe_src,
2905			      (pipe - primary_pipe) * width, 0);
2906}
2907
2908static void intel_get_pipe_src_size(struct intel_crtc *crtc,
2909				    struct intel_crtc_state *pipe_config)
2910{
2911	struct intel_display *display = to_intel_display(crtc);
2912	u32 tmp;
2913
2914	tmp = intel_de_read(display, PIPESRC(display, crtc->pipe));
2915
2916	drm_rect_init(&pipe_config->pipe_src, 0, 0,
2917		      REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
2918		      REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
2919
2920	intel_joiner_adjust_pipe_src(pipe_config);
2921}
2922
2923void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
2924{
2925	struct intel_display *display = to_intel_display(crtc_state);
2926	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2927	u32 val = 0;
2928
2929	/*
2930	 * - We keep both pipes enabled on 830
2931	 * - During modeset the pipe is still disabled and must remain so
2932	 * - During fastset the pipe is already enabled and must remain so
2933	 */
2934	if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state))
2935		val |= TRANSCONF_ENABLE;
2936
2937	if (crtc_state->double_wide)
2938		val |= TRANSCONF_DOUBLE_WIDE;
2939
2940	/* only g4x and later have fancy bpc/dither controls */
2941	if (display->platform.g4x || display->platform.valleyview ||
2942	    display->platform.cherryview) {
2943		/* Bspec claims that we can't use dithering for 30bpp pipes. */
2944		if (crtc_state->dither && crtc_state->pipe_bpp != 30)
2945			val |= TRANSCONF_DITHER_EN |
2946				TRANSCONF_DITHER_TYPE_SP;
2947
2948		switch (crtc_state->pipe_bpp) {
2949		default:
2950			/* Case prevented by intel_choose_pipe_bpp_dither. */
2951			MISSING_CASE(crtc_state->pipe_bpp);
2952			fallthrough;
2953		case 18:
2954			val |= TRANSCONF_BPC_6;
2955			break;
2956		case 24:
2957			val |= TRANSCONF_BPC_8;
2958			break;
2959		case 30:
2960			val |= TRANSCONF_BPC_10;
2961			break;
2962		}
2963	}
2964
2965	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2966		if (DISPLAY_VER(display) < 4 ||
2967		    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2968			val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
2969		else
2970			val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
2971	} else {
2972		val |= TRANSCONF_INTERLACE_PROGRESSIVE;
2973	}
2974
2975	if ((display->platform.valleyview || display->platform.cherryview) &&
2976	    crtc_state->limited_color_range)
2977		val |= TRANSCONF_COLOR_RANGE_SELECT;
2978
2979	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
2980
2981	if (crtc_state->wgc_enable)
2982		val |= TRANSCONF_WGC_ENABLE;
2983
2984	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
2985
2986	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
2987	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
2988}
2989
2990static enum intel_output_format
2991bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
2992{
2993	struct intel_display *display = to_intel_display(crtc);
2994	u32 tmp;
2995
2996	tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));
2997
2998	if (tmp & PIPE_MISC_YUV420_ENABLE) {
2999		/*
3000		 * We support 4:2:0 in full blend mode only.
3001		 * For xe3_lpd+ this is implied in YUV420 Enable bit.
3002		 * Ensure the same for prior platforms in YUV420 Mode bit.
3003		 */
3004		if (DISPLAY_VER(display) < 30)
3005			drm_WARN_ON(display->drm,
3006				    (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
3007
3008		return INTEL_OUTPUT_FORMAT_YCBCR420;
3009	} else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
3010		return INTEL_OUTPUT_FORMAT_YCBCR444;
3011	} else {
3012		return INTEL_OUTPUT_FORMAT_RGB;
3013	}
3014}
3015
3016static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
3017				 struct intel_crtc_state *pipe_config)
3018{
3019	struct intel_display *display = to_intel_display(crtc);
3020	enum intel_display_power_domain power_domain;
3021	enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe;
3022	intel_wakeref_t wakeref;
3023	bool ret = false;
3024	u32 tmp;
3025
3026	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3027	wakeref = intel_display_power_get_if_enabled(display, power_domain);
3028	if (!wakeref)
3029		return false;
3030
3031	tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
3032	if (!(tmp & TRANSCONF_ENABLE))
3033		goto out;
3034
3035	pipe_config->cpu_transcoder = cpu_transcoder;
3036
3037	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3038	pipe_config->sink_format = pipe_config->output_format;
3039
3040	if (display->platform.g4x || display->platform.valleyview ||
3041	    display->platform.cherryview) {
3042		switch (tmp & TRANSCONF_BPC_MASK) {
3043		case TRANSCONF_BPC_6:
3044			pipe_config->pipe_bpp = 18;
3045			break;
3046		case TRANSCONF_BPC_8:
3047			pipe_config->pipe_bpp = 24;
3048			break;
3049		case TRANSCONF_BPC_10:
3050			pipe_config->pipe_bpp = 30;
3051			break;
3052		default:
3053			MISSING_CASE(tmp);
3054			break;
3055		}
3056	}
3057
3058	if ((display->platform.valleyview || display->platform.cherryview) &&
3059	    (tmp & TRANSCONF_COLOR_RANGE_SELECT))
3060		pipe_config->limited_color_range = true;
3061
3062	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
3063
3064	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3065
3066	if ((display->platform.valleyview || display->platform.cherryview) &&
3067	    (tmp & TRANSCONF_WGC_ENABLE))
3068		pipe_config->wgc_enable = true;
3069
3070	intel_color_get_config(pipe_config);
3071
3072	if (HAS_DOUBLE_WIDE(display))
3073		pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
3074
3075	intel_get_transcoder_timings(crtc, pipe_config);
3076	intel_get_pipe_src_size(crtc, pipe_config);
3077
3078	i9xx_pfit_get_config(pipe_config);
3079
3080	i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state);
3081
3082	if (DISPLAY_VER(display) >= 4) {
3083		tmp = pipe_config->dpll_hw_state.i9xx.dpll_md;
3084		pipe_config->pixel_multiplier =
3085			((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
3086			 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
3087	} else if (display->platform.i945g || display->platform.i945gm ||
3088		   display->platform.g33 || display->platform.pineview) {
3089		tmp = pipe_config->dpll_hw_state.i9xx.dpll;
3090		pipe_config->pixel_multiplier =
3091			((tmp & SDVO_MULTIPLIER_MASK)
3092			 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
3093	} else {
3094		/* Note that on i915G/GM the pixel multiplier is in the sdvo
3095		 * port and will be fixed up in the encoder->get_config
3096		 * function. */
3097		pipe_config->pixel_multiplier = 1;
3098	}
3099
3100	if (display->platform.cherryview)
3101		chv_crtc_clock_get(pipe_config);
3102	else if (display->platform.valleyview)
3103		vlv_crtc_clock_get(pipe_config);
3104	else
3105		i9xx_crtc_clock_get(pipe_config);
3106
3107	/*
3108	 * Normally the dotclock is filled in by the encoder .get_config()
3109	 * but in case the pipe is enabled w/o any ports we need a sane
3110	 * default.
3111	 */
3112	pipe_config->hw.adjusted_mode.crtc_clock =
3113		pipe_config->port_clock / pipe_config->pixel_multiplier;
3114
3115	ret = true;
3116
3117out:
3118	intel_display_power_put(display, power_domain, wakeref);
3119
3120	return ret;
3121}
3122
3123void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3124{
3125	struct intel_display *display = to_intel_display(crtc_state);
3126	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3127	u32 val = 0;
3128
3129	/*
3130	 * - During modeset the pipe is still disabled and must remain so
3131	 * - During fastset the pipe is already enabled and must remain so
3132	 */
3133	if (!intel_crtc_needs_modeset(crtc_state))
3134		val |= TRANSCONF_ENABLE;
3135
3136	switch (crtc_state->pipe_bpp) {
3137	default:
3138		/* Case prevented by intel_choose_pipe_bpp_dither. */
3139		MISSING_CASE(crtc_state->pipe_bpp);
3140		fallthrough;
3141	case 18:
3142		val |= TRANSCONF_BPC_6;
3143		break;
3144	case 24:
3145		val |= TRANSCONF_BPC_8;
3146		break;
3147	case 30:
3148		val |= TRANSCONF_BPC_10;
3149		break;
3150	case 36:
3151		val |= TRANSCONF_BPC_12;
3152		break;
3153	}
3154
3155	if (crtc_state->dither)
3156		val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3157
3158	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3159		val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3160	else
3161		val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3162
3163	/*
3164	 * This would end up with an odd purple hue over
3165	 * the entire display. Make sure we don't do it.
3166	 */
3167	drm_WARN_ON(display->drm, crtc_state->limited_color_range &&
3168		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3169
3170	if (crtc_state->limited_color_range &&
3171	    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3172		val |= TRANSCONF_COLOR_RANGE_SELECT;
3173
3174	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3175		val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
3176
3177	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
3178
3179	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3180	val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3181
3182	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
3183	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
3184}
3185
3186static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3187{
3188	struct intel_display *display = to_intel_display(crtc_state);
3189	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3190	u32 val = 0;
3191
3192	/*
3193	 * - During modeset the pipe is still disabled and must remain so
3194	 * - During fastset the pipe is already enabled and must remain so
3195	 */
3196	if (!intel_crtc_needs_modeset(crtc_state))
3197		val |= TRANSCONF_ENABLE;
3198
3199	if (display->platform.haswell && crtc_state->dither)
3200		val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3201
3202	if (DISPLAY_VER(display) < 35) {
3203		if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3204			val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3205		else
3206			val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3207	}
3208
3209	if (display->platform.haswell &&
3210	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3211		val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
3212
3213	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
3214	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
3215}
3216
3217static void bdw_set_pipe_misc(struct intel_dsb *dsb,
3218			      const struct intel_crtc_state *crtc_state)
3219{
3220	struct intel_display *display = to_intel_display(crtc_state);
3221	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3222	u32 val = 0;
3223
3224	switch (crtc_state->pipe_bpp) {
3225	case 18:
3226		val |= PIPE_MISC_BPC_6;
3227		break;
3228	case 24:
3229		val |= PIPE_MISC_BPC_8;
3230		break;
3231	case 30:
3232		val |= PIPE_MISC_BPC_10;
3233		break;
3234	case 36:
3235		/* Port output 12BPC defined for ADLP+ */
3236		if (DISPLAY_VER(display) >= 13)
3237			val |= PIPE_MISC_BPC_12_ADLP;
3238		break;
3239	default:
3240		MISSING_CASE(crtc_state->pipe_bpp);
3241		break;
3242	}
3243
3244	if (crtc_state->dither)
3245		val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
3246
3247	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3248	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3249		val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
3250
3251	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3252		val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE :
3253			PIPE_MISC_YUV420_ENABLE | PIPE_MISC_YUV420_MODE_FULL_BLEND;
3254
3255	if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state))
3256		val |= PIPE_MISC_HDR_MODE_PRECISION;
3257
3258	if (DISPLAY_VER(display) >= 12)
3259		val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
3260
3261	/* allow PSR with sprite enabled */
3262	if (display->platform.broadwell)
3263		val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE;
3264
3265	intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val);
3266}
3267
3268int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
3269{
3270	struct intel_display *display = to_intel_display(crtc);
3271	u32 tmp;
3272
3273	tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));
3274
3275	switch (tmp & PIPE_MISC_BPC_MASK) {
3276	case PIPE_MISC_BPC_6:
3277		return 18;
3278	case PIPE_MISC_BPC_8:
3279		return 24;
3280	case PIPE_MISC_BPC_10:
3281		return 30;
3282	/*
3283	 * PORT OUTPUT 12 BPC defined for ADLP+.
3284	 *
3285	 * TODO:
3286	 * For previous platforms with DSI interface, bits 5:7
3287	 * are used for storing pipe_bpp irrespective of dithering.
3288	 * Since the value of 12 BPC is not defined for these bits
3289	 * on older platforms, need to find a workaround for 12 BPC
3290	 * MIPI DSI HW readout.
3291	 */
3292	case PIPE_MISC_BPC_12_ADLP:
3293		if (DISPLAY_VER(display) >= 13)
3294			return 36;
3295		fallthrough;
3296	default:
3297		MISSING_CASE(tmp);
3298		return 0;
3299	}
3300}
3301
3302int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3303{
3304	/*
3305	 * Account for spread spectrum to avoid
3306	 * oversubscribing the link. Max center spread
3307	 * is 2.5%; use 5% for safety's sake.
3308	 */
3309	u32 bps = target_clock * bpp * 21 / 20;
3310	return DIV_ROUND_UP(bps, link_bw * 8);
3311}
3312
3313void intel_get_m_n(struct intel_display *display,
3314		   struct intel_link_m_n *m_n,
3315		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3316		   i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3317{
3318	m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
3319	m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;
3320	m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;
3321	m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;
3322	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
3323}
3324
3325void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3326				    enum transcoder transcoder,
3327				    struct intel_link_m_n *m_n)
3328{
3329	struct intel_display *display = to_intel_display(crtc);
3330	enum pipe pipe = crtc->pipe;
3331
3332	if (DISPLAY_VER(display) >= 5)
3333		intel_get_m_n(display, m_n,
3334			      PIPE_DATA_M1(display, transcoder),
3335			      PIPE_DATA_N1(display, transcoder),
3336			      PIPE_LINK_M1(display, transcoder),
3337			      PIPE_LINK_N1(display, transcoder));
3338	else
3339		intel_get_m_n(display, m_n,
3340			      PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3341			      PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3342}
3343
3344void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3345				    enum transcoder transcoder,
3346				    struct intel_link_m_n *m_n)
3347{
3348	struct intel_display *display = to_intel_display(crtc);
3349
3350	if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))
3351		return;
3352
3353	intel_get_m_n(display, m_n,
3354		      PIPE_DATA_M2(display, transcoder),
3355		      PIPE_DATA_N2(display, transcoder),
3356		      PIPE_LINK_M2(display, transcoder),
3357		      PIPE_LINK_N2(display, transcoder));
3358}
3359
3360static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3361				struct intel_crtc_state *pipe_config)
3362{
3363	struct intel_display *display = to_intel_display(crtc);
3364	enum intel_display_power_domain power_domain;
3365	enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe;
3366	intel_wakeref_t wakeref;
3367	bool ret = false;
3368	u32 tmp;
3369
3370	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3371	wakeref = intel_display_power_get_if_enabled(display, power_domain);
3372	if (!wakeref)
3373		return false;
3374
3375	tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
3376	if (!(tmp & TRANSCONF_ENABLE))
3377		goto out;
3378
3379	pipe_config->cpu_transcoder = cpu_transcoder;
3380
3381	switch (tmp & TRANSCONF_BPC_MASK) {
3382	case TRANSCONF_BPC_6:
3383		pipe_config->pipe_bpp = 18;
3384		break;
3385	case TRANSCONF_BPC_8:
3386		pipe_config->pipe_bpp = 24;
3387		break;
3388	case TRANSCONF_BPC_10:
3389		pipe_config->pipe_bpp = 30;
3390		break;
3391	case TRANSCONF_BPC_12:
3392		pipe_config->pipe_bpp = 36;
3393		break;
3394	default:
3395		break;
3396	}
3397
3398	if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
3399		pipe_config->limited_color_range = true;
3400
3401	switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
3402	case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
3403	case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
3404		pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3405		break;
3406	default:
3407		pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3408		break;
3409	}
3410
3411	pipe_config->sink_format = pipe_config->output_format;
3412
3413	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
3414
3415	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3416
3417	pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
3418
3419	intel_color_get_config(pipe_config);
3420
3421	pipe_config->pixel_multiplier = 1;
3422
3423	ilk_pch_get_config(pipe_config);
3424
3425	intel_get_transcoder_timings(crtc, pipe_config);
3426	intel_get_pipe_src_size(crtc, pipe_config);
3427
3428	ilk_pfit_get_config(pipe_config);
3429
3430	ret = true;
3431
3432out:
3433	intel_display_power_put(display, power_domain, wakeref);
3434
3435	return ret;
3436}
3437
3438static u8 joiner_pipes(struct intel_display *display)
3439{
3440	u8 pipes;
3441
3442	if (DISPLAY_VER(display) >= 12)
3443		pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3444	else if (DISPLAY_VER(display) >= 11)
3445		pipes = BIT(PIPE_B) | BIT(PIPE_C);
3446	else
3447		pipes = 0;
3448
3449	return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask;
3450}
3451
3452static bool transcoder_ddi_func_is_enabled(struct intel_display *display,
3453					   enum transcoder cpu_transcoder)
3454{
3455	enum intel_display_power_domain power_domain;
3456	intel_wakeref_t wakeref;
3457	u32 tmp = 0;
3458
3459	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3460
3461	with_intel_display_power_if_enabled(display, power_domain, wakeref)
3462		tmp = intel_de_read(display,
3463				    TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
3464
3465	return tmp & TRANS_DDI_FUNC_ENABLE;
3466}
3467
3468static void enabled_uncompressed_joiner_pipes(struct intel_display *display,
3469					      u8 *primary_pipes, u8 *secondary_pipes)
3470{
3471	struct intel_crtc *crtc;
3472
3473	*primary_pipes = 0;
3474	*secondary_pipes = 0;
3475
3476	if (!HAS_UNCOMPRESSED_JOINER(display))
3477		return;
3478
3479	for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
3480					 joiner_pipes(display)) {
3481		enum intel_display_power_domain power_domain;
3482		enum pipe pipe = crtc->pipe;
3483		intel_wakeref_t wakeref;
3484
3485		power_domain = POWER_DOMAIN_PIPE(pipe);
3486		with_intel_display_power_if_enabled(display, power_domain, wakeref) {
3487			u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
3488
3489			if (tmp & UNCOMPRESSED_JOINER_PRIMARY)
3490				*primary_pipes |= BIT(pipe);
3491			if (tmp & UNCOMPRESSED_JOINER_SECONDARY)
3492				*secondary_pipes |= BIT(pipe);
3493		}
3494	}
3495}
3496
3497static void enabled_bigjoiner_pipes(struct intel_display *display,
3498				    u8 *primary_pipes, u8 *secondary_pipes)
3499{
3500	struct intel_crtc *crtc;
3501
3502	*primary_pipes = 0;
3503	*secondary_pipes = 0;
3504
3505	if (!HAS_BIGJOINER(display))
3506		return;
3507
3508	for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
3509					 joiner_pipes(display)) {
3510		enum intel_display_power_domain power_domain;
3511		enum pipe pipe = crtc->pipe;
3512		intel_wakeref_t wakeref;
3513
3514		power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe);
3515		with_intel_display_power_if_enabled(display, power_domain, wakeref) {
3516			u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
3517
3518			if (!(tmp & BIG_JOINER_ENABLE))
3519				continue;
3520
3521			if (tmp & PRIMARY_BIG_JOINER_ENABLE)
3522				*primary_pipes |= BIT(pipe);
3523			else
3524				*secondary_pipes |= BIT(pipe);
3525		}
3526	}
3527}
3528
3529static u8 expected_secondary_pipes(u8 primary_pipes, int num_pipes)
3530{
3531	u8 secondary_pipes = 0;
3532
3533	for (int i = 1; i < num_pipes; i++)
3534		secondary_pipes |= primary_pipes << i;
3535
3536	return secondary_pipes;
3537}
3538
3539static u8 expected_uncompressed_joiner_secondary_pipes(u8 uncompjoiner_primary_pipes)
3540{
3541	return expected_secondary_pipes(uncompjoiner_primary_pipes, 2);
3542}
3543
3544static u8 expected_bigjoiner_secondary_pipes(u8 bigjoiner_primary_pipes)
3545{
3546	return expected_secondary_pipes(bigjoiner_primary_pipes, 2);
3547}
3548
3549static u8 get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes)
3550{
3551	primary_pipes &= GENMASK(pipe, 0);
3552
3553	return primary_pipes ? BIT(fls(primary_pipes) - 1) : 0;
3554}
3555
3556static u8 expected_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes)
3557{
3558	return expected_secondary_pipes(ultrajoiner_primary_pipes, 4);
3559}
3560
3561static u8 fixup_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes,
3562					    u8 ultrajoiner_secondary_pipes)
3563{
3564	return ultrajoiner_secondary_pipes | ultrajoiner_primary_pipes << 3;
3565}
3566
3567static void enabled_ultrajoiner_pipes(struct intel_display *display,
3568				      u8 *primary_pipes, u8 *secondary_pipes)
3569{
3570	struct intel_crtc *crtc;
3571
3572	*primary_pipes = 0;
3573	*secondary_pipes = 0;
3574
3575	if (!HAS_ULTRAJOINER(display))
3576		return;
3577
3578	for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
3579					 joiner_pipes(display)) {
3580		enum intel_display_power_domain power_domain;
3581		enum pipe pipe = crtc->pipe;
3582		intel_wakeref_t wakeref;
3583
3584		power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe);
3585		with_intel_display_power_if_enabled(display, power_domain, wakeref) {
3586			u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
3587
3588			if (!(tmp & ULTRA_JOINER_ENABLE))
3589				continue;
3590
3591			if (tmp & PRIMARY_ULTRA_JOINER_ENABLE)
3592				*primary_pipes |= BIT(pipe);
3593			else
3594				*secondary_pipes |= BIT(pipe);
3595		}
3596	}
3597}
3598
3599static void enabled_joiner_pipes(struct intel_display *display,
3600				 enum pipe pipe,
3601				 u8 *primary_pipe, u8 *secondary_pipes)
3602{
3603	u8 primary_ultrajoiner_pipes;
3604	u8 primary_uncompressed_joiner_pipes, primary_bigjoiner_pipes;
3605	u8 secondary_ultrajoiner_pipes;
3606	u8 secondary_uncompressed_joiner_pipes, secondary_bigjoiner_pipes;
3607	u8 ultrajoiner_pipes;
3608	u8 uncompressed_joiner_pipes, bigjoiner_pipes;
3609
3610	enabled_ultrajoiner_pipes(display, &primary_ultrajoiner_pipes,
3611				  &secondary_ultrajoiner_pipes);
3612	/*
3613	 * For some strange reason the last pipe in the set of four
3614	 * shouldn't have ultrajoiner enable bit set in hardware.
3615	 * Set the bit anyway to make life easier.
3616	 */
3617	drm_WARN_ON(display->drm,
3618		    expected_secondary_pipes(primary_ultrajoiner_pipes, 3) !=
3619		    secondary_ultrajoiner_pipes);
3620	secondary_ultrajoiner_pipes =
3621		fixup_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes,
3622						  secondary_ultrajoiner_pipes);
3623
3624	drm_WARN_ON(display->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0);
3625
3626	enabled_uncompressed_joiner_pipes(display, &primary_uncompressed_joiner_pipes,
3627					  &secondary_uncompressed_joiner_pipes);
3628
3629	drm_WARN_ON(display->drm,
3630		    (primary_uncompressed_joiner_pipes & secondary_uncompressed_joiner_pipes) != 0);
3631
3632	enabled_bigjoiner_pipes(display, &primary_bigjoiner_pipes,
3633				&secondary_bigjoiner_pipes);
3634
3635	drm_WARN_ON(display->drm,
3636		    (primary_bigjoiner_pipes & secondary_bigjoiner_pipes) != 0);
3637
3638	ultrajoiner_pipes = primary_ultrajoiner_pipes | secondary_ultrajoiner_pipes;
3639	uncompressed_joiner_pipes = primary_uncompressed_joiner_pipes |
3640				    secondary_uncompressed_joiner_pipes;
3641	bigjoiner_pipes = primary_bigjoiner_pipes | secondary_bigjoiner_pipes;
3642
3643	drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes,
3644		 "Ultrajoiner pipes(%#x) should be bigjoiner pipes(%#x)\n",
3645		 ultrajoiner_pipes, bigjoiner_pipes);
3646
3647	drm_WARN(display->drm, secondary_ultrajoiner_pipes !=
3648		 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes),
3649		 "Wrong secondary ultrajoiner pipes(expected %#x, current %#x)\n",
3650		 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes),
3651		 secondary_ultrajoiner_pipes);
3652
3653	drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0,
3654		 "Uncompressed joiner pipes(%#x) and bigjoiner pipes(%#x) can't intersect\n",
3655		 uncompressed_joiner_pipes, bigjoiner_pipes);
3656
3657	drm_WARN(display->drm, secondary_bigjoiner_pipes !=
3658		 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes),
3659		 "Wrong secondary bigjoiner pipes(expected %#x, current %#x)\n",
3660		 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes),
3661		 secondary_bigjoiner_pipes);
3662
3663	drm_WARN(display->drm, secondary_uncompressed_joiner_pipes !=
3664		 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes),
3665		 "Wrong secondary uncompressed joiner pipes(expected %#x, current %#x)\n",
3666		 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes),
3667		 secondary_uncompressed_joiner_pipes);
3668
3669	*primary_pipe = 0;
3670	*secondary_pipes = 0;
3671
3672	if (ultrajoiner_pipes & BIT(pipe)) {
3673		*primary_pipe = get_joiner_primary_pipe(pipe, primary_ultrajoiner_pipes);
3674		*secondary_pipes = secondary_ultrajoiner_pipes &
3675				   expected_ultrajoiner_secondary_pipes(*primary_pipe);
3676
3677		drm_WARN(display->drm,
3678			 expected_ultrajoiner_secondary_pipes(*primary_pipe) !=
3679			 *secondary_pipes,
3680			 "Wrong ultrajoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n",
3681			 *primary_pipe,
3682			 expected_ultrajoiner_secondary_pipes(*primary_pipe),
3683			 *secondary_pipes);
3684		return;
3685	}
3686
3687	if (uncompressed_joiner_pipes & BIT(pipe)) {
3688		*primary_pipe = get_joiner_primary_pipe(pipe, primary_uncompressed_joiner_pipes);
3689		*secondary_pipes = secondary_uncompressed_joiner_pipes &
3690				   expected_uncompressed_joiner_secondary_pipes(*primary_pipe);
3691
3692		drm_WARN(display->drm,
3693			 expected_uncompressed_joiner_secondary_pipes(*primary_pipe) !=
3694			 *secondary_pipes,
3695			 "Wrong uncompressed joiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n",
3696			 *primary_pipe,
3697			 expected_uncompressed_joiner_secondary_pipes(*primary_pipe),
3698			 *secondary_pipes);
3699		return;
3700	}
3701
3702	if (bigjoiner_pipes & BIT(pipe)) {
3703		*primary_pipe = get_joiner_primary_pipe(pipe, primary_bigjoiner_pipes);
3704		*secondary_pipes = secondary_bigjoiner_pipes &
3705				   expected_bigjoiner_secondary_pipes(*primary_pipe);
3706
3707		drm_WARN(display->drm,
3708			 expected_bigjoiner_secondary_pipes(*primary_pipe) !=
3709			 *secondary_pipes,
3710			 "Wrong bigjoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n",
3711			 *primary_pipe,
3712			 expected_bigjoiner_secondary_pipes(*primary_pipe),
3713			 *secondary_pipes);
3714		return;
3715	}
3716}
3717
3718static u8 hsw_panel_transcoders(struct intel_display *display)
3719{
3720	u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3721
3722	if (DISPLAY_VER(display) >= 11)
3723		panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3724
3725	return panel_transcoder_mask;
3726}
3727
3728static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3729{
3730	struct intel_display *display = to_intel_display(crtc);
3731	u8 panel_transcoder_mask = hsw_panel_transcoders(display);
3732	enum transcoder cpu_transcoder;
3733	u8 primary_pipe, secondary_pipes;
3734	u8 enabled_transcoders = 0;
3735
3736	/*
3737	 * XXX: Do intel_display_power_get_if_enabled before reading this (for
3738	 * consistency and less surprising code; it's in always on power).
3739	 */
3740	for_each_cpu_transcoder_masked(display, cpu_transcoder,
3741				       panel_transcoder_mask) {
3742		enum intel_display_power_domain power_domain;
3743		intel_wakeref_t wakeref;
3744		enum pipe trans_pipe;
3745		u32 tmp = 0;
3746
3747		power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3748		with_intel_display_power_if_enabled(display, power_domain, wakeref)
3749			tmp = intel_de_read(display,
3750					    TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
3751
3752		if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3753			continue;
3754
3755		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3756		default:
3757			drm_WARN(display->drm, 1,
3758				 "unknown pipe linked to transcoder %s\n",
3759				 transcoder_name(cpu_transcoder));
3760			fallthrough;
3761		case TRANS_DDI_EDP_INPUT_A_ONOFF:
3762		case TRANS_DDI_EDP_INPUT_A_ON:
3763			trans_pipe = PIPE_A;
3764			break;
3765		case TRANS_DDI_EDP_INPUT_B_ONOFF:
3766			trans_pipe = PIPE_B;
3767			break;
3768		case TRANS_DDI_EDP_INPUT_C_ONOFF:
3769			trans_pipe = PIPE_C;
3770			break;
3771		case TRANS_DDI_EDP_INPUT_D_ONOFF:
3772			trans_pipe = PIPE_D;
3773			break;
3774		}
3775
3776		if (trans_pipe == crtc->pipe)
3777			enabled_transcoders |= BIT(cpu_transcoder);
3778	}
3779
3780	/* single pipe or joiner primary */
3781	cpu_transcoder = (enum transcoder) crtc->pipe;
3782	if (transcoder_ddi_func_is_enabled(display, cpu_transcoder))
3783		enabled_transcoders |= BIT(cpu_transcoder);
3784
3785	/* joiner secondary -> consider the primary pipe's transcoder as well */
3786	enabled_joiner_pipes(display, crtc->pipe, &primary_pipe, &secondary_pipes);
3787	if (secondary_pipes & BIT(crtc->pipe)) {
3788		cpu_transcoder = (enum transcoder)ffs(primary_pipe) - 1;
3789		if (transcoder_ddi_func_is_enabled(display, cpu_transcoder))
3790			enabled_transcoders |= BIT(cpu_transcoder);
3791	}
3792
3793	return enabled_transcoders;
3794}
3795
3796static bool has_edp_transcoders(u8 enabled_transcoders)
3797{
3798	return enabled_transcoders & BIT(TRANSCODER_EDP);
3799}
3800
3801static bool has_dsi_transcoders(u8 enabled_transcoders)
3802{
3803	return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3804				      BIT(TRANSCODER_DSI_1));
3805}
3806
3807static bool has_pipe_transcoders(u8 enabled_transcoders)
3808{
3809	return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3810				       BIT(TRANSCODER_DSI_0) |
3811				       BIT(TRANSCODER_DSI_1));
3812}
3813
3814static void assert_enabled_transcoders(struct intel_display *display,
3815				       u8 enabled_transcoders)
3816{
3817	/* Only one type of transcoder please */
3818	drm_WARN_ON(display->drm,
3819		    has_edp_transcoders(enabled_transcoders) +
3820		    has_dsi_transcoders(enabled_transcoders) +
3821		    has_pipe_transcoders(enabled_transcoders) > 1);
3822
3823	/* Only DSI transcoders can be ganged */
3824	drm_WARN_ON(display->drm,
3825		    !has_dsi_transcoders(enabled_transcoders) &&
3826		    !is_power_of_2(enabled_transcoders));
3827}
3828
3829static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3830				     struct intel_crtc_state *pipe_config,
3831				     struct intel_display_power_domain_set *power_domain_set)
3832{
3833	struct intel_display *display = to_intel_display(crtc);
3834	unsigned long enabled_transcoders;
3835	u32 tmp;
3836
3837	enabled_transcoders = hsw_enabled_transcoders(crtc);
3838	if (!enabled_transcoders)
3839		return false;
3840
3841	assert_enabled_transcoders(display, enabled_transcoders);
3842
3843	/*
3844	 * With the exception of DSI we should only ever have
3845	 * a single enabled transcoder. With DSI let's just
3846	 * pick the first one.
3847	 */
3848	pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3849
3850	if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set,
3851						       POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3852		return false;
3853
3854	if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) {
3855		tmp = intel_de_read(display,
3856				    TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder));
3857
3858		if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3859			pipe_config->pch_pfit.force_thru = true;
3860	}
3861
3862	tmp = intel_de_read(display,
3863			    TRANSCONF(display, pipe_config->cpu_transcoder));
3864
3865	return tmp & TRANSCONF_ENABLE;
3866}
3867
3868static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3869					 struct intel_crtc_state *pipe_config,
3870					 struct intel_display_power_domain_set *power_domain_set)
3871{
3872	struct intel_display *display = to_intel_display(crtc);
3873	enum transcoder cpu_transcoder;
3874	enum port port;
3875	u32 tmp;
3876
3877	for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3878		if (port == PORT_A)
3879			cpu_transcoder = TRANSCODER_DSI_A;
3880		else
3881			cpu_transcoder = TRANSCODER_DSI_C;
3882
3883		if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set,
3884							       POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3885			continue;
3886
3887		/*
3888		 * The PLL needs to be enabled with a valid divider
3889		 * configuration, otherwise accessing DSI registers will hang
3890		 * the machine. See BSpec North Display Engine
3891		 * registers/MIPI[BXT]. We can break out here early, since we
3892		 * need the same DSI PLL to be enabled for both DSI ports.
3893		 */
3894		if (!bxt_dsi_pll_is_enabled(display))
3895			break;
3896
3897		/* XXX: this works for video mode only */
3898		tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));
3899		if (!(tmp & DPI_ENABLE))
3900			continue;
3901
3902		tmp = intel_de_read(display, MIPI_CTRL(display, port));
3903		if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
3904			continue;
3905
3906		pipe_config->cpu_transcoder = cpu_transcoder;
3907		break;
3908	}
3909
3910	return transcoder_is_dsi(pipe_config->cpu_transcoder);
3911}
3912
3913static void intel_joiner_get_config(struct intel_crtc_state *crtc_state)
3914{
3915	struct intel_display *display = to_intel_display(crtc_state);
3916	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3917	u8 primary_pipe, secondary_pipes;
3918	enum pipe pipe = crtc->pipe;
3919
3920	enabled_joiner_pipes(display, pipe, &primary_pipe, &secondary_pipes);
3921
3922	if (((primary_pipe | secondary_pipes) & BIT(pipe)) == 0)
3923		return;
3924
3925	crtc_state->joiner_pipes = primary_pipe | secondary_pipes;
3926}
3927
3928static bool hsw_get_pipe_config(struct intel_crtc *crtc,
3929				struct intel_crtc_state *pipe_config)
3930{
3931	struct intel_display *display = to_intel_display(crtc);
3932	bool active;
3933	u32 tmp;
3934
3935	if (!intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,
3936						       POWER_DOMAIN_PIPE(crtc->pipe)))
3937		return false;
3938
3939	active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
3940
3941	if ((display->platform.geminilake || display->platform.broxton) &&
3942	    bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {
3943		drm_WARN_ON(display->drm, active);
3944		active = true;
3945	}
3946
3947	if (!active)
3948		goto out;
3949
3950	intel_joiner_get_config(pipe_config);
3951	intel_dsc_get_config(pipe_config);
3952
3953	/* intel_vrr_get_config() depends on .framestart_delay */
3954	if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3955		tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
3956
3957		pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
3958	} else {
3959		/* no idea if this is correct */
3960		pipe_config->framestart_delay = 1;
3961	}
3962
3963	/*
3964	 * intel_vrr_get_config() depends on TRANS_SET_CONTEXT_LATENCY
3965	 * readout done by intel_get_transcoder_timings().
3966	 */
3967	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
3968	    DISPLAY_VER(display) >= 11)
3969		intel_get_transcoder_timings(crtc, pipe_config);
3970
3971	if (transcoder_has_vrr(pipe_config))
3972		intel_vrr_get_config(pipe_config);
3973
3974	intel_get_pipe_src_size(crtc, pipe_config);
3975
3976	if (display->platform.haswell) {
3977		u32 tmp = intel_de_read(display,
3978					TRANSCONF(display, pipe_config->cpu_transcoder));
3979
3980		if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
3981			pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3982		else
3983			pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3984	} else {
3985		pipe_config->output_format =
3986			bdw_get_pipe_misc_output_format(crtc);
3987	}
3988
3989	pipe_config->sink_format = pipe_config->output_format;
3990
3991	intel_color_get_config(pipe_config);
3992
3993	tmp = intel_de_read(display, WM_LINETIME(crtc->pipe));
3994	pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
3995	if (display->platform.broadwell || display->platform.haswell)
3996		pipe_config->ips_linetime =
3997			REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
3998
3999	if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains,
4000						      POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
4001		if (DISPLAY_VER(display) >= 9)
4002			skl_scaler_get_config(pipe_config);
4003		else
4004			ilk_pfit_get_config(pipe_config);
4005	}
4006
4007	hsw_ips_get_config(pipe_config);
4008
4009	if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
4010	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
4011		pipe_config->pixel_multiplier =
4012			intel_de_read(display,
4013				      TRANS_MULT(display, pipe_config->cpu_transcoder)) + 1;
4014	} else {
4015		pipe_config->pixel_multiplier = 1;
4016	}
4017
4018out:
4019	intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains);
4020
4021	return active;
4022}
4023
4024bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
4025{
4026	struct intel_display *display = to_intel_display(crtc_state);
4027	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4028
4029	if (!display->funcs.display->get_pipe_config(crtc, crtc_state))
4030		return false;
4031
4032	crtc_state->hw.active = true;
4033
4034	intel_crtc_readout_derived_state(crtc_state);
4035
4036	return true;
4037}
4038
4039int intel_dotclock_calculate(int link_freq,
4040			     const struct intel_link_m_n *m_n)
4041{
4042	/*
4043	 * The calculation for the data clock -> pixel clock is:
4044	 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
4045	 * But we want to avoid losing precision if possible, so:
4046	 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
4047	 *
4048	 * and for link freq (10kbs units) -> pixel clock it is:
4049	 * link_symbol_clock = link_freq * 10 / link_symbol_size
4050	 * pixel_clock = (m * link_symbol_clock) / n
4051	 *    or for more precision:
4052	 * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size)
4053	 */
4054
4055	if (!m_n->link_n)
4056		return 0;
4057
4058	return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),
4059				m_n->link_n * intel_dp_link_symbol_size(link_freq));
4060}
4061
4062int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
4063{
4064	int dotclock;
4065
4066	if (intel_crtc_has_dp_encoder(pipe_config))
4067		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
4068						    &pipe_config->dp_m_n);
4069	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
4070		dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
4071					     pipe_config->pipe_bpp);
4072	else
4073		dotclock = pipe_config->port_clock;
4074
4075	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
4076	    !intel_crtc_has_dp_encoder(pipe_config))
4077		dotclock *= 2;
4078
4079	if (pipe_config->pixel_multiplier)
4080		dotclock /= pipe_config->pixel_multiplier;
4081
4082	return dotclock;
4083}
4084
4085/* Returns the currently programmed mode of the given encoder. */
4086struct drm_display_mode *
4087intel_encoder_current_mode(struct intel_encoder *encoder)
4088{
4089	struct intel_display *display = to_intel_display(encoder);
4090	struct intel_crtc_state *crtc_state;
4091	struct drm_display_mode *mode;
4092	struct intel_crtc *crtc;
4093	enum pipe pipe;
4094
4095	if (!encoder->get_hw_state(encoder, &pipe))
4096		return NULL;
4097
4098	crtc = intel_crtc_for_pipe(display, pipe);
4099
4100	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4101	if (!mode)
4102		return NULL;
4103
4104	crtc_state = intel_crtc_state_alloc(crtc);
4105	if (!crtc_state) {
4106		kfree(mode);
4107		return NULL;
4108	}
4109
4110	if (!intel_crtc_get_pipe_config(crtc_state)) {
4111		intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
4112		kfree(mode);
4113		return NULL;
4114	}
4115
4116	intel_encoder_get_config(encoder, crtc_state);
4117
4118	intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
4119
4120	intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
4121
4122	return mode;
4123}
4124
4125static bool encoders_cloneable(const struct intel_encoder *a,
4126			       const struct intel_encoder *b)
4127{
4128	/* masks could be asymmetric, so check both ways */
4129	return a == b || (a->cloneable & BIT(b->type) &&
4130			  b->cloneable & BIT(a->type));
4131}
4132
4133static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4134					 struct intel_crtc *crtc,
4135					 struct intel_encoder *encoder)
4136{
4137	struct intel_encoder *source_encoder;
4138	struct drm_connector *connector;
4139	struct drm_connector_state *connector_state;
4140	int i;
4141
4142	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4143		if (connector_state->crtc != &crtc->base)
4144			continue;
4145
4146		source_encoder =
4147			to_intel_encoder(connector_state->best_encoder);
4148		if (!encoders_cloneable(encoder, source_encoder))
4149			return false;
4150	}
4151
4152	return true;
4153}
4154
4155static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4156{
4157	const struct drm_display_mode *pipe_mode =
4158		&crtc_state->hw.pipe_mode;
4159	int linetime_wm;
4160
4161	if (!crtc_state->hw.enable)
4162		return 0;
4163
4164	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4165					pipe_mode->crtc_clock);
4166
4167	return min(linetime_wm, 0x1ff);
4168}
4169
4170static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4171			       const struct intel_cdclk_state *cdclk_state)
4172{
4173	const struct drm_display_mode *pipe_mode =
4174		&crtc_state->hw.pipe_mode;
4175	int linetime_wm;
4176
4177	if (!crtc_state->hw.enable)
4178		return 0;
4179
4180	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4181					intel_cdclk_logical(cdclk_state));
4182
4183	return min(linetime_wm, 0x1ff);
4184}
4185
4186static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4187{
4188	struct intel_display *display = to_intel_display(crtc_state);
4189	const struct drm_display_mode *pipe_mode =
4190		&crtc_state->hw.pipe_mode;
4191	int linetime_wm;
4192
4193	if (!crtc_state->hw.enable)
4194		return 0;
4195
4196	linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4197				   crtc_state->pixel_rate);
4198
4199	/* Display WA #1135: BXT:ALL GLK:ALL */
4200	if ((display->platform.geminilake || display->platform.broxton) &&
4201	    skl_watermark_ipc_enabled(display))
4202		linetime_wm /= 2;
4203
4204	return min(linetime_wm, 0x1ff);
4205}
4206
4207static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4208				   struct intel_crtc *crtc)
4209{
4210	struct intel_display *display = to_intel_display(state);
4211	struct intel_crtc_state *crtc_state =
4212		intel_atomic_get_new_crtc_state(state, crtc);
4213	const struct intel_cdclk_state *cdclk_state;
4214
4215	if (DISPLAY_VER(display) >= 9)
4216		crtc_state->linetime = skl_linetime_wm(crtc_state);
4217	else
4218		crtc_state->linetime = hsw_linetime_wm(crtc_state);
4219
4220	if (!hsw_crtc_supports_ips(crtc))
4221		return 0;
4222
4223	cdclk_state = intel_atomic_get_cdclk_state(state);
4224	if (IS_ERR(cdclk_state))
4225		return PTR_ERR(cdclk_state);
4226
4227	crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4228						       cdclk_state);
4229
4230	return 0;
4231}
4232
4233static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4234				   struct intel_crtc *crtc)
4235{
4236	struct intel_display *display = to_intel_display(crtc);
4237	struct intel_crtc_state *crtc_state =
4238		intel_atomic_get_new_crtc_state(state, crtc);
4239	int ret;
4240
4241	if (DISPLAY_VER(display) < 5 && !display->platform.g4x &&
4242	    intel_crtc_needs_modeset(crtc_state) &&
4243	    !crtc_state->hw.active)
4244		crtc_state->update_wm_post = true;
4245
4246	if (intel_crtc_needs_modeset(crtc_state)) {
4247		ret = intel_dpll_crtc_get_dpll(state, crtc);
4248		if (ret)
4249			return ret;
4250	}
4251
4252	ret = intel_color_check(state, crtc);
4253	if (ret)
4254		return ret;
4255
4256	ret = intel_wm_compute(state, crtc);
4257	if (ret) {
4258		drm_dbg_kms(display->drm,
4259			    "[CRTC:%d:%s] watermarks are invalid\n",
4260			    crtc->base.base.id, crtc->base.name);
4261		return ret;
4262	}
4263
4264	ret = intel_casf_compute_config(crtc_state);
4265	if (ret)
4266		return ret;
4267
4268	if (DISPLAY_VER(display) >= 9) {
4269		if (intel_crtc_needs_modeset(crtc_state) ||
4270		    intel_crtc_needs_fastset(crtc_state) ||
4271		    intel_casf_needs_scaler(crtc_state)) {
4272			ret = skl_update_scaler_crtc(crtc_state);
4273			if (ret)
4274				return ret;
4275		}
4276
4277		ret = intel_atomic_setup_scalers(state, crtc);
4278		if (ret)
4279			return ret;
4280	}
4281
4282	if (HAS_IPS(display)) {
4283		ret = hsw_ips_compute_config(state, crtc);
4284		if (ret)
4285			return ret;
4286	}
4287
4288	if (DISPLAY_VER(display) >= 9 ||
4289	    display->platform.broadwell || display->platform.haswell) {
4290		ret = hsw_compute_linetime_wm(state, crtc);
4291		if (ret)
4292			return ret;
4293
4294	}
4295
4296	ret = intel_psr2_sel_fetch_update(state, crtc);
4297	if (ret)
4298		return ret;
4299
4300	return 0;
4301}
4302
4303static int
4304compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4305		      struct intel_crtc_state *crtc_state)
4306{
4307	struct intel_display *display = to_intel_display(crtc_state);
4308	struct drm_connector *connector = conn_state->connector;
4309	const struct drm_display_info *info = &connector->display_info;
4310	int bpp;
4311
4312	switch (conn_state->max_bpc) {
4313	case 6 ... 7:
4314		bpp = 6 * 3;
4315		break;
4316	case 8 ... 9:
4317		bpp = 8 * 3;
4318		break;
4319	case 10 ... 11:
4320		bpp = 10 * 3;
4321		break;
4322	case 12 ... 16:
4323		bpp = 12 * 3;
4324		break;
4325	default:
4326		MISSING_CASE(conn_state->max_bpc);
4327		return -EINVAL;
4328	}
4329
4330	if (bpp < crtc_state->pipe_bpp) {
4331		drm_dbg_kms(display->drm,
4332			    "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4333			    "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4334			    connector->base.id, connector->name,
4335			    bpp, 3 * info->bpc,
4336			    3 * conn_state->max_requested_bpc,
4337			    crtc_state->pipe_bpp);
4338
4339		crtc_state->pipe_bpp = bpp;
4340	}
4341
4342	return 0;
4343}
4344
4345int intel_display_min_pipe_bpp(void)
4346{
4347	return 6 * 3;
4348}
4349
4350int intel_display_max_pipe_bpp(struct intel_display *display)
4351{
4352	if (display->platform.g4x || display->platform.valleyview ||
4353	    display->platform.cherryview)
4354		return 10*3;
4355	else if (DISPLAY_VER(display) >= 5)
4356		return 12*3;
4357	else
4358		return 8*3;
4359}
4360
4361static int
4362compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4363			  struct intel_crtc *crtc)
4364{
4365	struct intel_display *display = to_intel_display(crtc);
4366	struct intel_crtc_state *crtc_state =
4367		intel_atomic_get_new_crtc_state(state, crtc);
4368	struct drm_connector *connector;
4369	struct drm_connector_state *connector_state;
4370	int i;
4371
4372	crtc_state->pipe_bpp = intel_display_max_pipe_bpp(display);
4373
4374	/* Clamp display bpp to connector max bpp */
4375	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4376		int ret;
4377
4378		if (connector_state->crtc != &crtc->base)
4379			continue;
4380
4381		ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4382		if (ret)
4383			return ret;
4384	}
4385
4386	return 0;
4387}
4388
4389static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4390{
4391	struct intel_display *display = to_intel_display(state);
4392	struct drm_connector *connector;
4393	struct drm_connector_list_iter conn_iter;
4394	unsigned int used_ports = 0;
4395	unsigned int used_mst_ports = 0;
4396	bool ret = true;
4397
4398	/*
4399	 * We're going to peek into connector->state,
4400	 * hence connection_mutex must be held.
4401	 */
4402	drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);
4403
4404	/*
4405	 * Walk the connector list instead of the encoder
4406	 * list to detect the problem on ddi platforms
4407	 * where there's just one encoder per digital port.
4408	 */
4409	drm_connector_list_iter_begin(display->drm, &conn_iter);
4410	drm_for_each_connector_iter(connector, &conn_iter) {
4411		struct drm_connector_state *connector_state;
4412		struct intel_encoder *encoder;
4413
4414		connector_state =
4415			drm_atomic_get_new_connector_state(&state->base,
4416							   connector);
4417		if (!connector_state)
4418			connector_state = connector->state;
4419
4420		if (!connector_state->best_encoder)
4421			continue;
4422
4423		encoder = to_intel_encoder(connector_state->best_encoder);
4424
4425		drm_WARN_ON(display->drm, !connector_state->crtc);
4426
4427		switch (encoder->type) {
4428		case INTEL_OUTPUT_DDI:
4429			if (drm_WARN_ON(display->drm, !HAS_DDI(display)))
4430				break;
4431			fallthrough;
4432		case INTEL_OUTPUT_DP:
4433		case INTEL_OUTPUT_HDMI:
4434		case INTEL_OUTPUT_EDP:
4435			/* the same port mustn't appear more than once */
4436			if (used_ports & BIT(encoder->port))
4437				ret = false;
4438
4439			used_ports |= BIT(encoder->port);
4440			break;
4441		case INTEL_OUTPUT_DP_MST:
4442			used_mst_ports |=
4443				1 << encoder->port;
4444			break;
4445		default:
4446			break;
4447		}
4448	}
4449	drm_connector_list_iter_end(&conn_iter);
4450
4451	/* can't mix MST and SST/HDMI on the same port */
4452	if (used_ports & used_mst_ports)
4453		return false;
4454
4455	return ret;
4456}
4457
4458static void
4459intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
4460					   struct intel_crtc *crtc)
4461{
4462	struct intel_crtc_state *crtc_state =
4463		intel_atomic_get_new_crtc_state(state, crtc);
4464
4465	WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
4466
4467	drm_property_replace_blob(&crtc_state->hw.degamma_lut,
4468				  crtc_state->uapi.degamma_lut);
4469	drm_property_replace_blob(&crtc_state->hw.gamma_lut,
4470				  crtc_state->uapi.gamma_lut);
4471	drm_property_replace_blob(&crtc_state->hw.ctm,
4472				  crtc_state->uapi.ctm);
4473}
4474
4475static void
4476intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
4477					 struct intel_crtc *crtc)
4478{
4479	struct intel_crtc_state *crtc_state =
4480		intel_atomic_get_new_crtc_state(state, crtc);
4481
4482	WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
4483
4484	crtc_state->hw.enable = crtc_state->uapi.enable;
4485	crtc_state->hw.active = crtc_state->uapi.active;
4486	drm_mode_copy(&crtc_state->hw.mode,
4487		      &crtc_state->uapi.mode);
4488	drm_mode_copy(&crtc_state->hw.adjusted_mode,
4489		      &crtc_state->uapi.adjusted_mode);
4490	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
4491
4492	intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
4493}
4494
4495static void
4496copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state,
4497				 struct intel_crtc *secondary_crtc)
4498{
4499	struct intel_crtc_state *secondary_crtc_state =
4500		intel_atomic_get_new_crtc_state(state, secondary_crtc);
4501	struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state);
4502	const struct intel_crtc_state *primary_crtc_state =
4503		intel_atomic_get_new_crtc_state(state, primary_crtc);
4504
4505	drm_property_replace_blob(&secondary_crtc_state->hw.degamma_lut,
4506				  primary_crtc_state->hw.degamma_lut);
4507	drm_property_replace_blob(&secondary_crtc_state->hw.gamma_lut,
4508				  primary_crtc_state->hw.gamma_lut);
4509	drm_property_replace_blob(&secondary_crtc_state->hw.ctm,
4510				  primary_crtc_state->hw.ctm);
4511
4512	secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed;
4513}
4514
4515static int
4516copy_joiner_crtc_state_modeset(struct intel_atomic_state *state,
4517			       struct intel_crtc *secondary_crtc)
4518{
4519	struct intel_crtc_state *secondary_crtc_state =
4520		intel_atomic_get_new_crtc_state(state, secondary_crtc);
4521	struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state);
4522	const struct intel_crtc_state *primary_crtc_state =
4523		intel_atomic_get_new_crtc_state(state, primary_crtc);
4524	struct intel_crtc_state *saved_state;
4525
4526	WARN_ON(primary_crtc_state->joiner_pipes !=
4527		secondary_crtc_state->joiner_pipes);
4528
4529	saved_state = kmemdup(primary_crtc_state, sizeof(*saved_state), GFP_KERNEL);
4530	if (!saved_state)
4531		return -ENOMEM;
4532
4533	/* preserve some things from the slave's original crtc state */
4534	saved_state->uapi = secondary_crtc_state->uapi;
4535	saved_state->scaler_state = secondary_crtc_state->scaler_state;
4536	saved_state->intel_dpll = secondary_crtc_state->intel_dpll;
4537	saved_state->crc_enabled = secondary_crtc_state->crc_enabled;
4538
4539	intel_crtc_free_hw_state(secondary_crtc_state);
4540	if (secondary_crtc_state->dp_tunnel_ref.tunnel)
4541		drm_dp_tunnel_ref_put(&secondary_crtc_state->dp_tunnel_ref);
4542	memcpy(secondary_crtc_state, saved_state, sizeof(*secondary_crtc_state));
4543	kfree(saved_state);
4544
4545	/* Re-init hw state */
4546	memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw));
4547	secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable;
4548	secondary_crtc_state->hw.active = primary_crtc_state->hw.active;
4549	drm_mode_copy(&secondary_crtc_state->hw.mode,
4550		      &primary_crtc_state->hw.mode);
4551	drm_mode_copy(&secondary_crtc_state->hw.pipe_mode,
4552		      &primary_crtc_state->hw.pipe_mode);
4553	drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode,
4554		      &primary_crtc_state->hw.adjusted_mode);
4555	secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter;
4556
4557	if (primary_crtc_state->dp_tunnel_ref.tunnel)
4558		drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel,
4559				      &secondary_crtc_state->dp_tunnel_ref);
4560
4561	copy_joiner_crtc_state_nomodeset(state, secondary_crtc);
4562
4563	secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed;
4564	secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed;
4565	secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed;
4566
4567	WARN_ON(primary_crtc_state->joiner_pipes !=
4568		secondary_crtc_state->joiner_pipes);
4569
4570	return 0;
4571}
4572
4573static int
4574intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
4575				 struct intel_crtc *crtc)
4576{
4577	struct intel_display *display = to_intel_display(state);
4578	struct intel_crtc_state *crtc_state =
4579		intel_atomic_get_new_crtc_state(state, crtc);
4580	struct intel_crtc_state *saved_state;
4581	int err;
4582
4583	saved_state = intel_crtc_state_alloc(crtc);
4584	if (!saved_state)
4585		return -ENOMEM;
4586
4587	/* free the old crtc_state->hw members */
4588	intel_crtc_free_hw_state(crtc_state);
4589
4590	err = intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state);
4591	if (err) {
4592		kfree(saved_state);
4593
4594		return err;
4595	}
4596
4597	/* FIXME: before the switch to atomic started, a new pipe_config was
4598	 * kzalloc'd. Code that depends on any field being zero should be
4599	 * fixed, so that the crtc_state can be safely duplicated. For now,
4600	 * only fields that are know to not cause problems are preserved. */
4601
4602	saved_state->uapi = crtc_state->uapi;
4603	saved_state->inherited = crtc_state->inherited;
4604	saved_state->scaler_state = crtc_state->scaler_state;
4605	saved_state->intel_dpll = crtc_state->intel_dpll;
4606	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
4607	memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
4608	       sizeof(saved_state->icl_port_dplls));
4609	saved_state->crc_enabled = crtc_state->crc_enabled;
4610	if (display->platform.g4x ||
4611	    display->platform.valleyview || display->platform.cherryview)
4612		saved_state->wm = crtc_state->wm;
4613
4614	memcpy(crtc_state, saved_state, sizeof(*crtc_state));
4615	kfree(saved_state);
4616
4617	intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
4618
4619	return 0;
4620}
4621
4622static int
4623intel_modeset_pipe_config(struct intel_atomic_state *state,
4624			  struct intel_crtc *crtc,
4625			  const struct intel_link_bw_limits *limits)
4626{
4627	struct intel_display *display = to_intel_display(crtc);
4628	struct intel_crtc_state *crtc_state =
4629		intel_atomic_get_new_crtc_state(state, crtc);
4630	struct drm_connector *connector;
4631	struct drm_connector_state *connector_state;
4632	int pipe_src_w, pipe_src_h;
4633	int base_bpp, ret, i;
4634
4635	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
4636
4637	crtc_state->framestart_delay = 1;
4638
4639	/*
4640	 * Sanitize sync polarity flags based on requested ones. If neither
4641	 * positive or negative polarity is requested, treat this as meaning
4642	 * negative polarity.
4643	 */
4644	if (!(crtc_state->hw.adjusted_mode.flags &
4645	      (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
4646		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
4647
4648	if (!(crtc_state->hw.adjusted_mode.flags &
4649	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
4650		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
4651
4652	ret = compute_baseline_pipe_bpp(state, crtc);
4653	if (ret)
4654		return ret;
4655
4656	crtc_state->dsc.compression_enabled_on_link = limits->link_dsc_pipes & BIT(crtc->pipe);
4657	crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
4658
4659	if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) {
4660		drm_dbg_kms(display->drm,
4661			    "[CRTC:%d:%s] Link bpp limited to " FXP_Q4_FMT "\n",
4662			    crtc->base.base.id, crtc->base.name,
4663			    FXP_Q4_ARGS(crtc_state->max_link_bpp_x16));
4664		crtc_state->bw_constrained = true;
4665	}
4666
4667	base_bpp = crtc_state->pipe_bpp;
4668
4669	/*
4670	 * Determine the real pipe dimensions. Note that stereo modes can
4671	 * increase the actual pipe size due to the frame doubling and
4672	 * insertion of additional space for blanks between the frame. This
4673	 * is stored in the crtc timings. We use the requested mode to do this
4674	 * computation to clearly distinguish it from the adjusted mode, which
4675	 * can be changed by the connectors in the below retry loop.
4676	 */
4677	drm_mode_get_hv_timing(&crtc_state->hw.mode,
4678			       &pipe_src_w, &pipe_src_h);
4679	drm_rect_init(&crtc_state->pipe_src, 0, 0,
4680		      pipe_src_w, pipe_src_h);
4681
4682	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4683		struct intel_encoder *encoder =
4684			to_intel_encoder(connector_state->best_encoder);
4685
4686		if (connector_state->crtc != &crtc->base)
4687			continue;
4688
4689		if (!check_single_encoder_cloning(state, crtc, encoder)) {
4690			drm_dbg_kms(display->drm,
4691				    "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
4692				    encoder->base.base.id, encoder->base.name);
4693			return -EINVAL;
4694		}
4695
4696		/*
4697		 * Determine output_types before calling the .compute_config()
4698		 * hooks so that the hooks can use this information safely.
4699		 */
4700		if (encoder->compute_output_type)
4701			crtc_state->output_types |=
4702				BIT(encoder->compute_output_type(encoder, crtc_state,
4703								 connector_state));
4704		else
4705			crtc_state->output_types |= BIT(encoder->type);
4706	}
4707
4708	/* Ensure the port clock defaults are reset when retrying. */
4709	crtc_state->port_clock = 0;
4710	crtc_state->pixel_multiplier = 1;
4711
4712	/* Fill in default crtc timings, allow encoders to overwrite them. */
4713	drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
4714			      CRTC_STEREO_DOUBLE);
4715
4716	/* Pass our mode to the connectors and the CRTC to give them a chance to
4717	 * adjust it according to limitations or connector properties, and also
4718	 * a chance to reject the mode entirely.
4719	 */
4720	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4721		struct intel_encoder *encoder =
4722			to_intel_encoder(connector_state->best_encoder);
4723
4724		if (connector_state->crtc != &crtc->base)
4725			continue;
4726
4727		ret = encoder->compute_config(encoder, crtc_state,
4728					      connector_state);
4729		if (ret == -EDEADLK)
4730			return ret;
4731		if (ret < 0) {
4732			drm_dbg_kms(display->drm, "[ENCODER:%d:%s] config failure: %d\n",
4733				    encoder->base.base.id, encoder->base.name, ret);
4734			return ret;
4735		}
4736	}
4737
4738	/* Set default port clock if not overwritten by the encoder. Needs to be
4739	 * done afterwards in case the encoder adjusts the mode. */
4740	if (!crtc_state->port_clock)
4741		crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
4742			* crtc_state->pixel_multiplier;
4743
4744	ret = intel_crtc_compute_config(state, crtc);
4745	if (ret == -EDEADLK)
4746		return ret;
4747	if (ret < 0) {
4748		drm_dbg_kms(display->drm, "[CRTC:%d:%s] config failure: %d\n",
4749			    crtc->base.base.id, crtc->base.name, ret);
4750		return ret;
4751	}
4752
4753	/* Dithering seems to not pass-through bits correctly when it should, so
4754	 * only enable it on 6bpc panels and when its not a compliance
4755	 * test requesting 6bpc video pattern.
4756	 */
4757	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
4758		!crtc_state->dither_force_disable;
4759	drm_dbg_kms(display->drm,
4760		    "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
4761		    crtc->base.base.id, crtc->base.name,
4762		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
4763
4764	return 0;
4765}
4766
4767static int
4768intel_modeset_pipe_config_late(struct intel_atomic_state *state,
4769			       struct intel_crtc *crtc)
4770{
4771	struct intel_crtc_state *crtc_state =
4772		intel_atomic_get_new_crtc_state(state, crtc);
4773	struct drm_connector_state *conn_state;
4774	struct drm_connector *connector;
4775	int i;
4776
4777	for_each_new_connector_in_state(&state->base, connector,
4778					conn_state, i) {
4779		struct intel_encoder *encoder =
4780			to_intel_encoder(conn_state->best_encoder);
4781		int ret;
4782
4783		if (conn_state->crtc != &crtc->base ||
4784		    !encoder->compute_config_late)
4785			continue;
4786
4787		ret = encoder->compute_config_late(encoder, crtc_state,
4788						   conn_state);
4789		if (ret)
4790			return ret;
4791	}
4792
4793	return 0;
4794}
4795
4796bool intel_fuzzy_clock_check(int clock1, int clock2)
4797{
4798	int diff;
4799
4800	if (clock1 == clock2)
4801		return true;
4802
4803	if (!clock1 || !clock2)
4804		return false;
4805
4806	diff = abs(clock1 - clock2);
4807
4808	if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
4809		return true;
4810
4811	return false;
4812}
4813
4814static bool
4815intel_compare_link_m_n(const struct intel_link_m_n *m_n,
4816		       const struct intel_link_m_n *m2_n2)
4817{
4818	return m_n->tu == m2_n2->tu &&
4819		m_n->data_m == m2_n2->data_m &&
4820		m_n->data_n == m2_n2->data_n &&
4821		m_n->link_m == m2_n2->link_m &&
4822		m_n->link_n == m2_n2->link_n;
4823}
4824
4825static bool
4826intel_compare_infoframe(const union hdmi_infoframe *a,
4827			const union hdmi_infoframe *b)
4828{
4829	return memcmp(a, b, sizeof(*a)) == 0;
4830}
4831
4832static bool
4833intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
4834			 const struct drm_dp_vsc_sdp *b)
4835{
4836	return a->pixelformat == b->pixelformat &&
4837		a->colorimetry == b->colorimetry &&
4838		a->bpc == b->bpc &&
4839		a->dynamic_range == b->dynamic_range &&
4840		a->content_type == b->content_type;
4841}
4842
4843static bool
4844intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
4845			const struct drm_dp_as_sdp *b)
4846{
4847	return a->vtotal == b->vtotal &&
4848		a->target_rr == b->target_rr &&
4849		a->duration_incr_ms == b->duration_incr_ms &&
4850		a->duration_decr_ms == b->duration_decr_ms &&
4851		a->mode == b->mode;
4852}
4853
4854static bool
4855intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
4856{
4857	return memcmp(a, b, len) == 0;
4858}
4859
4860static void __printf(5, 6)
4861pipe_config_mismatch(struct drm_printer *p, bool fastset,
4862		     const struct intel_crtc *crtc,
4863		     const char *name, const char *format, ...)
4864{
4865	struct va_format vaf;
4866	va_list args;
4867
4868	va_start(args, format);
4869	vaf.fmt = format;
4870	vaf.va = &args;
4871
4872	if (fastset)
4873		drm_printf(p, "[CRTC:%d:%s] fastset requirement not met in %s %pV\n",
4874			   crtc->base.base.id, crtc->base.name, name, &vaf);
4875	else
4876		drm_printf(p, "[CRTC:%d:%s] mismatch in %s %pV\n",
4877			   crtc->base.base.id, crtc->base.name, name, &vaf);
4878
4879	va_end(args);
4880}
4881
4882static void
4883pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset,
4884			       const struct intel_crtc *crtc,
4885			       const char *name,
4886			       const union hdmi_infoframe *a,
4887			       const union hdmi_infoframe *b)
4888{
4889	struct intel_display *display = to_intel_display(crtc);
4890	const char *loglevel;
4891
4892	if (fastset) {
4893		if (!drm_debug_enabled(DRM_UT_KMS))
4894			return;
4895
4896		loglevel = KERN_DEBUG;
4897	} else {
4898		loglevel = KERN_ERR;
4899	}
4900
4901	pipe_config_mismatch(p, fastset, crtc, name, "infoframe");
4902
4903	drm_printf(p, "expected:\n");
4904	hdmi_infoframe_log(loglevel, display->drm->dev, a);
4905	drm_printf(p, "found:\n");
4906	hdmi_infoframe_log(loglevel, display->drm->dev, b);
4907}
4908
4909static void
4910pipe_config_dp_vsc_sdp_mismatch(struct drm_printer *p, bool fastset,
4911				const struct intel_crtc *crtc,
4912				const char *name,
4913				const struct drm_dp_vsc_sdp *a,
4914				const struct drm_dp_vsc_sdp *b)
4915{
4916	pipe_config_mismatch(p, fastset, crtc, name, "dp vsc sdp");
4917
4918	drm_printf(p, "expected:\n");
4919	drm_dp_vsc_sdp_log(p, a);
4920	drm_printf(p, "found:\n");
4921	drm_dp_vsc_sdp_log(p, b);
4922}
4923
4924static void
4925pipe_config_dp_as_sdp_mismatch(struct drm_printer *p, bool fastset,
4926			       const struct intel_crtc *crtc,
4927			       const char *name,
4928			       const struct drm_dp_as_sdp *a,
4929			       const struct drm_dp_as_sdp *b)
4930{
4931	pipe_config_mismatch(p, fastset, crtc, name, "dp as sdp");
4932
4933	drm_printf(p, "expected:\n");
4934	drm_dp_as_sdp_log(p, a);
4935	drm_printf(p, "found:\n");
4936	drm_dp_as_sdp_log(p, b);
4937}
4938
4939/* Returns the length up to and including the last differing byte */
4940static size_t
4941memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
4942{
4943	int i;
4944
4945	for (i = len - 1; i >= 0; i--) {
4946		if (a[i] != b[i])
4947			return i + 1;
4948	}
4949
4950	return 0;
4951}
4952
4953static void
4954pipe_config_buffer_mismatch(struct drm_printer *p, bool fastset,
4955			    const struct intel_crtc *crtc,
4956			    const char *name,
4957			    const u8 *a, const u8 *b, size_t len)
4958{
4959	pipe_config_mismatch(p, fastset, crtc, name, "buffer");
4960
4961	/* only dump up to the last difference */
4962	len = memcmp_diff_len(a, b, len);
4963
4964	drm_print_hex_dump(p, "expected: ", a, len);
4965	drm_print_hex_dump(p, "found:    ", b, len);
4966}
4967
4968static void
4969pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
4970			 const struct intel_crtc *crtc,
4971			 const char *name,
4972			 const struct intel_dpll_hw_state *a,
4973			 const struct intel_dpll_hw_state *b)
4974{
4975	struct intel_display *display = to_intel_display(crtc);
4976
4977	pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */
4978
4979	drm_printf(p, "expected:\n");
4980	intel_dpll_dump_hw_state(display, p, a);
4981	drm_printf(p, "found:\n");
4982	intel_dpll_dump_hw_state(display, p, b);
4983}
4984
4985static void
4986pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
4987			    const struct intel_crtc *crtc,
4988			    const char *name,
4989			    const struct intel_cx0pll_state *a,
4990			    const struct intel_cx0pll_state *b)
4991{
4992	struct intel_display *display = to_intel_display(crtc);
4993	char *chipname = a->use_c10 ? "C10" : "C20";
4994
4995	pipe_config_mismatch(p, fastset, crtc, name, chipname);
4996
4997	drm_printf(p, "expected:\n");
4998	intel_cx0pll_dump_hw_state(display, a);
4999	drm_printf(p, "found:\n");
5000	intel_cx0pll_dump_hw_state(display, b);
5001}
5002
5003static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state)
5004{
5005	struct intel_display *display = to_intel_display(old_crtc_state);
5006
5007	/*
5008	 * Allow fastboot to fix up vblank delay (handled via LRR
5009	 * codepaths), a bit dodgy as the registers aren't
5010	 * double buffered but seems to be working more or less...
5011	 *
5012	 * Also allow this when the VRR timing generator is always on,
5013	 * and optimized guardband is used. In such cases,
5014	 * vblank delay may vary even without inherited state, but it's
5015	 * still safe as VRR guardband is still same.
5016	 */
5017	return HAS_LRR(display) &&
5018	       (old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) &&
5019	       !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
5020}
5021
5022static void
5023pipe_config_lt_phy_pll_mismatch(struct drm_printer *p, bool fastset,
5024				const struct intel_crtc *crtc,
5025				const char *name,
5026				const struct intel_lt_phy_pll_state *a,
5027				const struct intel_lt_phy_pll_state *b)
5028{
5029	struct intel_display *display = to_intel_display(crtc);
5030	char *chipname = "LTPHY";
5031
5032	pipe_config_mismatch(p, fastset, crtc, name, chipname);
5033
5034	drm_printf(p, "expected:\n");
5035	intel_lt_phy_dump_hw_state(display, a);
5036	drm_printf(p, "found:\n");
5037	intel_lt_phy_dump_hw_state(display, b);
5038}
5039
5040bool
5041intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5042			  const struct intel_crtc_state *pipe_config,
5043			  bool fastset)
5044{
5045	struct intel_display *display = to_intel_display(current_config);
5046	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5047	struct drm_printer p;
5048	u32 exclude_infoframes = 0;
5049	bool ret = true;
5050
5051	if (fastset)
5052		p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
5053	else
5054		p = drm_err_printer(display->drm, NULL);
5055
5056#define PIPE_CONF_CHECK_X(name) do { \
5057	if (current_config->name != pipe_config->name) { \
5058		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5059				 __stringify(name) " is bool");	\
5060		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5061				     "(expected 0x%08x, found 0x%08x)", \
5062				     current_config->name, \
5063				     pipe_config->name); \
5064		ret = false; \
5065	} \
5066} while (0)
5067
5068#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
5069	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5070		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5071				 __stringify(name) " is bool");	\
5072		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5073				     "(expected 0x%08x, found 0x%08x)", \
5074				     current_config->name & (mask), \
5075				     pipe_config->name & (mask)); \
5076		ret = false; \
5077	} \
5078} while (0)
5079
5080#define PIPE_CONF_CHECK_I(name) do { \
5081	if (current_config->name != pipe_config->name) { \
5082		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5083				 __stringify(name) " is bool");	\
5084		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5085				     "(expected %i, found %i)", \
5086				     current_config->name, \
5087				     pipe_config->name); \
5088		ret = false; \
5089	} \
5090} while (0)
5091
5092#define PIPE_CONF_CHECK_LLI(name) do { \
5093	if (current_config->name != pipe_config->name) { \
5094		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5095				     "(expected %lli, found %lli)", \
5096				     current_config->name, \
5097				     pipe_config->name); \
5098		ret = false; \
5099	} \
5100} while (0)
5101
5102#define PIPE_CONF_CHECK_BOOL(name) do { \
5103	if (current_config->name != pipe_config->name) { \
5104		BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
5105				 __stringify(name) " is not bool");	\
5106		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5107				     "(expected %s, found %s)", \
5108				     str_yes_no(current_config->name), \
5109				     str_yes_no(pipe_config->name)); \
5110		ret = false; \
5111	} \
5112} while (0)
5113
5114#define PIPE_CONF_CHECK_P(name) do { \
5115	if (current_config->name != pipe_config->name) { \
5116		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5117				     "(expected %p, found %p)", \
5118				     current_config->name, \
5119				     pipe_config->name); \
5120		ret = false; \
5121	} \
5122} while (0)
5123
5124#define PIPE_CONF_CHECK_M_N(name) do { \
5125	if (!intel_compare_link_m_n(&current_config->name, \
5126				    &pipe_config->name)) { \
5127		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5128				     "(expected tu %i data %i/%i link %i/%i, " \
5129				     "found tu %i, data %i/%i link %i/%i)", \
5130				     current_config->name.tu, \
5131				     current_config->name.data_m, \
5132				     current_config->name.data_n, \
5133				     current_config->name.link_m, \
5134				     current_config->name.link_n, \
5135				     pipe_config->name.tu, \
5136				     pipe_config->name.data_m, \
5137				     pipe_config->name.data_n, \
5138				     pipe_config->name.link_m, \
5139				     pipe_config->name.link_n); \
5140		ret = false; \
5141	} \
5142} while (0)
5143
5144#define PIPE_CONF_CHECK_PLL(name) do { \
5145	if (!intel_dpll_compare_hw_state(display, &current_config->name, \
5146					 &pipe_config->name)) { \
5147		pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \
5148					 &current_config->name, \
5149					 &pipe_config->name); \
5150		ret = false; \
5151	} \
5152} while (0)
5153
5154#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
5155	if (!intel_cx0pll_compare_hw_state(&current_config->name, \
5156					   &pipe_config->name)) { \
5157		pipe_config_cx0pll_mismatch(&p, fastset, crtc, __stringify(name), \
5158					    &current_config->name, \
5159					    &pipe_config->name); \
5160		ret = false; \
5161	} \
5162} while (0)
5163
5164#define PIPE_CONF_CHECK_PLL_LT(name) do { \
5165	if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \
5166					       &pipe_config->name)) { \
5167		pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc, __stringify(name), \
5168						&current_config->name, \
5169						&pipe_config->name); \
5170		ret = false; \
5171	} \
5172} while (0)
5173
5174#define PIPE_CONF_CHECK_TIMINGS(name) do {     \
5175	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5176	PIPE_CONF_CHECK_I(name.crtc_htotal); \
5177	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5178	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5179	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5180	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5181	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5182	if (!fastset || !allow_vblank_delay_fastset(current_config)) \
5183		PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5184	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5185	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5186	if (!fastset || !pipe_config->update_lrr) { \
5187		PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5188		PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5189	} \
5190} while (0)
5191
5192#define PIPE_CONF_CHECK_RECT(name) do { \
5193	PIPE_CONF_CHECK_I(name.x1); \
5194	PIPE_CONF_CHECK_I(name.x2); \
5195	PIPE_CONF_CHECK_I(name.y1); \
5196	PIPE_CONF_CHECK_I(name.y2); \
5197} while (0)
5198
5199#define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5200	if ((current_config->name ^ pipe_config->name) & (mask)) { \
5201		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5202				     "(%x) (expected %i, found %i)", \
5203				     (mask), \
5204				     current_config->name & (mask), \
5205				     pipe_config->name & (mask)); \
5206		ret = false; \
5207	} \
5208} while (0)
5209
5210#define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5211	if (!intel_compare_infoframe(&current_config->infoframes.name, \
5212				     &pipe_config->infoframes.name)) { \
5213		pipe_config_infoframe_mismatch(&p, fastset, crtc, __stringify(name), \
5214					       &current_config->infoframes.name, \
5215					       &pipe_config->infoframes.name); \
5216		ret = false; \
5217	} \
5218} while (0)
5219
5220#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5221	if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
5222				      &pipe_config->infoframes.name)) { \
5223		pipe_config_dp_vsc_sdp_mismatch(&p, fastset, crtc, __stringify(name), \
5224						&current_config->infoframes.name, \
5225						&pipe_config->infoframes.name); \
5226		ret = false; \
5227	} \
5228} while (0)
5229
5230#define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \
5231	if (!intel_compare_dp_as_sdp(&current_config->infoframes.name, \
5232				      &pipe_config->infoframes.name)) { \
5233		pipe_config_dp_as_sdp_mismatch(&p, fastset, crtc, __stringify(name), \
5234						&current_config->infoframes.name, \
5235						&pipe_config->infoframes.name); \
5236		ret = false; \
5237	} \
5238} while (0)
5239
5240#define PIPE_CONF_CHECK_BUFFER(name, len) do { \
5241	BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
5242	BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
5243	if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5244		pipe_config_buffer_mismatch(&p, fastset, crtc, __stringify(name), \
5245					    current_config->name, \
5246					    pipe_config->name, \
5247					    (len)); \
5248		ret = false; \
5249	} \
5250} while (0)
5251
5252#define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5253	if (current_config->gamma_mode == pipe_config->gamma_mode && \
5254	    !intel_color_lut_equal(current_config, \
5255				   current_config->lut, pipe_config->lut, \
5256				   is_pre_csc_lut)) {	\
5257		pipe_config_mismatch(&p, fastset, crtc, __stringify(lut), \
5258				     "hw_state doesn't match sw_state"); \
5259		ret = false; \
5260	} \
5261} while (0)
5262
5263#define PIPE_CONF_CHECK_CSC(name) do { \
5264	PIPE_CONF_CHECK_X(name.preoff[0]); \
5265	PIPE_CONF_CHECK_X(name.preoff[1]); \
5266	PIPE_CONF_CHECK_X(name.preoff[2]); \
5267	PIPE_CONF_CHECK_X(name.coeff[0]); \
5268	PIPE_CONF_CHECK_X(name.coeff[1]); \
5269	PIPE_CONF_CHECK_X(name.coeff[2]); \
5270	PIPE_CONF_CHECK_X(name.coeff[3]); \
5271	PIPE_CONF_CHECK_X(name.coeff[4]); \
5272	PIPE_CONF_CHECK_X(name.coeff[5]); \
5273	PIPE_CONF_CHECK_X(name.coeff[6]); \
5274	PIPE_CONF_CHECK_X(name.coeff[7]); \
5275	PIPE_CONF_CHECK_X(name.coeff[8]); \
5276	PIPE_CONF_CHECK_X(name.postoff[0]); \
5277	PIPE_CONF_CHECK_X(name.postoff[1]); \
5278	PIPE_CONF_CHECK_X(name.postoff[2]); \
5279} while (0)
5280
5281#define PIPE_CONF_QUIRK(quirk) \
5282	((current_config->quirks | pipe_config->quirks) & (quirk))
5283
5284	PIPE_CONF_CHECK_BOOL(hw.enable);
5285	PIPE_CONF_CHECK_BOOL(hw.active);
5286
5287	PIPE_CONF_CHECK_I(cpu_transcoder);
5288	PIPE_CONF_CHECK_I(mst_master_transcoder);
5289
5290	PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5291	PIPE_CONF_CHECK_I(fdi_lanes);
5292	PIPE_CONF_CHECK_M_N(fdi_m_n);
5293
5294	PIPE_CONF_CHECK_I(lane_count);
5295	PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5296
5297	PIPE_CONF_CHECK_I(min_hblank);
5298
5299	if (HAS_DOUBLE_BUFFERED_M_N(display)) {
5300		if (!fastset || !pipe_config->update_m_n)
5301			PIPE_CONF_CHECK_M_N(dp_m_n);
5302	} else {
5303		PIPE_CONF_CHECK_M_N(dp_m_n);
5304		PIPE_CONF_CHECK_M_N(dp_m2_n2);
5305	}
5306
5307	PIPE_CONF_CHECK_X(output_types);
5308
5309	PIPE_CONF_CHECK_I(framestart_delay);
5310	PIPE_CONF_CHECK_I(msa_timing_delay);
5311
5312	PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5313	PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5314
5315	PIPE_CONF_CHECK_I(pixel_multiplier);
5316
5317	PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5318			      DRM_MODE_FLAG_INTERLACE);
5319
5320	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5321		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5322				      DRM_MODE_FLAG_PHSYNC);
5323		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5324				      DRM_MODE_FLAG_NHSYNC);
5325		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5326				      DRM_MODE_FLAG_PVSYNC);
5327		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5328				      DRM_MODE_FLAG_NVSYNC);
5329	}
5330
5331	PIPE_CONF_CHECK_I(output_format);
5332	PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5333	if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) ||
5334	    display->platform.valleyview || display->platform.cherryview)
5335		PIPE_CONF_CHECK_BOOL(limited_color_range);
5336
5337	PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5338	PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5339	PIPE_CONF_CHECK_BOOL(has_infoframe);
5340	PIPE_CONF_CHECK_BOOL(enhanced_framing);
5341	PIPE_CONF_CHECK_BOOL(fec_enable);
5342
5343	if (!fastset) {
5344		PIPE_CONF_CHECK_BOOL(has_audio);
5345		PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
5346	}
5347
5348	PIPE_CONF_CHECK_X(gmch_pfit.control);
5349	/* pfit ratios are autocomputed by the hw on gen4+ */
5350	if (DISPLAY_VER(display) < 4)
5351		PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5352	PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5353
5354	/*
5355	 * Changing the EDP transcoder input mux
5356	 * (A_ONOFF vs. A_ON) requires a full modeset.
5357	 */
5358	PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5359
5360	if (!fastset) {
5361		PIPE_CONF_CHECK_RECT(pipe_src);
5362
5363		PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5364		PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5365
5366		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5367		PIPE_CONF_CHECK_I(pixel_rate);
5368		PIPE_CONF_CHECK_BOOL(hw.casf_params.casf_enable);
5369		PIPE_CONF_CHECK_I(hw.casf_params.win_size);
5370		PIPE_CONF_CHECK_I(hw.casf_params.strength);
5371
5372		PIPE_CONF_CHECK_X(gamma_mode);
5373		if (display->platform.cherryview)
5374			PIPE_CONF_CHECK_X(cgm_mode);
5375		else
5376			PIPE_CONF_CHECK_X(csc_mode);
5377		PIPE_CONF_CHECK_BOOL(gamma_enable);
5378		PIPE_CONF_CHECK_BOOL(csc_enable);
5379		PIPE_CONF_CHECK_BOOL(wgc_enable);
5380
5381		PIPE_CONF_CHECK_I(linetime);
5382		PIPE_CONF_CHECK_I(ips_linetime);
5383
5384		PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
5385		PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
5386
5387		PIPE_CONF_CHECK_CSC(csc);
5388		PIPE_CONF_CHECK_CSC(output_csc);
5389	}
5390
5391	PIPE_CONF_CHECK_BOOL(double_wide);
5392
5393	if (display->dpll.mgr)
5394		PIPE_CONF_CHECK_P(intel_dpll);
5395
5396	/* FIXME convert everything over the dpll_mgr */
5397	if (display->dpll.mgr || HAS_GMCH(display))
5398		PIPE_CONF_CHECK_PLL(dpll_hw_state);
5399
5400	/* FIXME convert MTL+ platforms over to dpll_mgr */
5401	if (HAS_LT_PHY(display))
5402		PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
5403	else if (DISPLAY_VER(display) >= 14)
5404		PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
5405
5406	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5407	PIPE_CONF_CHECK_X(dsi_pll.div);
5408
5409	if (display->platform.g4x || DISPLAY_VER(display) >= 5)
5410		PIPE_CONF_CHECK_I(pipe_bpp);
5411
5412	if (!fastset || !pipe_config->update_m_n) {
5413		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
5414		PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
5415	}
5416	PIPE_CONF_CHECK_I(port_clock);
5417
5418	PIPE_CONF_CHECK_I(min_voltage_level);
5419
5420	if (current_config->has_psr || pipe_config->has_psr)
5421		exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
5422
5423	if (current_config->vrr.enable || pipe_config->vrr.enable)
5424		exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
5425
5426	PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, ~exclude_infoframes);
5427	PIPE_CONF_CHECK_X(infoframes.gcp);
5428	PIPE_CONF_CHECK_INFOFRAME(avi);
5429	PIPE_CONF_CHECK_INFOFRAME(spd);
5430	PIPE_CONF_CHECK_INFOFRAME(hdmi);
5431	if (!fastset) {
5432		PIPE_CONF_CHECK_INFOFRAME(drm);
5433		PIPE_CONF_CHECK_DP_AS_SDP(as_sdp);
5434	}
5435	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5436
5437	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5438	PIPE_CONF_CHECK_I(master_transcoder);
5439	PIPE_CONF_CHECK_X(joiner_pipes);
5440
5441	PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
5442	PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
5443	PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
5444	PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
5445	PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
5446	PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
5447	PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
5448	PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
5449	PIPE_CONF_CHECK_I(dsc.config.pic_width);
5450	PIPE_CONF_CHECK_I(dsc.config.pic_height);
5451	PIPE_CONF_CHECK_I(dsc.config.slice_width);
5452	PIPE_CONF_CHECK_I(dsc.config.slice_height);
5453	PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
5454	PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
5455	PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
5456	PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
5457	PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
5458	PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
5459	PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
5460	PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
5461	PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
5462	PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
5463	PIPE_CONF_CHECK_I(dsc.config.initial_offset);
5464	PIPE_CONF_CHECK_I(dsc.config.final_offset);
5465	PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
5466	PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
5467	PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
5468	PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
5469	PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
5470	PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
5471
5472	PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
5473	PIPE_CONF_CHECK_I(dsc.num_streams);
5474	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
5475
5476	PIPE_CONF_CHECK_BOOL(splitter.enable);
5477	PIPE_CONF_CHECK_I(splitter.link_count);
5478	PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5479
5480	if (!fastset) {
5481		PIPE_CONF_CHECK_BOOL(vrr.enable);
5482		PIPE_CONF_CHECK_I(vrr.vmin);
5483		PIPE_CONF_CHECK_I(vrr.vmax);
5484		PIPE_CONF_CHECK_I(vrr.flipline);
5485		PIPE_CONF_CHECK_I(vrr.vsync_start);
5486		PIPE_CONF_CHECK_I(vrr.vsync_end);
5487		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
5488		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
5489		PIPE_CONF_CHECK_BOOL(cmrr.enable);
5490	}
5491
5492	if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
5493		PIPE_CONF_CHECK_I(vrr.pipeline_full);
5494		PIPE_CONF_CHECK_I(vrr.guardband);
5495	}
5496
5497	PIPE_CONF_CHECK_I(set_context_latency);
5498
5499#undef PIPE_CONF_CHECK_X
5500#undef PIPE_CONF_CHECK_I
5501#undef PIPE_CONF_CHECK_LLI
5502#undef PIPE_CONF_CHECK_BOOL
5503#undef PIPE_CONF_CHECK_P
5504#undef PIPE_CONF_CHECK_FLAGS
5505#undef PIPE_CONF_CHECK_COLOR_LUT
5506#undef PIPE_CONF_CHECK_TIMINGS
5507#undef PIPE_CONF_CHECK_RECT
5508#undef PIPE_CONF_QUIRK
5509
5510	return ret;
5511}
5512
5513static void
5514intel_verify_planes(struct intel_atomic_state *state)
5515{
5516	struct intel_plane *plane;
5517	const struct intel_plane_state *plane_state;
5518	int i;
5519
5520	for_each_new_intel_plane_in_state(state, plane,
5521					  plane_state, i)
5522		assert_plane(plane, plane_state->is_y_plane ||
5523			     plane_state->uapi.visible);
5524}
5525
5526static int intel_modeset_pipe(struct intel_atomic_state *state,
5527			      struct intel_crtc_state *crtc_state,
5528			      const char *reason)
5529{
5530	struct intel_display *display = to_intel_display(state);
5531	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5532	int ret;
5533
5534	drm_dbg_kms(display->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5535		    crtc->base.base.id, crtc->base.name, reason);
5536
5537	ret = drm_atomic_add_affected_connectors(&state->base,
5538						 &crtc->base);
5539	if (ret)
5540		return ret;
5541
5542	ret = intel_dp_tunnel_atomic_add_state_for_crtc(state, crtc);
5543	if (ret)
5544		return ret;
5545
5546	ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
5547	if (ret)
5548		return ret;
5549
5550	ret = intel_plane_add_affected(state, crtc);
5551	if (ret)
5552		return ret;
5553
5554	crtc_state->uapi.mode_changed = true;
5555
5556	return 0;
5557}
5558
5559/**
5560 * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5561 * @state: intel atomic state
5562 * @reason: the reason for the full modeset
5563 * @mask: mask of pipes to modeset
5564 *
5565 * Add pipes in @mask to @state and force a full modeset on the enabled ones
5566 * due to the description in @reason.
5567 * This function can be called only before new plane states are computed.
5568 *
5569 * Returns 0 in case of success, negative error code otherwise.
5570 */
5571int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
5572				      const char *reason, u8 mask)
5573{
5574	struct intel_display *display = to_intel_display(state);
5575	struct intel_crtc *crtc;
5576
5577	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mask) {
5578		struct intel_crtc_state *crtc_state;
5579		int ret;
5580
5581		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5582		if (IS_ERR(crtc_state))
5583			return PTR_ERR(crtc_state);
5584
5585		if (!crtc_state->hw.enable ||
5586		    intel_crtc_needs_modeset(crtc_state))
5587			continue;
5588
5589		ret = intel_modeset_pipe(state, crtc_state, reason);
5590		if (ret)
5591			return ret;
5592	}
5593
5594	return 0;
5595}
5596
5597static void
5598intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state)
5599{
5600	crtc_state->uapi.mode_changed = true;
5601
5602	crtc_state->update_pipe = false;
5603	crtc_state->update_m_n = false;
5604	crtc_state->update_lrr = false;
5605}
5606
5607/**
5608 * intel_modeset_all_pipes_late - force a full modeset on all pipes
5609 * @state: intel atomic state
5610 * @reason: the reason for the full modeset
5611 *
5612 * Add all pipes to @state and force a full modeset on the active ones due to
5613 * the description in @reason.
5614 * This function can be called only after new plane states are computed already.
5615 *
5616 * Returns 0 in case of success, negative error code otherwise.
5617 */
5618int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
5619				 const char *reason)
5620{
5621	struct intel_display *display = to_intel_display(state);
5622	struct intel_crtc *crtc;
5623
5624	for_each_intel_crtc(display->drm, crtc) {
5625		struct intel_crtc_state *crtc_state;
5626		int ret;
5627
5628		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5629		if (IS_ERR(crtc_state))
5630			return PTR_ERR(crtc_state);
5631
5632		if (!crtc_state->hw.active ||
5633		    intel_crtc_needs_modeset(crtc_state))
5634			continue;
5635
5636		ret = intel_modeset_pipe(state, crtc_state, reason);
5637		if (ret)
5638			return ret;
5639
5640		intel_crtc_flag_modeset(crtc_state);
5641
5642		crtc_state->update_planes |= crtc_state->active_planes;
5643		crtc_state->async_flip_planes = 0;
5644		crtc_state->do_async_flip = false;
5645	}
5646
5647	return 0;
5648}
5649
5650int intel_modeset_commit_pipes(struct intel_display *display,
5651			       u8 pipe_mask,
5652			       struct drm_modeset_acquire_ctx *ctx)
5653{
5654	struct drm_atomic_state *state;
5655	struct intel_crtc *crtc;
5656	int ret;
5657
5658	state = drm_atomic_state_alloc(display->drm);
5659	if (!state)
5660		return -ENOMEM;
5661
5662	state->acquire_ctx = ctx;
5663	to_intel_atomic_state(state)->internal = true;
5664
5665	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {
5666		struct intel_crtc_state *crtc_state =
5667			intel_atomic_get_crtc_state(state, crtc);
5668
5669		if (IS_ERR(crtc_state)) {
5670			ret = PTR_ERR(crtc_state);
5671			goto out;
5672		}
5673
5674		crtc_state->uapi.connectors_changed = true;
5675	}
5676
5677	ret = drm_atomic_commit(state);
5678out:
5679	drm_atomic_state_put(state);
5680
5681	return ret;
5682}
5683
5684/*
5685 * This implements the workaround described in the "notes" section of the mode
5686 * set sequence documentation. When going from no pipes or single pipe to
5687 * multiple pipes, and planes are enabled after the pipe, we need to wait at
5688 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
5689 */
5690static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
5691{
5692	struct intel_crtc_state *crtc_state;
5693	struct intel_crtc *crtc;
5694	struct intel_crtc_state *first_crtc_state = NULL;
5695	struct intel_crtc_state *other_crtc_state = NULL;
5696	enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
5697	int i;
5698
5699	/* look at all crtc's that are going to be enabled in during modeset */
5700	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5701		if (!crtc_state->hw.active ||
5702		    !intel_crtc_needs_modeset(crtc_state))
5703			continue;
5704
5705		if (first_crtc_state) {
5706			other_crtc_state = crtc_state;
5707			break;
5708		} else {
5709			first_crtc_state = crtc_state;
5710			first_pipe = crtc->pipe;
5711		}
5712	}
5713
5714	/* No workaround needed? */
5715	if (!first_crtc_state)
5716		return 0;
5717
5718	/* w/a possibly needed, check how many crtc's are already enabled. */
5719	for_each_intel_crtc(state->base.dev, crtc) {
5720		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5721		if (IS_ERR(crtc_state))
5722			return PTR_ERR(crtc_state);
5723
5724		crtc_state->hsw_workaround_pipe = INVALID_PIPE;
5725
5726		if (!crtc_state->hw.active ||
5727		    intel_crtc_needs_modeset(crtc_state))
5728			continue;
5729
5730		/* 2 or more enabled crtcs means no need for w/a */
5731		if (enabled_pipe != INVALID_PIPE)
5732			return 0;
5733
5734		enabled_pipe = crtc->pipe;
5735	}
5736
5737	if (enabled_pipe != INVALID_PIPE)
5738		first_crtc_state->hsw_workaround_pipe = enabled_pipe;
5739	else if (other_crtc_state)
5740		other_crtc_state->hsw_workaround_pipe = first_pipe;
5741
5742	return 0;
5743}
5744
5745u8 intel_calc_enabled_pipes(struct intel_atomic_state *state,
5746			    u8 enabled_pipes)
5747{
5748	const struct intel_crtc_state *crtc_state;
5749	struct intel_crtc *crtc;
5750	int i;
5751
5752	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5753		if (crtc_state->hw.enable)
5754			enabled_pipes |= BIT(crtc->pipe);
5755		else
5756			enabled_pipes &= ~BIT(crtc->pipe);
5757	}
5758
5759	return enabled_pipes;
5760}
5761
5762u8 intel_calc_active_pipes(struct intel_atomic_state *state,
5763			   u8 active_pipes)
5764{
5765	const struct intel_crtc_state *crtc_state;
5766	struct intel_crtc *crtc;
5767	int i;
5768
5769	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5770		if (crtc_state->hw.active)
5771			active_pipes |= BIT(crtc->pipe);
5772		else
5773			active_pipes &= ~BIT(crtc->pipe);
5774	}
5775
5776	return active_pipes;
5777}
5778
5779static int intel_modeset_checks(struct intel_atomic_state *state)
5780{
5781	struct intel_display *display = to_intel_display(state);
5782
5783	state->modeset = true;
5784
5785	if (display->platform.haswell)
5786		return hsw_mode_set_planes_workaround(state);
5787
5788	return 0;
5789}
5790
5791static bool lrr_params_changed(const struct intel_crtc_state *old_crtc_state,
5792			       const struct intel_crtc_state *new_crtc_state)
5793{
5794	const struct drm_display_mode *old_adjusted_mode = &old_crtc_state->hw.adjusted_mode;
5795	const struct drm_display_mode *new_adjusted_mode = &new_crtc_state->hw.adjusted_mode;
5796
5797	return old_adjusted_mode->crtc_vblank_start != new_adjusted_mode->crtc_vblank_start ||
5798		old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end ||
5799		old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal ||
5800		old_crtc_state->set_context_latency != new_crtc_state->set_context_latency;
5801}
5802
5803static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
5804				     struct intel_crtc_state *new_crtc_state)
5805{
5806	struct intel_display *display = to_intel_display(new_crtc_state);
5807	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5808
5809	/* only allow LRR when the timings stay within the VRR range */
5810	if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
5811		new_crtc_state->update_lrr = false;
5812
5813	if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) {
5814		drm_dbg_kms(display->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n",
5815			    crtc->base.base.id, crtc->base.name);
5816	} else {
5817		if (allow_vblank_delay_fastset(old_crtc_state))
5818			new_crtc_state->update_lrr = true;
5819		new_crtc_state->uapi.mode_changed = false;
5820	}
5821
5822	if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,
5823				   &new_crtc_state->dp_m_n))
5824		new_crtc_state->update_m_n = false;
5825
5826	if (!lrr_params_changed(old_crtc_state, new_crtc_state))
5827		new_crtc_state->update_lrr = false;
5828
5829	if (intel_crtc_needs_modeset(new_crtc_state))
5830		intel_crtc_flag_modeset(new_crtc_state);
5831	else
5832		new_crtc_state->update_pipe = true;
5833}
5834
5835static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
5836{
5837	struct intel_display *display = to_intel_display(state);
5838	struct intel_crtc_state __maybe_unused *crtc_state;
5839	struct intel_crtc *crtc;
5840	int i;
5841
5842	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5843		int ret;
5844
5845		ret = intel_crtc_atomic_check(state, crtc);
5846		if (ret) {
5847			drm_dbg_atomic(display->drm,
5848				       "[CRTC:%d:%s] atomic driver check failed\n",
5849				       crtc->base.base.id, crtc->base.name);
5850			return ret;
5851		}
5852	}
5853
5854	return 0;
5855}
5856
5857static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
5858					       u8 transcoders)
5859{
5860	const struct intel_crtc_state *new_crtc_state;
5861	struct intel_crtc *crtc;
5862	int i;
5863
5864	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5865		if (new_crtc_state->hw.enable &&
5866		    transcoders & BIT(new_crtc_state->cpu_transcoder) &&
5867		    intel_crtc_needs_modeset(new_crtc_state))
5868			return true;
5869	}
5870
5871	return false;
5872}
5873
5874static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
5875				     u8 pipes)
5876{
5877	const struct intel_crtc_state *new_crtc_state;
5878	struct intel_crtc *crtc;
5879	int i;
5880
5881	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5882		if (new_crtc_state->hw.enable &&
5883		    pipes & BIT(crtc->pipe) &&
5884		    intel_crtc_needs_modeset(new_crtc_state))
5885			return true;
5886	}
5887
5888	return false;
5889}
5890
5891static int intel_atomic_check_joiner(struct intel_atomic_state *state,
5892				     struct intel_crtc *primary_crtc)
5893{
5894	struct intel_display *display = to_intel_display(state);
5895	struct intel_crtc_state *primary_crtc_state =
5896		intel_atomic_get_new_crtc_state(state, primary_crtc);
5897	struct intel_crtc *secondary_crtc;
5898
5899	if (!primary_crtc_state->joiner_pipes)
5900		return 0;
5901
5902	/* sanity check */
5903	if (drm_WARN_ON(display->drm,
5904			primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state)))
5905		return -EINVAL;
5906
5907	if (primary_crtc_state->joiner_pipes & ~joiner_pipes(display)) {
5908		drm_dbg_kms(display->drm,
5909			    "[CRTC:%d:%s] Cannot act as joiner primary "
5910			    "(need 0x%x as pipes, only 0x%x possible)\n",
5911			    primary_crtc->base.base.id, primary_crtc->base.name,
5912			    primary_crtc_state->joiner_pipes, joiner_pipes(display));
5913		return -EINVAL;
5914	}
5915
5916	for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,
5917					 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
5918		struct intel_crtc_state *secondary_crtc_state;
5919		int ret;
5920
5921		secondary_crtc_state = intel_atomic_get_crtc_state(&state->base, secondary_crtc);
5922		if (IS_ERR(secondary_crtc_state))
5923			return PTR_ERR(secondary_crtc_state);
5924
5925		/* primary being enabled, secondary was already configured? */
5926		if (secondary_crtc_state->uapi.enable) {
5927			drm_dbg_kms(display->drm,
5928				    "[CRTC:%d:%s] secondary is enabled as normal CRTC, but "
5929				    "[CRTC:%d:%s] claiming this CRTC for joiner.\n",
5930				    secondary_crtc->base.base.id, secondary_crtc->base.name,
5931				    primary_crtc->base.base.id, primary_crtc->base.name);
5932			return -EINVAL;
5933		}
5934
5935		/*
5936		 * The state copy logic assumes the primary crtc gets processed
5937		 * before the secondary crtc during the main compute_config loop.
5938		 * This works because the crtcs are created in pipe order,
5939		 * and the hardware requires primary pipe < secondary pipe as well.
5940		 * Should that change we need to rethink the logic.
5941		 */
5942		if (WARN_ON(drm_crtc_index(&primary_crtc->base) >
5943			    drm_crtc_index(&secondary_crtc->base)))
5944			return -EINVAL;
5945
5946		drm_dbg_kms(display->drm,
5947			    "[CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s]\n",
5948			    secondary_crtc->base.base.id, secondary_crtc->base.name,
5949			    primary_crtc->base.base.id, primary_crtc->base.name);
5950
5951		secondary_crtc_state->joiner_pipes =
5952			primary_crtc_state->joiner_pipes;
5953
5954		ret = copy_joiner_crtc_state_modeset(state, secondary_crtc);
5955		if (ret)
5956			return ret;
5957	}
5958
5959	return 0;
5960}
5961
5962static void kill_joiner_secondaries(struct intel_atomic_state *state,
5963				    struct intel_crtc *primary_crtc)
5964{
5965	struct intel_display *display = to_intel_display(state);
5966	struct intel_crtc_state *primary_crtc_state =
5967		intel_atomic_get_new_crtc_state(state, primary_crtc);
5968	struct intel_crtc *secondary_crtc;
5969
5970	for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,
5971					 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
5972		struct intel_crtc_state *secondary_crtc_state =
5973			intel_atomic_get_new_crtc_state(state, secondary_crtc);
5974
5975		secondary_crtc_state->joiner_pipes = 0;
5976
5977		intel_crtc_copy_uapi_to_hw_state_modeset(state, secondary_crtc);
5978	}
5979
5980	primary_crtc_state->joiner_pipes = 0;
5981}
5982
5983/**
5984 * DOC: asynchronous flip implementation
5985 *
5986 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
5987 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
5988 * Correspondingly, support is currently added for primary plane only.
5989 *
5990 * Async flip can only change the plane surface address, so anything else
5991 * changing is rejected from the intel_async_flip_check_hw() function.
5992 * Once this check is cleared, flip done interrupt is enabled using
5993 * the intel_crtc_enable_flip_done() function.
5994 *
5995 * As soon as the surface address register is written, flip done interrupt is
5996 * generated and the requested events are sent to the userspace in the interrupt
5997 * handler itself. The timestamp and sequence sent during the flip done event
5998 * correspond to the last vblank and have no relation to the actual time when
5999 * the flip done event was sent.
6000 */
6001static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
6002				       struct intel_crtc *crtc)
6003{
6004	struct intel_display *display = to_intel_display(state);
6005	const struct intel_crtc_state *new_crtc_state =
6006		intel_atomic_get_new_crtc_state(state, crtc);
6007	const struct intel_plane_state *old_plane_state;
6008	struct intel_plane_state *new_plane_state;
6009	struct intel_plane *plane;
6010	int i;
6011
6012	if (!new_crtc_state->uapi.async_flip)
6013		return 0;
6014
6015	if (!new_crtc_state->uapi.active) {
6016		drm_dbg_kms(display->drm,
6017			    "[CRTC:%d:%s] not active\n",
6018			    crtc->base.base.id, crtc->base.name);
6019		return -EINVAL;
6020	}
6021
6022	if (intel_crtc_needs_modeset(new_crtc_state)) {
6023		drm_dbg_kms(display->drm,
6024			    "[CRTC:%d:%s] modeset required\n",
6025			    crtc->base.base.id, crtc->base.name);
6026		return -EINVAL;
6027	}
6028
6029	/*
6030	 * FIXME: joiner+async flip is busted currently.
6031	 * Remove this check once the issues are fixed.
6032	 */
6033	if (new_crtc_state->joiner_pipes) {
6034		drm_dbg_kms(display->drm,
6035			    "[CRTC:%d:%s] async flip disallowed with joiner\n",
6036			    crtc->base.base.id, crtc->base.name);
6037		return -EINVAL;
6038	}
6039
6040	/* FIXME: selective fetch should be disabled for async flips */
6041	if (new_crtc_state->enable_psr2_sel_fetch) {
6042		drm_dbg_kms(display->drm,
6043			    "[CRTC:%d:%s] async flip disallowed with PSR2 selective fetch\n",
6044			    crtc->base.base.id, crtc->base.name);
6045		return -EINVAL;
6046	}
6047
6048	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6049					     new_plane_state, i) {
6050		if (plane->pipe != crtc->pipe)
6051			continue;
6052
6053		/*
6054		 * TODO: Async flip is only supported through the page flip IOCTL
6055		 * as of now. So support currently added for primary plane only.
6056		 * Support for other planes on platforms on which supports
6057		 * this(vlv/chv and icl+) should be added when async flip is
6058		 * enabled in the atomic IOCTL path.
6059		 */
6060		if (!plane->async_flip) {
6061			drm_dbg_kms(display->drm,
6062				    "[PLANE:%d:%s] async flip not supported\n",
6063				    plane->base.base.id, plane->base.name);
6064			return -EINVAL;
6065		}
6066
6067		if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
6068			drm_dbg_kms(display->drm,
6069				    "[PLANE:%d:%s] no old or new framebuffer\n",
6070				    plane->base.base.id, plane->base.name);
6071			return -EINVAL;
6072		}
6073	}
6074
6075	return 0;
6076}
6077
6078static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
6079{
6080	struct intel_display *display = to_intel_display(state);
6081	const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6082	const struct intel_plane_state *new_plane_state, *old_plane_state;
6083	struct intel_plane *plane;
6084	int i;
6085
6086	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6087	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6088
6089	if (!new_crtc_state->uapi.async_flip)
6090		return 0;
6091
6092	if (!new_crtc_state->hw.active) {
6093		drm_dbg_kms(display->drm,
6094			    "[CRTC:%d:%s] not active\n",
6095			    crtc->base.base.id, crtc->base.name);
6096		return -EINVAL;
6097	}
6098
6099	if (intel_crtc_needs_modeset(new_crtc_state)) {
6100		drm_dbg_kms(display->drm,
6101			    "[CRTC:%d:%s] modeset required\n",
6102			    crtc->base.base.id, crtc->base.name);
6103		return -EINVAL;
6104	}
6105
6106	if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
6107		drm_dbg_kms(display->drm,
6108			    "[CRTC:%d:%s] Active planes cannot be in async flip\n",
6109			    crtc->base.base.id, crtc->base.name);
6110		return -EINVAL;
6111	}
6112
6113	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6114					     new_plane_state, i) {
6115		if (plane->pipe != crtc->pipe)
6116			continue;
6117
6118		/*
6119		 * Only async flip capable planes should be in the state
6120		 * if we're really about to ask the hardware to perform
6121		 * an async flip. We should never get this far otherwise.
6122		 */
6123		if (drm_WARN_ON(display->drm,
6124				new_crtc_state->do_async_flip && !plane->async_flip))
6125			return -EINVAL;
6126
6127		/*
6128		 * Only check async flip capable planes other planes
6129		 * may be involved in the initial commit due to
6130		 * the wm0/ddb optimization.
6131		 *
6132		 * TODO maybe should track which planes actually
6133		 * were requested to do the async flip...
6134		 */
6135		if (!plane->async_flip)
6136			continue;
6137
6138		if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format->format,
6139						new_plane_state->hw.fb->modifier)) {
6140			drm_dbg_kms(display->drm,
6141				    "[PLANE:%d:%s] pixel format %p4cc / modifier 0x%llx does not support async flip\n",
6142				    plane->base.base.id, plane->base.name,
6143				    &new_plane_state->hw.fb->format->format,
6144				    new_plane_state->hw.fb->modifier);
6145			return -EINVAL;
6146		}
6147
6148		/*
6149		 * We turn the first async flip request into a sync flip
6150		 * so that we can reconfigure the plane (eg. change modifier).
6151		 */
6152		if (!new_crtc_state->do_async_flip)
6153			continue;
6154
6155		if (old_plane_state->view.color_plane[0].mapping_stride !=
6156		    new_plane_state->view.color_plane[0].mapping_stride) {
6157			drm_dbg_kms(display->drm,
6158				    "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6159				    plane->base.base.id, plane->base.name);
6160			return -EINVAL;
6161		}
6162
6163		if (old_plane_state->hw.fb->modifier !=
6164		    new_plane_state->hw.fb->modifier) {
6165			drm_dbg_kms(display->drm,
6166				    "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6167				    plane->base.base.id, plane->base.name);
6168			return -EINVAL;
6169		}
6170
6171		if (old_plane_state->hw.fb->format !=
6172		    new_plane_state->hw.fb->format) {
6173			drm_dbg_kms(display->drm,
6174				    "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6175				    plane->base.base.id, plane->base.name);
6176			return -EINVAL;
6177		}
6178
6179		if (old_plane_state->hw.rotation !=
6180		    new_plane_state->hw.rotation) {
6181			drm_dbg_kms(display->drm,
6182				    "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6183				    plane->base.base.id, plane->base.name);
6184			return -EINVAL;
6185		}
6186
6187		if (skl_plane_aux_dist(old_plane_state, 0) !=
6188		    skl_plane_aux_dist(new_plane_state, 0)) {
6189			drm_dbg_kms(display->drm,
6190				    "[PLANE:%d:%s] AUX_DIST cannot be changed in async flip\n",
6191				    plane->base.base.id, plane->base.name);
6192			return -EINVAL;
6193		}
6194
6195		if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
6196		    !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
6197			drm_dbg_kms(display->drm,
6198				    "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6199				    plane->base.base.id, plane->base.name);
6200			return -EINVAL;
6201		}
6202
6203		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6204			drm_dbg_kms(display->drm,
6205				    "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6206				    plane->base.base.id, plane->base.name);
6207			return -EINVAL;
6208		}
6209
6210		if (old_plane_state->hw.pixel_blend_mode !=
6211		    new_plane_state->hw.pixel_blend_mode) {
6212			drm_dbg_kms(display->drm,
6213				    "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6214				    plane->base.base.id, plane->base.name);
6215			return -EINVAL;
6216		}
6217
6218		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6219			drm_dbg_kms(display->drm,
6220				    "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6221				    plane->base.base.id, plane->base.name);
6222			return -EINVAL;
6223		}
6224
6225		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6226			drm_dbg_kms(display->drm,
6227				    "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6228				    plane->base.base.id, plane->base.name);
6229			return -EINVAL;
6230		}
6231
6232		/* plane decryption is allow to change only in synchronous flips */
6233		if (old_plane_state->decrypt != new_plane_state->decrypt) {
6234			drm_dbg_kms(display->drm,
6235				    "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6236				    plane->base.base.id, plane->base.name);
6237			return -EINVAL;
6238		}
6239	}
6240
6241	return 0;
6242}
6243
6244static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
6245{
6246	struct intel_display *display = to_intel_display(state);
6247	const struct intel_plane_state *plane_state;
6248	struct intel_crtc_state *crtc_state;
6249	struct intel_plane *plane;
6250	struct intel_crtc *crtc;
6251	u8 affected_pipes = 0;
6252	u8 modeset_pipes = 0;
6253	int i;
6254
6255	/*
6256	 * Any plane which is in use by the joiner needs its crtc.
6257	 * Pull those in first as this will not have happened yet
6258	 * if the plane remains disabled according to uapi.
6259	 */
6260	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6261		crtc = to_intel_crtc(plane_state->hw.crtc);
6262		if (!crtc)
6263			continue;
6264
6265		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6266		if (IS_ERR(crtc_state))
6267			return PTR_ERR(crtc_state);
6268	}
6269
6270	/* Now pull in all joined crtcs */
6271	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6272		affected_pipes |= crtc_state->joiner_pipes;
6273		if (intel_crtc_needs_modeset(crtc_state))
6274			modeset_pipes |= crtc_state->joiner_pipes;
6275	}
6276
6277	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, affected_pipes) {
6278		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6279		if (IS_ERR(crtc_state))
6280			return PTR_ERR(crtc_state);
6281	}
6282
6283	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, modeset_pipes) {
6284		int ret;
6285
6286		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6287
6288		crtc_state->uapi.mode_changed = true;
6289
6290		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6291		if (ret)
6292			return ret;
6293
6294		ret = intel_plane_add_affected(state, crtc);
6295		if (ret)
6296			return ret;
6297	}
6298
6299	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6300		/* Kill old joiner link, we may re-establish afterwards */
6301		if (intel_crtc_needs_modeset(crtc_state) &&
6302		    intel_crtc_is_joiner_primary(crtc_state))
6303			kill_joiner_secondaries(state, crtc);
6304	}
6305
6306	return 0;
6307}
6308
6309static int intel_atomic_check_config(struct intel_atomic_state *state,
6310				     struct intel_link_bw_limits *limits,
6311				     enum pipe *failed_pipe)
6312{
6313	struct intel_display *display = to_intel_display(state);
6314	struct intel_crtc_state *new_crtc_state;
6315	struct intel_crtc *crtc;
6316	int ret;
6317	int i;
6318
6319	*failed_pipe = INVALID_PIPE;
6320
6321	ret = intel_joiner_add_affected_crtcs(state);
6322	if (ret)
6323		return ret;
6324
6325	ret = intel_fdi_add_affected_crtcs(state);
6326	if (ret)
6327		return ret;
6328
6329	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6330		if (!intel_crtc_needs_modeset(new_crtc_state)) {
6331			if (intel_crtc_is_joiner_secondary(new_crtc_state))
6332				copy_joiner_crtc_state_nomodeset(state, crtc);
6333			else
6334				intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6335			continue;
6336		}
6337
6338		if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
6339			continue;
6340
6341		ret = intel_crtc_prepare_cleared_state(state, crtc);
6342		if (ret)
6343			goto fail;
6344
6345		if (!new_crtc_state->hw.enable)
6346			continue;
6347
6348		ret = intel_modeset_pipe_config(state, crtc, limits);
6349		if (ret)
6350			goto fail;
6351	}
6352
6353	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6354		if (!intel_crtc_needs_modeset(new_crtc_state))
6355			continue;
6356
6357		if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
6358			continue;
6359
6360		if (!new_crtc_state->hw.enable)
6361			continue;
6362
6363		ret = intel_modeset_pipe_config_late(state, crtc);
6364		if (ret)
6365			goto fail;
6366	}
6367
6368fail:
6369	if (ret)
6370		*failed_pipe = crtc->pipe;
6371
6372	return ret;
6373}
6374
6375static int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
6376{
6377	struct intel_link_bw_limits new_limits;
6378	struct intel_link_bw_limits old_limits;
6379	int ret;
6380
6381	intel_link_bw_init_limits(state, &new_limits);
6382	old_limits = new_limits;
6383
6384	while (true) {
6385		enum pipe failed_pipe;
6386
6387		ret = intel_atomic_check_config(state, &new_limits,
6388						&failed_pipe);
6389		if (ret) {
6390			/*
6391			 * The bpp limit for a pipe is below the minimum it supports, set the
6392			 * limit to the minimum and recalculate the config.
6393			 */
6394			if (ret == -EINVAL &&
6395			    intel_link_bw_set_bpp_limit_for_pipe(state,
6396								 &old_limits,
6397								 &new_limits,
6398								 failed_pipe))
6399				continue;
6400
6401			break;
6402		}
6403
6404		old_limits = new_limits;
6405
6406		ret = intel_link_bw_atomic_check(state, &new_limits);
6407		if (ret != -EAGAIN)
6408			break;
6409	}
6410
6411	return ret;
6412}
6413/**
6414 * intel_atomic_check - validate state object
6415 * @dev: drm device
6416 * @_state: state to validate
6417 */
6418int intel_atomic_check(struct drm_device *dev,
6419		       struct drm_atomic_state *_state)
6420{
6421	struct intel_display *display = to_intel_display(dev);
6422	struct intel_atomic_state *state = to_intel_atomic_state(_state);
6423	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6424	struct intel_crtc *crtc;
6425	int ret, i;
6426
6427	if (!intel_display_driver_check_access(display))
6428		return -ENODEV;
6429
6430	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6431					    new_crtc_state, i) {
6432		/*
6433		 * crtc's state no longer considered to be inherited
6434		 * after the first userspace/client initiated commit.
6435		 */
6436		if (!state->internal)
6437			new_crtc_state->inherited = false;
6438
6439		if (new_crtc_state->inherited != old_crtc_state->inherited)
6440			new_crtc_state->uapi.mode_changed = true;
6441
6442		if (new_crtc_state->uapi.scaling_filter !=
6443		    old_crtc_state->uapi.scaling_filter)
6444			new_crtc_state->uapi.mode_changed = true;
6445	}
6446
6447	intel_vrr_check_modeset(state);
6448
6449	ret = drm_atomic_helper_check_modeset(dev, &state->base);
6450	if (ret)
6451		goto fail;
6452
6453	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6454		ret = intel_async_flip_check_uapi(state, crtc);
6455		if (ret)
6456			return ret;
6457	}
6458
6459	ret = intel_atomic_check_config_and_link(state);
6460	if (ret)
6461		goto fail;
6462
6463	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6464		if (!intel_crtc_needs_modeset(new_crtc_state))
6465			continue;
6466
6467		if (intel_crtc_is_joiner_secondary(new_crtc_state)) {
6468			drm_WARN_ON(display->drm, new_crtc_state->uapi.enable);
6469			continue;
6470		}
6471
6472		ret = intel_atomic_check_joiner(state, crtc);
6473		if (ret)
6474			goto fail;
6475	}
6476
6477	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6478					    new_crtc_state, i) {
6479		if (!intel_crtc_needs_modeset(new_crtc_state))
6480			continue;
6481
6482		intel_joiner_adjust_pipe_src(new_crtc_state);
6483
6484		intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6485	}
6486
6487	/**
6488	 * Check if fastset is allowed by external dependencies like other
6489	 * pipes and transcoders.
6490	 *
6491	 * Right now it only forces a fullmodeset when the MST master
6492	 * transcoder did not changed but the pipe of the master transcoder
6493	 * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6494	 * in case of port synced crtcs, if one of the synced crtcs
6495	 * needs a full modeset, all other synced crtcs should be
6496	 * forced a full modeset.
6497	 */
6498	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6499		if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6500			continue;
6501
6502		if (intel_dp_mst_crtc_needs_modeset(state, crtc))
6503			intel_crtc_flag_modeset(new_crtc_state);
6504
6505		if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
6506			enum transcoder master = new_crtc_state->mst_master_transcoder;
6507
6508			if (intel_cpu_transcoders_need_modeset(state, BIT(master)))
6509				intel_crtc_flag_modeset(new_crtc_state);
6510		}
6511
6512		if (is_trans_port_sync_mode(new_crtc_state)) {
6513			u8 trans = new_crtc_state->sync_mode_slaves_mask;
6514
6515			if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6516				trans |= BIT(new_crtc_state->master_transcoder);
6517
6518			if (intel_cpu_transcoders_need_modeset(state, trans))
6519				intel_crtc_flag_modeset(new_crtc_state);
6520		}
6521
6522		if (new_crtc_state->joiner_pipes) {
6523			if (intel_pipes_need_modeset(state, new_crtc_state->joiner_pipes))
6524				intel_crtc_flag_modeset(new_crtc_state);
6525		}
6526	}
6527
6528	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6529					    new_crtc_state, i) {
6530		if (!intel_crtc_needs_modeset(new_crtc_state))
6531			continue;
6532
6533		intel_dpll_release(state, crtc);
6534	}
6535
6536	if (intel_any_crtc_needs_modeset(state) && !check_digital_port_conflicts(state)) {
6537		drm_dbg_kms(display->drm, "rejecting conflicting digital port configuration\n");
6538		ret = -EINVAL;
6539		goto fail;
6540	}
6541
6542	ret = intel_plane_atomic_check(state);
6543	if (ret)
6544		goto fail;
6545
6546	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
6547		new_crtc_state->min_cdclk = intel_crtc_min_cdclk(new_crtc_state);
6548
6549	ret = intel_compute_global_watermarks(state);
6550	if (ret)
6551		goto fail;
6552
6553	ret = intel_bw_atomic_check(state);
6554	if (ret)
6555		goto fail;
6556
6557	ret = intel_cdclk_atomic_check(state);
6558	if (ret)
6559		goto fail;
6560
6561	if (intel_any_crtc_needs_modeset(state)) {
6562		ret = intel_modeset_checks(state);
6563		if (ret)
6564			goto fail;
6565	}
6566
6567	ret = intel_pmdemand_atomic_check(state);
6568	if (ret)
6569		goto fail;
6570
6571	ret = intel_atomic_check_crtcs(state);
6572	if (ret)
6573		goto fail;
6574
6575	ret = intel_fbc_atomic_check(state);
6576	if (ret)
6577		goto fail;
6578
6579	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6580					    new_crtc_state, i) {
6581		intel_color_assert_luts(new_crtc_state);
6582
6583		ret = intel_async_flip_check_hw(state, crtc);
6584		if (ret)
6585			goto fail;
6586
6587		/* Either full modeset or fastset (or neither), never both */
6588		drm_WARN_ON(display->drm,
6589			    intel_crtc_needs_modeset(new_crtc_state) &&
6590			    intel_crtc_needs_fastset(new_crtc_state));
6591
6592		if (!intel_crtc_needs_modeset(new_crtc_state) &&
6593		    !intel_crtc_needs_fastset(new_crtc_state))
6594			continue;
6595
6596		intel_crtc_state_dump(new_crtc_state, state,
6597				      intel_crtc_needs_modeset(new_crtc_state) ?
6598				      "modeset" : "fastset");
6599	}
6600
6601	return 0;
6602
6603 fail:
6604	if (ret == -EDEADLK)
6605		return ret;
6606
6607	/*
6608	 * FIXME would probably be nice to know which crtc specifically
6609	 * caused the failure, in cases where we can pinpoint it.
6610	 */
6611	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6612					    new_crtc_state, i)
6613		intel_crtc_state_dump(new_crtc_state, state, "failed");
6614
6615	return ret;
6616}
6617
6618static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6619{
6620	int ret;
6621
6622	ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
6623	if (ret < 0)
6624		return ret;
6625
6626	return 0;
6627}
6628
6629void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
6630				  struct intel_crtc_state *crtc_state)
6631{
6632	struct intel_display *display = to_intel_display(crtc);
6633
6634	if (DISPLAY_VER(display) != 2 || crtc_state->active_planes)
6635		intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);
6636
6637	if (crtc_state->has_pch_encoder) {
6638		enum pipe pch_transcoder =
6639			intel_crtc_pch_transcoder(crtc);
6640
6641		intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, true);
6642	}
6643}
6644
6645static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
6646			       const struct intel_crtc_state *new_crtc_state)
6647{
6648	struct intel_display *display = to_intel_display(new_crtc_state);
6649	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6650
6651	/*
6652	 * Update pipe size and adjust fitter if needed: the reason for this is
6653	 * that in compute_mode_changes we check the native mode (not the pfit
6654	 * mode) to see if we can flip rather than do a full mode set. In the
6655	 * fastboot case, we'll flip, but if we don't update the pipesrc and
6656	 * pfit state, we'll end up with a big fb scanned out into the wrong
6657	 * sized surface.
6658	 */
6659	intel_set_pipe_src_size(new_crtc_state);
6660
6661	/* on skylake this is done by detaching scalers */
6662	if (DISPLAY_VER(display) >= 9) {
6663		if (new_crtc_state->pch_pfit.enabled)
6664			skl_pfit_enable(new_crtc_state);
6665	} else if (HAS_PCH_SPLIT(display)) {
6666		if (new_crtc_state->pch_pfit.enabled)
6667			ilk_pfit_enable(new_crtc_state);
6668		else if (old_crtc_state->pch_pfit.enabled)
6669			ilk_pfit_disable(old_crtc_state);
6670	}
6671
6672	/*
6673	 * The register is supposedly single buffered so perhaps
6674	 * not 100% correct to do this here. But SKL+ calculate
6675	 * this based on the adjust pixel rate so pfit changes do
6676	 * affect it and so it must be updated for fastsets.
6677	 * HSW/BDW only really need this here for fastboot, after
6678	 * that the value should not change without a full modeset.
6679	 */
6680	if (DISPLAY_VER(display) >= 9 ||
6681	    display->platform.broadwell || display->platform.haswell)
6682		hsw_set_linetime_wm(new_crtc_state);
6683
6684	if (new_crtc_state->update_m_n)
6685		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
6686					       &new_crtc_state->dp_m_n);
6687
6688	if (new_crtc_state->update_lrr)
6689		intel_set_transcoder_timings_lrr(new_crtc_state);
6690}
6691
6692static void commit_pipe_pre_planes(struct intel_atomic_state *state,
6693				   struct intel_crtc *crtc)
6694{
6695	struct intel_display *display = to_intel_display(state);
6696	const struct intel_crtc_state *old_crtc_state =
6697		intel_atomic_get_old_crtc_state(state, crtc);
6698	const struct intel_crtc_state *new_crtc_state =
6699		intel_atomic_get_new_crtc_state(state, crtc);
6700	bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6701
6702	drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);
6703
6704	/*
6705	 * During modesets pipe configuration was programmed as the
6706	 * CRTC was enabled.
6707	 */
6708	if (!modeset) {
6709		if (intel_crtc_needs_color_update(new_crtc_state))
6710			intel_color_commit_arm(NULL, new_crtc_state);
6711
6712		if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)
6713			bdw_set_pipe_misc(NULL, new_crtc_state);
6714
6715		if (intel_crtc_needs_fastset(new_crtc_state))
6716			intel_pipe_fastset(old_crtc_state, new_crtc_state);
6717	}
6718
6719	intel_psr2_program_trans_man_trk_ctl(NULL, new_crtc_state);
6720
6721	intel_atomic_update_watermarks(state, crtc);
6722}
6723
6724static void commit_pipe_post_planes(struct intel_atomic_state *state,
6725				    struct intel_crtc *crtc)
6726{
6727	struct intel_display *display = to_intel_display(state);
6728	const struct intel_crtc_state *new_crtc_state =
6729		intel_atomic_get_new_crtc_state(state, crtc);
6730	bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6731
6732	drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);
6733
6734	/*
6735	 * Disable the scaler(s) after the plane(s) so that we don't
6736	 * get a catastrophic underrun even if the two operations
6737	 * end up happening in two different frames.
6738	 */
6739	if (DISPLAY_VER(display) >= 9 && !modeset)
6740		skl_detach_scalers(NULL, new_crtc_state);
6741
6742	if (!modeset &&
6743	    intel_crtc_needs_color_update(new_crtc_state) &&
6744	    !intel_color_uses_dsb(new_crtc_state) &&
6745	    HAS_DOUBLE_BUFFERED_LUT(display))
6746		intel_color_load_luts(new_crtc_state);
6747
6748	if (intel_crtc_vrr_enabling(state, crtc))
6749		intel_vrr_enable(new_crtc_state);
6750}
6751
6752static void intel_enable_crtc(struct intel_atomic_state *state,
6753			      struct intel_crtc *crtc)
6754{
6755	struct intel_display *display = to_intel_display(state);
6756	const struct intel_crtc_state *new_crtc_state =
6757		intel_atomic_get_new_crtc_state(state, crtc);
6758	struct intel_crtc *pipe_crtc;
6759
6760	if (!intel_crtc_needs_modeset(new_crtc_state))
6761		return;
6762
6763	for_each_intel_crtc_in_pipe_mask_reverse(display->drm, pipe_crtc,
6764						 intel_crtc_joined_pipe_mask(new_crtc_state)) {
6765		const struct intel_crtc_state *pipe_crtc_state =
6766			intel_atomic_get_new_crtc_state(state, pipe_crtc);
6767
6768		/* VRR will be enable later, if required */
6769		intel_crtc_update_active_timings(pipe_crtc_state, false);
6770	}
6771
6772	intel_psr_notify_pipe_change(state, crtc, true);
6773
6774	display->funcs.display->crtc_enable(state, crtc);
6775
6776	/* vblanks work again, re-enable pipe CRC. */
6777	intel_crtc_enable_pipe_crc(crtc);
6778}
6779
6780static void intel_pre_update_crtc(struct intel_atomic_state *state,
6781				  struct intel_crtc *crtc)
6782{
6783	struct intel_display *display = to_intel_display(state);
6784	const struct intel_crtc_state *old_crtc_state =
6785		intel_atomic_get_old_crtc_state(state, crtc);
6786	struct intel_crtc_state *new_crtc_state =
6787		intel_atomic_get_new_crtc_state(state, crtc);
6788	bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6789
6790	if (old_crtc_state->inherited ||
6791	    intel_crtc_needs_modeset(new_crtc_state)) {
6792		if (HAS_DPT(display))
6793			intel_dpt_configure(crtc);
6794	}
6795
6796	if (!modeset) {
6797		if (new_crtc_state->preload_luts &&
6798		    intel_crtc_needs_color_update(new_crtc_state))
6799			intel_color_load_luts(new_crtc_state);
6800
6801		intel_pre_plane_update(state, crtc);
6802
6803		if (intel_crtc_needs_fastset(new_crtc_state))
6804			intel_encoders_update_pipe(state, crtc);
6805
6806		if (DISPLAY_VER(display) >= 11 &&
6807		    intel_crtc_needs_fastset(new_crtc_state))
6808			icl_set_pipe_chicken(new_crtc_state);
6809
6810		if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
6811		    cmrr_params_changed(old_crtc_state, new_crtc_state))
6812			intel_vrr_set_transcoder_timings(new_crtc_state);
6813	}
6814
6815	if (intel_casf_enabling(new_crtc_state, old_crtc_state))
6816		intel_casf_enable(new_crtc_state);
6817	else if (new_crtc_state->hw.casf_params.strength != old_crtc_state->hw.casf_params.strength)
6818		intel_casf_update_strength(new_crtc_state);
6819
6820	intel_fbc_update(state, crtc);
6821
6822	drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF));
6823
6824	if (!modeset &&
6825	    intel_crtc_needs_color_update(new_crtc_state) &&
6826	    !new_crtc_state->use_dsb && !new_crtc_state->use_flipq)
6827		intel_color_commit_noarm(NULL, new_crtc_state);
6828
6829	if (!new_crtc_state->use_dsb && !new_crtc_state->use_flipq)
6830		intel_crtc_planes_update_noarm(NULL, state, crtc);
6831}
6832
6833static void intel_update_crtc(struct intel_atomic_state *state,
6834			      struct intel_crtc *crtc)
6835{
6836	const struct intel_crtc_state *old_crtc_state =
6837		intel_atomic_get_old_crtc_state(state, crtc);
6838	struct intel_crtc_state *new_crtc_state =
6839		intel_atomic_get_new_crtc_state(state, crtc);
6840
6841	if (new_crtc_state->use_flipq) {
6842		intel_flipq_enable(new_crtc_state);
6843
6844		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->flipq_event);
6845
6846		intel_flipq_add(crtc, INTEL_FLIPQ_PLANE_1, 0, INTEL_DSB_0,
6847				new_crtc_state->dsb_commit);
6848	} else if (new_crtc_state->use_dsb) {
6849		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event);
6850
6851		intel_dsb_commit(new_crtc_state->dsb_commit);
6852	} else {
6853		/* Perform vblank evasion around commit operation */
6854		intel_pipe_update_start(state, crtc);
6855
6856		if (new_crtc_state->dsb_commit)
6857			intel_dsb_commit(new_crtc_state->dsb_commit);
6858
6859		commit_pipe_pre_planes(state, crtc);
6860
6861		intel_crtc_planes_update_arm(NULL, state, crtc);
6862
6863		commit_pipe_post_planes(state, crtc);
6864
6865		intel_pipe_update_end(state, crtc);
6866	}
6867
6868	/*
6869	 * VRR/Seamless M/N update may need to update frame timings.
6870	 *
6871	 * FIXME Should be synchronized with the start of vblank somehow...
6872	 */
6873	if (intel_crtc_vrr_enabling(state, crtc) ||
6874	    new_crtc_state->update_m_n || new_crtc_state->update_lrr)
6875		intel_crtc_update_active_timings(new_crtc_state,
6876						 new_crtc_state->vrr.enable);
6877
6878	/*
6879	 * We usually enable FIFO underrun interrupts as part of the
6880	 * CRTC enable sequence during modesets.  But when we inherit a
6881	 * valid pipe configuration from the BIOS we need to take care
6882	 * of enabling them on the CRTC's first fastset.
6883	 */
6884	if (intel_crtc_needs_fastset(new_crtc_state) &&
6885	    old_crtc_state->inherited)
6886		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
6887}
6888
6889static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
6890					  struct intel_crtc *crtc)
6891{
6892	struct intel_display *display = to_intel_display(state);
6893	const struct intel_crtc_state *old_crtc_state =
6894		intel_atomic_get_old_crtc_state(state, crtc);
6895	struct intel_crtc *pipe_crtc;
6896
6897	/*
6898	 * We need to disable pipe CRC before disabling the pipe,
6899	 * or we race against vblank off.
6900	 */
6901	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
6902					 intel_crtc_joined_pipe_mask(old_crtc_state))
6903		intel_crtc_disable_pipe_crc(pipe_crtc);
6904
6905	intel_psr_notify_pipe_change(state, crtc, false);
6906
6907	display->funcs.display->crtc_disable(state, crtc);
6908
6909	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
6910					 intel_crtc_joined_pipe_mask(old_crtc_state)) {
6911		const struct intel_crtc_state *new_pipe_crtc_state =
6912			intel_atomic_get_new_crtc_state(state, pipe_crtc);
6913
6914		pipe_crtc->active = false;
6915		intel_fbc_disable(pipe_crtc);
6916
6917		if (!new_pipe_crtc_state->hw.active)
6918			intel_initial_watermarks(state, pipe_crtc);
6919	}
6920}
6921
6922static void intel_commit_modeset_disables(struct intel_atomic_state *state)
6923{
6924	struct intel_display *display = to_intel_display(state);
6925	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
6926	struct intel_crtc *crtc;
6927	u8 disable_pipes = 0;
6928	int i;
6929
6930	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6931					    new_crtc_state, i) {
6932		if (!intel_crtc_needs_modeset(new_crtc_state))
6933			continue;
6934
6935		/*
6936		 * Needs to be done even for pipes
6937		 * that weren't enabled previously.
6938		 */
6939		intel_pre_plane_update(state, crtc);
6940
6941		if (!old_crtc_state->hw.active)
6942			continue;
6943
6944		disable_pipes |= BIT(crtc->pipe);
6945	}
6946
6947	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
6948		if ((disable_pipes & BIT(crtc->pipe)) == 0)
6949			continue;
6950
6951		intel_crtc_disable_planes(state, crtc);
6952
6953		drm_vblank_work_flush_all(&crtc->base);
6954	}
6955
6956	/* Only disable port sync and MST slaves */
6957	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
6958		if ((disable_pipes & BIT(crtc->pipe)) == 0)
6959			continue;
6960
6961		if (intel_crtc_is_joiner_secondary(old_crtc_state))
6962			continue;
6963
6964		/* In case of Transcoder port Sync master slave CRTCs can be
6965		 * assigned in any order and we need to make sure that
6966		 * slave CRTCs are disabled first and then master CRTC since
6967		 * Slave vblanks are masked till Master Vblanks.
6968		 */
6969		if (!is_trans_port_sync_slave(old_crtc_state) &&
6970		    !intel_dp_mst_is_slave_trans(old_crtc_state))
6971			continue;
6972
6973		intel_old_crtc_state_disables(state, crtc);
6974
6975		disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state);
6976	}
6977
6978	/* Disable everything else left on */
6979	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
6980		if ((disable_pipes & BIT(crtc->pipe)) == 0)
6981			continue;
6982
6983		if (intel_crtc_is_joiner_secondary(old_crtc_state))
6984			continue;
6985
6986		intel_old_crtc_state_disables(state, crtc);
6987
6988		disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state);
6989	}
6990
6991	drm_WARN_ON(display->drm, disable_pipes);
6992}
6993
6994static void intel_commit_modeset_enables(struct intel_atomic_state *state)
6995{
6996	struct intel_crtc_state *new_crtc_state;
6997	struct intel_crtc *crtc;
6998	int i;
6999
7000	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7001		if (!new_crtc_state->hw.active)
7002			continue;
7003
7004		intel_enable_crtc(state, crtc);
7005		intel_pre_update_crtc(state, crtc);
7006	}
7007
7008	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7009		if (!new_crtc_state->hw.active)
7010			continue;
7011
7012		intel_update_crtc(state, crtc);
7013	}
7014}
7015
7016static void skl_commit_modeset_enables(struct intel_atomic_state *state)
7017{
7018	struct intel_display *display = to_intel_display(state);
7019	struct intel_crtc *crtc;
7020	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
7021	struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
7022	u8 update_pipes = 0, modeset_pipes = 0;
7023	int i;
7024
7025	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7026		enum pipe pipe = crtc->pipe;
7027
7028		if (!new_crtc_state->hw.active)
7029			continue;
7030
7031		/* ignore allocations for crtc's that have been turned off. */
7032		if (!intel_crtc_needs_modeset(new_crtc_state)) {
7033			entries[pipe] = old_crtc_state->wm.skl.ddb;
7034			update_pipes |= BIT(pipe);
7035		} else {
7036			modeset_pipes |= BIT(pipe);
7037		}
7038	}
7039
7040	/*
7041	 * Whenever the number of active pipes changes, we need to make sure we
7042	 * update the pipes in the right order so that their ddb allocations
7043	 * never overlap with each other between CRTC updates. Otherwise we'll
7044	 * cause pipe underruns and other bad stuff.
7045	 *
7046	 * So first lets enable all pipes that do not need a fullmodeset as
7047	 * those don't have any external dependency.
7048	 */
7049	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7050		enum pipe pipe = crtc->pipe;
7051
7052		if ((update_pipes & BIT(pipe)) == 0)
7053			continue;
7054
7055		intel_pre_update_crtc(state, crtc);
7056	}
7057
7058	intel_dbuf_mbus_pre_ddb_update(state);
7059
7060	while (update_pipes) {
7061		/*
7062		 * Commit in reverse order to make joiner primary
7063		 * send the uapi events after secondaries are done.
7064		 */
7065		for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
7066							    new_crtc_state, i) {
7067			enum pipe pipe = crtc->pipe;
7068
7069			if ((update_pipes & BIT(pipe)) == 0)
7070				continue;
7071
7072			if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7073							entries, I915_MAX_PIPES, pipe))
7074				continue;
7075
7076			entries[pipe] = new_crtc_state->wm.skl.ddb;
7077			update_pipes &= ~BIT(pipe);
7078
7079			intel_update_crtc(state, crtc);
7080
7081			/*
7082			 * If this is an already active pipe, it's DDB changed,
7083			 * and this isn't the last pipe that needs updating
7084			 * then we need to wait for a vblank to pass for the
7085			 * new ddb allocation to take effect.
7086			 */
7087			if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
7088						 &old_crtc_state->wm.skl.ddb) &&
7089			    (update_pipes | modeset_pipes))
7090				intel_crtc_wait_for_next_vblank(crtc);
7091		}
7092	}
7093
7094	intel_dbuf_mbus_post_ddb_update(state);
7095
7096	update_pipes = modeset_pipes;
7097
7098	/*
7099	 * Enable all pipes that needs a modeset and do not depends on other
7100	 * pipes
7101	 */
7102	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7103		enum pipe pipe = crtc->pipe;
7104
7105		if ((modeset_pipes & BIT(pipe)) == 0)
7106			continue;
7107
7108		if (intel_crtc_is_joiner_secondary(new_crtc_state))
7109			continue;
7110
7111		if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
7112		    is_trans_port_sync_master(new_crtc_state))
7113			continue;
7114
7115		modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state);
7116
7117		intel_enable_crtc(state, crtc);
7118	}
7119
7120	/*
7121	 * Then we enable all remaining pipes that depend on other
7122	 * pipes: MST slaves and port sync masters
7123	 */
7124	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7125		enum pipe pipe = crtc->pipe;
7126
7127		if ((modeset_pipes & BIT(pipe)) == 0)
7128			continue;
7129
7130		if (intel_crtc_is_joiner_secondary(new_crtc_state))
7131			continue;
7132
7133		modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state);
7134
7135		intel_enable_crtc(state, crtc);
7136	}
7137
7138	/*
7139	 * Finally we do the plane updates/etc. for all pipes that got enabled.
7140	 */
7141	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7142		enum pipe pipe = crtc->pipe;
7143
7144		if ((update_pipes & BIT(pipe)) == 0)
7145			continue;
7146
7147		intel_pre_update_crtc(state, crtc);
7148	}
7149
7150	/*
7151	 * Commit in reverse order to make joiner primary
7152	 * send the uapi events after secondaries are done.
7153	 */
7154	for_each_new_intel_crtc_in_state_reverse(state, crtc, new_crtc_state, i) {
7155		enum pipe pipe = crtc->pipe;
7156
7157		if ((update_pipes & BIT(pipe)) == 0)
7158			continue;
7159
7160		drm_WARN_ON(display->drm,
7161			    skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7162							entries, I915_MAX_PIPES, pipe));
7163
7164		entries[pipe] = new_crtc_state->wm.skl.ddb;
7165		update_pipes &= ~BIT(pipe);
7166
7167		intel_update_crtc(state, crtc);
7168	}
7169
7170	drm_WARN_ON(display->drm, modeset_pipes);
7171	drm_WARN_ON(display->drm, update_pipes);
7172}
7173
7174static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
7175{
7176	struct drm_i915_private *i915 = to_i915(intel_state->base.dev);
7177	struct drm_plane *plane;
7178	struct drm_plane_state *new_plane_state;
7179	long ret;
7180	int i;
7181
7182	for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {
7183		if (new_plane_state->fence) {
7184			ret = dma_fence_wait_timeout(new_plane_state->fence, false,
7185						     i915_fence_timeout(i915));
7186			if (ret <= 0)
7187				break;
7188
7189			dma_fence_put(new_plane_state->fence);
7190			new_plane_state->fence = NULL;
7191		}
7192	}
7193}
7194
7195static void intel_atomic_dsb_wait_commit(struct intel_crtc_state *crtc_state)
7196{
7197	if (crtc_state->dsb_commit)
7198		intel_dsb_wait(crtc_state->dsb_commit);
7199
7200	intel_color_wait_commit(crtc_state);
7201}
7202
7203static void intel_atomic_dsb_cleanup(struct intel_crtc_state *crtc_state)
7204{
7205	if (crtc_state->dsb_commit) {
7206		intel_dsb_cleanup(crtc_state->dsb_commit);
7207		crtc_state->dsb_commit = NULL;
7208	}
7209
7210	intel_color_cleanup_commit(crtc_state);
7211}
7212
7213static void intel_atomic_cleanup_work(struct work_struct *work)
7214{
7215	struct intel_atomic_state *state =
7216		container_of(work, struct intel_atomic_state, cleanup_work);
7217	struct intel_display *display = to_intel_display(state);
7218	struct intel_crtc_state *old_crtc_state;
7219	struct intel_crtc *crtc;
7220	int i;
7221
7222	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i)
7223		intel_atomic_dsb_cleanup(old_crtc_state);
7224
7225	drm_atomic_helper_cleanup_planes(display->drm, &state->base);
7226	drm_atomic_helper_commit_cleanup_done(&state->base);
7227	drm_atomic_state_put(&state->base);
7228}
7229
7230static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
7231{
7232	struct intel_display *display = to_intel_display(state);
7233	struct intel_plane *plane;
7234	struct intel_plane_state *plane_state;
7235	int i;
7236
7237	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7238		struct drm_framebuffer *fb = plane_state->hw.fb;
7239		int cc_plane;
7240		int ret;
7241
7242		if (!fb)
7243			continue;
7244
7245		cc_plane = intel_fb_rc_ccs_cc_plane(fb);
7246		if (cc_plane < 0)
7247			continue;
7248
7249		/*
7250		 * The layout of the fast clear color value expected by HW
7251		 * (the DRM ABI requiring this value to be located in fb at
7252		 * offset 0 of cc plane, plane #2 previous generations or
7253		 * plane #1 for flat ccs):
7254		 * - 4 x 4 bytes per-channel value
7255		 *   (in surface type specific float/int format provided by the fb user)
7256		 * - 8 bytes native color value used by the display
7257		 *   (converted/written by GPU during a fast clear operation using the
7258		 *    above per-channel values)
7259		 *
7260		 * The commit's FB prepare hook already ensured that FB obj is pinned and the
7261		 * caller made sure that the object is synced wrt. the related color clear value
7262		 * GPU write on it.
7263		 */
7264		ret = intel_bo_read_from_page(intel_fb_bo(fb),
7265					      fb->offsets[cc_plane] + 16,
7266					      &plane_state->ccval,
7267					      sizeof(plane_state->ccval));
7268		/* The above could only fail if the FB obj has an unexpected backing store type. */
7269		drm_WARN_ON(display->drm, ret);
7270	}
7271}
7272
7273static void intel_atomic_dsb_prepare(struct intel_atomic_state *state,
7274				     struct intel_crtc *crtc)
7275{
7276	struct intel_display *display = to_intel_display(state);
7277	struct intel_crtc_state *new_crtc_state =
7278		intel_atomic_get_new_crtc_state(state, crtc);
7279
7280	if (!new_crtc_state->hw.active)
7281		return;
7282
7283	if (state->base.legacy_cursor_update)
7284		return;
7285
7286	/* FIXME deal with everything */
7287	new_crtc_state->use_flipq =
7288		intel_flipq_supported(display) &&
7289		!new_crtc_state->do_async_flip &&
7290		!new_crtc_state->vrr.enable &&
7291		!new_crtc_state->has_psr &&
7292		!intel_crtc_needs_modeset(new_crtc_state) &&
7293		!intel_crtc_needs_fastset(new_crtc_state) &&
7294		!intel_crtc_needs_color_update(new_crtc_state);
7295
7296	new_crtc_state->use_dsb =
7297		!new_crtc_state->use_flipq &&
7298		!new_crtc_state->do_async_flip &&
7299		(DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&
7300		!intel_crtc_needs_modeset(new_crtc_state) &&
7301		!intel_crtc_needs_fastset(new_crtc_state);
7302
7303	intel_color_prepare_commit(state, crtc);
7304}
7305
7306static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
7307				    struct intel_crtc *crtc)
7308{
7309	struct intel_display *display = to_intel_display(state);
7310	struct intel_crtc_state *new_crtc_state =
7311		intel_atomic_get_new_crtc_state(state, crtc);
7312	unsigned int size = new_crtc_state->plane_color_changed ? 8192 : 1024;
7313
7314	if (!new_crtc_state->use_flipq &&
7315	    !new_crtc_state->use_dsb &&
7316	    !new_crtc_state->dsb_color)
7317		return;
7318
7319	/*
7320	 * Rough estimate:
7321	 * ~64 registers per each plane * 8 planes = 512
7322	 * Double that for pipe stuff and other overhead.
7323	 * ~4913 registers for 3DLUT
7324	 * ~200 color registers * 3 HDR planes
7325	 */
7326	new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0,
7327						       new_crtc_state->use_dsb ||
7328						       new_crtc_state->use_flipq ? size : 16);
7329	if (!new_crtc_state->dsb_commit) {
7330		new_crtc_state->use_flipq = false;
7331		new_crtc_state->use_dsb = false;
7332		intel_color_cleanup_commit(new_crtc_state);
7333		return;
7334	}
7335
7336	if (new_crtc_state->use_flipq || new_crtc_state->use_dsb) {
7337		/* Wa_18034343758 */
7338		if (new_crtc_state->use_flipq)
7339			intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit, crtc);
7340
7341		if (intel_crtc_needs_color_update(new_crtc_state))
7342			intel_color_commit_noarm(new_crtc_state->dsb_commit,
7343						 new_crtc_state);
7344		intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit,
7345					       state, crtc);
7346
7347		/*
7348		 * Ensure we have "Frame Change" event when PSR state is
7349		 * SRDENT(PSR1) or DEEP_SLEEP(PSR2). Otherwise DSB vblank
7350		 * evasion hangs as PIPEDSL is reading as 0.
7351		 */
7352		intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit,
7353						     state, crtc);
7354
7355		intel_psr_wait_for_idle_dsb(new_crtc_state->dsb_commit,
7356					    new_crtc_state);
7357
7358		if (new_crtc_state->use_dsb)
7359			intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
7360
7361		if (intel_crtc_needs_color_update(new_crtc_state))
7362			intel_color_commit_arm(new_crtc_state->dsb_commit,
7363					       new_crtc_state);
7364		bdw_set_pipe_misc(new_crtc_state->dsb_commit,
7365				  new_crtc_state);
7366		intel_psr2_program_trans_man_trk_ctl(new_crtc_state->dsb_commit,
7367						     new_crtc_state);
7368		intel_crtc_planes_update_arm(new_crtc_state->dsb_commit,
7369					     state, crtc);
7370
7371		if (DISPLAY_VER(display) >= 9)
7372			skl_detach_scalers(new_crtc_state->dsb_commit,
7373					   new_crtc_state);
7374
7375		/* Wa_18034343758 */
7376		if (new_crtc_state->use_flipq)
7377			intel_flipq_unhalt_dmc(new_crtc_state->dsb_commit, crtc);
7378	}
7379
7380	if (intel_color_uses_chained_dsb(new_crtc_state))
7381		intel_dsb_chain(state, new_crtc_state->dsb_commit,
7382				new_crtc_state->dsb_color, true);
7383	else if (intel_color_uses_gosub_dsb(new_crtc_state))
7384		intel_dsb_gosub(new_crtc_state->dsb_commit,
7385				new_crtc_state->dsb_color);
7386
7387	if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) {
7388		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
7389
7390		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
7391		intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit);
7392		intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
7393					  new_crtc_state);
7394		intel_dsb_interrupt(new_crtc_state->dsb_commit);
7395	}
7396
7397	intel_dsb_finish(new_crtc_state->dsb_commit);
7398}
7399
7400static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7401{
7402	struct intel_display *display = to_intel_display(state);
7403	struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm);
7404	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7405	struct intel_crtc *crtc;
7406	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7407	intel_wakeref_t wakeref = NULL;
7408	int i;
7409
7410	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7411		intel_atomic_dsb_prepare(state, crtc);
7412
7413	intel_atomic_commit_fence_wait(state);
7414
7415	intel_td_flush(display);
7416
7417	intel_atomic_prepare_plane_clear_colors(state);
7418
7419	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7420		intel_fbc_prepare_dirty_rect(state, crtc);
7421
7422	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7423		intel_atomic_dsb_finish(state, crtc);
7424
7425	drm_atomic_helper_wait_for_dependencies(&state->base);
7426	drm_dp_mst_atomic_wait_for_dependencies(&state->base);
7427	intel_atomic_global_state_wait_for_dependencies(state);
7428
7429	/*
7430	 * During full modesets we write a lot of registers, wait
7431	 * for PLLs, etc. Doing that while DC states are enabled
7432	 * is not a good idea.
7433	 *
7434	 * During fastsets and other updates we also need to
7435	 * disable DC states due to the following scenario:
7436	 * 1. DC5 exit and PSR exit happen
7437	 * 2. Some or all _noarm() registers are written
7438	 * 3. Due to some long delay PSR is re-entered
7439	 * 4. DC5 entry -> DMC saves the already written new
7440	 *    _noarm() registers and the old not yet written
7441	 *    _arm() registers
7442	 * 5. DC5 exit -> DMC restores a mixture of old and
7443	 *    new register values and arms the update
7444	 * 6. PSR exit -> hardware latches a mixture of old and
7445	 *    new register values -> corrupted frame, or worse
7446	 * 7. New _arm() registers are finally written
7447	 * 8. Hardware finally latches a complete set of new
7448	 *    register values, and subsequent frames will be OK again
7449	 *
7450	 * Also note that due to the pipe CSC hardware issues on
7451	 * SKL/GLK DC states must remain off until the pipe CSC
7452	 * state readout has happened. Otherwise we risk corrupting
7453	 * the CSC latched register values with the readout (see
7454	 * skl_read_csc() and skl_color_commit_noarm()).
7455	 */
7456	wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF);
7457
7458	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7459					    new_crtc_state, i) {
7460		if (intel_crtc_needs_modeset(new_crtc_state) ||
7461		    intel_crtc_needs_fastset(new_crtc_state))
7462			intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
7463	}
7464
7465	intel_commit_modeset_disables(state);
7466
7467	intel_dp_tunnel_atomic_alloc_bw(state);
7468
7469	/* FIXME: Eventually get rid of our crtc->config pointer */
7470	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7471		crtc->config = new_crtc_state;
7472
7473	/*
7474	 * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
7475	 * plls, cdclk frequency, QGV point selection parameter etc. Voltage
7476	 * index, cdclk/ddiclk frequencies are supposed to be configured before
7477	 * the cdclk config is set.
7478	 */
7479	intel_pmdemand_pre_plane_update(state);
7480
7481	if (state->modeset)
7482		drm_atomic_helper_update_legacy_modeset_state(display->drm, &state->base);
7483
7484	intel_set_cdclk_pre_plane_update(state);
7485
7486	if (state->modeset)
7487		intel_modeset_verify_disabled(state);
7488
7489	intel_sagv_pre_plane_update(state);
7490
7491	/* Complete the events for pipes that have now been disabled */
7492	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7493		bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7494
7495		/* Complete events for now disable pipes here. */
7496		if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7497			spin_lock_irq(&display->drm->event_lock);
7498			drm_crtc_send_vblank_event(&crtc->base,
7499						   new_crtc_state->uapi.event);
7500			spin_unlock_irq(&display->drm->event_lock);
7501
7502			new_crtc_state->uapi.event = NULL;
7503		}
7504	}
7505
7506	intel_encoders_update_prepare(state);
7507
7508	intel_dbuf_pre_plane_update(state);
7509
7510	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7511		if (new_crtc_state->do_async_flip)
7512			intel_crtc_enable_flip_done(state, crtc);
7513	}
7514
7515	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
7516	display->funcs.display->commit_modeset_enables(state);
7517
7518	/* FIXME probably need to sequence this properly */
7519	intel_program_dpkgc_latency(state);
7520
7521	intel_wait_for_vblank_workers(state);
7522
7523	/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7524	 * already, but still need the state for the delayed optimization. To
7525	 * fix this:
7526	 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7527	 * - schedule that vblank worker _before_ calling hw_done
7528	 * - at the start of commit_tail, cancel it _synchrously
7529	 * - switch over to the vblank wait helper in the core after that since
7530	 *   we don't need out special handling any more.
7531	 */
7532	drm_atomic_helper_wait_for_flip_done(display->drm, &state->base);
7533
7534	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7535		if (new_crtc_state->do_async_flip)
7536			intel_crtc_disable_flip_done(state, crtc);
7537
7538		intel_atomic_dsb_wait_commit(new_crtc_state);
7539
7540		if (!state->base.legacy_cursor_update && !new_crtc_state->use_dsb)
7541			intel_vrr_check_push_sent(NULL, new_crtc_state);
7542
7543		if (new_crtc_state->use_flipq)
7544			intel_flipq_disable(new_crtc_state);
7545	}
7546
7547	/*
7548	 * Now that the vblank has passed, we can go ahead and program the
7549	 * optimal watermarks on platforms that need two-step watermark
7550	 * programming.
7551	 *
7552	 * TODO: Move this (and other cleanup) to an async worker eventually.
7553	 */
7554	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7555					    new_crtc_state, i) {
7556		/*
7557		 * Gen2 reports pipe underruns whenever all planes are disabled.
7558		 * So re-enable underrun reporting after some planes get enabled.
7559		 *
7560		 * We do this before .optimize_watermarks() so that we have a
7561		 * chance of catching underruns with the intermediate watermarks
7562		 * vs. the new plane configuration.
7563		 */
7564		if (DISPLAY_VER(display) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7565			intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true);
7566
7567		intel_optimize_watermarks(state, crtc);
7568	}
7569
7570	intel_dbuf_post_plane_update(state);
7571
7572	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7573		intel_post_plane_update(state, crtc);
7574
7575		intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7576
7577		intel_modeset_verify_crtc(state, crtc);
7578
7579		intel_post_plane_update_after_readout(state, crtc);
7580
7581		/*
7582		 * DSB cleanup is done in cleanup_work aligning with framebuffer
7583		 * cleanup. So copy and reset the dsb structure to sync with
7584		 * commit_done and later do dsb cleanup in cleanup_work.
7585		 *
7586		 * FIXME get rid of this funny new->old swapping
7587		 */
7588		old_crtc_state->dsb_color = fetch_and_zero(&new_crtc_state->dsb_color);
7589		old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit);
7590	}
7591
7592	/* Underruns don't always raise interrupts, so check manually */
7593	intel_check_cpu_fifo_underruns(display);
7594	intel_check_pch_fifo_underruns(display);
7595
7596	if (state->modeset)
7597		intel_verify_planes(state);
7598
7599	intel_sagv_post_plane_update(state);
7600	intel_set_cdclk_post_plane_update(state);
7601	intel_pmdemand_post_plane_update(state);
7602
7603	drm_atomic_helper_commit_hw_done(&state->base);
7604	intel_atomic_global_state_commit_done(state);
7605
7606	if (state->modeset) {
7607		/* As one of the primary mmio accessors, KMS has a high
7608		 * likelihood of triggering bugs in unclaimed access. After we
7609		 * finish modesetting, see if an error has been flagged, and if
7610		 * so enable debugging for the next modeset - and hope we catch
7611		 * the culprit.
7612		 */
7613		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7614	}
7615	/*
7616	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
7617	 * toggling overhead at and above 60 FPS.
7618	 */
7619	intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17);
7620	intel_display_rpm_put(display, state->wakeref);
7621
7622	/*
7623	 * Defer the cleanup of the old state to a separate worker to not
7624	 * impede the current task (userspace for blocking modesets) that
7625	 * are executed inline. For out-of-line asynchronous modesets/flips,
7626	 * deferring to a new worker seems overkill, but we would place a
7627	 * schedule point (cond_resched()) here anyway to keep latencies
7628	 * down.
7629	 */
7630	INIT_WORK(&state->cleanup_work, intel_atomic_cleanup_work);
7631	queue_work(display->wq.cleanup, &state->cleanup_work);
7632}
7633
7634static void intel_atomic_commit_work(struct work_struct *work)
7635{
7636	struct intel_atomic_state *state =
7637		container_of(work, struct intel_atomic_state, base.commit_work);
7638
7639	intel_atomic_commit_tail(state);
7640}
7641
7642static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7643{
7644	struct intel_plane_state *old_plane_state, *new_plane_state;
7645	struct intel_plane *plane;
7646	int i;
7647
7648	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7649					     new_plane_state, i)
7650		intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
7651					to_intel_frontbuffer(new_plane_state->hw.fb),
7652					plane->frontbuffer_bit);
7653}
7654
7655static int intel_atomic_setup_commit(struct intel_atomic_state *state, bool nonblock)
7656{
7657	int ret;
7658
7659	ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
7660	if (ret)
7661		return ret;
7662
7663	ret = intel_atomic_global_state_setup_commit(state);
7664	if (ret)
7665		return ret;
7666
7667	return 0;
7668}
7669
7670static int intel_atomic_swap_state(struct intel_atomic_state *state)
7671{
7672	int ret;
7673
7674	ret = drm_atomic_helper_swap_state(&state->base, true);
7675	if (ret)
7676		return ret;
7677
7678	intel_atomic_swap_global_state(state);
7679
7680	intel_dpll_swap_state(state);
7681
7682	intel_atomic_track_fbs(state);
7683
7684	return 0;
7685}
7686
7687int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
7688			bool nonblock)
7689{
7690	struct intel_display *display = to_intel_display(dev);
7691	struct intel_atomic_state *state = to_intel_atomic_state(_state);
7692	int ret = 0;
7693
7694	state->wakeref = intel_display_rpm_get(display);
7695
7696	/*
7697	 * The intel_legacy_cursor_update() fast path takes care
7698	 * of avoiding the vblank waits for simple cursor
7699	 * movement and flips. For cursor on/off and size changes,
7700	 * we want to perform the vblank waits so that watermark
7701	 * updates happen during the correct frames. Gen9+ have
7702	 * double buffered watermarks and so shouldn't need this.
7703	 *
7704	 * Unset state->legacy_cursor_update before the call to
7705	 * drm_atomic_helper_setup_commit() because otherwise
7706	 * drm_atomic_helper_wait_for_flip_done() is a noop and
7707	 * we get FIFO underruns because we didn't wait
7708	 * for vblank.
7709	 *
7710	 * FIXME doing watermarks and fb cleanup from a vblank worker
7711	 * (assuming we had any) would solve these problems.
7712	 */
7713	if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) {
7714		struct intel_crtc_state *new_crtc_state;
7715		struct intel_crtc *crtc;
7716		int i;
7717
7718		for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7719			if (new_crtc_state->wm.need_postvbl_update ||
7720			    new_crtc_state->update_wm_post)
7721				state->base.legacy_cursor_update = false;
7722	}
7723
7724	ret = intel_atomic_prepare_commit(state);
7725	if (ret) {
7726		drm_dbg_atomic(display->drm,
7727			       "Preparing state failed with %i\n", ret);
7728		intel_display_rpm_put(display, state->wakeref);
7729		return ret;
7730	}
7731
7732	ret = intel_atomic_setup_commit(state, nonblock);
7733	if (!ret)
7734		ret = intel_atomic_swap_state(state);
7735
7736	if (ret) {
7737		drm_atomic_helper_unprepare_planes(dev, &state->base);
7738		intel_display_rpm_put(display, state->wakeref);
7739		return ret;
7740	}
7741
7742	drm_atomic_state_get(&state->base);
7743	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7744
7745	if (nonblock && state->modeset) {
7746		queue_work(display->wq.modeset, &state->base.commit_work);
7747	} else if (nonblock) {
7748		queue_work(display->wq.flip, &state->base.commit_work);
7749	} else {
7750		if (state->modeset)
7751			flush_workqueue(display->wq.modeset);
7752		intel_atomic_commit_tail(state);
7753	}
7754
7755	return 0;
7756}
7757
7758static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7759{
7760	struct intel_display *display = to_intel_display(encoder);
7761	struct intel_encoder *source_encoder;
7762	u32 possible_clones = 0;
7763
7764	for_each_intel_encoder(display->drm, source_encoder) {
7765		if (encoders_cloneable(encoder, source_encoder))
7766			possible_clones |= drm_encoder_mask(&source_encoder->base);
7767	}
7768
7769	return possible_clones;
7770}
7771
7772static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7773{
7774	struct intel_display *display = to_intel_display(encoder);
7775	struct intel_crtc *crtc;
7776	u32 possible_crtcs = 0;
7777
7778	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, encoder->pipe_mask)
7779		possible_crtcs |= drm_crtc_mask(&crtc->base);
7780
7781	return possible_crtcs;
7782}
7783
7784static bool ilk_has_edp_a(struct intel_display *display)
7785{
7786	if (!display->platform.mobile)
7787		return false;
7788
7789	if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0)
7790		return false;
7791
7792	if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7793		return false;
7794
7795	return true;
7796}
7797
7798static bool intel_ddi_crt_present(struct intel_display *display)
7799{
7800	if (DISPLAY_VER(display) >= 9)
7801		return false;
7802
7803	if (display->platform.haswell_ult || display->platform.broadwell_ult)
7804		return false;
7805
7806	if (HAS_PCH_LPT_H(display) &&
7807	    intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7808		return false;
7809
7810	/* DDI E can't be used if DDI A requires 4 lanes */
7811	if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7812		return false;
7813
7814	if (!display->vbt.int_crt_support)
7815		return false;
7816
7817	return true;
7818}
7819
7820bool assert_port_valid(struct intel_display *display, enum port port)
7821{
7822	return !drm_WARN(display->drm, !(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)),
7823			 "Platform does not support port %c\n", port_name(port));
7824}
7825
7826void intel_setup_outputs(struct intel_display *display)
7827{
7828	struct intel_encoder *encoder;
7829	bool dpd_is_edp = false;
7830
7831	intel_pps_unlock_regs_wa(display);
7832
7833	if (!HAS_DISPLAY(display))
7834		return;
7835
7836	if (HAS_DDI(display)) {
7837		if (intel_ddi_crt_present(display))
7838			intel_crt_init(display);
7839
7840		intel_bios_for_each_encoder(display, intel_ddi_init);
7841
7842		if (display->platform.geminilake || display->platform.broxton)
7843			vlv_dsi_init(display);
7844	} else if (HAS_PCH_SPLIT(display)) {
7845		int found;
7846
7847		/*
7848		 * intel_edp_init_connector() depends on this completing first,
7849		 * to prevent the registration of both eDP and LVDS and the
7850		 * incorrect sharing of the PPS.
7851		 */
7852		intel_lvds_init(display);
7853		intel_crt_init(display);
7854
7855		dpd_is_edp = intel_dp_is_port_edp(display, PORT_D);
7856
7857		if (ilk_has_edp_a(display))
7858			g4x_dp_init(display, DP_A, PORT_A);
7859
7860		if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) {
7861			/* PCH SDVOB multiplex with HDMIB */
7862			found = intel_sdvo_init(display, PCH_SDVOB, PORT_B);
7863			if (!found)
7864				g4x_hdmi_init(display, PCH_HDMIB, PORT_B);
7865			if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED))
7866				g4x_dp_init(display, PCH_DP_B, PORT_B);
7867		}
7868
7869		if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED)
7870			g4x_hdmi_init(display, PCH_HDMIC, PORT_C);
7871
7872		if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED)
7873			g4x_hdmi_init(display, PCH_HDMID, PORT_D);
7874
7875		if (intel_de_read(display, PCH_DP_C) & DP_DETECTED)
7876			g4x_dp_init(display, PCH_DP_C, PORT_C);
7877
7878		if (intel_de_read(display, PCH_DP_D) & DP_DETECTED)
7879			g4x_dp_init(display, PCH_DP_D, PORT_D);
7880	} else if (display->platform.valleyview || display->platform.cherryview) {
7881		bool has_edp, has_port;
7882
7883		if (display->platform.valleyview && display->vbt.int_crt_support)
7884			intel_crt_init(display);
7885
7886		/*
7887		 * The DP_DETECTED bit is the latched state of the DDC
7888		 * SDA pin at boot. However since eDP doesn't require DDC
7889		 * (no way to plug in a DP->HDMI dongle) the DDC pins for
7890		 * eDP ports may have been muxed to an alternate function.
7891		 * Thus we can't rely on the DP_DETECTED bit alone to detect
7892		 * eDP ports. Consult the VBT as well as DP_DETECTED to
7893		 * detect eDP ports.
7894		 *
7895		 * Sadly the straps seem to be missing sometimes even for HDMI
7896		 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
7897		 * and VBT for the presence of the port. Additionally we can't
7898		 * trust the port type the VBT declares as we've seen at least
7899		 * HDMI ports that the VBT claim are DP or eDP.
7900		 */
7901		has_edp = intel_dp_is_port_edp(display, PORT_B);
7902		has_port = intel_bios_is_port_present(display, PORT_B);
7903		if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port)
7904			has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B);
7905		if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
7906			g4x_hdmi_init(display, VLV_HDMIB, PORT_B);
7907
7908		has_edp = intel_dp_is_port_edp(display, PORT_C);
7909		has_port = intel_bios_is_port_present(display, PORT_C);
7910		if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port)
7911			has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C);
7912		if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
7913			g4x_hdmi_init(display, VLV_HDMIC, PORT_C);
7914
7915		if (display->platform.cherryview) {
7916			/*
7917			 * eDP not supported on port D,
7918			 * so no need to worry about it
7919			 */
7920			has_port = intel_bios_is_port_present(display, PORT_D);
7921			if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port)
7922				g4x_dp_init(display, CHV_DP_D, PORT_D);
7923			if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port)
7924				g4x_hdmi_init(display, CHV_HDMID, PORT_D);
7925		}
7926
7927		vlv_dsi_init(display);
7928	} else if (display->platform.pineview) {
7929		intel_lvds_init(display);
7930		intel_crt_init(display);
7931	} else if (IS_DISPLAY_VER(display, 3, 4)) {
7932		bool found = false;
7933
7934		if (display->platform.mobile)
7935			intel_lvds_init(display);
7936
7937		intel_crt_init(display);
7938
7939		if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {
7940			drm_dbg_kms(display->drm, "probing SDVOB\n");
7941			found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B);
7942			if (!found && display->platform.g4x) {
7943				drm_dbg_kms(display->drm,
7944					    "probing HDMI on SDVOB\n");
7945				g4x_hdmi_init(display, GEN4_HDMIB, PORT_B);
7946			}
7947
7948			if (!found && display->platform.g4x)
7949				g4x_dp_init(display, DP_B, PORT_B);
7950		}
7951
7952		/* Before G4X SDVOC doesn't have its own detect register */
7953
7954		if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {
7955			drm_dbg_kms(display->drm, "probing SDVOC\n");
7956			found = intel_sdvo_init(display, GEN3_SDVOC, PORT_C);
7957		}
7958
7959		if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) {
7960
7961			if (display->platform.g4x) {
7962				drm_dbg_kms(display->drm,
7963					    "probing HDMI on SDVOC\n");
7964				g4x_hdmi_init(display, GEN4_HDMIC, PORT_C);
7965			}
7966			if (display->platform.g4x)
7967				g4x_dp_init(display, DP_C, PORT_C);
7968		}
7969
7970		if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED))
7971			g4x_dp_init(display, DP_D, PORT_D);
7972
7973		if (SUPPORTS_TV(display))
7974			intel_tv_init(display);
7975	} else if (DISPLAY_VER(display) == 2) {
7976		if (display->platform.i85x)
7977			intel_lvds_init(display);
7978
7979		intel_crt_init(display);
7980		intel_dvo_init(display);
7981	}
7982
7983	for_each_intel_encoder(display->drm, encoder) {
7984		encoder->base.possible_crtcs =
7985			intel_encoder_possible_crtcs(encoder);
7986		encoder->base.possible_clones =
7987			intel_encoder_possible_clones(encoder);
7988	}
7989
7990	intel_init_pch_refclk(display);
7991
7992	drm_helper_move_panel_connectors_to_head(display->drm);
7993}
7994
7995static int max_dotclock(struct intel_display *display)
7996{
7997	int max_dotclock = display->cdclk.max_dotclk_freq;
7998
7999	if (HAS_ULTRAJOINER(display))
8000		max_dotclock *= 4;
8001	else if (HAS_UNCOMPRESSED_JOINER(display) || HAS_BIGJOINER(display))
8002		max_dotclock *= 2;
8003
8004	return max_dotclock;
8005}
8006
8007enum drm_mode_status intel_mode_valid(struct drm_device *dev,
8008				      const struct drm_display_mode *mode)
8009{
8010	struct intel_display *display = to_intel_display(dev);
8011	int hdisplay_max, htotal_max;
8012	int vdisplay_max, vtotal_max;
8013
8014	/*
8015	 * Can't reject DBLSCAN here because Xorg ddxen can add piles
8016	 * of DBLSCAN modes to the output's mode list when they detect
8017	 * the scaling mode property on the connector. And they don't
8018	 * ask the kernel to validate those modes in any way until
8019	 * modeset time at which point the client gets a protocol error.
8020	 * So in order to not upset those clients we silently ignore the
8021	 * DBLSCAN flag on such connectors. For other connectors we will
8022	 * reject modes with the DBLSCAN flag in encoder->compute_config().
8023	 * And we always reject DBLSCAN modes in connector->mode_valid()
8024	 * as we never want such modes on the connector's mode list.
8025	 */
8026
8027	if (mode->vscan > 1)
8028		return MODE_NO_VSCAN;
8029
8030	if (mode->flags & DRM_MODE_FLAG_HSKEW)
8031		return MODE_H_ILLEGAL;
8032
8033	if (mode->flags & (DRM_MODE_FLAG_CSYNC |
8034			   DRM_MODE_FLAG_NCSYNC |
8035			   DRM_MODE_FLAG_PCSYNC))
8036		return MODE_HSYNC;
8037
8038	if (mode->flags & (DRM_MODE_FLAG_BCAST |
8039			   DRM_MODE_FLAG_PIXMUX |
8040			   DRM_MODE_FLAG_CLKDIV2))
8041		return MODE_BAD;
8042
8043	/*
8044	 * Reject clearly excessive dotclocks early to
8045	 * avoid having to worry about huge integers later.
8046	 */
8047	if (mode->clock > max_dotclock(display))
8048		return MODE_CLOCK_HIGH;
8049
8050	/* Transcoder timing limits */
8051	if (DISPLAY_VER(display) >= 11) {
8052		hdisplay_max = 16384;
8053		vdisplay_max = 8192;
8054		htotal_max = 16384;
8055		vtotal_max = 8192;
8056	} else if (DISPLAY_VER(display) >= 9 ||
8057		   display->platform.broadwell || display->platform.haswell) {
8058		hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
8059		vdisplay_max = 4096;
8060		htotal_max = 8192;
8061		vtotal_max = 8192;
8062	} else if (DISPLAY_VER(display) >= 3) {
8063		hdisplay_max = 4096;
8064		vdisplay_max = 4096;
8065		htotal_max = 8192;
8066		vtotal_max = 8192;
8067	} else {
8068		hdisplay_max = 2048;
8069		vdisplay_max = 2048;
8070		htotal_max = 4096;
8071		vtotal_max = 4096;
8072	}
8073
8074	if (mode->hdisplay > hdisplay_max ||
8075	    mode->hsync_start > htotal_max ||
8076	    mode->hsync_end > htotal_max ||
8077	    mode->htotal > htotal_max)
8078		return MODE_H_ILLEGAL;
8079
8080	if (mode->vdisplay > vdisplay_max ||
8081	    mode->vsync_start > vtotal_max ||
8082	    mode->vsync_end > vtotal_max ||
8083	    mode->vtotal > vtotal_max)
8084		return MODE_V_ILLEGAL;
8085
8086	/*
8087	 * WM_LINETIME only goes up to (almost) 64 usec, and also
8088	 * knowing that the linetime is always bounded will ease the
8089	 * mind during various calculations.
8090	 */
8091	if (DIV_ROUND_UP(mode->htotal * 1000, mode->clock) > 64)
8092		return MODE_H_ILLEGAL;
8093
8094	return MODE_OK;
8095}
8096
8097enum drm_mode_status intel_cpu_transcoder_mode_valid(struct intel_display *display,
8098						     const struct drm_display_mode *mode)
8099{
8100	/*
8101	 * Additional transcoder timing limits,
8102	 * excluding BXT/GLK DSI transcoders.
8103	 */
8104	if (DISPLAY_VER(display) >= 5) {
8105		if (mode->hdisplay < 64 ||
8106		    mode->htotal - mode->hdisplay < 32)
8107			return MODE_H_ILLEGAL;
8108
8109		if (mode->vtotal - mode->vdisplay < 5)
8110			return MODE_V_ILLEGAL;
8111	} else {
8112		if (mode->htotal - mode->hdisplay < 32)
8113			return MODE_H_ILLEGAL;
8114
8115		if (mode->vtotal - mode->vdisplay < 3)
8116			return MODE_V_ILLEGAL;
8117	}
8118
8119	/*
8120	 * Cantiga+ cannot handle modes with a hsync front porch of 0.
8121	 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8122	 */
8123	if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) &&
8124	    mode->hsync_start == mode->hdisplay)
8125		return MODE_H_ILLEGAL;
8126
8127	return MODE_OK;
8128}
8129
8130enum drm_mode_status
8131intel_mode_valid_max_plane_size(struct intel_display *display,
8132				const struct drm_display_mode *mode,
8133				int num_joined_pipes)
8134{
8135	int plane_width_max, plane_height_max;
8136
8137	/*
8138	 * intel_mode_valid() should be
8139	 * sufficient on older platforms.
8140	 */
8141	if (DISPLAY_VER(display) < 9)
8142		return MODE_OK;
8143
8144	/*
8145	 * Most people will probably want a fullscreen
8146	 * plane so let's not advertize modes that are
8147	 * too big for that.
8148	 */
8149	if (DISPLAY_VER(display) >= 30) {
8150		plane_width_max = 6144 * num_joined_pipes;
8151		plane_height_max = 4800;
8152	} else if (DISPLAY_VER(display) >= 11) {
8153		plane_width_max = 5120 * num_joined_pipes;
8154		plane_height_max = 4320;
8155	} else {
8156		plane_width_max = 5120;
8157		plane_height_max = 4096;
8158	}
8159
8160	if (mode->hdisplay > plane_width_max)
8161		return MODE_H_ILLEGAL;
8162
8163	if (mode->vdisplay > plane_height_max)
8164		return MODE_V_ILLEGAL;
8165
8166	return MODE_OK;
8167}
8168
8169static const struct intel_display_funcs skl_display_funcs = {
8170	.get_pipe_config = hsw_get_pipe_config,
8171	.crtc_enable = hsw_crtc_enable,
8172	.crtc_disable = hsw_crtc_disable,
8173	.commit_modeset_enables = skl_commit_modeset_enables,
8174	.get_initial_plane_config = skl_get_initial_plane_config,
8175	.fixup_initial_plane_config = skl_fixup_initial_plane_config,
8176};
8177
8178static const struct intel_display_funcs ddi_display_funcs = {
8179	.get_pipe_config = hsw_get_pipe_config,
8180	.crtc_enable = hsw_crtc_enable,
8181	.crtc_disable = hsw_crtc_disable,
8182	.commit_modeset_enables = intel_commit_modeset_enables,
8183	.get_initial_plane_config = i9xx_get_initial_plane_config,
8184	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8185};
8186
8187static const struct intel_display_funcs pch_split_display_funcs = {
8188	.get_pipe_config = ilk_get_pipe_config,
8189	.crtc_enable = ilk_crtc_enable,
8190	.crtc_disable = ilk_crtc_disable,
8191	.commit_modeset_enables = intel_commit_modeset_enables,
8192	.get_initial_plane_config = i9xx_get_initial_plane_config,
8193	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8194};
8195
8196static const struct intel_display_funcs vlv_display_funcs = {
8197	.get_pipe_config = i9xx_get_pipe_config,
8198	.crtc_enable = valleyview_crtc_enable,
8199	.crtc_disable = i9xx_crtc_disable,
8200	.commit_modeset_enables = intel_commit_modeset_enables,
8201	.get_initial_plane_config = i9xx_get_initial_plane_config,
8202	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8203};
8204
8205static const struct intel_display_funcs i9xx_display_funcs = {
8206	.get_pipe_config = i9xx_get_pipe_config,
8207	.crtc_enable = i9xx_crtc_enable,
8208	.crtc_disable = i9xx_crtc_disable,
8209	.commit_modeset_enables = intel_commit_modeset_enables,
8210	.get_initial_plane_config = i9xx_get_initial_plane_config,
8211	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8212};
8213
8214/**
8215 * intel_init_display_hooks - initialize the display modesetting hooks
8216 * @display: display device private
8217 */
8218void intel_init_display_hooks(struct intel_display *display)
8219{
8220	if (DISPLAY_VER(display) >= 9) {
8221		display->funcs.display = &skl_display_funcs;
8222	} else if (HAS_DDI(display)) {
8223		display->funcs.display = &ddi_display_funcs;
8224	} else if (HAS_PCH_SPLIT(display)) {
8225		display->funcs.display = &pch_split_display_funcs;
8226	} else if (display->platform.cherryview ||
8227		   display->platform.valleyview) {
8228		display->funcs.display = &vlv_display_funcs;
8229	} else {
8230		display->funcs.display = &i9xx_display_funcs;
8231	}
8232}
8233
8234int intel_initial_commit(struct intel_display *display)
8235{
8236	struct drm_atomic_state *state = NULL;
8237	struct drm_modeset_acquire_ctx ctx;
8238	struct intel_crtc *crtc;
8239	int ret = 0;
8240
8241	state = drm_atomic_state_alloc(display->drm);
8242	if (!state)
8243		return -ENOMEM;
8244
8245	drm_modeset_acquire_init(&ctx, 0);
8246
8247	state->acquire_ctx = &ctx;
8248	to_intel_atomic_state(state)->internal = true;
8249
8250retry:
8251	for_each_intel_crtc(display->drm, crtc) {
8252		struct intel_crtc_state *crtc_state =
8253			intel_atomic_get_crtc_state(state, crtc);
8254
8255		if (IS_ERR(crtc_state)) {
8256			ret = PTR_ERR(crtc_state);
8257			goto out;
8258		}
8259
8260		if (!crtc_state->hw.active)
8261			crtc_state->inherited = false;
8262
8263		if (crtc_state->hw.active) {
8264			struct intel_encoder *encoder;
8265
8266			ret = drm_atomic_add_affected_planes(state, &crtc->base);
8267			if (ret)
8268				goto out;
8269
8270			/*
8271			 * FIXME hack to force a LUT update to avoid the
8272			 * plane update forcing the pipe gamma on without
8273			 * having a proper LUT loaded. Remove once we
8274			 * have readout for pipe gamma enable.
8275			 */
8276			crtc_state->uapi.color_mgmt_changed = true;
8277
8278			for_each_intel_encoder_mask(display->drm, encoder,
8279						    crtc_state->uapi.encoder_mask) {
8280				if (encoder->initial_fastset_check &&
8281				    !encoder->initial_fastset_check(encoder, crtc_state)) {
8282					ret = drm_atomic_add_affected_connectors(state,
8283										 &crtc->base);
8284					if (ret)
8285						goto out;
8286				}
8287			}
8288		}
8289	}
8290
8291	ret = drm_atomic_commit(state);
8292
8293out:
8294	if (ret == -EDEADLK) {
8295		drm_atomic_state_clear(state);
8296		drm_modeset_backoff(&ctx);
8297		goto retry;
8298	}
8299
8300	drm_atomic_state_put(state);
8301
8302	drm_modeset_drop_locks(&ctx);
8303	drm_modeset_acquire_fini(&ctx);
8304
8305	return ret;
8306}
8307
8308void i830_enable_pipe(struct intel_display *display, enum pipe pipe)
8309{
8310	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
8311	enum transcoder cpu_transcoder = (enum transcoder)pipe;
8312	/* 640x480@60Hz, ~25175 kHz */
8313	struct dpll clock = {
8314		.m1 = 18,
8315		.m2 = 7,
8316		.p1 = 13,
8317		.p2 = 4,
8318		.n = 2,
8319	};
8320	u32 dpll, fp;
8321	int i;
8322
8323	drm_WARN_ON(display->drm,
8324		    i9xx_calc_dpll_params(48000, &clock) != 25154);
8325
8326	drm_dbg_kms(display->drm,
8327		    "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
8328		    pipe_name(pipe), clock.vco, clock.dot);
8329
8330	fp = i9xx_dpll_compute_fp(&clock);
8331	dpll = DPLL_DVO_2X_MODE |
8332		DPLL_VGA_MODE_DIS |
8333		((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
8334		PLL_P2_DIVIDE_BY_4 |
8335		PLL_REF_INPUT_DREFCLK |
8336		DPLL_VCO_ENABLE;
8337
8338	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
8339		       HACTIVE(640 - 1) | HTOTAL(800 - 1));
8340	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
8341		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
8342	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
8343		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
8344	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
8345		       VACTIVE(480 - 1) | VTOTAL(525 - 1));
8346	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
8347		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
8348	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
8349		       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
8350	intel_de_write(display, PIPESRC(display, pipe),
8351		       PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
8352
8353	intel_de_write(display, FP0(pipe), fp);
8354	intel_de_write(display, FP1(pipe), fp);
8355
8356	/*
8357	 * Apparently we need to have VGA mode enabled prior to changing
8358	 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8359	 * dividers, even though the register value does change.
8360	 */
8361	intel_de_write(display, DPLL(display, pipe),
8362		       dpll & ~DPLL_VGA_MODE_DIS);
8363	intel_de_write(display, DPLL(display, pipe), dpll);
8364
8365	/* Wait for the clocks to stabilize. */
8366	intel_de_posting_read(display, DPLL(display, pipe));
8367	udelay(150);
8368
8369	/* The pixel multiplier can only be updated once the
8370	 * DPLL is enabled and the clocks are stable.
8371	 *
8372	 * So write it again.
8373	 */
8374	intel_de_write(display, DPLL(display, pipe), dpll);
8375
8376	/* We do this three times for luck */
8377	for (i = 0; i < 3 ; i++) {
8378		intel_de_write(display, DPLL(display, pipe), dpll);
8379		intel_de_posting_read(display, DPLL(display, pipe));
8380		udelay(150); /* wait for warmup */
8381	}
8382
8383	intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE);
8384	intel_de_posting_read(display, TRANSCONF(display, pipe));
8385
8386	intel_wait_for_pipe_scanline_moving(crtc);
8387}
8388
8389void i830_disable_pipe(struct intel_display *display, enum pipe pipe)
8390{
8391	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
8392
8393	drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n",
8394		    pipe_name(pipe));
8395
8396	drm_WARN_ON(display->drm,
8397		    intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE);
8398	drm_WARN_ON(display->drm,
8399		    intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE);
8400	drm_WARN_ON(display->drm,
8401		    intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE);
8402	drm_WARN_ON(display->drm,
8403		    intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK);
8404	drm_WARN_ON(display->drm,
8405		    intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK);
8406
8407	intel_de_write(display, TRANSCONF(display, pipe), 0);
8408	intel_de_posting_read(display, TRANSCONF(display, pipe));
8409
8410	intel_wait_for_pipe_scanline_stopped(crtc);
8411
8412	intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);
8413	intel_de_posting_read(display, DPLL(display, pipe));
8414}
8415
8416bool intel_scanout_needs_vtd_wa(struct intel_display *display)
8417{
8418	return IS_DISPLAY_VER(display, 6, 11) && intel_display_vtd_active(display);
8419}