intel_de.h

  1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2019 Intel Corporation
  4 */
  5
  6#ifndef __INTEL_DE_H__
  7#define __INTEL_DE_H__
  8
  9#include "intel_display_core.h"
 10#include "intel_dmc_wl.h"
 11#include "intel_dsb.h"
 12#include "intel_uncore.h"
 13#include "intel_uncore_trace.h"
 14
 15static inline struct intel_uncore *__to_uncore(struct intel_display *display)
 16{
 17	return to_intel_uncore(display->drm);
 18}
 19
 20static inline u32
 21intel_de_read(struct intel_display *display, i915_reg_t reg)
 22{
 23	u32 val;
 24
 25	intel_dmc_wl_get(display, reg);
 26
 27	val = intel_uncore_read(__to_uncore(display), reg);
 28
 29	intel_dmc_wl_put(display, reg);
 30
 31	return val;
 32}
 33
 34static inline u8
 35intel_de_read8(struct intel_display *display, i915_reg_t reg)
 36{
 37	u8 val;
 38
 39	intel_dmc_wl_get(display, reg);
 40
 41	val = intel_uncore_read8(__to_uncore(display), reg);
 42
 43	intel_dmc_wl_put(display, reg);
 44
 45	return val;
 46}
 47
 48static inline u64
 49intel_de_read64_2x32(struct intel_display *display,
 50		     i915_reg_t lower_reg, i915_reg_t upper_reg)
 51{
 52	u64 val;
 53
 54	intel_dmc_wl_get(display, lower_reg);
 55	intel_dmc_wl_get(display, upper_reg);
 56
 57	val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg,
 58				       upper_reg);
 59
 60	intel_dmc_wl_put(display, upper_reg);
 61	intel_dmc_wl_put(display, lower_reg);
 62
 63	return val;
 64}
 65
 66static inline void
 67intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
 68{
 69	intel_dmc_wl_get(display, reg);
 70
 71	intel_uncore_posting_read(__to_uncore(display), reg);
 72
 73	intel_dmc_wl_put(display, reg);
 74}
 75
 76static inline void
 77intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
 78{
 79	intel_dmc_wl_get(display, reg);
 80
 81	intel_uncore_write(__to_uncore(display), reg, val);
 82
 83	intel_dmc_wl_put(display, reg);
 84}
 85
 86static inline u32
 87intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
 88{
 89	u32 val;
 90
 91	intel_dmc_wl_get(display, reg);
 92
 93	val = intel_uncore_rmw(__to_uncore(display), reg, clear, set);
 94
 95	intel_dmc_wl_put(display, reg);
 96
 97	return val;
 98}
 99
100static inline int
101intel_de_wait_us(struct intel_display *display, i915_reg_t reg,
102		 u32 mask, u32 value, unsigned int timeout_us,
103		 u32 *out_value)
104{
105	int ret;
106
107	intel_dmc_wl_get(display, reg);
108
109	ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
110					value, timeout_us, 0, out_value);
111
112	intel_dmc_wl_put(display, reg);
113
114	return ret;
115}
116
117static inline int
118intel_de_wait_ms(struct intel_display *display, i915_reg_t reg,
119		 u32 mask, u32 value, unsigned int timeout_ms,
120		 u32 *out_value)
121{
122	int ret;
123
124	intel_dmc_wl_get(display, reg);
125
126	ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
127					value, 2, timeout_ms, out_value);
128
129	intel_dmc_wl_put(display, reg);
130
131	return ret;
132}
133
134static inline int
135intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg,
136		    u32 mask, u32 value, unsigned int timeout_ms,
137		    u32 *out_value)
138{
139	return __intel_wait_for_register_fw(__to_uncore(display), reg, mask,
140					    value, 2, timeout_ms, out_value);
141}
142
143static inline int
144intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg,
145			   u32 mask, u32 value, unsigned int timeout_us,
146			   u32 *out_value)
147{
148	return __intel_wait_for_register_fw(__to_uncore(display), reg, mask,
149					    value, timeout_us, 0, out_value);
150}
151
152static inline int
153intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg,
154			 u32 mask, unsigned int timeout_us)
155{
156	return intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL);
157}
158
159static inline int
160intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg,
161			   u32 mask, unsigned int timeout_us)
162{
163	return intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL);
164}
165
166static inline int
167intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg,
168			 u32 mask, unsigned int timeout_ms)
169{
170	return intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL);
171}
172
173static inline int
174intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg,
175			   u32 mask, unsigned int timeout_ms)
176{
177	return intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL);
178}
179
180/*
181 * Unlocked mmio-accessors, think carefully before using these.
182 *
183 * Certain architectures will die if the same cacheline is concurrently accessed
184 * by different clients (e.g. on Ivybridge). Access to registers should
185 * therefore generally be serialised, by either the dev_priv->uncore.lock or
186 * a more localised lock guarding all access to that bank of registers.
187 */
188static inline u32
189intel_de_read_fw(struct intel_display *display, i915_reg_t reg)
190{
191	u32 val;
192
193	val = intel_uncore_read_fw(__to_uncore(display), reg);
194	trace_i915_reg_rw(false, reg, val, sizeof(val), true);
195
196	return val;
197}
198
199static inline void
200intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)
201{
202	trace_i915_reg_rw(true, reg, val, sizeof(val), true);
203	intel_uncore_write_fw(__to_uncore(display), reg, val);
204}
205
206static inline u32
207intel_de_rmw_fw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set)
208{
209	u32 old, val;
210
211	old = intel_de_read_fw(display, reg);
212	val = (old & ~clear) | set;
213	intel_de_write_fw(display, reg, val);
214
215	return old;
216}
217
218static inline u32
219intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
220{
221	return intel_uncore_read_notrace(__to_uncore(display), reg);
222}
223
224static inline void
225intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)
226{
227	intel_uncore_write_notrace(__to_uncore(display), reg, val);
228}
229
230static __always_inline void
231intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,
232		   i915_reg_t reg, u32 val)
233{
234	if (dsb)
235		intel_dsb_reg_write(dsb, reg, val);
236	else
237		intel_de_write_fw(display, reg, val);
238}
239
240#endif /* __INTEL_DE_H__ */