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intel_color_pipeline.c

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linux-6.19.14/drivers/gpu/drm/i915/display/intel_color_pipeline.c C
  1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright © 2025 Intel Corporation
  4 */
  5#include "intel_color.h"
  6#include "intel_colorop.h"
  7#include "intel_color_pipeline.h"
  8#include "intel_de.h"
  9#include "intel_display_types.h"
 10#include "skl_universal_plane.h"
 11
 12#define MAX_COLOR_PIPELINES 1
 13#define PLANE_DEGAMMA_SIZE 128
 14#define PLANE_GAMMA_SIZE 32
 15
 16static
 17int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_enum_list *list,
 18				     enum pipe pipe)
 19{
 20	struct drm_device *dev = plane->dev;
 21	struct intel_display *display = to_intel_display(dev);
 22	struct drm_colorop *prev_op;
 23	struct intel_colorop *colorop;
 24	int ret;
 25
 26	colorop = intel_colorop_create(INTEL_PLANE_CB_PRE_CSC_LUT);
 27
 28	ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
 29						  PLANE_DEGAMMA_SIZE,
 30						  DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
 31						  DRM_COLOROP_FLAG_ALLOW_BYPASS);
 32
 33	if (ret)
 34		return ret;
 35
 36	list->type = colorop->base.base.id;
 37
 38	/* TODO: handle failures and clean up */
 39	prev_op = &colorop->base;
 40
 41	colorop = intel_colorop_create(INTEL_PLANE_CB_CSC);
 42	ret = drm_plane_colorop_ctm_3x4_init(dev, &colorop->base, plane,
 43					     DRM_COLOROP_FLAG_ALLOW_BYPASS);
 44	if (ret)
 45		return ret;
 46
 47	drm_colorop_set_next_property(prev_op, &colorop->base);
 48	prev_op = &colorop->base;
 49
 50	if (DISPLAY_VER(display) >= 35 &&
 51	    intel_color_crtc_has_3dlut(display, pipe) &&
 52	    plane->type == DRM_PLANE_TYPE_PRIMARY) {
 53		colorop = intel_colorop_create(INTEL_PLANE_CB_3DLUT);
 54
 55		ret = drm_plane_colorop_3dlut_init(dev, &colorop->base, plane, 17,
 56						   DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL,
 57						   true);
 58		if (ret)
 59			return ret;
 60
 61		drm_colorop_set_next_property(prev_op, &colorop->base);
 62
 63		prev_op = &colorop->base;
 64	}
 65
 66	colorop = intel_colorop_create(INTEL_PLANE_CB_POST_CSC_LUT);
 67	ret = drm_plane_colorop_curve_1d_lut_init(dev, &colorop->base, plane,
 68						  PLANE_GAMMA_SIZE,
 69						  DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
 70						  DRM_COLOROP_FLAG_ALLOW_BYPASS);
 71	if (ret)
 72		return ret;
 73
 74	drm_colorop_set_next_property(prev_op, &colorop->base);
 75
 76	list->name = kasprintf(GFP_KERNEL, "Color Pipeline %d", list->type);
 77
 78	return 0;
 79}
 80
 81int intel_color_pipeline_plane_init(struct drm_plane *plane, enum pipe pipe)
 82{
 83	struct drm_device *dev = plane->dev;
 84	struct intel_display *display = to_intel_display(dev);
 85	struct drm_prop_enum_list pipelines[MAX_COLOR_PIPELINES] = {};
 86	int len = 0;
 87	int ret = 0;
 88	int i;
 89
 90	/* Currently expose pipeline only for HDR planes */
 91	if (!icl_is_hdr_plane(display, to_intel_plane(plane)->id))
 92		return 0;
 93
 94	/* Add pipeline consisting of transfer functions */
 95	ret = _intel_color_pipeline_plane_init(plane, &pipelines[len], pipe);
 96	if (ret)
 97		goto out;
 98	len++;
 99
100	ret = drm_plane_create_color_pipeline_property(plane, pipelines, len);
101
102	for (i = 0; i < len; i++)
103		kfree(pipelines[i].name);
104
105out:
106	return ret;
107}
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