intel_audio.c

   1/*
   2 * Copyright © 2014 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21 * DEALINGS IN THE SOFTWARE.
  22 */
  23
  24#include <linux/component.h>
  25#include <linux/kernel.h>
  26
  27#include <drm/drm_edid.h>
  28#include <drm/drm_eld.h>
  29#include <drm/drm_fixed.h>
  30#include <drm/drm_print.h>
  31#include <drm/intel/i915_component.h>
  32
  33#include "intel_atomic.h"
  34#include "intel_audio.h"
  35#include "intel_audio_regs.h"
  36#include "intel_cdclk.h"
  37#include "intel_crtc.h"
  38#include "intel_de.h"
  39#include "intel_display_types.h"
  40#include "intel_lpe_audio.h"
  41
  42/**
  43 * DOC: High Definition Audio over HDMI and Display Port
  44 *
  45 * The graphics and audio drivers together support High Definition Audio over
  46 * HDMI and Display Port. The audio programming sequences are divided into audio
  47 * codec and controller enable and disable sequences. The graphics driver
  48 * handles the audio codec sequences, while the audio driver handles the audio
  49 * controller sequences.
  50 *
  51 * The disable sequences must be performed before disabling the transcoder or
  52 * port. The enable sequences may only be performed after enabling the
  53 * transcoder and port, and after completed link training. Therefore the audio
  54 * enable/disable sequences are part of the modeset sequence.
  55 *
  56 * The codec and controller sequences could be done either parallel or serial,
  57 * but generally the ELDV/PD change in the codec sequence indicates to the audio
  58 * driver that the controller sequence should start. Indeed, most of the
  59 * co-operation between the graphics and audio drivers is handled via audio
  60 * related registers. (The notable exception is the power management, not
  61 * covered here.)
  62 *
  63 * The struct &i915_audio_component is used to interact between the graphics
  64 * and audio drivers. The struct &i915_audio_component_ops @ops in it is
  65 * defined in graphics driver and called in audio driver. The
  66 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
  67 */
  68
  69struct intel_audio_funcs {
  70	void (*audio_codec_enable)(struct intel_encoder *encoder,
  71				   const struct intel_crtc_state *crtc_state,
  72				   const struct drm_connector_state *conn_state);
  73	void (*audio_codec_disable)(struct intel_encoder *encoder,
  74				    const struct intel_crtc_state *old_crtc_state,
  75				    const struct drm_connector_state *old_conn_state);
  76	void (*audio_codec_get_config)(struct intel_encoder *encoder,
  77				       struct intel_crtc_state *crtc_state);
  78};
  79
  80struct hdmi_aud_ncts {
  81	int sample_rate;
  82	int clock;
  83	int n;
  84	int cts;
  85};
  86
  87static const struct {
  88	int clock;
  89	u32 config;
  90} hdmi_audio_clock[] = {
  91	{ 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
  92	{ 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
  93	{ 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
  94	{ 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
  95	{ 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
  96	{ 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
  97	{ 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
  98	{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
  99	{ 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
 100	{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
 101	{ 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 },
 102	{ 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 },
 103	{ 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 },
 104	{ 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 },
 105};
 106
 107/* HDMI N/CTS table */
 108#define TMDS_297M 297000
 109#define TMDS_296M 296703
 110#define TMDS_594M 594000
 111#define TMDS_593M 593407
 112
 113static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = {
 114	{ 32000, TMDS_296M, 5824, 421875 },
 115	{ 32000, TMDS_297M, 3072, 222750 },
 116	{ 32000, TMDS_593M, 5824, 843750 },
 117	{ 32000, TMDS_594M, 3072, 445500 },
 118	{ 44100, TMDS_296M, 4459, 234375 },
 119	{ 44100, TMDS_297M, 4704, 247500 },
 120	{ 44100, TMDS_593M, 8918, 937500 },
 121	{ 44100, TMDS_594M, 9408, 990000 },
 122	{ 88200, TMDS_296M, 8918, 234375 },
 123	{ 88200, TMDS_297M, 9408, 247500 },
 124	{ 88200, TMDS_593M, 17836, 937500 },
 125	{ 88200, TMDS_594M, 18816, 990000 },
 126	{ 176400, TMDS_296M, 17836, 234375 },
 127	{ 176400, TMDS_297M, 18816, 247500 },
 128	{ 176400, TMDS_593M, 35672, 937500 },
 129	{ 176400, TMDS_594M, 37632, 990000 },
 130	{ 48000, TMDS_296M, 5824, 281250 },
 131	{ 48000, TMDS_297M, 5120, 247500 },
 132	{ 48000, TMDS_593M, 5824, 562500 },
 133	{ 48000, TMDS_594M, 6144, 594000 },
 134	{ 96000, TMDS_296M, 11648, 281250 },
 135	{ 96000, TMDS_297M, 10240, 247500 },
 136	{ 96000, TMDS_593M, 11648, 562500 },
 137	{ 96000, TMDS_594M, 12288, 594000 },
 138	{ 192000, TMDS_296M, 23296, 281250 },
 139	{ 192000, TMDS_297M, 20480, 247500 },
 140	{ 192000, TMDS_593M, 23296, 562500 },
 141	{ 192000, TMDS_594M, 24576, 594000 },
 142};
 143
 144/* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
 145/* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
 146#define TMDS_371M 371250
 147#define TMDS_370M 370878
 148
 149static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = {
 150	{ 32000, TMDS_370M, 5824, 527344 },
 151	{ 32000, TMDS_371M, 6144, 556875 },
 152	{ 44100, TMDS_370M, 8918, 585938 },
 153	{ 44100, TMDS_371M, 4704, 309375 },
 154	{ 88200, TMDS_370M, 17836, 585938 },
 155	{ 88200, TMDS_371M, 9408, 309375 },
 156	{ 176400, TMDS_370M, 35672, 585938 },
 157	{ 176400, TMDS_371M, 18816, 309375 },
 158	{ 48000, TMDS_370M, 11648, 703125 },
 159	{ 48000, TMDS_371M, 5120, 309375 },
 160	{ 96000, TMDS_370M, 23296, 703125 },
 161	{ 96000, TMDS_371M, 10240, 309375 },
 162	{ 192000, TMDS_370M, 46592, 703125 },
 163	{ 192000, TMDS_371M, 20480, 309375 },
 164};
 165
 166/* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
 167#define TMDS_445_5M 445500
 168#define TMDS_445M 445054
 169
 170static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
 171	{ 32000, TMDS_445M, 5824, 632813 },
 172	{ 32000, TMDS_445_5M, 4096, 445500 },
 173	{ 44100, TMDS_445M, 8918, 703125 },
 174	{ 44100, TMDS_445_5M, 4704, 371250 },
 175	{ 88200, TMDS_445M, 17836, 703125 },
 176	{ 88200, TMDS_445_5M, 9408, 371250 },
 177	{ 176400, TMDS_445M, 35672, 703125 },
 178	{ 176400, TMDS_445_5M, 18816, 371250 },
 179	{ 48000, TMDS_445M, 5824, 421875 },
 180	{ 48000, TMDS_445_5M, 5120, 371250 },
 181	{ 96000, TMDS_445M, 11648, 421875 },
 182	{ 96000, TMDS_445_5M, 10240, 371250 },
 183	{ 192000, TMDS_445M, 23296, 421875 },
 184	{ 192000, TMDS_445_5M, 20480, 371250 },
 185};
 186
 187/*
 188 * WA_14020863754: Implement Audio Workaround
 189 * Corner case with Min Hblank Fix can cause audio hang
 190 */
 191static bool needs_wa_14020863754(struct intel_display *display)
 192{
 193	return DISPLAY_VERx100(display) == 3000 ||
 194		DISPLAY_VERx100(display) == 2000 ||
 195		DISPLAY_VERx100(display) == 1401;
 196}
 197
 198/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
 199static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
 200{
 201	struct intel_display *display = to_intel_display(crtc_state);
 202	const struct drm_display_mode *adjusted_mode =
 203		&crtc_state->hw.adjusted_mode;
 204	int i;
 205
 206	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
 207		if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
 208			break;
 209	}
 210
 211	if (DISPLAY_VER(display) < 12 && adjusted_mode->crtc_clock > 148500)
 212		i = ARRAY_SIZE(hdmi_audio_clock);
 213
 214	if (i == ARRAY_SIZE(hdmi_audio_clock)) {
 215		drm_dbg_kms(display->drm,
 216			    "HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
 217			    adjusted_mode->crtc_clock);
 218		i = 1;
 219	}
 220
 221	drm_dbg_kms(display->drm,
 222		    "Configuring HDMI audio for pixel clock %d (0x%08x)\n",
 223		    hdmi_audio_clock[i].clock,
 224		    hdmi_audio_clock[i].config);
 225
 226	return hdmi_audio_clock[i].config;
 227}
 228
 229static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
 230				   int rate)
 231{
 232	const struct hdmi_aud_ncts *hdmi_ncts_table;
 233	int i, size;
 234
 235	if (crtc_state->pipe_bpp == 36) {
 236		hdmi_ncts_table = hdmi_aud_ncts_36bpp;
 237		size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
 238	} else if (crtc_state->pipe_bpp == 30) {
 239		hdmi_ncts_table = hdmi_aud_ncts_30bpp;
 240		size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
 241	} else {
 242		hdmi_ncts_table = hdmi_aud_ncts_24bpp;
 243		size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
 244	}
 245
 246	for (i = 0; i < size; i++) {
 247		if (rate == hdmi_ncts_table[i].sample_rate &&
 248		    crtc_state->port_clock == hdmi_ncts_table[i].clock) {
 249			return hdmi_ncts_table[i].n;
 250		}
 251	}
 252	return 0;
 253}
 254
 255/* ELD buffer size in dwords */
 256static int g4x_eld_buffer_size(struct intel_display *display)
 257{
 258	u32 tmp;
 259
 260	tmp = intel_de_read(display, G4X_AUD_CNTL_ST);
 261
 262	return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp);
 263}
 264
 265static void g4x_audio_codec_get_config(struct intel_encoder *encoder,
 266				       struct intel_crtc_state *crtc_state)
 267{
 268	struct intel_display *display = to_intel_display(encoder);
 269	u32 *eld = (u32 *)crtc_state->eld;
 270	int eld_buffer_size, len, i;
 271	u32 tmp;
 272
 273	tmp = intel_de_read(display, G4X_AUD_CNTL_ST);
 274	if ((tmp & G4X_ELD_VALID) == 0)
 275		return;
 276
 277	intel_de_rmw(display, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0);
 278
 279	eld_buffer_size = g4x_eld_buffer_size(display);
 280	len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size);
 281
 282	for (i = 0; i < len; i++)
 283		eld[i] = intel_de_read(display, G4X_HDMIW_HDMIEDID);
 284}
 285
 286static void g4x_audio_codec_disable(struct intel_encoder *encoder,
 287				    const struct intel_crtc_state *old_crtc_state,
 288				    const struct drm_connector_state *old_conn_state)
 289{
 290	struct intel_display *display = to_intel_display(encoder);
 291	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 292
 293	/* Invalidate ELD */
 294	intel_de_rmw(display, G4X_AUD_CNTL_ST,
 295		     G4X_ELD_VALID, 0);
 296
 297	intel_crtc_wait_for_next_vblank(crtc);
 298	intel_crtc_wait_for_next_vblank(crtc);
 299}
 300
 301static void g4x_audio_codec_enable(struct intel_encoder *encoder,
 302				   const struct intel_crtc_state *crtc_state,
 303				   const struct drm_connector_state *conn_state)
 304{
 305	struct intel_display *display = to_intel_display(encoder);
 306	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 307	const u32 *eld = (const u32 *)crtc_state->eld;
 308	int eld_buffer_size, len, i;
 309
 310	intel_crtc_wait_for_next_vblank(crtc);
 311
 312	intel_de_rmw(display, G4X_AUD_CNTL_ST,
 313		     G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0);
 314
 315	eld_buffer_size = g4x_eld_buffer_size(display);
 316	len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size);
 317
 318	for (i = 0; i < len; i++)
 319		intel_de_write(display, G4X_HDMIW_HDMIEDID, eld[i]);
 320	for (; i < eld_buffer_size; i++)
 321		intel_de_write(display, G4X_HDMIW_HDMIEDID, 0);
 322
 323	drm_WARN_ON(display->drm,
 324		    (intel_de_read(display, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0);
 325
 326	intel_de_rmw(display, G4X_AUD_CNTL_ST,
 327		     0, G4X_ELD_VALID);
 328}
 329
 330static void
 331hsw_dp_audio_config_update(struct intel_encoder *encoder,
 332			   const struct intel_crtc_state *crtc_state)
 333{
 334	struct intel_display *display = to_intel_display(encoder);
 335	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 336
 337	/* Enable time stamps. Let HW calculate Maud/Naud values */
 338	intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder),
 339		     AUD_CONFIG_N_VALUE_INDEX |
 340		     AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK |
 341		     AUD_CONFIG_UPPER_N_MASK |
 342		     AUD_CONFIG_LOWER_N_MASK |
 343		     AUD_CONFIG_N_PROG_ENABLE,
 344		     AUD_CONFIG_N_VALUE_INDEX);
 345
 346}
 347
 348static void
 349hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
 350			     const struct intel_crtc_state *crtc_state)
 351{
 352	struct intel_display *display = to_intel_display(encoder);
 353	struct i915_audio_component *acomp = display->audio.component;
 354	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 355	enum port port = encoder->port;
 356	int n, rate;
 357	u32 tmp;
 358
 359	rate = acomp ? acomp->aud_sample_rate[port] : 0;
 360
 361	tmp = intel_de_read(display, HSW_AUD_CFG(cpu_transcoder));
 362	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
 363	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
 364	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
 365	tmp |= audio_config_hdmi_pixel_clock(crtc_state);
 366
 367	n = audio_config_hdmi_get_n(crtc_state, rate);
 368	if (n != 0) {
 369		drm_dbg_kms(display->drm, "using N %d\n", n);
 370
 371		tmp &= ~AUD_CONFIG_N_MASK;
 372		tmp |= AUD_CONFIG_N(n);
 373		tmp |= AUD_CONFIG_N_PROG_ENABLE;
 374	} else {
 375		drm_dbg_kms(display->drm, "using automatic N\n");
 376	}
 377
 378	intel_de_write(display, HSW_AUD_CFG(cpu_transcoder), tmp);
 379
 380	/*
 381	 * Let's disable "Enable CTS or M Prog bit"
 382	 * and let HW calculate the value
 383	 */
 384	tmp = intel_de_read(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
 385	tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
 386	tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
 387	intel_de_write(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
 388}
 389
 390static void
 391hsw_audio_config_update(struct intel_encoder *encoder,
 392			const struct intel_crtc_state *crtc_state)
 393{
 394	if (intel_crtc_has_dp_encoder(crtc_state))
 395		hsw_dp_audio_config_update(encoder, crtc_state);
 396	else
 397		hsw_hdmi_audio_config_update(encoder, crtc_state);
 398}
 399
 400static void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state,
 401					 bool enable)
 402{
 403	struct intel_display *display = to_intel_display(crtc_state);
 404	enum transcoder trans = crtc_state->cpu_transcoder;
 405
 406	if (!HAS_DP20(display))
 407		return;
 408
 409	intel_de_rmw(display, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT,
 410		     enable && crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0);
 411}
 412
 413static void hsw_audio_codec_disable(struct intel_encoder *encoder,
 414				    const struct intel_crtc_state *old_crtc_state,
 415				    const struct drm_connector_state *old_conn_state)
 416{
 417	struct intel_display *display = to_intel_display(encoder);
 418	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 419	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 420
 421	mutex_lock(&display->audio.mutex);
 422
 423	/* Disable timestamps */
 424	intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder),
 425		     AUD_CONFIG_N_VALUE_INDEX |
 426		     AUD_CONFIG_UPPER_N_MASK |
 427		     AUD_CONFIG_LOWER_N_MASK,
 428		     AUD_CONFIG_N_PROG_ENABLE |
 429		     (intel_crtc_has_dp_encoder(old_crtc_state) ?
 430		      AUD_CONFIG_N_VALUE_INDEX : 0));
 431
 432	/* Invalidate ELD */
 433	intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,
 434		     AUDIO_ELD_VALID(cpu_transcoder), 0);
 435
 436	intel_crtc_wait_for_next_vblank(crtc);
 437	intel_crtc_wait_for_next_vblank(crtc);
 438
 439	/* Disable audio presence detect */
 440	intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,
 441		     AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0);
 442
 443	if (needs_wa_14020863754(display))
 444		intel_de_rmw(display, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0);
 445
 446	intel_audio_sdp_split_update(old_crtc_state, false);
 447
 448	mutex_unlock(&display->audio.mutex);
 449}
 450
 451static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 452					   const struct intel_crtc_state *crtc_state)
 453{
 454	struct intel_display *display = to_intel_display(encoder);
 455	unsigned int link_clks_available, link_clks_required;
 456	unsigned int tu_data, tu_line, link_clks_active;
 457	unsigned int h_active, h_total, hblank_delta, pixel_clk;
 458	unsigned int fec_coeff, cdclk, vdsc_bppx16;
 459	unsigned int link_clk, lanes;
 460	unsigned int hblank_rise;
 461
 462	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 463	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
 464	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
 465	vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16;
 466	cdclk = display->cdclk.hw.cdclk;
 467	/* fec= 0.972261, using rounding multiplier of 1000000 */
 468	fec_coeff = 972261;
 469	link_clk = crtc_state->port_clock;
 470	lanes = crtc_state->lane_count;
 471
 472	drm_dbg_kms(display->drm,
 473		    "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " FXP_Q4_FMT " cdclk = %u\n",
 474		    h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk);
 475
 476	if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk))
 477		return 0;
 478
 479	link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28;
 480	link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2);
 481
 482	if (link_clks_available > link_clks_required)
 483		hblank_delta = 32;
 484	else
 485		hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
 486						  mul_u32_u32(link_clk, cdclk));
 487
 488	tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000),
 489			    mul_u32_u32(link_clk * lanes * 16, fec_coeff));
 490	tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
 491			    mul_u32_u32(64 * pixel_clk, 1000000));
 492	link_clks_active  = (tu_line - 1) * 64 + tu_data;
 493
 494	hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk;
 495
 496	return h_active - hblank_rise + hblank_delta;
 497}
 498
 499static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state)
 500{
 501	unsigned int h_active, h_total, pixel_clk;
 502	unsigned int link_clk, lanes;
 503
 504	h_active = crtc_state->hw.adjusted_mode.hdisplay;
 505	h_total = crtc_state->hw.adjusted_mode.htotal;
 506	pixel_clk = crtc_state->hw.adjusted_mode.clock;
 507	link_clk = crtc_state->port_clock;
 508	lanes = crtc_state->lane_count;
 509
 510	return ((h_total - h_active) * link_clk - 12 * pixel_clk) /
 511		(pixel_clk * (48 / lanes + 2));
 512}
 513
 514static void enable_audio_dsc_wa(struct intel_encoder *encoder,
 515				const struct intel_crtc_state *crtc_state)
 516{
 517	struct intel_display *display = to_intel_display(encoder);
 518	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 519	unsigned int hblank_early_prog, samples_room;
 520	unsigned int val;
 521
 522	if (DISPLAY_VER(display) < 11)
 523		return;
 524
 525	val = intel_de_read(display, AUD_CONFIG_BE);
 526
 527	if (DISPLAY_VER(display) == 11)
 528		val |= HBLANK_EARLY_ENABLE_ICL(cpu_transcoder);
 529	else if (DISPLAY_VER(display) >= 12)
 530		val |= HBLANK_EARLY_ENABLE_TGL(cpu_transcoder);
 531
 532	if (crtc_state->dsc.compression_enable &&
 533	    crtc_state->hw.adjusted_mode.hdisplay >= 3840 &&
 534	    crtc_state->hw.adjusted_mode.vdisplay >= 2160) {
 535		/* Get hblank early enable value required */
 536		val &= ~HBLANK_START_COUNT_MASK(cpu_transcoder);
 537		hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state);
 538		if (hblank_early_prog < 32)
 539			val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_32);
 540		else if (hblank_early_prog < 64)
 541			val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_64);
 542		else if (hblank_early_prog < 96)
 543			val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_96);
 544		else
 545			val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_128);
 546
 547		/* Get samples room value required */
 548		val &= ~NUMBER_SAMPLES_PER_LINE_MASK(cpu_transcoder);
 549		samples_room = calc_samples_room(crtc_state);
 550		if (samples_room < 3)
 551			val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, samples_room);
 552		else /* Program 0 i.e "All Samples available in buffer" */
 553			val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, 0x0);
 554	}
 555
 556	intel_de_write(display, AUD_CONFIG_BE, val);
 557}
 558
 559static void hsw_audio_codec_enable(struct intel_encoder *encoder,
 560				   const struct intel_crtc_state *crtc_state,
 561				   const struct drm_connector_state *conn_state)
 562{
 563	struct intel_display *display = to_intel_display(encoder);
 564	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 565	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 566
 567	mutex_lock(&display->audio.mutex);
 568
 569	/* Enable Audio WA for 4k DSC usecases */
 570	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
 571		enable_audio_dsc_wa(encoder, crtc_state);
 572
 573	intel_audio_sdp_split_update(crtc_state, true);
 574
 575	if (needs_wa_14020863754(display))
 576		intel_de_rmw(display, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX);
 577
 578	/* Enable audio presence detect */
 579	intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,
 580		     0, AUDIO_OUTPUT_ENABLE(cpu_transcoder));
 581
 582	intel_crtc_wait_for_next_vblank(crtc);
 583
 584	/* Invalidate ELD */
 585	intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD,
 586		     AUDIO_ELD_VALID(cpu_transcoder), 0);
 587
 588	/*
 589	 * The audio component is used to convey the ELD
 590	 * instead using of the hardware ELD buffer.
 591	 */
 592
 593	/* Enable timestamps */
 594	hsw_audio_config_update(encoder, crtc_state);
 595
 596	mutex_unlock(&display->audio.mutex);
 597}
 598
 599struct ibx_audio_regs {
 600	i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
 601};
 602
 603static void ibx_audio_regs_init(struct intel_display *display,
 604				enum pipe pipe,
 605				struct ibx_audio_regs *regs)
 606{
 607	if (display->platform.valleyview || display->platform.cherryview) {
 608		regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
 609		regs->aud_config = VLV_AUD_CFG(pipe);
 610		regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
 611		regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 612	} else if (HAS_PCH_CPT(display)) {
 613		regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
 614		regs->aud_config = CPT_AUD_CFG(pipe);
 615		regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
 616		regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
 617	} else if (HAS_PCH_IBX(display)) {
 618		regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
 619		regs->aud_config = IBX_AUD_CFG(pipe);
 620		regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 621		regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
 622	}
 623}
 624
 625static void ibx_audio_codec_disable(struct intel_encoder *encoder,
 626				    const struct intel_crtc_state *old_crtc_state,
 627				    const struct drm_connector_state *old_conn_state)
 628{
 629	struct intel_display *display = to_intel_display(encoder);
 630	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 631	enum port port = encoder->port;
 632	enum pipe pipe = crtc->pipe;
 633	struct ibx_audio_regs regs;
 634
 635	if (drm_WARN_ON(display->drm, port == PORT_A))
 636		return;
 637
 638	ibx_audio_regs_init(display, pipe, &regs);
 639
 640	mutex_lock(&display->audio.mutex);
 641
 642	/* Disable timestamps */
 643	intel_de_rmw(display, regs.aud_config,
 644		     AUD_CONFIG_N_VALUE_INDEX |
 645		     AUD_CONFIG_UPPER_N_MASK |
 646		     AUD_CONFIG_LOWER_N_MASK,
 647		     AUD_CONFIG_N_PROG_ENABLE |
 648		     (intel_crtc_has_dp_encoder(old_crtc_state) ?
 649		      AUD_CONFIG_N_VALUE_INDEX : 0));
 650
 651	/* Invalidate ELD */
 652	intel_de_rmw(display, regs.aud_cntrl_st2,
 653		     IBX_ELD_VALID(port), 0);
 654
 655	mutex_unlock(&display->audio.mutex);
 656
 657	intel_crtc_wait_for_next_vblank(crtc);
 658	intel_crtc_wait_for_next_vblank(crtc);
 659}
 660
 661static void ibx_audio_codec_enable(struct intel_encoder *encoder,
 662				   const struct intel_crtc_state *crtc_state,
 663				   const struct drm_connector_state *conn_state)
 664{
 665	struct intel_display *display = to_intel_display(encoder);
 666	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 667	enum port port = encoder->port;
 668	enum pipe pipe = crtc->pipe;
 669	struct ibx_audio_regs regs;
 670
 671	if (drm_WARN_ON(display->drm, port == PORT_A))
 672		return;
 673
 674	intel_crtc_wait_for_next_vblank(crtc);
 675
 676	ibx_audio_regs_init(display, pipe, &regs);
 677
 678	mutex_lock(&display->audio.mutex);
 679
 680	/* Invalidate ELD */
 681	intel_de_rmw(display, regs.aud_cntrl_st2,
 682		     IBX_ELD_VALID(port), 0);
 683
 684	/*
 685	 * The audio component is used to convey the ELD
 686	 * instead using of the hardware ELD buffer.
 687	 */
 688
 689	/* Enable timestamps */
 690	intel_de_rmw(display, regs.aud_config,
 691		     AUD_CONFIG_N_VALUE_INDEX |
 692		     AUD_CONFIG_N_PROG_ENABLE |
 693		     AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK,
 694		     (intel_crtc_has_dp_encoder(crtc_state) ?
 695		      AUD_CONFIG_N_VALUE_INDEX :
 696		      audio_config_hdmi_pixel_clock(crtc_state)));
 697
 698	mutex_unlock(&display->audio.mutex);
 699}
 700
 701bool intel_audio_compute_config(struct intel_encoder *encoder,
 702				struct intel_crtc_state *crtc_state,
 703				struct drm_connector_state *conn_state)
 704{
 705	struct intel_display *display = to_intel_display(encoder);
 706	struct drm_connector *connector = conn_state->connector;
 707	const struct drm_display_mode *adjusted_mode =
 708		&crtc_state->hw.adjusted_mode;
 709
 710	mutex_lock(&connector->eld_mutex);
 711	if (!connector->eld[0]) {
 712		drm_dbg_kms(display->drm,
 713			    "Bogus ELD on [CONNECTOR:%d:%s]\n",
 714			    connector->base.id, connector->name);
 715		mutex_unlock(&connector->eld_mutex);
 716		return false;
 717	}
 718
 719	BUILD_BUG_ON(sizeof(crtc_state->eld) != sizeof(connector->eld));
 720	memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld));
 721
 722	crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
 723	mutex_unlock(&connector->eld_mutex);
 724
 725	return true;
 726}
 727
 728/**
 729 * intel_audio_codec_enable - Enable the audio codec for HD audio
 730 * @encoder: encoder on which to enable audio
 731 * @crtc_state: pointer to the current crtc state.
 732 * @conn_state: pointer to the current connector state.
 733 *
 734 * The enable sequences may only be performed after enabling the transcoder and
 735 * port, and after completed link training.
 736 */
 737void intel_audio_codec_enable(struct intel_encoder *encoder,
 738			      const struct intel_crtc_state *crtc_state,
 739			      const struct drm_connector_state *conn_state)
 740{
 741	struct intel_display *display = to_intel_display(encoder);
 742	struct i915_audio_component *acomp = display->audio.component;
 743	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 744	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 745	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 746	struct intel_audio_state *audio_state;
 747	enum port port = encoder->port;
 748
 749	if (!crtc_state->has_audio)
 750		return;
 751
 752	drm_dbg_kms(display->drm,
 753		    "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on [CRTC:%d:%s], %u bytes ELD\n",
 754		    connector->base.base.id, connector->base.name,
 755		    encoder->base.base.id, encoder->base.name,
 756		    crtc->base.base.id, crtc->base.name,
 757		    drm_eld_size(crtc_state->eld));
 758
 759	if (display->funcs.audio)
 760		display->funcs.audio->audio_codec_enable(encoder,
 761							      crtc_state,
 762							      conn_state);
 763
 764	mutex_lock(&display->audio.mutex);
 765
 766	audio_state = &display->audio.state[cpu_transcoder];
 767
 768	audio_state->encoder = encoder;
 769	BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld));
 770	memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld));
 771
 772	mutex_unlock(&display->audio.mutex);
 773
 774	if (acomp && acomp->base.audio_ops &&
 775	    acomp->base.audio_ops->pin_eld_notify) {
 776		/* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */
 777		if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
 778			cpu_transcoder = -1;
 779		acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
 780						      (int)port, (int)cpu_transcoder);
 781	}
 782
 783	intel_lpe_audio_notify(display, cpu_transcoder, port, crtc_state->eld,
 784			       crtc_state->port_clock,
 785			       intel_crtc_has_dp_encoder(crtc_state));
 786}
 787
 788/**
 789 * intel_audio_codec_disable - Disable the audio codec for HD audio
 790 * @encoder: encoder on which to disable audio
 791 * @old_crtc_state: pointer to the old crtc state.
 792 * @old_conn_state: pointer to the old connector state.
 793 *
 794 * The disable sequences must be performed before disabling the transcoder or
 795 * port.
 796 */
 797void intel_audio_codec_disable(struct intel_encoder *encoder,
 798			       const struct intel_crtc_state *old_crtc_state,
 799			       const struct drm_connector_state *old_conn_state)
 800{
 801	struct intel_display *display = to_intel_display(encoder);
 802	struct i915_audio_component *acomp = display->audio.component;
 803	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 804	struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
 805	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 806	struct intel_audio_state *audio_state;
 807	enum port port = encoder->port;
 808
 809	if (!old_crtc_state->has_audio)
 810		return;
 811
 812	drm_dbg_kms(display->drm,
 813		    "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on [CRTC:%d:%s]\n",
 814		    connector->base.base.id, connector->base.name,
 815		    encoder->base.base.id, encoder->base.name,
 816		    crtc->base.base.id, crtc->base.name);
 817
 818	if (display->funcs.audio)
 819		display->funcs.audio->audio_codec_disable(encoder,
 820							       old_crtc_state,
 821							       old_conn_state);
 822
 823	mutex_lock(&display->audio.mutex);
 824
 825	audio_state = &display->audio.state[cpu_transcoder];
 826
 827	audio_state->encoder = NULL;
 828	memset(audio_state->eld, 0, sizeof(audio_state->eld));
 829
 830	mutex_unlock(&display->audio.mutex);
 831
 832	if (acomp && acomp->base.audio_ops &&
 833	    acomp->base.audio_ops->pin_eld_notify) {
 834		/* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */
 835		if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
 836			cpu_transcoder = -1;
 837		acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
 838						      (int)port, (int)cpu_transcoder);
 839	}
 840
 841	intel_lpe_audio_notify(display, cpu_transcoder, port, NULL, 0, false);
 842}
 843
 844static void intel_acomp_get_config(struct intel_encoder *encoder,
 845				   struct intel_crtc_state *crtc_state)
 846{
 847	struct intel_display *display = to_intel_display(encoder);
 848	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 849	struct intel_audio_state *audio_state;
 850
 851	mutex_lock(&display->audio.mutex);
 852
 853	audio_state = &display->audio.state[cpu_transcoder];
 854
 855	if (audio_state->encoder)
 856		memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld));
 857
 858	mutex_unlock(&display->audio.mutex);
 859}
 860
 861void intel_audio_codec_get_config(struct intel_encoder *encoder,
 862				  struct intel_crtc_state *crtc_state)
 863{
 864	struct intel_display *display = to_intel_display(encoder);
 865
 866	if (!crtc_state->has_audio)
 867		return;
 868
 869	if (display->funcs.audio)
 870		display->funcs.audio->audio_codec_get_config(encoder, crtc_state);
 871}
 872
 873static const struct intel_audio_funcs g4x_audio_funcs = {
 874	.audio_codec_enable = g4x_audio_codec_enable,
 875	.audio_codec_disable = g4x_audio_codec_disable,
 876	.audio_codec_get_config = g4x_audio_codec_get_config,
 877};
 878
 879static const struct intel_audio_funcs ibx_audio_funcs = {
 880	.audio_codec_enable = ibx_audio_codec_enable,
 881	.audio_codec_disable = ibx_audio_codec_disable,
 882	.audio_codec_get_config = intel_acomp_get_config,
 883};
 884
 885static const struct intel_audio_funcs hsw_audio_funcs = {
 886	.audio_codec_enable = hsw_audio_codec_enable,
 887	.audio_codec_disable = hsw_audio_codec_disable,
 888	.audio_codec_get_config = intel_acomp_get_config,
 889};
 890
 891/**
 892 * intel_audio_hooks_init - Set up chip specific audio hooks
 893 * @display: display device
 894 */
 895void intel_audio_hooks_init(struct intel_display *display)
 896{
 897	if (display->platform.g4x)
 898		display->funcs.audio = &g4x_audio_funcs;
 899	else if (display->platform.valleyview || display->platform.cherryview ||
 900		 HAS_PCH_CPT(display) || HAS_PCH_IBX(display))
 901		display->funcs.audio = &ibx_audio_funcs;
 902	else if (display->platform.haswell || DISPLAY_VER(display) >= 8)
 903		display->funcs.audio = &hsw_audio_funcs;
 904}
 905
 906struct aud_ts_cdclk_m_n {
 907	u8 m;
 908	u16 n;
 909};
 910
 911void intel_audio_cdclk_change_pre(struct intel_display *display)
 912{
 913	if (DISPLAY_VER(display) >= 13)
 914		intel_de_rmw(display, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0);
 915}
 916
 917static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts)
 918{
 919	aud_ts->m = 60;
 920	aud_ts->n = cdclk * aud_ts->m / 24000;
 921}
 922
 923void intel_audio_cdclk_change_post(struct intel_display *display)
 924{
 925	struct aud_ts_cdclk_m_n aud_ts;
 926
 927	if (DISPLAY_VER(display) >= 13) {
 928		get_aud_ts_cdclk_m_n(display->cdclk.hw.ref,
 929				     display->cdclk.hw.cdclk, &aud_ts);
 930
 931		intel_de_write(display, AUD_TS_CDCLK_N, aud_ts.n);
 932		intel_de_write(display, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN);
 933		drm_dbg_kms(display->drm, "aud_ts_cdclk set to M=%u, N=%u\n",
 934			    aud_ts.m, aud_ts.n);
 935	}
 936}
 937
 938static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
 939					struct intel_crtc *crtc,
 940					bool enable)
 941{
 942	struct intel_cdclk_state *cdclk_state;
 943	int ret;
 944
 945	/* need to hold at least one crtc lock for the global state */
 946	ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
 947	if (ret)
 948		return ret;
 949
 950	cdclk_state = intel_atomic_get_cdclk_state(state);
 951	if (IS_ERR(cdclk_state))
 952		return PTR_ERR(cdclk_state);
 953
 954	intel_cdclk_force_min_cdclk(cdclk_state, enable ? 2 * 96000 : 0);
 955
 956	return drm_atomic_commit(&state->base);
 957}
 958
 959static void glk_force_audio_cdclk(struct intel_display *display,
 960				  bool enable)
 961{
 962	struct drm_modeset_acquire_ctx ctx;
 963	struct drm_atomic_state *state;
 964	struct intel_crtc *crtc;
 965	int ret;
 966
 967	crtc = intel_first_crtc(display);
 968	if (!crtc)
 969		return;
 970
 971	drm_modeset_acquire_init(&ctx, 0);
 972	state = drm_atomic_state_alloc(display->drm);
 973	if (drm_WARN_ON(display->drm, !state))
 974		return;
 975
 976	state->acquire_ctx = &ctx;
 977	to_intel_atomic_state(state)->internal = true;
 978
 979retry:
 980	ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc,
 981					   enable);
 982	if (ret == -EDEADLK) {
 983		drm_atomic_state_clear(state);
 984		drm_modeset_backoff(&ctx);
 985		goto retry;
 986	}
 987
 988	drm_WARN_ON(display->drm, ret);
 989
 990	drm_atomic_state_put(state);
 991
 992	drm_modeset_drop_locks(&ctx);
 993	drm_modeset_acquire_fini(&ctx);
 994}
 995
 996int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
 997{
 998	struct intel_display *display = to_intel_display(crtc_state);
 999	int min_cdclk = 0;
1000
1001	if (!crtc_state->has_audio)
1002		return 0;
1003
1004	/* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
1005	 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
1006	 * there may be audio corruption or screen corruption." This cdclk
1007	 * restriction for GLK is 316.8 MHz.
1008	 */
1009	if (intel_crtc_has_dp_encoder(crtc_state) &&
1010	    crtc_state->port_clock >= 540000 &&
1011	    crtc_state->lane_count == 4) {
1012		if (DISPLAY_VER(display) == 10) {
1013			/* Display WA #1145: glk */
1014			min_cdclk = max(min_cdclk, 316800);
1015		} else if (DISPLAY_VER(display) == 9 || display->platform.broadwell) {
1016			/* Display WA #1144: skl,bxt */
1017			min_cdclk = max(min_cdclk, 432000);
1018		}
1019	}
1020
1021	/*
1022	 * According to BSpec, "The CD clock frequency must be at least twice
1023	 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
1024	 */
1025	if (DISPLAY_VER(display) >= 9)
1026		min_cdclk = max(min_cdclk, 2 * 96000);
1027
1028	/*
1029	 * "For DP audio configuration, cdclk frequency shall be set to
1030	 *  meet the following requirements:
1031	 *  DP Link Frequency(MHz) | Cdclk frequency(MHz)
1032	 *  270                    | 320 or higher
1033	 *  162                    | 200 or higher"
1034	 */
1035	if ((display->platform.valleyview || display->platform.cherryview) &&
1036	    intel_crtc_has_dp_encoder(crtc_state))
1037		min_cdclk = max(min_cdclk, crtc_state->port_clock);
1038
1039	return min_cdclk;
1040}
1041
1042static unsigned long intel_audio_component_get_power(struct device *kdev)
1043{
1044	struct intel_display *display = to_intel_display(kdev);
1045	intel_wakeref_t wakeref;
1046
1047	/* Catch potential impedance mismatches before they occur! */
1048	BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
1049
1050	wakeref = intel_display_power_get(display, POWER_DOMAIN_AUDIO_PLAYBACK);
1051
1052	if (display->audio.power_refcount++ == 0) {
1053		if (DISPLAY_VER(display) >= 9) {
1054			intel_de_write(display, AUD_FREQ_CNTRL,
1055				       display->audio.freq_cntrl);
1056			drm_dbg_kms(display->drm,
1057				    "restored AUD_FREQ_CNTRL to 0x%x\n",
1058				    display->audio.freq_cntrl);
1059		}
1060
1061		/* Force CDCLK to 2*BCLK as long as we need audio powered. */
1062		if (display->platform.geminilake)
1063			glk_force_audio_cdclk(display, true);
1064
1065		if (DISPLAY_VER(display) >= 10)
1066			intel_de_rmw(display, AUD_PIN_BUF_CTL,
1067				     0, AUD_PIN_BUF_ENABLE);
1068	}
1069
1070	return (unsigned long)wakeref;
1071}
1072
1073static void intel_audio_component_put_power(struct device *kdev,
1074					    unsigned long cookie)
1075{
1076	struct intel_display *display = to_intel_display(kdev);
1077	intel_wakeref_t wakeref = (intel_wakeref_t)cookie;
1078
1079	/* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
1080	if (--display->audio.power_refcount == 0)
1081		if (display->platform.geminilake)
1082			glk_force_audio_cdclk(display, false);
1083
1084	intel_display_power_put(display, POWER_DOMAIN_AUDIO_PLAYBACK, wakeref);
1085}
1086
1087static void intel_audio_component_codec_wake_override(struct device *kdev,
1088						      bool enable)
1089{
1090	struct intel_display *display = to_intel_display(kdev);
1091	unsigned long cookie;
1092
1093	if (DISPLAY_VER(display) < 9)
1094		return;
1095
1096	cookie = intel_audio_component_get_power(kdev);
1097
1098	/*
1099	 * Enable/disable generating the codec wake signal, overriding the
1100	 * internal logic to generate the codec wake to controller.
1101	 */
1102	intel_de_rmw(display, HSW_AUD_CHICKENBIT,
1103		     SKL_AUD_CODEC_WAKE_SIGNAL, 0);
1104	usleep_range(1000, 1500);
1105
1106	if (enable) {
1107		intel_de_rmw(display, HSW_AUD_CHICKENBIT,
1108			     0, SKL_AUD_CODEC_WAKE_SIGNAL);
1109		usleep_range(1000, 1500);
1110	}
1111
1112	intel_audio_component_put_power(kdev, cookie);
1113}
1114
1115/* Get CDCLK in kHz  */
1116static int intel_audio_component_get_cdclk_freq(struct device *kdev)
1117{
1118	struct intel_display *display = to_intel_display(kdev);
1119
1120	if (drm_WARN_ON_ONCE(display->drm, !HAS_DDI(display)))
1121		return -ENODEV;
1122
1123	return display->cdclk.hw.cdclk;
1124}
1125
1126/*
1127 * get the intel audio state according to the parameter port and cpu_transcoder
1128 * MST & (cpu_transcoder >= 0): return the audio.state[cpu_transcoder].encoder],
1129 *   when port is matched
1130 * MST & (cpu_transcoder < 0): this is invalid
1131 * Non-MST & (cpu_transcoder >= 0): only cpu_transcoder = 0 (the first device entry)
1132 *   will get the right intel_encoder with port matched
1133 * Non-MST & (cpu_transcoder < 0): get the right intel_encoder with port matched
1134 */
1135static struct intel_audio_state *find_audio_state(struct intel_display *display,
1136						  int port, int cpu_transcoder)
1137{
1138	/* MST */
1139	if (cpu_transcoder >= 0) {
1140		struct intel_audio_state *audio_state;
1141		struct intel_encoder *encoder;
1142
1143		if (drm_WARN_ON(display->drm,
1144				cpu_transcoder >= ARRAY_SIZE(display->audio.state)))
1145			return NULL;
1146
1147		audio_state = &display->audio.state[cpu_transcoder];
1148		encoder = audio_state->encoder;
1149
1150		if (encoder && encoder->port == port &&
1151		    encoder->type == INTEL_OUTPUT_DP_MST)
1152			return audio_state;
1153	}
1154
1155	/* Non-MST */
1156	if (cpu_transcoder > 0)
1157		return NULL;
1158
1159	for_each_cpu_transcoder(display, cpu_transcoder) {
1160		struct intel_audio_state *audio_state;
1161		struct intel_encoder *encoder;
1162
1163		audio_state = &display->audio.state[cpu_transcoder];
1164		encoder = audio_state->encoder;
1165
1166		if (encoder && encoder->port == port &&
1167		    encoder->type != INTEL_OUTPUT_DP_MST)
1168			return audio_state;
1169	}
1170
1171	return NULL;
1172}
1173
1174static int intel_audio_component_sync_audio_rate(struct device *kdev, int port,
1175						 int cpu_transcoder, int rate)
1176{
1177	struct intel_display *display = to_intel_display(kdev);
1178	struct i915_audio_component *acomp = display->audio.component;
1179	const struct intel_audio_state *audio_state;
1180	struct intel_encoder *encoder;
1181	struct intel_crtc *crtc;
1182	unsigned long cookie;
1183	int err = 0;
1184
1185	if (!HAS_DDI(display))
1186		return 0;
1187
1188	cookie = intel_audio_component_get_power(kdev);
1189	mutex_lock(&display->audio.mutex);
1190
1191	audio_state = find_audio_state(display, port, cpu_transcoder);
1192	if (!audio_state) {
1193		drm_dbg_kms(display->drm, "Not valid for port %c\n",
1194			    port_name(port));
1195		err = -ENODEV;
1196		goto unlock;
1197	}
1198
1199	encoder = audio_state->encoder;
1200
1201	/* FIXME stop using the legacy crtc pointer */
1202	crtc = to_intel_crtc(encoder->base.crtc);
1203
1204	/* port must be valid now, otherwise the cpu_transcoder will be invalid */
1205	acomp->aud_sample_rate[port] = rate;
1206
1207	/* FIXME get rid of the crtc->config stuff */
1208	hsw_audio_config_update(encoder, crtc->config);
1209
1210 unlock:
1211	mutex_unlock(&display->audio.mutex);
1212	intel_audio_component_put_power(kdev, cookie);
1213	return err;
1214}
1215
1216static int intel_audio_component_get_eld(struct device *kdev, int port,
1217					 int cpu_transcoder, bool *enabled,
1218					 unsigned char *buf, int max_bytes)
1219{
1220	struct intel_display *display = to_intel_display(kdev);
1221	const struct intel_audio_state *audio_state;
1222	int ret = 0;
1223
1224	mutex_lock(&display->audio.mutex);
1225
1226	audio_state = find_audio_state(display, port, cpu_transcoder);
1227	if (!audio_state) {
1228		drm_dbg_kms(display->drm, "Not valid for port %c\n",
1229			    port_name(port));
1230		mutex_unlock(&display->audio.mutex);
1231		return -EINVAL;
1232	}
1233
1234	*enabled = audio_state->encoder != NULL;
1235	if (*enabled) {
1236		const u8 *eld = audio_state->eld;
1237
1238		ret = drm_eld_size(eld);
1239		memcpy(buf, eld, min(max_bytes, ret));
1240	}
1241
1242	mutex_unlock(&display->audio.mutex);
1243	return ret;
1244}
1245
1246static const struct drm_audio_component_ops intel_audio_component_ops = {
1247	.owner = THIS_MODULE,
1248	.get_power = intel_audio_component_get_power,
1249	.put_power = intel_audio_component_put_power,
1250	.codec_wake_override = intel_audio_component_codec_wake_override,
1251	.get_cdclk_freq = intel_audio_component_get_cdclk_freq,
1252	.sync_audio_rate = intel_audio_component_sync_audio_rate,
1253	.get_eld = intel_audio_component_get_eld,
1254};
1255
1256static int intel_audio_component_bind(struct device *drv_kdev,
1257				      struct device *hda_kdev, void *data)
1258{
1259	struct intel_display *display = to_intel_display(drv_kdev);
1260	struct i915_audio_component *acomp = data;
1261	int i;
1262
1263	if (drm_WARN_ON(display->drm, acomp->base.ops || acomp->base.dev))
1264		return -EEXIST;
1265
1266	if (drm_WARN_ON(display->drm,
1267			!device_link_add(hda_kdev, drv_kdev,
1268					 DL_FLAG_STATELESS)))
1269		return -ENOMEM;
1270
1271	drm_modeset_lock_all(display->drm);
1272	acomp->base.ops = &intel_audio_component_ops;
1273	acomp->base.dev = drv_kdev;
1274	BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
1275	for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
1276		acomp->aud_sample_rate[i] = 0;
1277	display->audio.component = acomp;
1278	drm_modeset_unlock_all(display->drm);
1279
1280	return 0;
1281}
1282
1283static void intel_audio_component_unbind(struct device *drv_kdev,
1284					 struct device *hda_kdev, void *data)
1285{
1286	struct intel_display *display = to_intel_display(drv_kdev);
1287	struct i915_audio_component *acomp = data;
1288
1289	drm_modeset_lock_all(display->drm);
1290	acomp->base.ops = NULL;
1291	acomp->base.dev = NULL;
1292	display->audio.component = NULL;
1293	drm_modeset_unlock_all(display->drm);
1294
1295	device_link_remove(hda_kdev, drv_kdev);
1296
1297	if (display->audio.power_refcount)
1298		drm_err(display->drm,
1299			"audio power refcount %d after unbind\n",
1300			display->audio.power_refcount);
1301}
1302
1303static const struct component_ops intel_audio_component_bind_ops = {
1304	.bind = intel_audio_component_bind,
1305	.unbind = intel_audio_component_unbind,
1306};
1307
1308#define AUD_FREQ_TMODE_SHIFT	14
1309#define AUD_FREQ_4T		0
1310#define AUD_FREQ_8T		(2 << AUD_FREQ_TMODE_SHIFT)
1311#define AUD_FREQ_PULLCLKS(x)	(((x) & 0x3) << 11)
1312#define AUD_FREQ_BCLK_96M	BIT(4)
1313
1314#define AUD_FREQ_GEN12          (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M)
1315#define AUD_FREQ_TGL_BROKEN     (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M)
1316
1317/**
1318 * intel_audio_component_init - initialize and register the audio component
1319 * @display: display device
1320 *
1321 * This will register with the component framework a child component which
1322 * will bind dynamically to the snd_hda_intel driver's corresponding master
1323 * component when the latter is registered. During binding the child
1324 * initializes an instance of struct i915_audio_component which it receives
1325 * from the master. The master can then start to use the interface defined by
1326 * this struct. Each side can break the binding at any point by deregistering
1327 * its own component after which each side's component unbind callback is
1328 * called.
1329 *
1330 * We ignore any error during registration and continue with reduced
1331 * functionality (i.e. without HDMI audio).
1332 */
1333static void intel_audio_component_init(struct intel_display *display)
1334{
1335	u32 aud_freq, aud_freq_init;
1336
1337	if (DISPLAY_VER(display) >= 9) {
1338		aud_freq_init = intel_de_read(display, AUD_FREQ_CNTRL);
1339
1340		if (DISPLAY_VER(display) >= 12)
1341			aud_freq = AUD_FREQ_GEN12;
1342		else
1343			aud_freq = aud_freq_init;
1344
1345		/* use BIOS provided value for TGL and RKL unless it is a known bad value */
1346		if ((display->platform.tigerlake || display->platform.rocketlake) &&
1347		    aud_freq_init != AUD_FREQ_TGL_BROKEN)
1348			aud_freq = aud_freq_init;
1349
1350		drm_dbg_kms(display->drm,
1351			    "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n",
1352			    aud_freq, aud_freq_init);
1353
1354		display->audio.freq_cntrl = aud_freq;
1355	}
1356
1357	/* init with current cdclk */
1358	intel_audio_cdclk_change_post(display);
1359}
1360
1361static void intel_audio_component_register(struct intel_display *display)
1362{
1363	int ret;
1364
1365	ret = component_add_typed(display->drm->dev,
1366				  &intel_audio_component_bind_ops,
1367				  I915_COMPONENT_AUDIO);
1368	if (ret < 0) {
1369		drm_err(display->drm,
1370			"failed to add audio component (%d)\n", ret);
1371		/* continue with reduced functionality */
1372		return;
1373	}
1374
1375	display->audio.component_registered = true;
1376}
1377
1378/**
1379 * intel_audio_component_cleanup - deregister the audio component
1380 * @display: display device
1381 *
1382 * Deregisters the audio component, breaking any existing binding to the
1383 * corresponding snd_hda_intel driver's master component.
1384 */
1385static void intel_audio_component_cleanup(struct intel_display *display)
1386{
1387	if (!display->audio.component_registered)
1388		return;
1389
1390	component_del(display->drm->dev, &intel_audio_component_bind_ops);
1391	display->audio.component_registered = false;
1392}
1393
1394/**
1395 * intel_audio_init() - Initialize the audio driver either using
1396 * component framework or using lpe audio bridge
1397 * @display: display device
1398 *
1399 */
1400void intel_audio_init(struct intel_display *display)
1401{
1402	if (intel_lpe_audio_init(display) < 0)
1403		intel_audio_component_init(display);
1404}
1405
1406void intel_audio_register(struct intel_display *display)
1407{
1408	if (!display->audio.lpe.platdev)
1409		intel_audio_component_register(display);
1410}
1411
1412/**
1413 * intel_audio_deinit() - deinitialize the audio driver
1414 * @display: display device
1415 */
1416void intel_audio_deinit(struct intel_display *display)
1417{
1418	if (display->audio.lpe.platdev)
1419		intel_lpe_audio_teardown(display);
1420	else
1421		intel_audio_component_cleanup(display);
1422}