icl_dsi.c

   1/*
   2 * Copyright © 2018 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21 * DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors:
  24 *   Madhav Chauhan <madhav.chauhan@intel.com>
  25 *   Jani Nikula <jani.nikula@intel.com>
  26 */
  27
  28#include <linux/iopoll.h>
  29
  30#include <drm/display/drm_dsc_helper.h>
  31#include <drm/drm_atomic_helper.h>
  32#include <drm/drm_fixed.h>
  33#include <drm/drm_mipi_dsi.h>
  34#include <drm/drm_print.h>
  35#include <drm/drm_probe_helper.h>
  36
  37#include "i915_reg.h"
  38#include "icl_dsi.h"
  39#include "icl_dsi_regs.h"
  40#include "intel_atomic.h"
  41#include "intel_backlight.h"
  42#include "intel_backlight_regs.h"
  43#include "intel_combo_phy.h"
  44#include "intel_combo_phy_regs.h"
  45#include "intel_connector.h"
  46#include "intel_crtc.h"
  47#include "intel_ddi.h"
  48#include "intel_de.h"
  49#include "intel_display_regs.h"
  50#include "intel_display_utils.h"
  51#include "intel_dsi.h"
  52#include "intel_dsi_vbt.h"
  53#include "intel_panel.h"
  54#include "intel_pfit.h"
  55#include "intel_vdsc.h"
  56#include "intel_vdsc_regs.h"
  57#include "skl_scaler.h"
  58#include "skl_universal_plane.h"
  59
  60static int header_credits_available(struct intel_display *display,
  61				    enum transcoder dsi_trans)
  62{
  63	return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
  64		>> FREE_HEADER_CREDIT_SHIFT;
  65}
  66
  67static int payload_credits_available(struct intel_display *display,
  68				     enum transcoder dsi_trans)
  69{
  70	return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
  71		>> FREE_PLOAD_CREDIT_SHIFT;
  72}
  73
  74static bool wait_for_header_credits(struct intel_display *display,
  75				    enum transcoder dsi_trans, int hdr_credit)
  76{
  77	int ret, available;
  78
  79	ret = poll_timeout_us(available = header_credits_available(display, dsi_trans),
  80			      available >= hdr_credit,
  81			      10, 100, false);
  82	if (ret) {
  83		drm_err(display->drm, "DSI header credits not released\n");
  84		return false;
  85	}
  86
  87	return true;
  88}
  89
  90static bool wait_for_payload_credits(struct intel_display *display,
  91				     enum transcoder dsi_trans, int payld_credit)
  92{
  93	int ret, available;
  94
  95	ret = poll_timeout_us(available = payload_credits_available(display, dsi_trans),
  96			      available >= payld_credit,
  97			      10, 100, false);
  98	if (ret) {
  99		drm_err(display->drm, "DSI payload credits not released\n");
 100		return false;
 101	}
 102
 103	return true;
 104}
 105
 106static enum transcoder dsi_port_to_transcoder(enum port port)
 107{
 108	if (port == PORT_A)
 109		return TRANSCODER_DSI_0;
 110	else
 111		return TRANSCODER_DSI_1;
 112}
 113
 114static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
 115{
 116	struct intel_display *display = to_intel_display(encoder);
 117	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 118	struct mipi_dsi_device *dsi;
 119	enum port port;
 120	enum transcoder dsi_trans;
 121	int ret;
 122
 123	/* wait for header/payload credits to be released */
 124	for_each_dsi_port(port, intel_dsi->ports) {
 125		dsi_trans = dsi_port_to_transcoder(port);
 126		wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
 127		wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT);
 128	}
 129
 130	/* send nop DCS command */
 131	for_each_dsi_port(port, intel_dsi->ports) {
 132		dsi = intel_dsi->dsi_hosts[port]->device;
 133		dsi->mode_flags |= MIPI_DSI_MODE_LPM;
 134		dsi->channel = 0;
 135		ret = mipi_dsi_dcs_nop(dsi);
 136		if (ret < 0)
 137			drm_err(display->drm,
 138				"error sending DCS NOP command\n");
 139	}
 140
 141	/* wait for header credits to be released */
 142	for_each_dsi_port(port, intel_dsi->ports) {
 143		dsi_trans = dsi_port_to_transcoder(port);
 144		wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
 145	}
 146
 147	/* wait for LP TX in progress bit to be cleared */
 148	for_each_dsi_port(port, intel_dsi->ports) {
 149		dsi_trans = dsi_port_to_transcoder(port);
 150
 151		ret = intel_de_wait_for_clear_us(display,
 152						 DSI_LP_MSG(dsi_trans),
 153						 LPTX_IN_PROGRESS, 20);
 154		if (ret)
 155			drm_err(display->drm, "LPTX bit not cleared\n");
 156	}
 157}
 158
 159static int dsi_send_pkt_payld(struct intel_dsi_host *host,
 160			      const struct mipi_dsi_packet *packet)
 161{
 162	struct intel_dsi *intel_dsi = host->intel_dsi;
 163	struct intel_display *display = to_intel_display(&intel_dsi->base);
 164	enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 165	const u8 *data = packet->payload;
 166	u32 len = packet->payload_length;
 167	int i, j;
 168
 169	/* payload queue can accept *256 bytes*, check limit */
 170	if (len > MAX_PLOAD_CREDIT * 4) {
 171		drm_err(display->drm, "payload size exceeds max queue limit\n");
 172		return -EINVAL;
 173	}
 174
 175	for (i = 0; i < len; i += 4) {
 176		u32 tmp = 0;
 177
 178		if (!wait_for_payload_credits(display, dsi_trans, 1))
 179			return -EBUSY;
 180
 181		for (j = 0; j < min_t(u32, len - i, 4); j++)
 182			tmp |= *data++ << 8 * j;
 183
 184		intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp);
 185	}
 186
 187	return 0;
 188}
 189
 190static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
 191			    const struct mipi_dsi_packet *packet,
 192			    bool enable_lpdt)
 193{
 194	struct intel_dsi *intel_dsi = host->intel_dsi;
 195	struct intel_display *display = to_intel_display(&intel_dsi->base);
 196	enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 197	u32 tmp;
 198
 199	if (!wait_for_header_credits(display, dsi_trans, 1))
 200		return -EBUSY;
 201
 202	tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));
 203
 204	if (packet->payload)
 205		tmp |= PAYLOAD_PRESENT;
 206	else
 207		tmp &= ~PAYLOAD_PRESENT;
 208
 209	tmp &= ~(VBLANK_FENCE | LP_DATA_TRANSFER | PIPELINE_FLUSH);
 210
 211	if (enable_lpdt)
 212		tmp |= LP_DATA_TRANSFER;
 213	else
 214		tmp |= PIPELINE_FLUSH;
 215
 216	tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
 217	tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT);
 218	tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT);
 219	tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT);
 220	tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT);
 221	intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp);
 222
 223	return 0;
 224}
 225
 226void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
 227{
 228	struct intel_display *display = to_intel_display(crtc_state);
 229	u32 mode_flags;
 230	enum port port;
 231
 232	mode_flags = crtc_state->mode_flags;
 233
 234	/*
 235	 * case 1 also covers dual link
 236	 * In case of dual link, frame update should be set on
 237	 * DSI_0
 238	 */
 239	if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0)
 240		port = PORT_A;
 241	else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
 242		port = PORT_B;
 243	else
 244		return;
 245
 246	intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0,
 247		     DSI_FRAME_UPDATE_REQUEST);
 248}
 249
 250static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 251{
 252	struct intel_display *display = to_intel_display(encoder);
 253	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 254	enum phy phy;
 255	u32 tmp, mask, val;
 256	int lane;
 257
 258	for_each_dsi_phy(phy, intel_dsi->phys) {
 259		/*
 260		 * Program voltage swing and pre-emphasis level values as per
 261		 * table in BSPEC under DDI buffer programming.
 262		 */
 263		mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK;
 264		val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE |
 265		      RTERM_SELECT(0x6);
 266		tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
 267		tmp &= ~mask;
 268		tmp |= val;
 269		intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
 270		intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val);
 271
 272		mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 273		       RCOMP_SCALAR_MASK;
 274		val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) |
 275		      RCOMP_SCALAR(0x98);
 276		tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
 277		tmp &= ~mask;
 278		tmp |= val;
 279		intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
 280		intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val);
 281
 282		mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 283		       CURSOR_COEFF_MASK;
 284		val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) |
 285		      CURSOR_COEFF(0x3f);
 286		intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val);
 287
 288		/* Bspec: must not use GRP register for write */
 289		for (lane = 0; lane <= 3; lane++)
 290			intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
 291				     mask, val);
 292	}
 293}
 294
 295static void configure_dual_link_mode(struct intel_encoder *encoder,
 296				     const struct intel_crtc_state *pipe_config)
 297{
 298	struct intel_display *display = to_intel_display(encoder);
 299	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 300	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
 301	u32 dss_ctl1;
 302
 303	/* FIXME: Move all DSS handling to intel_vdsc.c */
 304	if (DISPLAY_VER(display) >= 12) {
 305		struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 306
 307		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
 308		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
 309	} else {
 310		dss_ctl1_reg = DSS_CTL1;
 311		dss_ctl2_reg = DSS_CTL2;
 312	}
 313
 314	dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
 315	dss_ctl1 |= SPLITTER_ENABLE;
 316	dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
 317	dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
 318
 319	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 320		const struct drm_display_mode *adjusted_mode =
 321					&pipe_config->hw.adjusted_mode;
 322		u16 hactive = adjusted_mode->crtc_hdisplay;
 323		u16 dl_buffer_depth;
 324
 325		dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
 326		dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
 327
 328		if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
 329			drm_err(display->drm,
 330				"DL buffer depth exceed max value\n");
 331
 332		dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
 333		dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
 334		intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
 335			     RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
 336	} else {
 337		/* Interleave */
 338		dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
 339	}
 340
 341	intel_de_write(display, dss_ctl1_reg, dss_ctl1);
 342}
 343
 344/* aka DSI 8X clock */
 345static int afe_clk(struct intel_encoder *encoder,
 346		   const struct intel_crtc_state *crtc_state)
 347{
 348	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 349	int bpp;
 350
 351	if (crtc_state->dsc.compression_enable)
 352		bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
 353	else
 354		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 355
 356	return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
 357}
 358
 359static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
 360					  const struct intel_crtc_state *crtc_state)
 361{
 362	struct intel_display *display = to_intel_display(encoder);
 363	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 364	enum port port;
 365	int afe_clk_khz;
 366	int theo_word_clk, act_word_clk;
 367	u32 esc_clk_div_m, esc_clk_div_m_phy;
 368
 369	afe_clk_khz = afe_clk(encoder, crtc_state);
 370
 371	if (display->platform.alderlake_s || display->platform.alderlake_p) {
 372		theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK);
 373		act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2);
 374		esc_clk_div_m = act_word_clk * 8;
 375		esc_clk_div_m_phy = (act_word_clk - 1) / 2;
 376	} else {
 377		esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
 378	}
 379
 380	for_each_dsi_port(port, intel_dsi->ports) {
 381		intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port),
 382			       esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 383		intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port));
 384	}
 385
 386	for_each_dsi_port(port, intel_dsi->ports) {
 387		intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port),
 388			       esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 389		intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port));
 390	}
 391
 392	if (display->platform.alderlake_s || display->platform.alderlake_p) {
 393		for_each_dsi_port(port, intel_dsi->ports) {
 394			intel_de_write(display, ADL_MIPIO_DW(port, 8),
 395				       esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
 396			intel_de_posting_read(display, ADL_MIPIO_DW(port, 8));
 397		}
 398	}
 399}
 400
 401static void get_dsi_io_power_domains(struct intel_dsi *intel_dsi)
 402{
 403	struct intel_display *display = to_intel_display(&intel_dsi->base);
 404	enum port port;
 405
 406	for_each_dsi_port(port, intel_dsi->ports) {
 407		drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]);
 408		intel_dsi->io_wakeref[port] =
 409			intel_display_power_get(display,
 410						port == PORT_A ?
 411						POWER_DOMAIN_PORT_DDI_IO_A :
 412						POWER_DOMAIN_PORT_DDI_IO_B);
 413	}
 414}
 415
 416static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
 417{
 418	struct intel_display *display = to_intel_display(encoder);
 419	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 420	enum port port;
 421
 422	for_each_dsi_port(port, intel_dsi->ports)
 423		intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
 424			     0, COMBO_PHY_MODE_DSI);
 425
 426	get_dsi_io_power_domains(intel_dsi);
 427}
 428
 429static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
 430{
 431	struct intel_display *display = to_intel_display(encoder);
 432	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 433	enum phy phy;
 434
 435	for_each_dsi_phy(phy, intel_dsi->phys)
 436		intel_combo_phy_power_up_lanes(display, phy, true,
 437					       intel_dsi->lane_count, false);
 438}
 439
 440static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 441{
 442	struct intel_display *display = to_intel_display(encoder);
 443	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 444	enum phy phy;
 445	u32 tmp;
 446	int lane;
 447
 448	/* Step 4b(i) set loadgen select for transmit and aux lanes */
 449	for_each_dsi_phy(phy, intel_dsi->phys) {
 450		intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy),
 451			     LOADGEN_SELECT, 0);
 452		for (lane = 0; lane <= 3; lane++)
 453			intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
 454				     LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0);
 455	}
 456
 457	/* Step 4b(ii) set latency optimization for transmit and aux lanes */
 458	for_each_dsi_phy(phy, intel_dsi->phys) {
 459		intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy),
 460			     FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5));
 461		tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
 462		tmp &= ~FRC_LATENCY_OPTIM_MASK;
 463		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 464		intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
 465
 466		/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
 467		if (display->platform.jasperlake || display->platform.elkhartlake ||
 468		    (DISPLAY_VER(display) >= 12)) {
 469			intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy),
 470				     LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
 471
 472			tmp = intel_de_read(display,
 473					    ICL_PORT_PCS_DW1_LN(0, phy));
 474			tmp &= ~LATENCY_OPTIM_MASK;
 475			tmp |= LATENCY_OPTIM_VAL(0x1);
 476			intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy),
 477				       tmp);
 478		}
 479	}
 480
 481}
 482
 483static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
 484{
 485	struct intel_display *display = to_intel_display(encoder);
 486	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 487	u32 tmp;
 488	enum phy phy;
 489
 490	/* clear common keeper enable bit */
 491	for_each_dsi_phy(phy, intel_dsi->phys) {
 492		tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
 493		tmp &= ~COMMON_KEEPER_EN;
 494		intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp);
 495		intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);
 496	}
 497
 498	/*
 499	 * Set SUS Clock Config bitfield to 11b
 500	 * Note: loadgen select program is done
 501	 * as part of lane phy sequence configuration
 502	 */
 503	for_each_dsi_phy(phy, intel_dsi->phys)
 504		intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0,
 505			     SUS_CLOCK_CONFIG);
 506
 507	/* Clear training enable to change swing values */
 508	for_each_dsi_phy(phy, intel_dsi->phys) {
 509		tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
 510		tmp &= ~TX_TRAINING_EN;
 511		intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
 512		intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);
 513	}
 514
 515	/* Program swing and de-emphasis */
 516	dsi_program_swing_and_deemphasis(encoder);
 517
 518	/* Set training enable to trigger update */
 519	for_each_dsi_phy(phy, intel_dsi->phys) {
 520		tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
 521		tmp |= TX_TRAINING_EN;
 522		intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
 523		intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);
 524	}
 525}
 526
 527static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
 528{
 529	struct intel_display *display = to_intel_display(encoder);
 530	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 531	enum port port;
 532	int ret;
 533
 534	for_each_dsi_port(port, intel_dsi->ports) {
 535		intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
 536
 537		ret = intel_de_wait_for_clear_us(display, DDI_BUF_CTL(port),
 538						 DDI_BUF_IS_IDLE, 500);
 539		if (ret)
 540			drm_err(display->drm, "DDI port:%c buffer idle\n",
 541				port_name(port));
 542	}
 543}
 544
 545static void
 546gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
 547			     const struct intel_crtc_state *crtc_state)
 548{
 549	struct intel_display *display = to_intel_display(encoder);
 550	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 551	enum port port;
 552	enum phy phy;
 553
 554	/* Program DPHY clock lanes timings */
 555	for_each_dsi_port(port, intel_dsi->ports)
 556		intel_de_write(display, DPHY_CLK_TIMING_PARAM(port),
 557			       intel_dsi->dphy_reg);
 558
 559	/* Program DPHY data lanes timings */
 560	for_each_dsi_port(port, intel_dsi->ports)
 561		intel_de_write(display, DPHY_DATA_TIMING_PARAM(port),
 562			       intel_dsi->dphy_data_lane_reg);
 563
 564	/*
 565	 * If DSI link operating at or below an 800 MHz,
 566	 * TA_SURE should be override and programmed to
 567	 * a value '0' inside TA_PARAM_REGISTERS otherwise
 568	 * leave all fields at HW default values.
 569	 */
 570	if (DISPLAY_VER(display) == 11) {
 571		if (afe_clk(encoder, crtc_state) <= 800000) {
 572			for_each_dsi_port(port, intel_dsi->ports)
 573				intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port),
 574					     TA_SURE_MASK,
 575					     TA_SURE_OVERRIDE | TA_SURE(0));
 576		}
 577	}
 578
 579	if (display->platform.jasperlake || display->platform.elkhartlake) {
 580		for_each_dsi_phy(phy, intel_dsi->phys)
 581			intel_de_rmw(display, ICL_DPHY_CHKN(phy),
 582				     0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
 583	}
 584}
 585
 586static void
 587gen11_dsi_setup_timings(struct intel_encoder *encoder,
 588			const struct intel_crtc_state *crtc_state)
 589{
 590	struct intel_display *display = to_intel_display(encoder);
 591	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 592	enum port port;
 593
 594	/* Program T-INIT master registers */
 595	for_each_dsi_port(port, intel_dsi->ports)
 596		intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port),
 597			     DSI_T_INIT_MASTER_MASK, intel_dsi->init_count);
 598
 599	/* shadow register inside display core */
 600	for_each_dsi_port(port, intel_dsi->ports)
 601		intel_de_write(display, DSI_CLK_TIMING_PARAM(port),
 602			       intel_dsi->dphy_reg);
 603
 604	/* shadow register inside display core */
 605	for_each_dsi_port(port, intel_dsi->ports)
 606		intel_de_write(display, DSI_DATA_TIMING_PARAM(port),
 607			       intel_dsi->dphy_data_lane_reg);
 608
 609	/* shadow register inside display core */
 610	if (DISPLAY_VER(display) == 11) {
 611		if (afe_clk(encoder, crtc_state) <= 800000) {
 612			for_each_dsi_port(port, intel_dsi->ports) {
 613				intel_de_rmw(display, DSI_TA_TIMING_PARAM(port),
 614					     TA_SURE_MASK,
 615					     TA_SURE_OVERRIDE | TA_SURE(0));
 616			}
 617		}
 618	}
 619}
 620
 621static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
 622{
 623	struct intel_display *display = to_intel_display(encoder);
 624	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 625	u32 tmp;
 626	enum phy phy;
 627
 628	mutex_lock(&display->dpll.lock);
 629	tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
 630	for_each_dsi_phy(phy, intel_dsi->phys)
 631		tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 632
 633	intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
 634	mutex_unlock(&display->dpll.lock);
 635}
 636
 637static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
 638{
 639	struct intel_display *display = to_intel_display(encoder);
 640	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 641	u32 tmp;
 642	enum phy phy;
 643
 644	mutex_lock(&display->dpll.lock);
 645	tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
 646	for_each_dsi_phy(phy, intel_dsi->phys)
 647		tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 648
 649	intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
 650	mutex_unlock(&display->dpll.lock);
 651}
 652
 653static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
 654{
 655	struct intel_display *display = to_intel_display(encoder);
 656	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 657	bool clock_enabled = false;
 658	enum phy phy;
 659	u32 tmp;
 660
 661	tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
 662
 663	for_each_dsi_phy(phy, intel_dsi->phys) {
 664		if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
 665			clock_enabled = true;
 666	}
 667
 668	return clock_enabled;
 669}
 670
 671static void gen11_dsi_map_pll(struct intel_encoder *encoder,
 672			      const struct intel_crtc_state *crtc_state)
 673{
 674	struct intel_display *display = to_intel_display(encoder);
 675	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 676	struct intel_dpll *pll = crtc_state->intel_dpll;
 677	enum phy phy;
 678	u32 val;
 679
 680	mutex_lock(&display->dpll.lock);
 681
 682	val = intel_de_read(display, ICL_DPCLKA_CFGCR0);
 683	for_each_dsi_phy(phy, intel_dsi->phys) {
 684		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
 685		val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 686	}
 687	intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
 688
 689	for_each_dsi_phy(phy, intel_dsi->phys) {
 690		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 691	}
 692	intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
 693
 694	intel_de_posting_read(display, ICL_DPCLKA_CFGCR0);
 695
 696	mutex_unlock(&display->dpll.lock);
 697}
 698
 699static void
 700gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 701			       const struct intel_crtc_state *pipe_config)
 702{
 703	struct intel_display *display = to_intel_display(encoder);
 704	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 705	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 706	enum pipe pipe = crtc->pipe;
 707	u32 tmp;
 708	enum port port;
 709	enum transcoder dsi_trans;
 710
 711	for_each_dsi_port(port, intel_dsi->ports) {
 712		dsi_trans = dsi_port_to_transcoder(port);
 713		tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
 714
 715		if (intel_dsi->eotp_pkt)
 716			tmp &= ~EOTP_DISABLED;
 717		else
 718			tmp |= EOTP_DISABLED;
 719
 720		/* enable link calibration if freq > 1.5Gbps */
 721		if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
 722			tmp &= ~LINK_CALIBRATION_MASK;
 723			tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
 724		}
 725
 726		/* configure continuous clock */
 727		tmp &= ~CONTINUOUS_CLK_MASK;
 728		if (intel_dsi->clock_stop)
 729			tmp |= CLK_ENTER_LP_AFTER_DATA;
 730		else
 731			tmp |= CLK_HS_CONTINUOUS;
 732
 733		/* configure buffer threshold limit to minimum */
 734		tmp &= ~PIX_BUF_THRESHOLD_MASK;
 735		tmp |= PIX_BUF_THRESHOLD_1_4;
 736
 737		/* set virtual channel to '0' */
 738		tmp &= ~PIX_VIRT_CHAN_MASK;
 739		tmp |= PIX_VIRT_CHAN(0);
 740
 741		/* program BGR transmission */
 742		if (intel_dsi->bgr_enabled)
 743			tmp |= BGR_TRANSMISSION;
 744
 745		/* select pixel format */
 746		tmp &= ~PIX_FMT_MASK;
 747		if (pipe_config->dsc.compression_enable) {
 748			tmp |= PIX_FMT_COMPRESSED;
 749		} else {
 750			switch (intel_dsi->pixel_format) {
 751			default:
 752				MISSING_CASE(intel_dsi->pixel_format);
 753				fallthrough;
 754			case MIPI_DSI_FMT_RGB565:
 755				tmp |= PIX_FMT_RGB565;
 756				break;
 757			case MIPI_DSI_FMT_RGB666_PACKED:
 758				tmp |= PIX_FMT_RGB666_PACKED;
 759				break;
 760			case MIPI_DSI_FMT_RGB666:
 761				tmp |= PIX_FMT_RGB666_LOOSE;
 762				break;
 763			case MIPI_DSI_FMT_RGB888:
 764				tmp |= PIX_FMT_RGB888;
 765				break;
 766			}
 767		}
 768
 769		if (DISPLAY_VER(display) >= 12) {
 770			if (is_vid_mode(intel_dsi))
 771				tmp |= BLANKING_PACKET_ENABLE;
 772		}
 773
 774		/* program DSI operation mode */
 775		if (is_vid_mode(intel_dsi)) {
 776			tmp &= ~OP_MODE_MASK;
 777			switch (intel_dsi->video_mode) {
 778			default:
 779				MISSING_CASE(intel_dsi->video_mode);
 780				fallthrough;
 781			case NON_BURST_SYNC_EVENTS:
 782				tmp |= VIDEO_MODE_SYNC_EVENT;
 783				break;
 784			case NON_BURST_SYNC_PULSE:
 785				tmp |= VIDEO_MODE_SYNC_PULSE;
 786				break;
 787			}
 788		} else {
 789			/*
 790			 * FIXME: Retrieve this info from VBT.
 791			 * As per the spec when dsi transcoder is operating
 792			 * in TE GATE mode, TE comes from GPIO
 793			 * which is UTIL PIN for DSI 0.
 794			 * Also this GPIO would not be used for other
 795			 * purposes is an assumption.
 796			 */
 797			tmp &= ~OP_MODE_MASK;
 798			tmp |= CMD_MODE_TE_GATE;
 799			tmp |= TE_SOURCE_GPIO;
 800		}
 801
 802		intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
 803	}
 804
 805	/* enable port sync mode if dual link */
 806	if (intel_dsi->dual_link) {
 807		for_each_dsi_port(port, intel_dsi->ports) {
 808			dsi_trans = dsi_port_to_transcoder(port);
 809			intel_de_rmw(display,
 810				     TRANS_DDI_FUNC_CTL2(display, dsi_trans),
 811				     0, PORT_SYNC_MODE_ENABLE);
 812		}
 813
 814		/* configure stream splitting */
 815		configure_dual_link_mode(encoder, pipe_config);
 816	}
 817
 818	for_each_dsi_port(port, intel_dsi->ports) {
 819		dsi_trans = dsi_port_to_transcoder(port);
 820
 821		/* select data lane width */
 822		tmp = intel_de_read(display,
 823				    TRANS_DDI_FUNC_CTL(display, dsi_trans));
 824		tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
 825		tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count);
 826
 827		/* select input pipe */
 828		tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
 829		switch (pipe) {
 830		default:
 831			MISSING_CASE(pipe);
 832			fallthrough;
 833		case PIPE_A:
 834			tmp |= TRANS_DDI_EDP_INPUT_A_ON;
 835			break;
 836		case PIPE_B:
 837			tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 838			break;
 839		case PIPE_C:
 840			tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 841			break;
 842		case PIPE_D:
 843			tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
 844			break;
 845		}
 846
 847		/* enable DDI buffer */
 848		tmp |= TRANS_DDI_FUNC_ENABLE;
 849		intel_de_write(display,
 850			       TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp);
 851	}
 852
 853	/* wait for link ready */
 854	for_each_dsi_port(port, intel_dsi->ports) {
 855		int ret;
 856
 857		dsi_trans = dsi_port_to_transcoder(port);
 858
 859		ret = intel_de_wait_for_set_us(display,
 860					       DSI_TRANS_FUNC_CONF(dsi_trans),
 861					       LINK_READY, 2500);
 862		if (ret)
 863			drm_err(display->drm, "DSI link not ready\n");
 864	}
 865}
 866
 867static void
 868gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 869				 const struct intel_crtc_state *crtc_state)
 870{
 871	struct intel_display *display = to_intel_display(encoder);
 872	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 873	const struct drm_display_mode *adjusted_mode =
 874		&crtc_state->hw.adjusted_mode;
 875	enum port port;
 876	enum transcoder dsi_trans;
 877	/* horizontal timings */
 878	u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
 879	u16 hback_porch;
 880	/* vertical timings */
 881	u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
 882	int mul = 1, div = 1;
 883
 884	/*
 885	 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
 886	 * for slower link speed if DSC is enabled.
 887	 *
 888	 * The compression frequency ratio is the ratio between compressed and
 889	 * non-compressed link speeds, and simplifies down to the ratio between
 890	 * compressed and non-compressed bpp.
 891	 */
 892	if (is_vid_mode(intel_dsi) && crtc_state->dsc.compression_enable) {
 893		mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
 894		div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 895	}
 896
 897	hactive = adjusted_mode->crtc_hdisplay;
 898
 899	if (is_vid_mode(intel_dsi))
 900		htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
 901	else
 902		htotal = DIV_ROUND_UP((hactive + 160) * mul, div);
 903
 904	hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
 905	hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
 906	hsync_size  = hsync_end - hsync_start;
 907	hback_porch = (adjusted_mode->crtc_htotal -
 908		       adjusted_mode->crtc_hsync_end);
 909	vactive = adjusted_mode->crtc_vdisplay;
 910
 911	if (is_vid_mode(intel_dsi)) {
 912		vtotal = adjusted_mode->crtc_vtotal;
 913	} else {
 914		int bpp, line_time_us, byte_clk_period_ns;
 915
 916		if (crtc_state->dsc.compression_enable)
 917			bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
 918		else
 919			bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 920
 921		byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state);
 922		line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
 923		vtotal = vactive + DIV_ROUND_UP(400, line_time_us);
 924	}
 925	vsync_start = adjusted_mode->crtc_vsync_start;
 926	vsync_end = adjusted_mode->crtc_vsync_end;
 927	vsync_shift = hsync_start - htotal / 2;
 928
 929	if (intel_dsi->dual_link) {
 930		hactive /= 2;
 931		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 932			hactive += intel_dsi->pixel_overlap;
 933		htotal /= 2;
 934	}
 935
 936	/* minimum hactive as per bspec: 256 pixels */
 937	if (adjusted_mode->crtc_hdisplay < 256)
 938		drm_err(display->drm, "hactive is less then 256 pixels\n");
 939
 940	/* if RGB666 format, then hactive must be multiple of 4 pixels */
 941	if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
 942		drm_err(display->drm,
 943			"hactive pixels are not multiple of 4\n");
 944
 945	/* program TRANS_HTOTAL register */
 946	for_each_dsi_port(port, intel_dsi->ports) {
 947		dsi_trans = dsi_port_to_transcoder(port);
 948		intel_de_write(display, TRANS_HTOTAL(display, dsi_trans),
 949			       HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
 950	}
 951
 952	/* TRANS_HSYNC register to be programmed only for video mode */
 953	if (is_vid_mode(intel_dsi)) {
 954		if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) {
 955			/* BSPEC: hsync size should be atleast 16 pixels */
 956			if (hsync_size < 16)
 957				drm_err(display->drm,
 958					"hsync size < 16 pixels\n");
 959		}
 960
 961		if (hback_porch < 16)
 962			drm_err(display->drm, "hback porch < 16 pixels\n");
 963
 964		if (intel_dsi->dual_link) {
 965			hsync_start /= 2;
 966			hsync_end /= 2;
 967		}
 968
 969		for_each_dsi_port(port, intel_dsi->ports) {
 970			dsi_trans = dsi_port_to_transcoder(port);
 971			intel_de_write(display,
 972				       TRANS_HSYNC(display, dsi_trans),
 973				       HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
 974		}
 975	}
 976
 977	/* program TRANS_VTOTAL register */
 978	for_each_dsi_port(port, intel_dsi->ports) {
 979		dsi_trans = dsi_port_to_transcoder(port);
 980		/*
 981		 * FIXME: Programming this by assuming progressive mode, since
 982		 * non-interlaced info from VBT is not saved inside
 983		 * struct drm_display_mode.
 984		 * For interlace mode: program required pixel minus 2
 985		 */
 986		intel_de_write(display, TRANS_VTOTAL(display, dsi_trans),
 987			       VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
 988	}
 989
 990	if (vsync_end < vsync_start || vsync_end > vtotal)
 991		drm_err(display->drm, "Invalid vsync_end value\n");
 992
 993	if (vsync_start < vactive)
 994		drm_err(display->drm, "vsync_start less than vactive\n");
 995
 996	/* program TRANS_VSYNC register for video mode only */
 997	if (is_vid_mode(intel_dsi)) {
 998		for_each_dsi_port(port, intel_dsi->ports) {
 999			dsi_trans = dsi_port_to_transcoder(port);
1000			intel_de_write(display,
1001				       TRANS_VSYNC(display, dsi_trans),
1002				       VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
1003		}
1004	}
1005
1006	/*
1007	 * FIXME: It has to be programmed only for video modes and interlaced
1008	 * modes. Put the check condition here once interlaced
1009	 * info available as described above.
1010	 * program TRANS_VSYNCSHIFT register
1011	 */
1012	if (is_vid_mode(intel_dsi)) {
1013		for_each_dsi_port(port, intel_dsi->ports) {
1014			dsi_trans = dsi_port_to_transcoder(port);
1015			intel_de_write(display,
1016				       TRANS_VSYNCSHIFT(display, dsi_trans),
1017				       vsync_shift);
1018		}
1019	}
1020
1021	/*
1022	 * program TRANS_VBLANK register, should be same as vtotal programmed
1023	 *
1024	 * FIXME get rid of these local hacks and do it right,
1025	 * this will not handle eg. delayed vblank correctly.
1026	 */
1027	if (DISPLAY_VER(display) >= 12) {
1028		for_each_dsi_port(port, intel_dsi->ports) {
1029			dsi_trans = dsi_port_to_transcoder(port);
1030			intel_de_write(display,
1031				       TRANS_VBLANK(display, dsi_trans),
1032				       VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
1033		}
1034	}
1035}
1036
1037static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
1038{
1039	struct intel_display *display = to_intel_display(encoder);
1040	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1041	enum port port;
1042	enum transcoder dsi_trans;
1043
1044	for_each_dsi_port(port, intel_dsi->ports) {
1045		dsi_trans = dsi_port_to_transcoder(port);
1046		intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0,
1047			     TRANSCONF_ENABLE);
1048
1049		/* wait for transcoder to be enabled */
1050		if (intel_de_wait_for_set_ms(display, TRANSCONF(display, dsi_trans),
1051					     TRANSCONF_STATE_ENABLE, 10))
1052			drm_err(display->drm,
1053				"DSI transcoder not enabled\n");
1054	}
1055}
1056
1057static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
1058				     const struct intel_crtc_state *crtc_state)
1059{
1060	struct intel_display *display = to_intel_display(encoder);
1061	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1062	enum port port;
1063	enum transcoder dsi_trans;
1064	u32 hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
1065
1066	/*
1067	 * escape clock count calculation:
1068	 * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
1069	 * UI (nsec) = (10^6)/Bitrate
1070	 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
1071	 * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
1072	 */
1073	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
1074	mul = 8 * 1000000;
1075	hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
1076				     divisor);
1077	lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
1078	ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
1079
1080	for_each_dsi_port(port, intel_dsi->ports) {
1081		dsi_trans = dsi_port_to_transcoder(port);
1082
1083		/* program hst_tx_timeout */
1084		intel_de_rmw(display, DSI_HSTX_TO(dsi_trans),
1085			     HSTX_TIMEOUT_VALUE_MASK,
1086			     HSTX_TIMEOUT_VALUE(hs_tx_timeout));
1087
1088		/* FIXME: DSI_CALIB_TO */
1089
1090		/* program lp_rx_host timeout */
1091		intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans),
1092			     LPRX_TIMEOUT_VALUE_MASK,
1093			     LPRX_TIMEOUT_VALUE(lp_rx_timeout));
1094
1095		/* FIXME: DSI_PWAIT_TO */
1096
1097		/* program turn around timeout */
1098		intel_de_rmw(display, DSI_TA_TO(dsi_trans),
1099			     TA_TIMEOUT_VALUE_MASK,
1100			     TA_TIMEOUT_VALUE(ta_timeout));
1101	}
1102}
1103
1104static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
1105				      bool enable)
1106{
1107	struct intel_display *display = to_intel_display(encoder);
1108	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1109	u32 tmp;
1110
1111	/*
1112	 * used as TE i/p for DSI0,
1113	 * for dual link/DSI1 TE is from slave DSI1
1114	 * through GPIO.
1115	 */
1116	if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
1117		return;
1118
1119	tmp = intel_de_read(display, UTIL_PIN_CTL);
1120
1121	if (enable) {
1122		tmp |= UTIL_PIN_DIRECTION_INPUT;
1123		tmp |= UTIL_PIN_ENABLE;
1124	} else {
1125		tmp &= ~UTIL_PIN_ENABLE;
1126	}
1127	intel_de_write(display, UTIL_PIN_CTL, tmp);
1128}
1129
1130static void
1131gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
1132			      const struct intel_crtc_state *crtc_state)
1133{
1134	/* step 4a: power up all lanes of the DDI used by DSI */
1135	gen11_dsi_power_up_lanes(encoder);
1136
1137	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
1138	gen11_dsi_config_phy_lanes_sequence(encoder);
1139
1140	/* step 4c: configure voltage swing and skew */
1141	gen11_dsi_voltage_swing_program_seq(encoder);
1142
1143	/* setup D-PHY timings */
1144	gen11_dsi_setup_dphy_timings(encoder, crtc_state);
1145
1146	/* enable DDI buffer */
1147	gen11_dsi_enable_ddi_buffer(encoder);
1148
1149	gen11_dsi_gate_clocks(encoder);
1150
1151	gen11_dsi_setup_timings(encoder, crtc_state);
1152
1153	/* Since transcoder is configured to take events from GPIO */
1154	gen11_dsi_config_util_pin(encoder, true);
1155
1156	/* step 4h: setup DSI protocol timeouts */
1157	gen11_dsi_setup_timeouts(encoder, crtc_state);
1158
1159	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
1160	gen11_dsi_configure_transcoder(encoder, crtc_state);
1161}
1162
1163static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
1164{
1165	struct intel_display *display = to_intel_display(encoder);
1166	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1167	struct mipi_dsi_device *dsi;
1168	enum port port;
1169	enum transcoder dsi_trans;
1170	u32 tmp;
1171	int ret;
1172
1173	/* set maximum return packet size */
1174	for_each_dsi_port(port, intel_dsi->ports) {
1175		dsi_trans = dsi_port_to_transcoder(port);
1176
1177		/*
1178		 * FIXME: This uses the number of DW's currently in the payload
1179		 * receive queue. This is probably not what we want here.
1180		 */
1181		tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));
1182		tmp &= NUMBER_RX_PLOAD_DW_MASK;
1183		/* multiply "Number Rx Payload DW" by 4 to get max value */
1184		tmp = tmp * 4;
1185		dsi = intel_dsi->dsi_hosts[port]->device;
1186		ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
1187		if (ret < 0)
1188			drm_err(display->drm,
1189				"error setting max return pkt size%d\n", tmp);
1190	}
1191
1192	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
1193
1194	/* ensure all panel commands dispatched before enabling transcoder */
1195	wait_for_cmds_dispatched_to_panel(encoder);
1196}
1197
1198static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state,
1199				     struct intel_encoder *encoder,
1200				     const struct intel_crtc_state *crtc_state,
1201				     const struct drm_connector_state *conn_state)
1202{
1203	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1204
1205	intel_dsi_wait_panel_power_cycle(intel_dsi);
1206
1207	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
1208	msleep(intel_dsi->panel_on_delay);
1209	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
1210
1211	/* step2: enable IO power */
1212	gen11_dsi_enable_io_power(encoder);
1213
1214	/* step3: enable DSI PLL */
1215	gen11_dsi_program_esc_clk_div(encoder, crtc_state);
1216}
1217
1218static void gen11_dsi_pre_enable(struct intel_atomic_state *state,
1219				 struct intel_encoder *encoder,
1220				 const struct intel_crtc_state *pipe_config,
1221				 const struct drm_connector_state *conn_state)
1222{
1223	/* step3b */
1224	gen11_dsi_map_pll(encoder, pipe_config);
1225
1226	/* step4: enable DSI port and DPHY */
1227	gen11_dsi_enable_port_and_phy(encoder, pipe_config);
1228
1229	/* step5: program and powerup panel */
1230	gen11_dsi_powerup_panel(encoder);
1231
1232	intel_dsc_dsi_pps_write(encoder, pipe_config);
1233
1234	/* step6c: configure transcoder timings */
1235	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
1236}
1237
1238/*
1239 * Wa_1409054076:icl,jsl,ehl
1240 * When pipe A is disabled and MIPI DSI is enabled on pipe B,
1241 * the AMT KVMR feature will incorrectly see pipe A as enabled.
1242 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
1243 * it set while DSI is enabled on pipe B
1244 */
1245static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
1246				     enum pipe pipe, bool enable)
1247{
1248	struct intel_display *display = to_intel_display(encoder);
1249
1250	if (DISPLAY_VER(display) == 11 && pipe == PIPE_B)
1251		intel_de_rmw(display, CHICKEN_PAR1_1,
1252			     IGNORE_KVMR_PIPE_A,
1253			     enable ? IGNORE_KVMR_PIPE_A : 0);
1254}
1255
1256/*
1257 * Wa_16012360555:adl-p
1258 * SW will have to program the "LP to HS Wakeup Guardband"
1259 * to account for the repeaters on the HS Request/Ready
1260 * PPI signaling between the Display engine and the DPHY.
1261 */
1262static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
1263{
1264	struct intel_display *display = to_intel_display(encoder);
1265	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1266	enum port port;
1267
1268	if (DISPLAY_VER(display) == 13) {
1269		for_each_dsi_port(port, intel_dsi->ports)
1270			intel_de_rmw(display, TGL_DSI_CHKN_REG(port),
1271				     TGL_DSI_CHKN_LSHS_GB_MASK,
1272				     TGL_DSI_CHKN_LSHS_GB(4));
1273	}
1274}
1275
1276static void gen11_dsi_enable(struct intel_atomic_state *state,
1277			     struct intel_encoder *encoder,
1278			     const struct intel_crtc_state *crtc_state,
1279			     const struct drm_connector_state *conn_state)
1280{
1281	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1282	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1283
1284	/* Wa_1409054076:icl,jsl,ehl */
1285	icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);
1286
1287	/* Wa_16012360555:adl-p */
1288	adlp_set_lp_hs_wakeup_gb(encoder);
1289
1290	/* step6d: enable dsi transcoder */
1291	gen11_dsi_enable_transcoder(encoder);
1292
1293	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
1294
1295	/* step7: enable backlight */
1296	intel_backlight_enable(crtc_state, conn_state);
1297	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
1298
1299	intel_panel_prepare(crtc_state, conn_state);
1300
1301	intel_crtc_vblank_on(crtc_state);
1302}
1303
1304static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1305{
1306	struct intel_display *display = to_intel_display(encoder);
1307	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1308	enum port port;
1309	enum transcoder dsi_trans;
1310
1311	for_each_dsi_port(port, intel_dsi->ports) {
1312		dsi_trans = dsi_port_to_transcoder(port);
1313
1314		/* disable transcoder */
1315		intel_de_rmw(display, TRANSCONF(display, dsi_trans),
1316			     TRANSCONF_ENABLE, 0);
1317
1318		/* wait for transcoder to be disabled */
1319		if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, dsi_trans),
1320					       TRANSCONF_STATE_ENABLE, 50))
1321			drm_err(display->drm,
1322				"DSI trancoder not disabled\n");
1323	}
1324}
1325
1326static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
1327{
1328	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1329
1330	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
1331
1332	/* ensure cmds dispatched to panel */
1333	wait_for_cmds_dispatched_to_panel(encoder);
1334}
1335
1336static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1337{
1338	struct intel_display *display = to_intel_display(encoder);
1339	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1340	enum port port;
1341	enum transcoder dsi_trans;
1342	u32 tmp;
1343	int ret;
1344
1345	/* disable periodic update mode */
1346	if (is_cmd_mode(intel_dsi)) {
1347		for_each_dsi_port(port, intel_dsi->ports)
1348			intel_de_rmw(display, DSI_CMD_FRMCTL(port),
1349				     DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0);
1350	}
1351
1352	/* put dsi link in ULPS */
1353	for_each_dsi_port(port, intel_dsi->ports) {
1354		dsi_trans = dsi_port_to_transcoder(port);
1355		tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));
1356		tmp |= LINK_ENTER_ULPS;
1357		tmp &= ~LINK_ULPS_TYPE_LP11;
1358		intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
1359
1360		ret = intel_de_wait_for_set_us(display, DSI_LP_MSG(dsi_trans),
1361					       LINK_IN_ULPS, 10);
1362		if (ret)
1363			drm_err(display->drm, "DSI link not in ULPS\n");
1364	}
1365
1366	/* disable ddi function */
1367	for_each_dsi_port(port, intel_dsi->ports) {
1368		dsi_trans = dsi_port_to_transcoder(port);
1369		intel_de_rmw(display,
1370			     TRANS_DDI_FUNC_CTL(display, dsi_trans),
1371			     TRANS_DDI_FUNC_ENABLE, 0);
1372	}
1373
1374	/* disable port sync mode if dual link */
1375	if (intel_dsi->dual_link) {
1376		for_each_dsi_port(port, intel_dsi->ports) {
1377			dsi_trans = dsi_port_to_transcoder(port);
1378			intel_de_rmw(display,
1379				     TRANS_DDI_FUNC_CTL2(display, dsi_trans),
1380				     PORT_SYNC_MODE_ENABLE, 0);
1381		}
1382	}
1383}
1384
1385static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1386{
1387	struct intel_display *display = to_intel_display(encoder);
1388	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1389	enum port port;
1390	int ret;
1391
1392	gen11_dsi_ungate_clocks(encoder);
1393	for_each_dsi_port(port, intel_dsi->ports) {
1394		intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
1395
1396		ret = intel_de_wait_for_set_us(display, DDI_BUF_CTL(port),
1397					       DDI_BUF_IS_IDLE, 8);
1398
1399		if (ret)
1400			drm_err(display->drm,
1401				"DDI port:%c buffer not idle\n",
1402				port_name(port));
1403	}
1404	gen11_dsi_gate_clocks(encoder);
1405}
1406
1407static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1408{
1409	struct intel_display *display = to_intel_display(encoder);
1410	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1411	enum port port;
1412
1413	for_each_dsi_port(port, intel_dsi->ports) {
1414		intel_wakeref_t wakeref;
1415
1416		wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1417		intel_display_power_put(display,
1418					port == PORT_A ?
1419					POWER_DOMAIN_PORT_DDI_IO_A :
1420					POWER_DOMAIN_PORT_DDI_IO_B,
1421					wakeref);
1422	}
1423
1424	/* set mode to DDI */
1425	for_each_dsi_port(port, intel_dsi->ports)
1426		intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
1427			     COMBO_PHY_MODE_DSI, 0);
1428}
1429
1430static void gen11_dsi_disable(struct intel_atomic_state *state,
1431			      struct intel_encoder *encoder,
1432			      const struct intel_crtc_state *old_crtc_state,
1433			      const struct drm_connector_state *old_conn_state)
1434{
1435	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1436
1437	intel_panel_unprepare(old_conn_state);
1438
1439	/* step1: turn off backlight */
1440	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
1441	intel_backlight_disable(old_conn_state);
1442}
1443
1444static void gen11_dsi_post_disable(struct intel_atomic_state *state,
1445				   struct intel_encoder *encoder,
1446				   const struct intel_crtc_state *old_crtc_state,
1447				   const struct drm_connector_state *old_conn_state)
1448{
1449	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1450	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1451
1452	intel_crtc_vblank_off(old_crtc_state);
1453
1454	/* step2d,e: disable transcoder and wait */
1455	gen11_dsi_disable_transcoder(encoder);
1456
1457	/* Wa_1409054076:icl,jsl,ehl */
1458	icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false);
1459
1460	/* step2f,g: powerdown panel */
1461	gen11_dsi_powerdown_panel(encoder);
1462
1463	/* step2h,i,j: deconfig trancoder */
1464	gen11_dsi_deconfigure_trancoder(encoder);
1465
1466	intel_dsc_disable(old_crtc_state);
1467	skl_scaler_disable(old_crtc_state);
1468
1469	/* step3: disable port */
1470	gen11_dsi_disable_port(encoder);
1471
1472	gen11_dsi_config_util_pin(encoder, false);
1473
1474	/* step4: disable IO power */
1475	gen11_dsi_disable_io_power(encoder);
1476
1477	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1478
1479	msleep(intel_dsi->panel_off_delay);
1480	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1481
1482	intel_dsi->panel_power_off_time = ktime_get_boottime();
1483}
1484
1485static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
1486						 const struct drm_display_mode *mode)
1487{
1488	struct intel_display *display = to_intel_display(connector->dev);
1489	enum drm_mode_status status;
1490
1491	status = intel_cpu_transcoder_mode_valid(display, mode);
1492	if (status != MODE_OK)
1493		return status;
1494
1495	/* FIXME: DSC? */
1496	return intel_dsi_mode_valid(connector, mode);
1497}
1498
1499static void gen11_dsi_get_timings(struct intel_encoder *encoder,
1500				  struct intel_crtc_state *pipe_config)
1501{
1502	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1503	struct drm_display_mode *adjusted_mode =
1504					&pipe_config->hw.adjusted_mode;
1505
1506	if (is_vid_mode(intel_dsi) && pipe_config->dsc.compressed_bpp_x16) {
1507		int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);
1508		int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1509
1510		adjusted_mode->crtc_htotal =
1511			DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
1512		adjusted_mode->crtc_hsync_start =
1513			DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
1514		adjusted_mode->crtc_hsync_end =
1515			DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
1516	}
1517
1518	if (intel_dsi->dual_link) {
1519		adjusted_mode->crtc_hdisplay *= 2;
1520		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1521			adjusted_mode->crtc_hdisplay -=
1522						intel_dsi->pixel_overlap;
1523		adjusted_mode->crtc_htotal *= 2;
1524	}
1525	adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1526	adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1527
1528	if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
1529		if (intel_dsi->dual_link) {
1530			adjusted_mode->crtc_hsync_start *= 2;
1531			adjusted_mode->crtc_hsync_end *= 2;
1532		}
1533	}
1534	adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1535	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1536}
1537
1538static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
1539{
1540	struct intel_display *display = to_intel_display(&intel_dsi->base);
1541	enum transcoder dsi_trans;
1542	u32 val;
1543
1544	if (intel_dsi->ports == BIT(PORT_B))
1545		dsi_trans = TRANSCODER_DSI_1;
1546	else
1547		dsi_trans = TRANSCODER_DSI_0;
1548
1549	val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
1550	return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
1551}
1552
1553static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi,
1554					  struct intel_crtc_state *pipe_config)
1555{
1556	if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
1557		pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 |
1558					    I915_MODE_FLAG_DSI_USE_TE0;
1559	else if (intel_dsi->ports == BIT(PORT_B))
1560		pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1;
1561	else
1562		pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0;
1563}
1564
1565static void gen11_dsi_get_config(struct intel_encoder *encoder,
1566				 struct intel_crtc_state *pipe_config)
1567{
1568	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1569	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1570
1571	intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder));
1572
1573	pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
1574	if (intel_dsi->dual_link)
1575		pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1576
1577	gen11_dsi_get_timings(encoder, pipe_config);
1578	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1579	pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
1580
1581	/* Get the details on which TE should be enabled */
1582	if (is_cmd_mode(intel_dsi))
1583		gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1584
1585	if (gen11_dsi_is_periodic_cmd_mode(intel_dsi))
1586		pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
1587}
1588
1589static void gen11_dsi_sync_state(struct intel_encoder *encoder,
1590				 const struct intel_crtc_state *crtc_state)
1591{
1592	struct intel_display *display = to_intel_display(encoder);
1593	struct intel_crtc *intel_crtc;
1594	enum pipe pipe;
1595
1596	if (!crtc_state)
1597		return;
1598
1599	intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1600	pipe = intel_crtc->pipe;
1601
1602	/* wa verify 1409054076:icl,jsl,ehl */
1603	if (DISPLAY_VER(display) == 11 && pipe == PIPE_B &&
1604	    !(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
1605		drm_dbg_kms(display->drm,
1606			    "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n",
1607			    encoder->base.base.id,
1608			    encoder->base.name);
1609}
1610
1611static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
1612					struct intel_crtc_state *crtc_state)
1613{
1614	struct intel_display *display = to_intel_display(encoder);
1615	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1616	int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10;
1617	bool use_dsc;
1618	int ret;
1619
1620	use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc);
1621	if (!use_dsc)
1622		return 0;
1623
1624	if (crtc_state->pipe_bpp < 8 * 3)
1625		return -EINVAL;
1626
1627	/* FIXME: split only when necessary */
1628	if (crtc_state->dsc.slice_count > 1)
1629		crtc_state->dsc.num_streams = 2;
1630	else
1631		crtc_state->dsc.num_streams = 1;
1632
1633	/* FIXME: initialize from VBT */
1634	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1635
1636	vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1637
1638	ret = intel_dsc_compute_params(crtc_state);
1639	if (ret)
1640		return ret;
1641
1642	/* DSI specific sanity checks on the common code */
1643	drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable);
1644	drm_WARN_ON(display->drm, vdsc_cfg->simple_422);
1645	drm_WARN_ON(display->drm,
1646		    vdsc_cfg->pic_width % vdsc_cfg->slice_width);
1647	drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8);
1648	drm_WARN_ON(display->drm,
1649		    vdsc_cfg->pic_height % vdsc_cfg->slice_height);
1650
1651	ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
1652	if (ret)
1653		return ret;
1654
1655	intel_dsc_enable_on_crtc(crtc_state);
1656
1657	return 0;
1658}
1659
1660static int gen11_dsi_compute_config(struct intel_encoder *encoder,
1661				    struct intel_crtc_state *pipe_config,
1662				    struct drm_connector_state *conn_state)
1663{
1664	struct intel_display *display = to_intel_display(encoder);
1665	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1666	struct intel_connector *intel_connector = intel_dsi->attached_connector;
1667	struct drm_display_mode *adjusted_mode =
1668		&pipe_config->hw.adjusted_mode;
1669	int ret;
1670
1671	pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
1672	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1673
1674	ret = intel_panel_compute_config(intel_connector, adjusted_mode);
1675	if (ret)
1676		return ret;
1677
1678	ret = intel_pfit_compute_config(pipe_config, conn_state);
1679	if (ret)
1680		return ret;
1681
1682	adjusted_mode->flags = 0;
1683
1684	/* Dual link goes to trancoder DSI'0' */
1685	if (intel_dsi->ports == BIT(PORT_B))
1686		pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1687	else
1688		pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1689
1690	if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
1691		pipe_config->pipe_bpp = 24;
1692	else
1693		pipe_config->pipe_bpp = 18;
1694
1695	pipe_config->clock_set = true;
1696
1697	if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
1698		drm_dbg_kms(display->drm, "Attempting to use DSC failed\n");
1699
1700	pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
1701
1702	/*
1703	 * In case of TE GATE cmd mode, we
1704	 * receive TE from the slave if
1705	 * dual link is enabled
1706	 */
1707	if (is_cmd_mode(intel_dsi))
1708		gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1709
1710	return 0;
1711}
1712
1713static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1714					struct intel_crtc_state *crtc_state)
1715{
1716	get_dsi_io_power_domains(enc_to_intel_dsi(encoder));
1717}
1718
1719static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1720				   enum pipe *pipe)
1721{
1722	struct intel_display *display = to_intel_display(encoder);
1723	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1724	enum transcoder dsi_trans;
1725	intel_wakeref_t wakeref;
1726	enum port port;
1727	bool ret = false;
1728	u32 tmp;
1729
1730	wakeref = intel_display_power_get_if_enabled(display,
1731						     encoder->power_domain);
1732	if (!wakeref)
1733		return false;
1734
1735	for_each_dsi_port(port, intel_dsi->ports) {
1736		dsi_trans = dsi_port_to_transcoder(port);
1737		tmp = intel_de_read(display,
1738				    TRANS_DDI_FUNC_CTL(display, dsi_trans));
1739		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1740		case TRANS_DDI_EDP_INPUT_A_ON:
1741			*pipe = PIPE_A;
1742			break;
1743		case TRANS_DDI_EDP_INPUT_B_ONOFF:
1744			*pipe = PIPE_B;
1745			break;
1746		case TRANS_DDI_EDP_INPUT_C_ONOFF:
1747			*pipe = PIPE_C;
1748			break;
1749		case TRANS_DDI_EDP_INPUT_D_ONOFF:
1750			*pipe = PIPE_D;
1751			break;
1752		default:
1753			drm_err(display->drm, "Invalid PIPE input\n");
1754			goto out;
1755		}
1756
1757		tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));
1758		ret = tmp & TRANSCONF_ENABLE;
1759	}
1760out:
1761	intel_display_power_put(display, encoder->power_domain, wakeref);
1762	return ret;
1763}
1764
1765static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
1766					    struct intel_crtc_state *crtc_state)
1767{
1768	if (crtc_state->dsc.compression_enable) {
1769		drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
1770		crtc_state->uapi.mode_changed = true;
1771
1772		return false;
1773	}
1774
1775	return true;
1776}
1777
1778static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
1779{
1780	intel_encoder_destroy(encoder);
1781}
1782
1783static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
1784	.destroy = gen11_dsi_encoder_destroy,
1785};
1786
1787static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
1788	.detect = intel_panel_detect,
1789	.late_register = intel_connector_register,
1790	.early_unregister = intel_connector_unregister,
1791	.destroy = intel_connector_destroy,
1792	.fill_modes = drm_helper_probe_single_connector_modes,
1793	.atomic_get_property = intel_digital_connector_atomic_get_property,
1794	.atomic_set_property = intel_digital_connector_atomic_set_property,
1795	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1796	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
1797};
1798
1799static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
1800	.get_modes = intel_dsi_get_modes,
1801	.mode_valid = gen11_dsi_mode_valid,
1802	.atomic_check = intel_digital_connector_atomic_check,
1803};
1804
1805static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
1806				 struct mipi_dsi_device *dsi)
1807{
1808	return 0;
1809}
1810
1811static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
1812				 struct mipi_dsi_device *dsi)
1813{
1814	return 0;
1815}
1816
1817static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
1818				       const struct mipi_dsi_msg *msg)
1819{
1820	struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
1821	struct mipi_dsi_packet dsi_pkt;
1822	ssize_t ret;
1823	bool enable_lpdt = false;
1824
1825	ret = mipi_dsi_create_packet(&dsi_pkt, msg);
1826	if (ret < 0)
1827		return ret;
1828
1829	if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1830		enable_lpdt = true;
1831
1832	/* only long packet contains payload */
1833	if (mipi_dsi_packet_format_is_long(msg->type)) {
1834		ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt);
1835		if (ret < 0)
1836			return ret;
1837	}
1838
1839	/* send packet header */
1840	ret  = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt);
1841	if (ret < 0)
1842		return ret;
1843
1844	//TODO: add payload receive code if needed
1845
1846	ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
1847
1848	return ret;
1849}
1850
1851static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
1852	.attach = gen11_dsi_host_attach,
1853	.detach = gen11_dsi_host_detach,
1854	.transfer = gen11_dsi_host_transfer,
1855};
1856
1857static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
1858{
1859	struct intel_connector *connector = intel_dsi->attached_connector;
1860	struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1861	u32 tlpx_ns;
1862	u32 tclk_prepare_esc_clk, tclk_zero_esc_clk, tclk_pre_esc_clk;
1863	u32 ths_prepare_esc_clk, ths_zero_esc_clk, ths_exit_esc_clk;
1864
1865	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1866
1867	/*
1868	 * The clock and data lane prepare timing parameters are in expressed in
1869	 * units of 1/4 escape clocks, and all the other timings parameters in
1870	 * escape clocks.
1871	 */
1872	tclk_prepare_esc_clk = DIV_ROUND_UP(mipi_config->tclk_prepare * 4, tlpx_ns);
1873	tclk_prepare_esc_clk = min(tclk_prepare_esc_clk, 7);
1874
1875	tclk_zero_esc_clk = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
1876					 mipi_config->tclk_prepare, tlpx_ns);
1877	tclk_zero_esc_clk = min(tclk_zero_esc_clk, 15);
1878
1879	tclk_pre_esc_clk = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
1880	tclk_pre_esc_clk = min(tclk_pre_esc_clk, 3);
1881
1882	ths_prepare_esc_clk = DIV_ROUND_UP(mipi_config->ths_prepare * 4, tlpx_ns);
1883	ths_prepare_esc_clk = min(ths_prepare_esc_clk, 7);
1884
1885	ths_zero_esc_clk = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
1886					mipi_config->ths_prepare, tlpx_ns);
1887	ths_zero_esc_clk = min(ths_zero_esc_clk, 15);
1888
1889	ths_exit_esc_clk = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
1890	ths_exit_esc_clk = min(ths_exit_esc_clk, 7);
1891
1892	/* clock lane dphy timings */
1893	intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
1894			       CLK_PREPARE(tclk_prepare_esc_clk) |
1895			       CLK_ZERO_OVERRIDE |
1896			       CLK_ZERO(tclk_zero_esc_clk) |
1897			       CLK_PRE_OVERRIDE |
1898			       CLK_PRE(tclk_pre_esc_clk));
1899
1900	/* data lanes dphy timings */
1901	intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
1902					 HS_PREPARE(ths_prepare_esc_clk) |
1903					 HS_ZERO_OVERRIDE |
1904					 HS_ZERO(ths_zero_esc_clk) |
1905					 HS_EXIT_OVERRIDE |
1906					 HS_EXIT(ths_exit_esc_clk));
1907
1908	intel_dsi_log_params(intel_dsi);
1909}
1910
1911static void icl_dsi_add_properties(struct intel_connector *connector)
1912{
1913	const struct drm_display_mode *fixed_mode =
1914		intel_panel_preferred_fixed_mode(connector);
1915
1916	intel_attach_scaling_mode_property(&connector->base);
1917
1918	drm_connector_set_panel_orientation_with_quirk(&connector->base,
1919						       intel_dsi_get_panel_orientation(connector),
1920						       fixed_mode->hdisplay,
1921						       fixed_mode->vdisplay);
1922}
1923
1924void icl_dsi_init(struct intel_display *display,
1925		  const struct intel_bios_encoder_data *devdata)
1926{
1927	struct intel_dsi *intel_dsi;
1928	struct intel_encoder *encoder;
1929	struct intel_connector *intel_connector;
1930	struct drm_connector *connector;
1931	enum port port;
1932
1933	port = intel_bios_encoder_port(devdata);
1934	if (port == PORT_NONE)
1935		return;
1936
1937	intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1938	if (!intel_dsi)
1939		return;
1940
1941	intel_connector = intel_connector_alloc();
1942	if (!intel_connector) {
1943		kfree(intel_dsi);
1944		return;
1945	}
1946
1947	encoder = &intel_dsi->base;
1948	intel_dsi->attached_connector = intel_connector;
1949	connector = &intel_connector->base;
1950
1951	encoder->devdata = devdata;
1952
1953	/* register DSI encoder with DRM subsystem */
1954	drm_encoder_init(display->drm, &encoder->base,
1955			 &gen11_dsi_encoder_funcs,
1956			 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1957
1958	encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
1959	encoder->pre_enable = gen11_dsi_pre_enable;
1960	encoder->enable = gen11_dsi_enable;
1961	encoder->disable = gen11_dsi_disable;
1962	encoder->post_disable = gen11_dsi_post_disable;
1963	encoder->port = port;
1964	encoder->get_config = gen11_dsi_get_config;
1965	encoder->sync_state = gen11_dsi_sync_state;
1966	encoder->update_pipe = intel_backlight_update;
1967	encoder->compute_config = gen11_dsi_compute_config;
1968	encoder->get_hw_state = gen11_dsi_get_hw_state;
1969	encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
1970	encoder->type = INTEL_OUTPUT_DSI;
1971	encoder->cloneable = 0;
1972	encoder->pipe_mask = ~0;
1973	encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1974	encoder->get_power_domains = gen11_dsi_get_power_domains;
1975	encoder->disable_clock = gen11_dsi_gate_clocks;
1976	encoder->is_clock_enabled = gen11_dsi_is_clock_enabled;
1977	encoder->shutdown = intel_dsi_shutdown;
1978
1979	/* register DSI connector with DRM subsystem */
1980	drm_connector_init(display->drm, connector,
1981			   &gen11_dsi_connector_funcs,
1982			   DRM_MODE_CONNECTOR_DSI);
1983	drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
1984	connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1985	intel_connector->get_hw_state = intel_connector_get_hw_state;
1986
1987	/* attach connector to encoder */
1988	intel_connector_attach_encoder(intel_connector, encoder);
1989
1990	intel_dsi->panel_power_off_time = ktime_get_boottime();
1991
1992	intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL);
1993
1994	mutex_lock(&display->drm->mode_config.mutex);
1995	intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
1996	mutex_unlock(&display->drm->mode_config.mutex);
1997
1998	if (!intel_panel_preferred_fixed_mode(intel_connector)) {
1999		drm_err(display->drm, "DSI fixed mode info missing\n");
2000		goto err;
2001	}
2002
2003	intel_panel_init(intel_connector, NULL);
2004
2005	intel_backlight_setup(intel_connector, INVALID_PIPE);
2006
2007	if (intel_connector->panel.vbt.dsi.config->dual_link)
2008		intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
2009	else
2010		intel_dsi->ports = BIT(port);
2011
2012	if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
2013		intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
2014
2015	if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
2016		intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
2017
2018	for_each_dsi_port(port, intel_dsi->ports) {
2019		struct intel_dsi_host *host;
2020
2021		host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
2022		if (!host)
2023			goto err;
2024
2025		intel_dsi->dsi_hosts[port] = host;
2026	}
2027
2028	if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
2029		drm_dbg_kms(display->drm, "no device found\n");
2030		goto err;
2031	}
2032
2033	icl_dphy_param_init(intel_dsi);
2034
2035	icl_dsi_add_properties(intel_connector);
2036	return;
2037
2038err:
2039	drm_connector_cleanup(connector);
2040	drm_encoder_cleanup(&encoder->base);
2041	kfree(intel_dsi);
2042	kfree(intel_connector);
2043}