hsw_ips.c

  1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright © 2022 Intel Corporation
  4 */
  5
  6#include <linux/debugfs.h>
  7
  8#include <drm/drm_print.h>
  9
 10#include "hsw_ips.h"
 11#include "i915_reg.h"
 12#include "intel_color_regs.h"
 13#include "intel_de.h"
 14#include "intel_display_regs.h"
 15#include "intel_display_rpm.h"
 16#include "intel_display_types.h"
 17#include "intel_pcode.h"
 18
 19static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
 20{
 21	struct intel_display *display = to_intel_display(crtc_state);
 22	u32 val;
 23
 24	if (!crtc_state->ips_enabled)
 25		return;
 26
 27	/*
 28	 * We can only enable IPS after we enable a plane and wait for a vblank
 29	 * This function is called from post_plane_update, which is run after
 30	 * a vblank wait.
 31	 */
 32	drm_WARN_ON(display->drm,
 33		    !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
 34
 35	val = IPS_ENABLE;
 36
 37	if (display->ips.false_color)
 38		val |= IPS_FALSE_COLOR;
 39
 40	if (display->platform.broadwell) {
 41		drm_WARN_ON(display->drm,
 42			    intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL,
 43					      val | IPS_PCODE_CONTROL));
 44		/*
 45		 * Quoting Art Runyan: "its not safe to expect any particular
 46		 * value in IPS_CTL bit 31 after enabling IPS through the
 47		 * mailbox." Moreover, the mailbox may return a bogus state,
 48		 * so we need to just enable it and continue on.
 49		 */
 50	} else {
 51		intel_de_write(display, IPS_CTL, val);
 52		/*
 53		 * The bit only becomes 1 in the next vblank, so this wait here
 54		 * is essentially intel_wait_for_vblank. If we don't have this
 55		 * and don't wait for vblanks until the end of crtc_enable, then
 56		 * the HW state readout code will complain that the expected
 57		 * IPS_CTL value is not the one we read.
 58		 */
 59		if (intel_de_wait_for_set_ms(display, IPS_CTL, IPS_ENABLE, 50))
 60			drm_err(display->drm,
 61				"Timed out waiting for IPS enable\n");
 62	}
 63}
 64
 65bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
 66{
 67	struct intel_display *display = to_intel_display(crtc_state);
 68	bool need_vblank_wait = false;
 69
 70	if (!crtc_state->ips_enabled)
 71		return need_vblank_wait;
 72
 73	if (display->platform.broadwell) {
 74		drm_WARN_ON(display->drm,
 75			    intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL, 0));
 76		/*
 77		 * Wait for PCODE to finish disabling IPS. The BSpec specified
 78		 * 42ms timeout value leads to occasional timeouts so use 100ms
 79		 * instead.
 80		 */
 81		if (intel_de_wait_for_clear_ms(display, IPS_CTL, IPS_ENABLE, 100))
 82			drm_err(display->drm,
 83				"Timed out waiting for IPS disable\n");
 84	} else {
 85		intel_de_write(display, IPS_CTL, 0);
 86		intel_de_posting_read(display, IPS_CTL);
 87	}
 88
 89	/* We need to wait for a vblank before we can disable the plane. */
 90	need_vblank_wait = true;
 91
 92	return need_vblank_wait;
 93}
 94
 95static bool hsw_ips_need_disable(struct intel_atomic_state *state,
 96				 struct intel_crtc *crtc)
 97{
 98	struct intel_display *display = to_intel_display(state);
 99	const struct intel_crtc_state *old_crtc_state =
100		intel_atomic_get_old_crtc_state(state, crtc);
101	const struct intel_crtc_state *new_crtc_state =
102		intel_atomic_get_new_crtc_state(state, crtc);
103
104	if (!old_crtc_state->ips_enabled)
105		return false;
106
107	if (intel_crtc_needs_modeset(new_crtc_state))
108		return true;
109
110	/*
111	 * Workaround : Do not read or write the pipe palette/gamma data while
112	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
113	 *
114	 * Disable IPS before we program the LUT.
115	 */
116	if (display->platform.haswell &&
117	    intel_crtc_needs_color_update(new_crtc_state) &&
118	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
119		return true;
120
121	return !new_crtc_state->ips_enabled;
122}
123
124bool hsw_ips_pre_update(struct intel_atomic_state *state,
125			struct intel_crtc *crtc)
126{
127	const struct intel_crtc_state *old_crtc_state =
128		intel_atomic_get_old_crtc_state(state, crtc);
129
130	if (!hsw_ips_need_disable(state, crtc))
131		return false;
132
133	return hsw_ips_disable(old_crtc_state);
134}
135
136static bool hsw_ips_need_enable(struct intel_atomic_state *state,
137				struct intel_crtc *crtc)
138{
139	struct intel_display *display = to_intel_display(state);
140	const struct intel_crtc_state *old_crtc_state =
141		intel_atomic_get_old_crtc_state(state, crtc);
142	const struct intel_crtc_state *new_crtc_state =
143		intel_atomic_get_new_crtc_state(state, crtc);
144
145	if (!new_crtc_state->ips_enabled)
146		return false;
147
148	if (intel_crtc_needs_modeset(new_crtc_state))
149		return true;
150
151	/*
152	 * Workaround : Do not read or write the pipe palette/gamma data while
153	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
154	 *
155	 * Re-enable IPS after the LUT has been programmed.
156	 */
157	if (display->platform.haswell &&
158	    intel_crtc_needs_color_update(new_crtc_state) &&
159	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)
160		return true;
161
162	/*
163	 * We can't read out IPS on broadwell, assume the worst and
164	 * forcibly enable IPS on the first fastset.
165	 */
166	if (intel_crtc_needs_fastset(new_crtc_state) && old_crtc_state->inherited)
167		return true;
168
169	return !old_crtc_state->ips_enabled;
170}
171
172void hsw_ips_post_update(struct intel_atomic_state *state,
173			 struct intel_crtc *crtc)
174{
175	const struct intel_crtc_state *new_crtc_state =
176		intel_atomic_get_new_crtc_state(state, crtc);
177
178	if (!hsw_ips_need_enable(state, crtc))
179		return;
180
181	hsw_ips_enable(new_crtc_state);
182}
183
184/* IPS only exists on ULT machines and is tied to pipe A. */
185bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
186{
187	struct intel_display *display = to_intel_display(crtc);
188
189	return HAS_IPS(display) && crtc->pipe == PIPE_A;
190}
191
192static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
193{
194	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
195
196	if (!hsw_crtc_supports_ips(crtc))
197		return false;
198
199	if (crtc_state->pipe_bpp > 24)
200		return false;
201
202	return true;
203}
204
205static int _hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
206{
207	struct intel_display *display = to_intel_display(crtc_state);
208
209	if (display->platform.broadwell)
210		return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);
211
212	/* no IPS specific limits to worry about */
213	return 0;
214}
215
216int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
217{
218	struct intel_display *display = to_intel_display(crtc_state);
219	int min_cdclk;
220
221	if (!hsw_crtc_state_ips_capable(crtc_state))
222		return 0;
223
224	min_cdclk = _hsw_ips_min_cdclk(crtc_state);
225
226	/*
227	 * Do not ask for more than the max CDCLK frequency,
228	 * if that is not enough IPS will simply not be used.
229	 */
230	if (min_cdclk > display->cdclk.max_cdclk_freq)
231		return 0;
232
233	return min_cdclk;
234}
235
236int hsw_ips_compute_config(struct intel_atomic_state *state,
237			   struct intel_crtc *crtc)
238{
239	struct intel_display *display = to_intel_display(state);
240	struct intel_crtc_state *crtc_state =
241		intel_atomic_get_new_crtc_state(state, crtc);
242
243	crtc_state->ips_enabled = false;
244
245	if (!hsw_crtc_state_ips_capable(crtc_state))
246		return 0;
247
248	if (_hsw_ips_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq)
249		return 0;
250
251	if (!display->params.enable_ips)
252		return 0;
253
254	/*
255	 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
256	 * enabled and disabled dynamically based on package C states,
257	 * user space can't make reliable use of the CRCs, so let's just
258	 * completely disable it.
259	 */
260	if (crtc_state->crc_enabled)
261		return 0;
262
263	/* IPS should be fine as long as at least one plane is enabled. */
264	if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
265		return 0;
266
267	crtc_state->ips_enabled = true;
268
269	return 0;
270}
271
272void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
273{
274	struct intel_display *display = to_intel_display(crtc_state);
275	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
276
277	if (!hsw_crtc_supports_ips(crtc))
278		return;
279
280	if (display->platform.haswell) {
281		crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;
282	} else {
283		/*
284		 * We cannot readout IPS state on broadwell, set to
285		 * true so we can set it to a defined state on first
286		 * commit.
287		 */
288		crtc_state->ips_enabled = true;
289	}
290}
291
292static int hsw_ips_debugfs_false_color_get(void *data, u64 *val)
293{
294	struct intel_crtc *crtc = data;
295	struct intel_display *display = to_intel_display(crtc);
296
297	*val = display->ips.false_color;
298
299	return 0;
300}
301
302static int hsw_ips_debugfs_false_color_set(void *data, u64 val)
303{
304	struct intel_crtc *crtc = data;
305	struct intel_display *display = to_intel_display(crtc);
306	struct intel_crtc_state *crtc_state;
307	int ret;
308
309	ret = drm_modeset_lock(&crtc->base.mutex, NULL);
310	if (ret)
311		return ret;
312
313	display->ips.false_color = val;
314
315	crtc_state = to_intel_crtc_state(crtc->base.state);
316
317	if (!crtc_state->hw.active)
318		goto unlock;
319
320	if (crtc_state->uapi.commit &&
321	    !try_wait_for_completion(&crtc_state->uapi.commit->hw_done))
322		goto unlock;
323
324	hsw_ips_enable(crtc_state);
325
326 unlock:
327	drm_modeset_unlock(&crtc->base.mutex);
328
329	return ret;
330}
331
332DEFINE_DEBUGFS_ATTRIBUTE(hsw_ips_debugfs_false_color_fops,
333			 hsw_ips_debugfs_false_color_get,
334			 hsw_ips_debugfs_false_color_set,
335			 "%llu\n");
336
337static int hsw_ips_debugfs_status_show(struct seq_file *m, void *unused)
338{
339	struct intel_crtc *crtc = m->private;
340	struct intel_display *display = to_intel_display(crtc);
341	struct ref_tracker *wakeref;
342
343	wakeref = intel_display_rpm_get(display);
344
345	seq_printf(m, "Enabled by kernel parameter: %s\n",
346		   str_yes_no(display->params.enable_ips));
347
348	if (DISPLAY_VER(display) >= 8) {
349		seq_puts(m, "Currently: unknown\n");
350	} else {
351		if (intel_de_read(display, IPS_CTL) & IPS_ENABLE)
352			seq_puts(m, "Currently: enabled\n");
353		else
354			seq_puts(m, "Currently: disabled\n");
355	}
356
357	intel_display_rpm_put(display, wakeref);
358
359	return 0;
360}
361
362DEFINE_SHOW_ATTRIBUTE(hsw_ips_debugfs_status);
363
364void hsw_ips_crtc_debugfs_add(struct intel_crtc *crtc)
365{
366	if (!hsw_crtc_supports_ips(crtc))
367		return;
368
369	debugfs_create_file("i915_ips_false_color", 0644, crtc->base.debugfs_entry,
370			    crtc, &hsw_ips_debugfs_false_color_fops);
371
372	debugfs_create_file("i915_ips_status", 0444, crtc->base.debugfs_entry,
373			    crtc, &hsw_ips_debugfs_status_fops);
374}