FILE
g4x_hdmi.c
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linux-6.19.14/drivers/gpu/drm/i915/display/g4x_hdmi.c
1// SPDX-License-Identifier: MIT 2/* 3 * Copyright © 2020 Intel Corporation 4 * 5 * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). 6 */ 7 8#include <drm/drm_print.h> 9 10#include "g4x_hdmi.h" 11#include "i915_reg.h" 12#include "intel_atomic.h" 13#include "intel_audio.h" 14#include "intel_connector.h" 15#include "intel_crtc.h" 16#include "intel_de.h" 17#include "intel_display_power.h" 18#include "intel_display_regs.h" 19#include "intel_display_types.h" 20#include "intel_dp_aux.h" 21#include "intel_dpio_phy.h" 22#include "intel_encoder.h" 23#include "intel_fifo_underrun.h" 24#include "intel_hdmi.h" 25#include "intel_hotplug.h" 26#include "intel_sdvo.h" 27 28static void intel_hdmi_prepare(struct intel_encoder *encoder, 29 const struct intel_crtc_state *crtc_state) 30{ 31 struct intel_display *display = to_intel_display(encoder); 32 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 33 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 34 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 35 u32 hdmi_val; 36 37 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 38 39 hdmi_val = SDVO_ENCODING_HDMI; 40 if (!HAS_PCH_SPLIT(display) && crtc_state->limited_color_range) 41 hdmi_val |= HDMI_COLOR_RANGE_16_235; 42 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 43 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 44 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 45 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 46 47 if (crtc_state->pipe_bpp > 24) 48 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 49 else 50 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 51 52 if (crtc_state->has_hdmi_sink) 53 hdmi_val |= HDMI_MODE_SELECT_HDMI; 54 55 if (HAS_PCH_CPT(display)) 56 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 57 else if (display->platform.cherryview) 58 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 59 else 60 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 61 62 intel_de_write(display, intel_hdmi->hdmi_reg, hdmi_val); 63 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 64} 65 66static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 67 enum pipe *pipe) 68{ 69 struct intel_display *display = to_intel_display(encoder); 70 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 71 intel_wakeref_t wakeref; 72 bool ret; 73 74 wakeref = intel_display_power_get_if_enabled(display, 75 encoder->power_domain); 76 if (!wakeref) 77 return false; 78 79 ret = intel_sdvo_port_enabled(display, intel_hdmi->hdmi_reg, pipe); 80 81 intel_display_power_put(display, encoder->power_domain, wakeref); 82 83 return ret; 84} 85 86static bool connector_is_hdmi(struct drm_connector *connector) 87{ 88 struct intel_encoder *encoder = 89 intel_attached_encoder(to_intel_connector(connector)); 90 91 return encoder && encoder->type == INTEL_OUTPUT_HDMI; 92} 93 94static bool g4x_compute_has_hdmi_sink(struct intel_atomic_state *state, 95 struct intel_crtc *this_crtc) 96{ 97 const struct drm_connector_state *conn_state; 98 struct drm_connector *connector; 99 int i; 100 101 /* 102 * On g4x only one HDMI port can transmit infoframes/audio at 103 * any given time. Select the first suitable port for this duty. 104 * 105 * See also g4x_hdmi_connector_atomic_check(). 106 */ 107 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 108 struct intel_encoder *encoder = to_intel_encoder(conn_state->best_encoder); 109 const struct intel_crtc_state *crtc_state; 110 struct intel_crtc *crtc; 111 112 if (!connector_is_hdmi(connector)) 113 continue; 114 115 crtc = to_intel_crtc(conn_state->crtc); 116 if (!crtc) 117 continue; 118 119 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 120 121 if (!intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state, conn_state)) 122 continue; 123 124 return crtc == this_crtc; 125 } 126 127 return false; 128} 129 130static int g4x_hdmi_compute_config(struct intel_encoder *encoder, 131 struct intel_crtc_state *crtc_state, 132 struct drm_connector_state *conn_state) 133{ 134 struct intel_display *display = to_intel_display(encoder); 135 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 136 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 137 138 if (HAS_PCH_SPLIT(display)) 139 crtc_state->has_pch_encoder = true; 140 141 if (display->platform.g4x) 142 crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc); 143 else 144 crtc_state->has_hdmi_sink = 145 intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state, conn_state); 146 147 return intel_hdmi_compute_config(encoder, crtc_state, conn_state); 148} 149 150static void intel_hdmi_get_config(struct intel_encoder *encoder, 151 struct intel_crtc_state *pipe_config) 152{ 153 struct intel_display *display = to_intel_display(encoder); 154 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 155 u32 tmp, flags = 0; 156 int dotclock; 157 158 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 159 160 tmp = intel_de_read(display, intel_hdmi->hdmi_reg); 161 162 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 163 flags |= DRM_MODE_FLAG_PHSYNC; 164 else 165 flags |= DRM_MODE_FLAG_NHSYNC; 166 167 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 168 flags |= DRM_MODE_FLAG_PVSYNC; 169 else 170 flags |= DRM_MODE_FLAG_NVSYNC; 171 172 if (tmp & HDMI_MODE_SELECT_HDMI) 173 pipe_config->has_hdmi_sink = true; 174 175 pipe_config->infoframes.enable |= 176 intel_hdmi_infoframes_enabled(encoder, pipe_config); 177 178 if (pipe_config->infoframes.enable) 179 pipe_config->has_infoframe = true; 180 181 if (tmp & HDMI_AUDIO_ENABLE) 182 pipe_config->has_audio = true; 183 184 if (!HAS_PCH_SPLIT(display) && 185 tmp & HDMI_COLOR_RANGE_16_235) 186 pipe_config->limited_color_range = true; 187 188 pipe_config->hw.adjusted_mode.flags |= flags; 189 190 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 191 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3); 192 else 193 dotclock = pipe_config->port_clock; 194 195 if (pipe_config->pixel_multiplier) 196 dotclock /= pipe_config->pixel_multiplier; 197 198 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 199 200 pipe_config->lane_count = 4; 201 202 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 203 204 intel_read_infoframe(encoder, pipe_config, 205 HDMI_INFOFRAME_TYPE_AVI, 206 &pipe_config->infoframes.avi); 207 intel_read_infoframe(encoder, pipe_config, 208 HDMI_INFOFRAME_TYPE_SPD, 209 &pipe_config->infoframes.spd); 210 intel_read_infoframe(encoder, pipe_config, 211 HDMI_INFOFRAME_TYPE_VENDOR, 212 &pipe_config->infoframes.hdmi); 213 214 intel_audio_codec_get_config(encoder, pipe_config); 215} 216 217static void g4x_hdmi_enable_port(struct intel_encoder *encoder, 218 const struct intel_crtc_state *pipe_config) 219{ 220 struct intel_display *display = to_intel_display(encoder); 221 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 222 u32 temp; 223 224 temp = intel_de_read(display, intel_hdmi->hdmi_reg); 225 226 temp |= SDVO_ENABLE; 227 228 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 229 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 230} 231 232static void g4x_hdmi_audio_enable(struct intel_encoder *encoder, 233 const struct intel_crtc_state *crtc_state, 234 const struct drm_connector_state *conn_state) 235{ 236 struct intel_display *display = to_intel_display(encoder); 237 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 238 239 if (!crtc_state->has_audio) 240 return; 241 242 drm_WARN_ON(display->drm, !crtc_state->has_hdmi_sink); 243 244 /* Enable audio presence detect */ 245 intel_de_rmw(display, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE); 246 247 intel_audio_codec_enable(encoder, crtc_state, conn_state); 248} 249 250static void g4x_hdmi_audio_disable(struct intel_encoder *encoder, 251 const struct intel_crtc_state *old_crtc_state, 252 const struct drm_connector_state *old_conn_state) 253{ 254 struct intel_display *display = to_intel_display(encoder); 255 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 256 257 if (!old_crtc_state->has_audio) 258 return; 259 260 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 261 262 /* Disable audio presence detect */ 263 intel_de_rmw(display, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0); 264} 265 266static void g4x_enable_hdmi(struct intel_atomic_state *state, 267 struct intel_encoder *encoder, 268 const struct intel_crtc_state *pipe_config, 269 const struct drm_connector_state *conn_state) 270{ 271 g4x_hdmi_enable_port(encoder, pipe_config); 272} 273 274static void ibx_enable_hdmi(struct intel_atomic_state *state, 275 struct intel_encoder *encoder, 276 const struct intel_crtc_state *pipe_config, 277 const struct drm_connector_state *conn_state) 278{ 279 struct intel_display *display = to_intel_display(encoder); 280 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 281 u32 temp; 282 283 temp = intel_de_read(display, intel_hdmi->hdmi_reg); 284 285 temp |= SDVO_ENABLE; 286 287 /* 288 * HW workaround, need to write this twice for issue 289 * that may result in first write getting masked. 290 */ 291 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 292 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 293 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 294 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 295 296 /* 297 * HW workaround, need to toggle enable bit off and on 298 * for 12bpc with pixel repeat. 299 * 300 * FIXME: BSpec says this should be done at the end of 301 * the modeset sequence, so not sure if this isn't too soon. 302 */ 303 if (pipe_config->pipe_bpp > 24 && 304 pipe_config->pixel_multiplier > 1) { 305 intel_de_write(display, intel_hdmi->hdmi_reg, 306 temp & ~SDVO_ENABLE); 307 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 308 309 /* 310 * HW workaround, need to write this twice for issue 311 * that may result in first write getting masked. 312 */ 313 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 314 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 315 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 316 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 317 } 318} 319 320static void cpt_enable_hdmi(struct intel_atomic_state *state, 321 struct intel_encoder *encoder, 322 const struct intel_crtc_state *pipe_config, 323 const struct drm_connector_state *conn_state) 324{ 325 struct intel_display *display = to_intel_display(encoder); 326 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 327 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 328 enum pipe pipe = crtc->pipe; 329 u32 temp; 330 331 temp = intel_de_read(display, intel_hdmi->hdmi_reg); 332 333 temp |= SDVO_ENABLE; 334 335 /* 336 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 337 * 338 * The procedure for 12bpc is as follows: 339 * 1. disable HDMI clock gating 340 * 2. enable HDMI with 8bpc 341 * 3. enable HDMI with 12bpc 342 * 4. enable HDMI clock gating 343 */ 344 345 if (pipe_config->pipe_bpp > 24) { 346 intel_de_rmw(display, TRANS_CHICKEN1(pipe), 347 0, TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 348 349 temp &= ~SDVO_COLOR_FORMAT_MASK; 350 temp |= SDVO_COLOR_FORMAT_8bpc; 351 } 352 353 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 354 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 355 356 if (pipe_config->pipe_bpp > 24) { 357 temp &= ~SDVO_COLOR_FORMAT_MASK; 358 temp |= HDMI_COLOR_FORMAT_12bpc; 359 360 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 361 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 362 363 intel_de_rmw(display, TRANS_CHICKEN1(pipe), 364 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE, 0); 365 } 366} 367 368static void vlv_enable_hdmi(struct intel_atomic_state *state, 369 struct intel_encoder *encoder, 370 const struct intel_crtc_state *pipe_config, 371 const struct drm_connector_state *conn_state) 372{ 373} 374 375static void intel_disable_hdmi(struct intel_atomic_state *state, 376 struct intel_encoder *encoder, 377 const struct intel_crtc_state *old_crtc_state, 378 const struct drm_connector_state *old_conn_state) 379{ 380 struct intel_display *display = to_intel_display(encoder); 381 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 382 struct intel_digital_port *dig_port = 383 hdmi_to_dig_port(intel_hdmi); 384 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 385 u32 temp; 386 387 temp = intel_de_read(display, intel_hdmi->hdmi_reg); 388 389 temp &= ~SDVO_ENABLE; 390 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 391 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 392 393 /* 394 * HW workaround for IBX, we need to move the port 395 * to transcoder A after disabling it to allow the 396 * matching DP port to be enabled on transcoder A. 397 */ 398 if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) { 399 /* 400 * We get CPU/PCH FIFO underruns on the other pipe when 401 * doing the workaround. Sweep them under the rug. 402 */ 403 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); 404 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); 405 406 temp &= ~SDVO_PIPE_SEL_MASK; 407 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 408 /* 409 * HW workaround, need to write this twice for issue 410 * that may result in first write getting masked. 411 */ 412 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 413 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 414 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 415 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 416 417 temp &= ~SDVO_ENABLE; 418 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 419 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 420 421 intel_wait_for_vblank_if_active(display, PIPE_A); 422 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); 423 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); 424 } 425 426 dig_port->set_infoframes(encoder, 427 false, 428 old_crtc_state, old_conn_state); 429 430 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 431} 432 433static void g4x_disable_hdmi(struct intel_atomic_state *state, 434 struct intel_encoder *encoder, 435 const struct intel_crtc_state *old_crtc_state, 436 const struct drm_connector_state *old_conn_state) 437{ 438 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 439} 440 441static void pch_disable_hdmi(struct intel_atomic_state *state, 442 struct intel_encoder *encoder, 443 const struct intel_crtc_state *old_crtc_state, 444 const struct drm_connector_state *old_conn_state) 445{ 446} 447 448static void pch_post_disable_hdmi(struct intel_atomic_state *state, 449 struct intel_encoder *encoder, 450 const struct intel_crtc_state *old_crtc_state, 451 const struct drm_connector_state *old_conn_state) 452{ 453 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 454} 455 456static void intel_hdmi_pre_enable(struct intel_atomic_state *state, 457 struct intel_encoder *encoder, 458 const struct intel_crtc_state *pipe_config, 459 const struct drm_connector_state *conn_state) 460{ 461 struct intel_digital_port *dig_port = 462 enc_to_dig_port(encoder); 463 464 intel_hdmi_prepare(encoder, pipe_config); 465 466 dig_port->set_infoframes(encoder, 467 pipe_config->has_infoframe, 468 pipe_config, conn_state); 469} 470 471static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, 472 struct intel_encoder *encoder, 473 const struct intel_crtc_state *pipe_config, 474 const struct drm_connector_state *conn_state) 475{ 476 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 477 478 vlv_phy_pre_encoder_enable(encoder, pipe_config); 479 480 /* HDMI 1.0V-2dB */ 481 vlv_set_phy_signal_level(encoder, pipe_config, 482 0x2b245f5f, 0x00002000, 483 0x5578b83a, 0x2b247878); 484 485 dig_port->set_infoframes(encoder, 486 pipe_config->has_infoframe, 487 pipe_config, conn_state); 488 489 g4x_hdmi_enable_port(encoder, pipe_config); 490 491 vlv_wait_port_ready(encoder, 0x0); 492} 493 494static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 495 struct intel_encoder *encoder, 496 const struct intel_crtc_state *pipe_config, 497 const struct drm_connector_state *conn_state) 498{ 499 intel_hdmi_prepare(encoder, pipe_config); 500 501 vlv_phy_pre_pll_enable(encoder, pipe_config); 502} 503 504static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 505 struct intel_encoder *encoder, 506 const struct intel_crtc_state *pipe_config, 507 const struct drm_connector_state *conn_state) 508{ 509 intel_hdmi_prepare(encoder, pipe_config); 510 511 chv_phy_pre_pll_enable(encoder, pipe_config); 512} 513 514static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state, 515 struct intel_encoder *encoder, 516 const struct intel_crtc_state *old_crtc_state, 517 const struct drm_connector_state *old_conn_state) 518{ 519 chv_phy_post_pll_disable(encoder, old_crtc_state); 520} 521 522static void vlv_hdmi_post_disable(struct intel_atomic_state *state, 523 struct intel_encoder *encoder, 524 const struct intel_crtc_state *old_crtc_state, 525 const struct drm_connector_state *old_conn_state) 526{ 527 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 528 vlv_phy_reset_lanes(encoder, old_crtc_state); 529} 530 531static void chv_hdmi_post_disable(struct intel_atomic_state *state, 532 struct intel_encoder *encoder, 533 const struct intel_crtc_state *old_crtc_state, 534 const struct drm_connector_state *old_conn_state) 535{ 536 /* Assert data lane reset */ 537 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 538} 539 540static void chv_hdmi_pre_enable(struct intel_atomic_state *state, 541 struct intel_encoder *encoder, 542 const struct intel_crtc_state *pipe_config, 543 const struct drm_connector_state *conn_state) 544{ 545 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 546 547 chv_phy_pre_encoder_enable(encoder, pipe_config); 548 549 /* FIXME: Program the support xxx V-dB */ 550 /* Use 800mV-0dB */ 551 chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false); 552 553 dig_port->set_infoframes(encoder, 554 pipe_config->has_infoframe, 555 pipe_config, conn_state); 556 557 g4x_hdmi_enable_port(encoder, pipe_config); 558 559 vlv_wait_port_ready(encoder, 0x0); 560 561 /* Second common lane will stay alive on its own now */ 562 chv_phy_release_cl2_override(encoder); 563} 564 565static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 566 .destroy = intel_encoder_destroy, 567}; 568 569static enum intel_hotplug_state 570intel_hdmi_hotplug(struct intel_encoder *encoder, 571 struct intel_connector *connector) 572{ 573 enum intel_hotplug_state state; 574 575 state = intel_encoder_hotplug(encoder, connector); 576 577 /* 578 * On many platforms the HDMI live state signal is known to be 579 * unreliable, so we can't use it to detect if a sink is connected or 580 * not. Instead we detect if it's connected based on whether we can 581 * read the EDID or not. That in turn has a problem during disconnect, 582 * since the HPD interrupt may be raised before the DDC lines get 583 * disconnected (due to how the required length of DDC vs. HPD 584 * connector pins are specified) and so we'll still be able to get a 585 * valid EDID. To solve this schedule another detection cycle if this 586 * time around we didn't detect any change in the sink's connection 587 * status. 588 */ 589 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 590 state = INTEL_HOTPLUG_RETRY; 591 592 return state; 593} 594 595int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, 596 struct drm_atomic_state *state) 597{ 598 struct intel_display *display = to_intel_display(connector->dev); 599 struct drm_connector_list_iter conn_iter; 600 struct drm_connector *conn; 601 int ret; 602 603 ret = intel_digital_connector_atomic_check(connector, state); 604 if (ret) 605 return ret; 606 607 if (!display->platform.g4x) 608 return 0; 609 610 if (!intel_connector_needs_modeset(to_intel_atomic_state(state), connector)) 611 return 0; 612 613 /* 614 * On g4x only one HDMI port can transmit infoframes/audio 615 * at any given time. Make sure all enabled HDMI ports are 616 * included in the state so that it's possible to select 617 * one of them for this duty. 618 * 619 * See also g4x_compute_has_hdmi_sink(). 620 */ 621 drm_connector_list_iter_begin(display->drm, &conn_iter); 622 drm_for_each_connector_iter(conn, &conn_iter) { 623 struct drm_connector_state *conn_state; 624 struct drm_crtc_state *crtc_state; 625 struct drm_crtc *crtc; 626 627 if (!connector_is_hdmi(conn)) 628 continue; 629 630 drm_dbg_kms(display->drm, "Adding [CONNECTOR:%d:%s]\n", 631 conn->base.id, conn->name); 632 633 conn_state = drm_atomic_get_connector_state(state, conn); 634 if (IS_ERR(conn_state)) { 635 ret = PTR_ERR(conn_state); 636 break; 637 } 638 639 crtc = conn_state->crtc; 640 if (!crtc) 641 continue; 642 643 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 644 crtc_state->mode_changed = true; 645 646 ret = drm_atomic_add_affected_planes(state, crtc); 647 if (ret) 648 break; 649 } 650 drm_connector_list_iter_end(&conn_iter); 651 652 return ret; 653} 654 655static bool is_hdmi_port_valid(struct intel_display *display, enum port port) 656{ 657 if (display->platform.g4x || display->platform.valleyview) 658 return port == PORT_B || port == PORT_C; 659 else 660 return port == PORT_B || port == PORT_C || port == PORT_D; 661} 662 663static bool assert_hdmi_port_valid(struct intel_display *display, enum port port) 664{ 665 return !drm_WARN(display->drm, !is_hdmi_port_valid(display, port), 666 "Platform does not support HDMI %c\n", port_name(port)); 667} 668 669bool g4x_hdmi_init(struct intel_display *display, 670 i915_reg_t hdmi_reg, enum port port) 671{ 672 const struct intel_bios_encoder_data *devdata; 673 struct intel_digital_port *dig_port; 674 struct intel_encoder *intel_encoder; 675 struct intel_connector *intel_connector; 676 677 if (!assert_port_valid(display, port)) 678 return false; 679 680 if (!assert_hdmi_port_valid(display, port)) 681 return false; 682 683 devdata = intel_bios_encoder_data_lookup(display, port); 684 685 /* FIXME bail? */ 686 if (!devdata) 687 drm_dbg_kms(display->drm, "No VBT child device for HDMI-%c\n", 688 port_name(port)); 689 690 dig_port = intel_dig_port_alloc(); 691 if (!dig_port) 692 return false; 693 694 intel_connector = intel_connector_alloc(); 695 if (!intel_connector) 696 goto err_connector_alloc; 697 698 intel_encoder = &dig_port->base; 699 700 intel_encoder->devdata = devdata; 701 702 if (drm_encoder_init(display->drm, &intel_encoder->base, 703 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 704 "HDMI %c", port_name(port))) 705 goto err_encoder_init; 706 707 intel_encoder->hotplug = intel_hdmi_hotplug; 708 intel_encoder->compute_config = g4x_hdmi_compute_config; 709 if (HAS_PCH_SPLIT(display)) { 710 intel_encoder->disable = pch_disable_hdmi; 711 intel_encoder->post_disable = pch_post_disable_hdmi; 712 } else { 713 intel_encoder->disable = g4x_disable_hdmi; 714 } 715 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 716 intel_encoder->get_config = intel_hdmi_get_config; 717 if (display->platform.cherryview) { 718 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 719 intel_encoder->pre_enable = chv_hdmi_pre_enable; 720 intel_encoder->enable = vlv_enable_hdmi; 721 intel_encoder->post_disable = chv_hdmi_post_disable; 722 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 723 } else if (display->platform.valleyview) { 724 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 725 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 726 intel_encoder->enable = vlv_enable_hdmi; 727 intel_encoder->post_disable = vlv_hdmi_post_disable; 728 } else { 729 intel_encoder->pre_enable = intel_hdmi_pre_enable; 730 if (HAS_PCH_CPT(display)) 731 intel_encoder->enable = cpt_enable_hdmi; 732 else if (HAS_PCH_IBX(display)) 733 intel_encoder->enable = ibx_enable_hdmi; 734 else 735 intel_encoder->enable = g4x_enable_hdmi; 736 } 737 intel_encoder->audio_enable = g4x_hdmi_audio_enable; 738 intel_encoder->audio_disable = g4x_hdmi_audio_disable; 739 intel_encoder->shutdown = intel_hdmi_encoder_shutdown; 740 741 intel_encoder->type = INTEL_OUTPUT_HDMI; 742 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 743 intel_encoder->port = port; 744 if (display->platform.cherryview) { 745 if (port == PORT_D) 746 intel_encoder->pipe_mask = BIT(PIPE_C); 747 else 748 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 749 } else { 750 intel_encoder->pipe_mask = ~0; 751 } 752 intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG); 753 intel_encoder->hpd_pin = intel_hpd_pin_default(port); 754 /* 755 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 756 * to work on real hardware. And since g4x can send infoframes to 757 * only one port anyway, nothing is lost by allowing it. 758 */ 759 if (display->platform.g4x) 760 intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI); 761 762 dig_port->hdmi.hdmi_reg = hdmi_reg; 763 764 intel_infoframe_init(dig_port); 765 766 if (!intel_hdmi_init_connector(dig_port, intel_connector)) 767 goto err_init_connector; 768 769 return true; 770 771err_init_connector: 772 drm_encoder_cleanup(&intel_encoder->base); 773err_encoder_init: 774 kfree(intel_connector); 775err_connector_alloc: 776 kfree(dig_port); 777 778 return false; 779}
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