kirin_drm_ade.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Hisilicon Hi6220 SoC ADE(Advanced Display Engine)'s crtc&plane driver
  4 *
  5 * Copyright (c) 2016 Linaro Limited.
  6 * Copyright (c) 2014-2016 HiSilicon Limited.
  7 *
  8 * Author:
  9 *	Xinliang Liu <z.liuxinliang@hisilicon.com>
 10 *	Xinliang Liu <xinliang.liu@linaro.org>
 11 *	Xinwei Kong <kong.kongxinwei@hisilicon.com>
 12 */
 13
 14#include <linux/bitops.h>
 15#include <linux/clk.h>
 16#include <linux/mfd/syscon.h>
 17#include <linux/platform_device.h>
 18#include <linux/regmap.h>
 19#include <linux/reset.h>
 20
 21#include <video/display_timing.h>
 22
 23#include <drm/drm_atomic.h>
 24#include <drm/drm_atomic_helper.h>
 25#include <drm/drm_crtc.h>
 26#include <drm/drm_drv.h>
 27#include <drm/drm_fb_dma_helper.h>
 28#include <drm/drm_fbdev_dma.h>
 29#include <drm/drm_fourcc.h>
 30#include <drm/drm_framebuffer.h>
 31#include <drm/drm_gem_dma_helper.h>
 32#include <drm/drm_print.h>
 33#include <drm/drm_probe_helper.h>
 34#include <drm/drm_vblank.h>
 35#include <drm/drm_gem_framebuffer_helper.h>
 36
 37#include "kirin_drm_drv.h"
 38#include "kirin_ade_reg.h"
 39
 40#define OUT_OVLY	ADE_OVLY2 /* output overlay compositor */
 41#define ADE_DEBUG	1
 42
 43
 44struct ade_hw_ctx {
 45	void __iomem  *base;
 46	struct regmap *noc_regmap;
 47	struct clk *ade_core_clk;
 48	struct clk *media_noc_clk;
 49	struct clk *ade_pix_clk;
 50	struct reset_control *reset;
 51	bool power_on;
 52	int irq;
 53
 54	struct drm_crtc *crtc;
 55};
 56
 57static const struct kirin_format ade_formats[] = {
 58	/* 16bpp RGB: */
 59	{ DRM_FORMAT_RGB565, ADE_RGB_565 },
 60	{ DRM_FORMAT_BGR565, ADE_BGR_565 },
 61	/* 24bpp RGB: */
 62	{ DRM_FORMAT_RGB888, ADE_RGB_888 },
 63	{ DRM_FORMAT_BGR888, ADE_BGR_888 },
 64	/* 32bpp [A]RGB: */
 65	{ DRM_FORMAT_XRGB8888, ADE_XRGB_8888 },
 66	{ DRM_FORMAT_XBGR8888, ADE_XBGR_8888 },
 67	{ DRM_FORMAT_RGBA8888, ADE_RGBA_8888 },
 68	{ DRM_FORMAT_BGRA8888, ADE_BGRA_8888 },
 69	{ DRM_FORMAT_ARGB8888, ADE_ARGB_8888 },
 70	{ DRM_FORMAT_ABGR8888, ADE_ABGR_8888 },
 71};
 72
 73static const u32 channel_formats[] = {
 74	/* channel 1,2,3,4 */
 75	DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888,
 76	DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
 77	DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888,
 78	DRM_FORMAT_ABGR8888
 79};
 80
 81/* convert from fourcc format to ade format */
 82static u32 ade_get_format(u32 pixel_format)
 83{
 84	int i;
 85
 86	for (i = 0; i < ARRAY_SIZE(ade_formats); i++)
 87		if (ade_formats[i].pixel_format == pixel_format)
 88			return ade_formats[i].hw_format;
 89
 90	/* not found */
 91	DRM_ERROR("Not found pixel format!!fourcc_format= %d\n",
 92		  pixel_format);
 93	return ADE_FORMAT_UNSUPPORT;
 94}
 95
 96static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val)
 97{
 98	u32 bit_ofst, reg_num;
 99
100	bit_ofst = bit_num % 32;
101	reg_num = bit_num / 32;
102
103	ade_update_bits(base + ADE_RELOAD_DIS(reg_num), bit_ofst,
104			MASK(1), !!val);
105}
106
107static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num)
108{
109	u32 tmp, bit_ofst, reg_num;
110
111	bit_ofst = bit_num % 32;
112	reg_num = bit_num / 32;
113
114	tmp = readl(base + ADE_RELOAD_DIS(reg_num));
115	return !!(BIT(bit_ofst) & tmp);
116}
117
118static void ade_init(struct ade_hw_ctx *ctx)
119{
120	void __iomem *base = ctx->base;
121
122	/* enable clk gate */
123	ade_update_bits(base + ADE_CTRL1, AUTO_CLK_GATE_EN_OFST,
124			AUTO_CLK_GATE_EN, ADE_ENABLE);
125	/* clear overlay */
126	writel(0, base + ADE_OVLY1_TRANS_CFG);
127	writel(0, base + ADE_OVLY_CTL);
128	writel(0, base + ADE_OVLYX_CTL(OUT_OVLY));
129	/* clear reset and reload regs */
130	writel(MASK(32), base + ADE_SOFT_RST_SEL(0));
131	writel(MASK(32), base + ADE_SOFT_RST_SEL(1));
132	writel(MASK(32), base + ADE_RELOAD_DIS(0));
133	writel(MASK(32), base + ADE_RELOAD_DIS(1));
134	/*
135	 * for video mode, all the ade registers should
136	 * become effective at frame end.
137	 */
138	ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST,
139			FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND);
140}
141
142static bool ade_crtc_mode_fixup(struct drm_crtc *crtc,
143				const struct drm_display_mode *mode,
144				struct drm_display_mode *adjusted_mode)
145{
146	struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
147	struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
148
149	adjusted_mode->clock =
150		clk_round_rate(ctx->ade_pix_clk, mode->clock * 1000) / 1000;
151	return true;
152}
153
154
155static void ade_set_pix_clk(struct ade_hw_ctx *ctx,
156			    struct drm_display_mode *mode,
157			    struct drm_display_mode *adj_mode)
158{
159	u32 clk_Hz = mode->clock * 1000;
160	int ret;
161
162	/*
163	 * Success should be guaranteed in mode_valid call back,
164	 * so failure shouldn't happen here
165	 */
166	ret = clk_set_rate(ctx->ade_pix_clk, clk_Hz);
167	if (ret)
168		DRM_ERROR("failed to set pixel clk %dHz (%d)\n", clk_Hz, ret);
169	adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000;
170}
171
172static void ade_ldi_set_mode(struct ade_hw_ctx *ctx,
173			     struct drm_display_mode *mode,
174			     struct drm_display_mode *adj_mode)
175{
176	void __iomem *base = ctx->base;
177	u32 width = mode->hdisplay;
178	u32 height = mode->vdisplay;
179	u32 hfp, hbp, hsw, vfp, vbp, vsw;
180	u32 plr_flags;
181
182	plr_flags = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? FLAG_NVSYNC : 0;
183	plr_flags |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? FLAG_NHSYNC : 0;
184	hfp = mode->hsync_start - mode->hdisplay;
185	hbp = mode->htotal - mode->hsync_end;
186	hsw = mode->hsync_end - mode->hsync_start;
187	vfp = mode->vsync_start - mode->vdisplay;
188	vbp = mode->vtotal - mode->vsync_end;
189	vsw = mode->vsync_end - mode->vsync_start;
190	if (vsw > 15) {
191		DRM_DEBUG_DRIVER("vsw exceeded 15\n");
192		vsw = 15;
193	}
194
195	writel((hbp << HBP_OFST) | hfp, base + LDI_HRZ_CTRL0);
196	 /* the configured value is actual value - 1 */
197	writel(hsw - 1, base + LDI_HRZ_CTRL1);
198	writel((vbp << VBP_OFST) | vfp, base + LDI_VRT_CTRL0);
199	 /* the configured value is actual value - 1 */
200	writel(vsw - 1, base + LDI_VRT_CTRL1);
201	 /* the configured value is actual value - 1 */
202	writel(((height - 1) << VSIZE_OFST) | (width - 1),
203	       base + LDI_DSP_SIZE);
204	writel(plr_flags, base + LDI_PLR_CTRL);
205
206	/* set overlay compositor output size */
207	writel(((width - 1) << OUTPUT_XSIZE_OFST) | (height - 1),
208	       base + ADE_OVLY_OUTPUT_SIZE(OUT_OVLY));
209
210	/* ctran6 setting */
211	writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6));
212	 /* the configured value is actual value - 1 */
213	writel(width * height - 1, base + ADE_CTRAN_IMAGE_SIZE(ADE_CTRAN6));
214	ade_update_reload_bit(base, CTRAN_OFST + ADE_CTRAN6, 0);
215
216	ade_set_pix_clk(ctx, mode, adj_mode);
217
218	DRM_DEBUG_DRIVER("set mode: %dx%d\n", width, height);
219}
220
221static int ade_power_up(struct ade_hw_ctx *ctx)
222{
223	int ret;
224
225	ret = clk_prepare_enable(ctx->media_noc_clk);
226	if (ret) {
227		DRM_ERROR("failed to enable media_noc_clk (%d)\n", ret);
228		return ret;
229	}
230
231	ret = reset_control_deassert(ctx->reset);
232	if (ret) {
233		DRM_ERROR("failed to deassert reset\n");
234		return ret;
235	}
236
237	ret = clk_prepare_enable(ctx->ade_core_clk);
238	if (ret) {
239		DRM_ERROR("failed to enable ade_core_clk (%d)\n", ret);
240		return ret;
241	}
242
243	ade_init(ctx);
244	ctx->power_on = true;
245	return 0;
246}
247
248static void ade_power_down(struct ade_hw_ctx *ctx)
249{
250	void __iomem *base = ctx->base;
251
252	writel(ADE_DISABLE, base + LDI_CTRL);
253	/* dsi pixel off */
254	writel(DSI_PCLK_OFF, base + LDI_HDMI_DSI_GT);
255
256	clk_disable_unprepare(ctx->ade_core_clk);
257	reset_control_assert(ctx->reset);
258	clk_disable_unprepare(ctx->media_noc_clk);
259	ctx->power_on = false;
260}
261
262static void ade_set_medianoc_qos(struct ade_hw_ctx *ctx)
263{
264	struct regmap *map = ctx->noc_regmap;
265
266	regmap_update_bits(map, ADE0_QOSGENERATOR_MODE,
267			   QOSGENERATOR_MODE_MASK, BYPASS_MODE);
268	regmap_update_bits(map, ADE0_QOSGENERATOR_EXTCONTROL,
269			   SOCKET_QOS_EN, SOCKET_QOS_EN);
270
271	regmap_update_bits(map, ADE1_QOSGENERATOR_MODE,
272			   QOSGENERATOR_MODE_MASK, BYPASS_MODE);
273	regmap_update_bits(map, ADE1_QOSGENERATOR_EXTCONTROL,
274			   SOCKET_QOS_EN, SOCKET_QOS_EN);
275}
276
277static int ade_crtc_enable_vblank(struct drm_crtc *crtc)
278{
279	struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
280	struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
281	void __iomem *base = ctx->base;
282
283	if (!ctx->power_on)
284		(void)ade_power_up(ctx);
285
286	ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
287			MASK(1), 1);
288
289	return 0;
290}
291
292static void ade_crtc_disable_vblank(struct drm_crtc *crtc)
293{
294	struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
295	struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
296	void __iomem *base = ctx->base;
297
298	if (!ctx->power_on) {
299		DRM_ERROR("power is down! vblank disable fail\n");
300		return;
301	}
302
303	ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST,
304			MASK(1), 0);
305}
306
307static irqreturn_t ade_irq_handler(int irq, void *data)
308{
309	struct ade_hw_ctx *ctx = data;
310	struct drm_crtc *crtc = ctx->crtc;
311	void __iomem *base = ctx->base;
312	u32 status;
313
314	status = readl(base + LDI_MSK_INT);
315	DRM_DEBUG_VBL("LDI IRQ: status=0x%X\n", status);
316
317	/* vblank irq */
318	if (status & BIT(FRAME_END_INT_EN_OFST)) {
319		ade_update_bits(base + LDI_INT_CLR, FRAME_END_INT_EN_OFST,
320				MASK(1), 1);
321		drm_crtc_handle_vblank(crtc);
322	}
323
324	return IRQ_HANDLED;
325}
326
327static void ade_display_enable(struct ade_hw_ctx *ctx)
328{
329	void __iomem *base = ctx->base;
330	u32 out_fmt = LDI_OUT_RGB_888;
331
332	/* enable output overlay compositor */
333	writel(ADE_ENABLE, base + ADE_OVLYX_CTL(OUT_OVLY));
334	ade_update_reload_bit(base, OVLY_OFST + OUT_OVLY, 0);
335
336	/* display source setting */
337	writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG);
338
339	/* enable ade */
340	writel(ADE_ENABLE, base + ADE_EN);
341	/* enable ldi */
342	writel(NORMAL_MODE, base + LDI_WORK_MODE);
343	writel((out_fmt << BPP_OFST) | DATA_GATE_EN | LDI_EN,
344	       base + LDI_CTRL);
345	/* dsi pixel on */
346	writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT);
347}
348
349#if ADE_DEBUG
350static void ade_rdma_dump_regs(void __iomem *base, u32 ch)
351{
352	u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
353	u32 val;
354
355	reg_ctrl = RD_CH_CTRL(ch);
356	reg_addr = RD_CH_ADDR(ch);
357	reg_size = RD_CH_SIZE(ch);
358	reg_stride = RD_CH_STRIDE(ch);
359	reg_space = RD_CH_SPACE(ch);
360	reg_en = RD_CH_EN(ch);
361
362	val = ade_read_reload_bit(base, RDMA_OFST + ch);
363	DRM_DEBUG_DRIVER("[rdma%d]: reload(%d)\n", ch + 1, val);
364	val = readl(base + reg_ctrl);
365	DRM_DEBUG_DRIVER("[rdma%d]: reg_ctrl(0x%08x)\n", ch + 1, val);
366	val = readl(base + reg_addr);
367	DRM_DEBUG_DRIVER("[rdma%d]: reg_addr(0x%08x)\n", ch + 1, val);
368	val = readl(base + reg_size);
369	DRM_DEBUG_DRIVER("[rdma%d]: reg_size(0x%08x)\n", ch + 1, val);
370	val = readl(base + reg_stride);
371	DRM_DEBUG_DRIVER("[rdma%d]: reg_stride(0x%08x)\n", ch + 1, val);
372	val = readl(base + reg_space);
373	DRM_DEBUG_DRIVER("[rdma%d]: reg_space(0x%08x)\n", ch + 1, val);
374	val = readl(base + reg_en);
375	DRM_DEBUG_DRIVER("[rdma%d]: reg_en(0x%08x)\n", ch + 1, val);
376}
377
378static void ade_clip_dump_regs(void __iomem *base, u32 ch)
379{
380	u32 val;
381
382	val = ade_read_reload_bit(base, CLIP_OFST + ch);
383	DRM_DEBUG_DRIVER("[clip%d]: reload(%d)\n", ch + 1, val);
384	val = readl(base + ADE_CLIP_DISABLE(ch));
385	DRM_DEBUG_DRIVER("[clip%d]: reg_clip_disable(0x%08x)\n", ch + 1, val);
386	val = readl(base + ADE_CLIP_SIZE0(ch));
387	DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size0(0x%08x)\n", ch + 1, val);
388	val = readl(base + ADE_CLIP_SIZE1(ch));
389	DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size1(0x%08x)\n", ch + 1, val);
390}
391
392static void ade_compositor_routing_dump_regs(void __iomem *base, u32 ch)
393{
394	u8 ovly_ch = 0; /* TODO: Only primary plane now */
395	u32 val;
396
397	val = readl(base + ADE_OVLY_CH_XY0(ovly_ch));
398	DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy0(0x%08x)\n", ovly_ch, val);
399	val = readl(base + ADE_OVLY_CH_XY1(ovly_ch));
400	DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy1(0x%08x)\n", ovly_ch, val);
401	val = readl(base + ADE_OVLY_CH_CTL(ovly_ch));
402	DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_ctl(0x%08x)\n", ovly_ch, val);
403}
404
405static void ade_dump_overlay_compositor_regs(void __iomem *base, u32 comp)
406{
407	u32 val;
408
409	val = ade_read_reload_bit(base, OVLY_OFST + comp);
410	DRM_DEBUG_DRIVER("[overlay%d]: reload(%d)\n", comp + 1, val);
411	writel(ADE_ENABLE, base + ADE_OVLYX_CTL(comp));
412	DRM_DEBUG_DRIVER("[overlay%d]: reg_ctl(0x%08x)\n", comp + 1, val);
413	val = readl(base + ADE_OVLY_CTL);
414	DRM_DEBUG_DRIVER("ovly_ctl(0x%08x)\n", val);
415}
416
417static void ade_dump_regs(void __iomem *base)
418{
419	u32 i;
420
421	/* dump channel regs */
422	for (i = 0; i < ADE_CH_NUM; i++) {
423		/* dump rdma regs */
424		ade_rdma_dump_regs(base, i);
425
426		/* dump clip regs */
427		ade_clip_dump_regs(base, i);
428
429		/* dump compositor routing regs */
430		ade_compositor_routing_dump_regs(base, i);
431	}
432
433	/* dump overlay compositor regs */
434	ade_dump_overlay_compositor_regs(base, OUT_OVLY);
435}
436#else
437static void ade_dump_regs(void __iomem *base) { }
438#endif
439
440static void ade_crtc_atomic_enable(struct drm_crtc *crtc,
441				   struct drm_atomic_state *state)
442{
443	struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
444	struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
445	int ret;
446
447	if (kcrtc->enable)
448		return;
449
450	if (!ctx->power_on) {
451		ret = ade_power_up(ctx);
452		if (ret)
453			return;
454	}
455
456	ade_set_medianoc_qos(ctx);
457	ade_display_enable(ctx);
458	ade_dump_regs(ctx->base);
459	drm_crtc_vblank_on(crtc);
460	kcrtc->enable = true;
461}
462
463static void ade_crtc_atomic_disable(struct drm_crtc *crtc,
464				    struct drm_atomic_state *state)
465{
466	struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
467	struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
468
469	if (!kcrtc->enable)
470		return;
471
472	drm_crtc_vblank_off(crtc);
473	ade_power_down(ctx);
474	kcrtc->enable = false;
475}
476
477static void ade_crtc_mode_set_nofb(struct drm_crtc *crtc)
478{
479	struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
480	struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
481	struct drm_display_mode *mode = &crtc->state->mode;
482	struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode;
483
484	if (!ctx->power_on)
485		(void)ade_power_up(ctx);
486	ade_ldi_set_mode(ctx, mode, adj_mode);
487}
488
489static void ade_crtc_atomic_begin(struct drm_crtc *crtc,
490				  struct drm_atomic_state *state)
491{
492	struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
493	struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
494	struct drm_display_mode *mode = &crtc->state->mode;
495	struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode;
496
497	if (!ctx->power_on)
498		(void)ade_power_up(ctx);
499	ade_ldi_set_mode(ctx, mode, adj_mode);
500}
501
502static void ade_crtc_atomic_flush(struct drm_crtc *crtc,
503				  struct drm_atomic_state *state)
504
505{
506	struct kirin_crtc *kcrtc = to_kirin_crtc(crtc);
507	struct ade_hw_ctx *ctx = kcrtc->hw_ctx;
508	struct drm_pending_vblank_event *event = crtc->state->event;
509	void __iomem *base = ctx->base;
510
511	/* only crtc is enabled regs take effect */
512	if (kcrtc->enable) {
513		ade_dump_regs(base);
514		/* flush ade registers */
515		writel(ADE_ENABLE, base + ADE_EN);
516	}
517
518	if (event) {
519		crtc->state->event = NULL;
520
521		spin_lock_irq(&crtc->dev->event_lock);
522		if (drm_crtc_vblank_get(crtc) == 0)
523			drm_crtc_arm_vblank_event(crtc, event);
524		else
525			drm_crtc_send_vblank_event(crtc, event);
526		spin_unlock_irq(&crtc->dev->event_lock);
527	}
528}
529
530static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs = {
531	.mode_fixup	= ade_crtc_mode_fixup,
532	.mode_set_nofb	= ade_crtc_mode_set_nofb,
533	.atomic_begin	= ade_crtc_atomic_begin,
534	.atomic_flush	= ade_crtc_atomic_flush,
535	.atomic_enable	= ade_crtc_atomic_enable,
536	.atomic_disable	= ade_crtc_atomic_disable,
537};
538
539static const struct drm_crtc_funcs ade_crtc_funcs = {
540	.destroy	= drm_crtc_cleanup,
541	.set_config	= drm_atomic_helper_set_config,
542	.page_flip	= drm_atomic_helper_page_flip,
543	.reset		= drm_atomic_helper_crtc_reset,
544	.atomic_duplicate_state	= drm_atomic_helper_crtc_duplicate_state,
545	.atomic_destroy_state	= drm_atomic_helper_crtc_destroy_state,
546	.enable_vblank	= ade_crtc_enable_vblank,
547	.disable_vblank	= ade_crtc_disable_vblank,
548};
549
550static void ade_rdma_set(void __iomem *base, struct drm_framebuffer *fb,
551			 u32 ch, u32 y, u32 in_h, u32 fmt)
552{
553	struct drm_gem_dma_object *obj = drm_fb_dma_get_gem_obj(fb, 0);
554	u32 reg_ctrl, reg_addr, reg_size, reg_stride, reg_space, reg_en;
555	u32 stride = fb->pitches[0];
556	u32 addr = (u32) obj->dma_addr + y * stride;
557
558	DRM_DEBUG_DRIVER("rdma%d: (y=%d, height=%d), stride=%d, paddr=0x%x\n",
559			 ch + 1, y, in_h, stride, (u32) obj->dma_addr);
560	DRM_DEBUG_DRIVER("addr=0x%x, fb:%dx%d, pixel_format=%d(%p4cc)\n",
561			 addr, fb->width, fb->height, fmt,
562			 &fb->format->format);
563
564	/* get reg offset */
565	reg_ctrl = RD_CH_CTRL(ch);
566	reg_addr = RD_CH_ADDR(ch);
567	reg_size = RD_CH_SIZE(ch);
568	reg_stride = RD_CH_STRIDE(ch);
569	reg_space = RD_CH_SPACE(ch);
570	reg_en = RD_CH_EN(ch);
571
572	/*
573	 * TODO: set rotation
574	 */
575	writel((fmt << 16) & 0x1f0000, base + reg_ctrl);
576	writel(addr, base + reg_addr);
577	writel((in_h << 16) | stride, base + reg_size);
578	writel(stride, base + reg_stride);
579	writel(in_h * stride, base + reg_space);
580	writel(ADE_ENABLE, base + reg_en);
581	ade_update_reload_bit(base, RDMA_OFST + ch, 0);
582}
583
584static void ade_rdma_disable(void __iomem *base, u32 ch)
585{
586	u32 reg_en;
587
588	/* get reg offset */
589	reg_en = RD_CH_EN(ch);
590	writel(0, base + reg_en);
591	ade_update_reload_bit(base, RDMA_OFST + ch, 1);
592}
593
594static void ade_clip_set(void __iomem *base, u32 ch, u32 fb_w, u32 x,
595			 u32 in_w, u32 in_h)
596{
597	u32 disable_val;
598	u32 clip_left;
599	u32 clip_right;
600
601	/*
602	 * clip width, no need to clip height
603	 */
604	if (fb_w == in_w) { /* bypass */
605		disable_val = 1;
606		clip_left = 0;
607		clip_right = 0;
608	} else {
609		disable_val = 0;
610		clip_left = x;
611		clip_right = fb_w - (x + in_w) - 1;
612	}
613
614	DRM_DEBUG_DRIVER("clip%d: clip_left=%d, clip_right=%d\n",
615			 ch + 1, clip_left, clip_right);
616
617	writel(disable_val, base + ADE_CLIP_DISABLE(ch));
618	writel((fb_w - 1) << 16 | (in_h - 1), base + ADE_CLIP_SIZE0(ch));
619	writel(clip_left << 16 | clip_right, base + ADE_CLIP_SIZE1(ch));
620	ade_update_reload_bit(base, CLIP_OFST + ch, 0);
621}
622
623static void ade_clip_disable(void __iomem *base, u32 ch)
624{
625	writel(1, base + ADE_CLIP_DISABLE(ch));
626	ade_update_reload_bit(base, CLIP_OFST + ch, 1);
627}
628
629static bool has_Alpha_channel(int format)
630{
631	switch (format) {
632	case ADE_ARGB_8888:
633	case ADE_ABGR_8888:
634	case ADE_RGBA_8888:
635	case ADE_BGRA_8888:
636		return true;
637	default:
638		return false;
639	}
640}
641
642static void ade_get_blending_params(u32 fmt, u8 glb_alpha, u8 *alp_mode,
643				    u8 *alp_sel, u8 *under_alp_sel)
644{
645	bool has_alpha = has_Alpha_channel(fmt);
646
647	/*
648	 * get alp_mode
649	 */
650	if (has_alpha && glb_alpha < 255)
651		*alp_mode = ADE_ALP_PIXEL_AND_GLB;
652	else if (has_alpha)
653		*alp_mode = ADE_ALP_PIXEL;
654	else
655		*alp_mode = ADE_ALP_GLOBAL;
656
657	/*
658	 * get alp sel
659	 */
660	*alp_sel = ADE_ALP_MUL_COEFF_3; /* 1 */
661	*under_alp_sel = ADE_ALP_MUL_COEFF_2; /* 0 */
662}
663
664static void ade_compositor_routing_set(void __iomem *base, u8 ch,
665				       u32 x0, u32 y0,
666				       u32 in_w, u32 in_h, u32 fmt)
667{
668	u8 ovly_ch = 0; /* TODO: This is the zpos, only one plane now */
669	u8 glb_alpha = 255;
670	u32 x1 = x0 + in_w - 1;
671	u32 y1 = y0 + in_h - 1;
672	u32 val;
673	u8 alp_sel;
674	u8 under_alp_sel;
675	u8 alp_mode;
676
677	ade_get_blending_params(fmt, glb_alpha, &alp_mode, &alp_sel,
678				&under_alp_sel);
679
680	/* overlay routing setting
681	 */
682	writel(x0 << 16 | y0, base + ADE_OVLY_CH_XY0(ovly_ch));
683	writel(x1 << 16 | y1, base + ADE_OVLY_CH_XY1(ovly_ch));
684	val = (ch + 1) << CH_SEL_OFST | BIT(CH_EN_OFST) |
685		alp_sel << CH_ALP_SEL_OFST |
686		under_alp_sel << CH_UNDER_ALP_SEL_OFST |
687		glb_alpha << CH_ALP_GBL_OFST |
688		alp_mode << CH_ALP_MODE_OFST;
689	writel(val, base + ADE_OVLY_CH_CTL(ovly_ch));
690	/* connect this plane/channel to overlay2 compositor */
691	ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch),
692			CH_OVLY_SEL_MASK, CH_OVLY_SEL_VAL(OUT_OVLY));
693}
694
695static void ade_compositor_routing_disable(void __iomem *base, u32 ch)
696{
697	u8 ovly_ch = 0; /* TODO: Only primary plane now */
698
699	/* disable this plane/channel */
700	ade_update_bits(base + ADE_OVLY_CH_CTL(ovly_ch), CH_EN_OFST,
701			MASK(1), 0);
702	/* dis-connect this plane/channel of overlay2 compositor */
703	ade_update_bits(base + ADE_OVLY_CTL, CH_OVLY_SEL_OFST(ovly_ch),
704			CH_OVLY_SEL_MASK, 0);
705}
706
707/*
708 * Typicaly, a channel looks like: DMA-->clip-->scale-->ctrans-->compositor
709 */
710static void ade_update_channel(struct kirin_plane *kplane,
711			       struct drm_framebuffer *fb, int crtc_x,
712			       int crtc_y, unsigned int crtc_w,
713			       unsigned int crtc_h, u32 src_x,
714			       u32 src_y, u32 src_w, u32 src_h)
715{
716	struct ade_hw_ctx *ctx = kplane->hw_ctx;
717	void __iomem *base = ctx->base;
718	u32 fmt = ade_get_format(fb->format->format);
719	u32 ch = kplane->ch;
720	u32 in_w;
721	u32 in_h;
722
723	DRM_DEBUG_DRIVER("channel%d: src:(%d, %d)-%dx%d, crtc:(%d, %d)-%dx%d",
724			 ch + 1, src_x, src_y, src_w, src_h,
725			 crtc_x, crtc_y, crtc_w, crtc_h);
726
727	/* 1) DMA setting */
728	in_w = src_w;
729	in_h = src_h;
730	ade_rdma_set(base, fb, ch, src_y, in_h, fmt);
731
732	/* 2) clip setting */
733	ade_clip_set(base, ch, fb->width, src_x, in_w, in_h);
734
735	/* 3) TODO: scale setting for overlay planes */
736
737	/* 4) TODO: ctran/csc setting for overlay planes */
738
739	/* 5) compositor routing setting */
740	ade_compositor_routing_set(base, ch, crtc_x, crtc_y, in_w, in_h, fmt);
741}
742
743static void ade_disable_channel(struct kirin_plane *kplane)
744{
745	struct ade_hw_ctx *ctx = kplane->hw_ctx;
746	void __iomem *base = ctx->base;
747	u32 ch = kplane->ch;
748
749	DRM_DEBUG_DRIVER("disable channel%d\n", ch + 1);
750
751	/* disable read DMA */
752	ade_rdma_disable(base, ch);
753
754	/* disable clip */
755	ade_clip_disable(base, ch);
756
757	/* disable compositor routing */
758	ade_compositor_routing_disable(base, ch);
759}
760
761static int ade_plane_atomic_check(struct drm_plane *plane,
762				  struct drm_atomic_state *state)
763{
764	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
765										 plane);
766	struct drm_framebuffer *fb = new_plane_state->fb;
767	struct drm_crtc *crtc = new_plane_state->crtc;
768	struct drm_crtc_state *crtc_state;
769	u32 src_x = new_plane_state->src_x >> 16;
770	u32 src_y = new_plane_state->src_y >> 16;
771	u32 src_w = new_plane_state->src_w >> 16;
772	u32 src_h = new_plane_state->src_h >> 16;
773	int crtc_x = new_plane_state->crtc_x;
774	int crtc_y = new_plane_state->crtc_y;
775	u32 crtc_w = new_plane_state->crtc_w;
776	u32 crtc_h = new_plane_state->crtc_h;
777	u32 fmt;
778
779	if (!crtc || !fb)
780		return 0;
781
782	fmt = ade_get_format(fb->format->format);
783	if (fmt == ADE_FORMAT_UNSUPPORT)
784		return -EINVAL;
785
786	crtc_state = drm_atomic_get_crtc_state(state, crtc);
787	if (IS_ERR(crtc_state))
788		return PTR_ERR(crtc_state);
789
790	if (src_w != crtc_w || src_h != crtc_h) {
791		return -EINVAL;
792	}
793
794	if (src_x + src_w > fb->width ||
795	    src_y + src_h > fb->height)
796		return -EINVAL;
797
798	if (crtc_x < 0 || crtc_y < 0)
799		return -EINVAL;
800
801	if (crtc_x + crtc_w > crtc_state->adjusted_mode.hdisplay ||
802	    crtc_y + crtc_h > crtc_state->adjusted_mode.vdisplay)
803		return -EINVAL;
804
805	return 0;
806}
807
808static void ade_plane_atomic_update(struct drm_plane *plane,
809				    struct drm_atomic_state *state)
810{
811	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
812									   plane);
813	struct kirin_plane *kplane = to_kirin_plane(plane);
814
815	ade_update_channel(kplane, new_state->fb, new_state->crtc_x,
816			   new_state->crtc_y,
817			   new_state->crtc_w, new_state->crtc_h,
818			   new_state->src_x >> 16, new_state->src_y >> 16,
819			   new_state->src_w >> 16, new_state->src_h >> 16);
820}
821
822static void ade_plane_atomic_disable(struct drm_plane *plane,
823				     struct drm_atomic_state *state)
824{
825	struct kirin_plane *kplane = to_kirin_plane(plane);
826
827	ade_disable_channel(kplane);
828}
829
830static const struct drm_plane_helper_funcs ade_plane_helper_funcs = {
831	.atomic_check = ade_plane_atomic_check,
832	.atomic_update = ade_plane_atomic_update,
833	.atomic_disable = ade_plane_atomic_disable,
834};
835
836static struct drm_plane_funcs ade_plane_funcs = {
837	.update_plane	= drm_atomic_helper_update_plane,
838	.disable_plane	= drm_atomic_helper_disable_plane,
839	.destroy = drm_plane_cleanup,
840	.reset = drm_atomic_helper_plane_reset,
841	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
842	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
843};
844
845static void *ade_hw_ctx_alloc(struct platform_device *pdev,
846			      struct drm_crtc *crtc)
847{
848	struct device *dev = &pdev->dev;
849	struct device_node *np = pdev->dev.of_node;
850	struct ade_hw_ctx *ctx = NULL;
851	int ret;
852
853	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
854	if (!ctx) {
855		DRM_ERROR("failed to alloc ade_hw_ctx\n");
856		return ERR_PTR(-ENOMEM);
857	}
858
859	ctx->base = devm_platform_ioremap_resource(pdev, 0);
860	if (IS_ERR(ctx->base)) {
861		DRM_ERROR("failed to remap ade io base\n");
862		return ERR_PTR(-EIO);
863	}
864
865	ctx->reset = devm_reset_control_get(dev, NULL);
866	if (IS_ERR(ctx->reset))
867		return ERR_PTR(-ENODEV);
868
869	ctx->noc_regmap =
870		syscon_regmap_lookup_by_phandle(np, "hisilicon,noc-syscon");
871	if (IS_ERR(ctx->noc_regmap)) {
872		DRM_ERROR("failed to get noc regmap\n");
873		return ERR_PTR(-ENODEV);
874	}
875
876	ctx->irq = platform_get_irq(pdev, 0);
877	if (ctx->irq < 0) {
878		DRM_ERROR("failed to get irq\n");
879		return ERR_PTR(-ENODEV);
880	}
881
882	ctx->ade_core_clk = devm_clk_get(dev, "clk_ade_core");
883	if (IS_ERR(ctx->ade_core_clk)) {
884		DRM_ERROR("failed to parse clk ADE_CORE\n");
885		return ERR_PTR(-ENODEV);
886	}
887
888	ctx->media_noc_clk = devm_clk_get(dev, "clk_codec_jpeg");
889	if (IS_ERR(ctx->media_noc_clk)) {
890		DRM_ERROR("failed to parse clk CODEC_JPEG\n");
891		return ERR_PTR(-ENODEV);
892	}
893
894	ctx->ade_pix_clk = devm_clk_get(dev, "clk_ade_pix");
895	if (IS_ERR(ctx->ade_pix_clk)) {
896		DRM_ERROR("failed to parse clk ADE_PIX\n");
897		return ERR_PTR(-ENODEV);
898	}
899
900	/* vblank irq init */
901	ret = devm_request_irq(dev, ctx->irq, ade_irq_handler,
902			       IRQF_SHARED, dev->driver->name, ctx);
903	if (ret)
904		return ERR_PTR(-EIO);
905
906	ctx->crtc = crtc;
907
908	return ctx;
909}
910
911static void ade_hw_ctx_cleanup(void *hw_ctx)
912{
913}
914
915static const struct drm_mode_config_funcs ade_mode_config_funcs = {
916	.fb_create = drm_gem_fb_create,
917	.atomic_check = drm_atomic_helper_check,
918	.atomic_commit = drm_atomic_helper_commit,
919
920};
921
922DEFINE_DRM_GEM_DMA_FOPS(ade_fops);
923
924static const struct drm_driver ade_driver = {
925	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
926	.fops = &ade_fops,
927	DRM_GEM_DMA_DRIVER_OPS,
928	DRM_FBDEV_DMA_DRIVER_OPS,
929	.name = "kirin",
930	.desc = "Hisilicon Kirin620 SoC DRM Driver",
931	.major = 1,
932	.minor = 0,
933};
934
935struct kirin_drm_data ade_driver_data = {
936	.num_planes = ADE_CH_NUM,
937	.prim_plane = ADE_CH1,
938	.channel_formats = channel_formats,
939	.channel_formats_cnt = ARRAY_SIZE(channel_formats),
940	.config_max_width = 2048,
941	.config_max_height = 2048,
942	.driver = &ade_driver,
943	.crtc_helper_funcs = &ade_crtc_helper_funcs,
944	.crtc_funcs = &ade_crtc_funcs,
945	.plane_helper_funcs = &ade_plane_helper_funcs,
946	.plane_funcs = &ade_plane_funcs,
947	.mode_config_funcs = &ade_mode_config_funcs,
948
949	.alloc_hw_ctx = ade_hw_ctx_alloc,
950	.cleanup_hw_ctx = ade_hw_ctx_cleanup,
951};