dp_serdes.c

 1// SPDX-License-Identifier: GPL-2.0-or-later
 2// Copyright (c) 2025 Hisilicon Limited.
 3
 4#include <linux/delay.h>
 5#include <drm/drm_device.h>
 6#include <drm/drm_print.h>
 7#include "dp_comm.h"
 8#include "dp_config.h"
 9#include "dp_reg.h"
10
11int hibmc_dp_serdes_set_tx_cfg(struct hibmc_dp_dev *dp, u8 train_set[HIBMC_DP_LANE_NUM_MAX])
12{
13	static const u32 serdes_tx_cfg[4][4] = { {DP_SERDES_VOL0_PRE0, DP_SERDES_VOL0_PRE1,
14						  DP_SERDES_VOL0_PRE2, DP_SERDES_VOL0_PRE3},
15						 {DP_SERDES_VOL1_PRE0, DP_SERDES_VOL1_PRE1,
16						  DP_SERDES_VOL1_PRE2}, {DP_SERDES_VOL2_PRE0,
17						  DP_SERDES_VOL2_PRE1}, {DP_SERDES_VOL3_PRE0}};
18	int cfg[2];
19	int i;
20
21	for (i = 0; i < HIBMC_DP_LANE_NUM_MAX; i++) {
22		cfg[i] = serdes_tx_cfg[FIELD_GET(DP_TRAIN_VOLTAGE_SWING_MASK, train_set[i])]
23				      [FIELD_GET(DP_TRAIN_PRE_EMPHASIS_MASK, train_set[i])];
24		if (!cfg[i])
25			return -EINVAL;
26
27		/* lane1 offset is 4 */
28		writel(FIELD_PREP(HIBMC_DP_PMA_TXDEEMPH, cfg[i]),
29		       dp->serdes_base + HIBMC_DP_PMA_LANE0_OFFSET + i * 4);
30	}
31
32	usleep_range(300, 500);
33
34	if (readl(dp->serdes_base + HIBMC_DP_LANE_STATUS_OFFSET) != DP_SERDES_DONE) {
35		drm_dbg_dp(dp->dev, "dp serdes cfg failed\n");
36		return -EAGAIN;
37	}
38
39	return 0;
40}
41
42int hibmc_dp_serdes_rate_switch(u8 rate, struct hibmc_dp_dev *dp)
43{
44	writel(rate, dp->serdes_base + HIBMC_DP_LANE0_RATE_OFFSET);
45	writel(rate, dp->serdes_base + HIBMC_DP_LANE1_RATE_OFFSET);
46
47	usleep_range(300, 500);
48
49	if (readl(dp->serdes_base + HIBMC_DP_LANE_STATUS_OFFSET) != DP_SERDES_DONE) {
50		drm_dbg_dp(dp->dev, "dp serdes rate switching failed\n");
51		return -EAGAIN;
52	}
53
54	if (rate < DP_SERDES_BW_8_1)
55		drm_dbg_dp(dp->dev, "reducing serdes rate to :%d\n",
56			   rate ? rate * HIBMC_DP_LINK_RATE_CAL * 10 : 162);
57
58	return 0;
59}
60
61int hibmc_dp_serdes_init(struct hibmc_dp_dev *dp)
62{
63	dp->serdes_base = dp->base + HIBMC_DP_HOST_OFFSET;
64
65	writel(FIELD_PREP(HIBMC_DP_PMA_TXDEEMPH, DP_SERDES_VOL0_PRE0),
66	       dp->serdes_base + HIBMC_DP_PMA_LANE0_OFFSET);
67	writel(FIELD_PREP(HIBMC_DP_PMA_TXDEEMPH, DP_SERDES_VOL0_PRE0),
68	       dp->serdes_base + HIBMC_DP_PMA_LANE1_OFFSET);
69
70	return hibmc_dp_serdes_rate_switch(DP_SERDES_BW_8_1, dp);
71}