dp_reg.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/* Copyright (c) 2024 Hisilicon Limited. */
  3
  4#ifndef DP_REG_H
  5#define DP_REG_H
  6
  7#define HIBMC_DP_AUX_CMD_ADDR			0x50
  8
  9#define HIBMC_DP_AUX_WR_DATA0			0x54
 10#define HIBMC_DP_AUX_WR_DATA1			0x58
 11#define HIBMC_DP_AUX_WR_DATA2			0x5c
 12#define HIBMC_DP_AUX_WR_DATA3			0x60
 13#define HIBMC_DP_AUX_RD_DATA0			0x64
 14
 15#define HIBMC_DP_AUX_REQ			0x74
 16#define HIBMC_DP_CFG_AUX_REQ			BIT(0)
 17#define HIBMC_DP_CFG_AUX_SYNC_LEN_SEL		BIT(1)
 18#define HIBMC_DP_CFG_AUX_TIMER_TIMEOUT		BIT(2)
 19#define HIBMC_DP_CFG_AUX_MIN_PULSE_NUM		GENMASK(13, 9)
 20
 21#define HIBMC_DP_AUX_STATUS			0x78
 22#define HIBMC_DP_CFG_AUX_TIMEOUT		BIT(0)
 23#define HIBMC_DP_CFG_AUX_STATUS			GENMASK(11, 4)
 24#define HIBMC_DP_CFG_AUX_READY_DATA_BYTE	GENMASK(16, 12)
 25#define HIBMC_DP_CFG_AUX			GENMASK(24, 17)
 26
 27#define HIBMC_DP_HPD_STATUS			0x98
 28#define HIBMC_DP_HPD_CUR_STATE		GENMASK(7, 4)
 29
 30#define HIBMC_DP_PHYIF_CTRL0			0xa0
 31#define HIBMC_DP_CFG_SCRAMBLE_EN		BIT(0)
 32#define HIBMC_DP_CFG_PAT_SEL			GENMASK(7, 4)
 33#define HIBMC_DP_CFG_LANE_DATA_EN		GENMASK(11, 8)
 34
 35#define HIBMC_DP_VIDEO_CTRL			0x100
 36#define HIBMC_DP_CFG_STREAM_RGB_ENABLE		BIT(1)
 37#define HIBMC_DP_CFG_STREAM_VIDEO_MAPPING	GENMASK(5, 2)
 38#define HIBMC_DP_CFG_STREAM_FRAME_MODE		BIT(6)
 39#define HIBMC_DP_CFG_STREAM_HSYNC_POLARITY	BIT(7)
 40#define HIBMC_DP_CFG_STREAM_VSYNC_POLARITY	BIT(8)
 41
 42#define HIBMC_DP_VIDEO_CONFIG0			0x104
 43#define HIBMC_DP_CFG_STREAM_HACTIVE		GENMASK(31, 16)
 44#define HIBMC_DP_CFG_STREAM_HBLANK		GENMASK(15, 0)
 45
 46#define HIBMC_DP_VIDEO_CONFIG1			0x108
 47#define HIBMC_DP_CFG_STREAM_VACTIVE		GENMASK(31, 16)
 48#define HIBMC_DP_CFG_STREAM_VBLANK		GENMASK(15, 0)
 49
 50#define HIBMC_DP_VIDEO_CONFIG2			0x10c
 51#define HIBMC_DP_CFG_STREAM_HSYNC_WIDTH		GENMASK(15, 0)
 52
 53#define HIBMC_DP_VIDEO_CONFIG3			0x110
 54#define HIBMC_DP_CFG_STREAM_VSYNC_WIDTH		GENMASK(15, 0)
 55#define HIBMC_DP_CFG_STREAM_VFRONT_PORCH	GENMASK(31, 16)
 56
 57#define HIBMC_DP_VIDEO_PACKET			0x114
 58#define HIBMC_DP_CFG_STREAM_TU_SYMBOL_SIZE	GENMASK(5, 0)
 59#define HIBMC_DP_CFG_STREAM_TU_SYMBOL_FRAC_SIZE	GENMASK(9, 6)
 60#define HIBMC_DP_CFG_STREAM_SYNC_CALIBRATION	GENMASK(31, 20)
 61
 62#define HIBMC_DP_VIDEO_MSA0			0x118
 63#define HIBMC_DP_CFG_STREAM_VSTART		GENMASK(31, 16)
 64#define HIBMC_DP_CFG_STREAM_HSTART		GENMASK(15, 0)
 65
 66#define HIBMC_DP_VIDEO_MSA1			0x11c
 67#define HIBMC_DP_VIDEO_MSA2			0x120
 68
 69#define HIBMC_DP_VIDEO_HORIZONTAL_SIZE		0X124
 70#define HIBMC_DP_CFG_STREAM_HTOTAL_SIZE		GENMASK(31, 16)
 71#define HIBMC_DP_CFG_STREAM_HBLANK_SIZE		GENMASK(15, 0)
 72
 73#define HIBMC_DP_COLOR_BAR_CTRL			0x260
 74#define HIBMC_DP_COLOR_BAR_CTRL1		0x264
 75
 76#define HIBMC_DP_TIMING_GEN_CONFIG0		0x26c
 77#define HIBMC_DP_CFG_TIMING_GEN0_HACTIVE	GENMASK(31, 16)
 78#define HIBMC_DP_CFG_TIMING_GEN0_HBLANK		GENMASK(15, 0)
 79
 80#define HIBMC_DP_TIMING_GEN_CONFIG2		0x274
 81#define HIBMC_DP_CFG_TIMING_GEN0_VACTIVE	GENMASK(31, 16)
 82#define HIBMC_DP_CFG_TIMING_GEN0_VBLANK		GENMASK(15, 0)
 83
 84#define HIBMC_DP_TIMING_GEN_CONFIG3		0x278
 85#define HIBMC_DP_CFG_TIMING_GEN0_VFRONT_PORCH	GENMASK(31, 16)
 86
 87#define HIBMC_DP_HDCP_CFG			0x600
 88
 89#define HIBMC_DP_DPTX_RST_CTRL			0x700
 90#define HIBMC_DP_CFG_AUX_RST_N			BIT(4)
 91
 92#define HIBMC_DP_DPTX_CLK_CTRL			0x704
 93
 94#define HIBMC_DP_DPTX_GCTL0			0x708
 95#define HIBMC_DP_CFG_PHY_LANE_NUM		GENMASK(2, 1)
 96
 97#define HIBMC_DP_INTR_ENABLE			0x720
 98#define HIBMC_DP_INTR_ORIGINAL_STATUS		0x728
 99
100#define HIBMC_DP_TIMING_MODEL_CTRL		0x884
101#define HIBMC_DP_CFG_PIXEL_NUM_TIMING_MODE_SEL1	GENMASK(31, 16)
102
103#define HIBMC_DP_TIMING_SYNC_CTRL		0xFF0
104
105#define HIBMC_DP_INTSTAT			0x1e0724
106#define HIBMC_DP_INTCLR				0x1e0728
107
108/* dp serdes reg */
109#define HIBMC_DP_HOST_OFFSET		0x10000
110#define HIBMC_DP_LANE0_RATE_OFFSET	0x4
111#define HIBMC_DP_LANE1_RATE_OFFSET	0xc
112#define HIBMC_DP_LANE_STATUS_OFFSET	0x10
113#define HIBMC_DP_PMA_LANE0_OFFSET	0x18
114#define HIBMC_DP_PMA_LANE1_OFFSET	0x1c
115#define HIBMC_DP_HOST_SERDES_CTRL	0x1f001c
116#define HIBMC_DP_PMA_TXDEEMPH		GENMASK(18, 1)
117#define DP_SERDES_DONE			0x3
118
119/* dp serdes TX-Deempth Configuration */
120#define DP_SERDES_VOL0_PRE0		0x280
121#define DP_SERDES_VOL0_PRE1		0x2300
122#define DP_SERDES_VOL0_PRE2		0x53c0
123#define DP_SERDES_VOL0_PRE3		0x8400
124#define DP_SERDES_VOL1_PRE0		0x380
125#define DP_SERDES_VOL1_PRE1		0x3440
126#define DP_SERDES_VOL1_PRE2		0x6480
127#define DP_SERDES_VOL2_PRE0		0x4c1
128#define DP_SERDES_VOL2_PRE1		0x4500
129#define DP_SERDES_VOL3_PRE0		0x600
130#define DP_SERDES_BW_8_1		0x3
131#define DP_SERDES_BW_5_4		0x2
132#define DP_SERDES_BW_2_7		0x1
133#define DP_SERDES_BW_1_62		0x0
134
135#endif