dp_comm.h

 1/* SPDX-License-Identifier: GPL-2.0-or-later */
 2/* Copyright (c) 2024 Hisilicon Limited. */
 3
 4#ifndef DP_COMM_H
 5#define DP_COMM_H
 6
 7#include <linux/types.h>
 8#include <linux/bitops.h>
 9#include <linux/errno.h>
10#include <linux/mutex.h>
11#include <linux/kernel.h>
12#include <linux/bitfield.h>
13#include <linux/io.h>
14#include <drm/display/drm_dp_helper.h>
15
16#include "dp_hw.h"
17
18#define HIBMC_DP_LANE_NUM_MAX 2
19
20struct hibmc_link_status {
21	bool clock_recovered;
22	bool channel_equalized;
23};
24
25struct hibmc_link_cap {
26	u8 link_rate;
27	u8 lanes;
28};
29
30struct hibmc_dp_link {
31	struct hibmc_link_status status;
32	u8 train_set[HIBMC_DP_LANE_NUM_MAX];
33	struct hibmc_link_cap cap;
34};
35
36struct hibmc_dp_dev {
37	struct drm_dp_aux *aux;
38	struct drm_device *dev;
39	void __iomem *base;
40	struct mutex lock; /* protects concurrent RW in hibmc_dp_reg_write_field() */
41	struct hibmc_dp_link link;
42	u8 dpcd[DP_RECEIVER_CAP_SIZE];
43	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
44	struct drm_dp_desc desc;
45	bool is_branch;
46	int hpd_status;
47	void __iomem *serdes_base;
48};
49
50#define dp_field_modify(reg_value, mask, val)				\
51	do {								\
52		(reg_value) &= ~(mask);					\
53		(reg_value) |= FIELD_PREP(mask, val);			\
54	} while (0)							\
55
56#define hibmc_dp_reg_write_field(dp, offset, mask, val)			\
57	do {								\
58		typeof(dp) _dp = dp;					\
59		typeof(_dp->base) addr = (_dp->base + (offset));	\
60		mutex_lock(&_dp->lock);					\
61		u32 reg_value = readl(addr);				\
62		dp_field_modify(reg_value, mask, val);			\
63		writel(reg_value, addr);				\
64		mutex_unlock(&_dp->lock);				\
65	} while (0)
66
67void hibmc_dp_aux_init(struct hibmc_dp *dp);
68int hibmc_dp_link_training(struct hibmc_dp_dev *dp);
69int hibmc_dp_serdes_init(struct hibmc_dp_dev *dp);
70int hibmc_dp_serdes_rate_switch(u8 rate, struct hibmc_dp_dev *dp);
71int hibmc_dp_serdes_set_tx_cfg(struct hibmc_dp_dev *dp, u8 train_set[HIBMC_DP_LANE_NUM_MAX]);
72
73#endif