psb_drv.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/**************************************************************************
  3 * Copyright (c) 2007-2011, Intel Corporation.
  4 * All Rights Reserved.
  5 *
  6 **************************************************************************/
  7
  8#ifndef _PSB_DRV_H_
  9#define _PSB_DRV_H_
 10
 11#include <linux/kref.h>
 12#include <linux/mm_types.h>
 13
 14#include <drm/drm_device.h>
 15
 16#include "gtt.h"
 17#include "intel_bios.h"
 18#include "mmu.h"
 19#include "oaktrail.h"
 20#include "opregion.h"
 21#include "power.h"
 22#include "psb_intel_drv.h"
 23#include "psb_reg.h"
 24
 25#define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others"
 26
 27#define DRIVER_NAME "gma500"
 28#define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650"
 29
 30#define DRIVER_MAJOR 1
 31#define DRIVER_MINOR 0
 32#define DRIVER_PATCHLEVEL 0
 33
 34/* Append new drm mode definition here, align with libdrm definition */
 35#define DRM_MODE_SCALE_NO_SCALE   	2
 36
 37#define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108)
 38#define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100)
 39#define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0)
 40
 41/* Hardware offsets */
 42#define PSB_VDC_OFFSET		 0x00000000
 43#define PSB_VDC_SIZE		 0x000080000
 44#define MRST_MMIO_SIZE		 0x0000C0000
 45#define PSB_SGX_SIZE		 0x8000
 46#define PSB_SGX_OFFSET		 0x00040000
 47#define MRST_SGX_OFFSET		 0x00080000
 48
 49/* PCI resource identifiers */
 50#define PSB_MMIO_RESOURCE	 0
 51#define PSB_AUX_RESOURCE	 0
 52#define PSB_GATT_RESOURCE	 2
 53#define PSB_GTT_RESOURCE	 3
 54
 55/* PCI configuration */
 56#define PSB_GMCH_CTRL		 0x52
 57#define PSB_BSM			 0x5C
 58#define _PSB_GMCH_ENABLED	 0x4
 59#define PSB_PGETBL_CTL		 0x2020
 60#define _PSB_PGETBL_ENABLED	 0x00000001
 61#define PSB_SGX_2D_SLAVE_PORT	 0x4000
 62#define PSB_LPC_GBA		 0x44
 63
 64/* TODO: To get rid of */
 65#define PSB_TT_PRIV0_LIMIT	 (256*1024*1024)
 66#define PSB_TT_PRIV0_PLIMIT	 (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
 67
 68/* SGX side MMU definitions (these can probably go) */
 69
 70/* Flags for external memory type field */
 71#define PSB_MMU_CACHED_MEMORY	  0x0001	/* Bind to MMU only */
 72#define PSB_MMU_RO_MEMORY	  0x0002	/* MMU RO memory */
 73#define PSB_MMU_WO_MEMORY	  0x0004	/* MMU WO memory */
 74
 75/* PTE's and PDE's */
 76#define PSB_PDE_MASK		  0x003FFFFF
 77#define PSB_PDE_SHIFT		  22
 78#define PSB_PTE_SHIFT		  12
 79
 80/* Cache control */
 81#define PSB_PTE_VALID		  0x0001	/* PTE / PDE valid */
 82#define PSB_PTE_WO		  0x0002	/* Write only */
 83#define PSB_PTE_RO		  0x0004	/* Read only */
 84#define PSB_PTE_CACHED		  0x0008	/* CPU cache coherent */
 85
 86/* VDC registers and bits */
 87#define PSB_MSVDX_CLOCKGATING	  0x2064
 88#define PSB_TOPAZ_CLOCKGATING	  0x2068
 89#define PSB_HWSTAM		  0x2098
 90#define PSB_INSTPM		  0x20C0
 91#define PSB_INT_IDENTITY_R        0x20A4
 92#define _PSB_IRQ_ASLE		  (1<<0)
 93#define _MDFLD_PIPEC_EVENT_FLAG   (1<<2)
 94#define _MDFLD_PIPEC_VBLANK_FLAG  (1<<3)
 95#define _PSB_DPST_PIPEB_FLAG      (1<<4)
 96#define _MDFLD_PIPEB_EVENT_FLAG   (1<<4)
 97#define _PSB_VSYNC_PIPEB_FLAG	  (1<<5)
 98#define _PSB_DPST_PIPEA_FLAG      (1<<6)
 99#define _PSB_PIPEA_EVENT_FLAG     (1<<6)
100#define _PSB_VSYNC_PIPEA_FLAG	  (1<<7)
101#define _PSB_IRQ_DISP_HOTSYNC	  (1<<17)
102#define _PSB_IRQ_SGX_FLAG	  (1<<18)
103#define _PSB_IRQ_MSVDX_FLAG	  (1<<19)
104#define _LNC_IRQ_TOPAZ_FLAG	  (1<<20)
105
106#define _PSB_PIPE_EVENT_FLAG	(_PSB_VSYNC_PIPEA_FLAG | \
107				 _PSB_VSYNC_PIPEB_FLAG)
108
109#define PSB_INT_IDENTITY_R	  0x20A4
110#define PSB_INT_MASK_R		  0x20A8
111#define PSB_INT_ENABLE_R	  0x20A0
112
113#define _PSB_MMU_ER_MASK      0x0001FF00
114#define _PSB_MMU_ER_HOST      (1 << 16)
115#define GPIOA			0x5010
116#define GPIOB			0x5014
117#define GPIOC			0x5018
118#define GPIOD			0x501c
119#define GPIOE			0x5020
120#define GPIOF			0x5024
121#define GPIOG			0x5028
122#define GPIOH			0x502c
123#define GPIO_CLOCK_DIR_MASK		(1 << 0)
124#define GPIO_CLOCK_DIR_IN		(0 << 1)
125#define GPIO_CLOCK_DIR_OUT		(1 << 1)
126#define GPIO_CLOCK_VAL_MASK		(1 << 2)
127#define GPIO_CLOCK_VAL_OUT		(1 << 3)
128#define GPIO_CLOCK_VAL_IN		(1 << 4)
129#define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
130#define GPIO_DATA_DIR_MASK		(1 << 8)
131#define GPIO_DATA_DIR_IN		(0 << 9)
132#define GPIO_DATA_DIR_OUT		(1 << 9)
133#define GPIO_DATA_VAL_MASK		(1 << 10)
134#define GPIO_DATA_VAL_OUT		(1 << 11)
135#define GPIO_DATA_VAL_IN		(1 << 12)
136#define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
137
138#define VCLK_DIVISOR_VGA0   0x6000
139#define VCLK_DIVISOR_VGA1   0x6004
140#define VCLK_POST_DIV	    0x6010
141
142#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
143#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
144#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
145#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
146#define PSB_COMM_USER_IRQ (1024 >> 2)
147#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
148#define PSB_COMM_FW (2048 >> 2)
149
150#define PSB_UIRQ_VISTEST	       1
151#define PSB_UIRQ_OOM_REPLY	       2
152#define PSB_UIRQ_FIRE_TA_REPLY	       3
153#define PSB_UIRQ_FIRE_RASTER_REPLY     4
154
155#define PSB_2D_SIZE (256*1024*1024)
156#define PSB_MAX_RELOC_PAGES 1024
157
158#define PSB_LOW_REG_OFFS 0x0204
159#define PSB_HIGH_REG_OFFS 0x0600
160
161#define PSB_NUM_VBLANKS 2
162
163#define PSB_WATCHDOG_DELAY (HZ * 2)
164
165#define PSB_MAX_BRIGHTNESS		100
166
167#define PSB_PWR_STATE_ON		1
168#define PSB_PWR_STATE_OFF		2
169
170#define PSB_PMPOLICY_NOPM		0
171#define PSB_PMPOLICY_CLOCKGATING	1
172#define PSB_PMPOLICY_POWERDOWN		2
173
174#define PSB_PMSTATE_POWERUP		0
175#define PSB_PMSTATE_CLOCKGATED		1
176#define PSB_PMSTATE_POWERDOWN		2
177#define PSB_PCIx_MSI_ADDR_LOC		0x94
178#define PSB_PCIx_MSI_DATA_LOC		0x98
179
180/* Medfield crystal settings */
181#define KSEL_CRYSTAL_19 1
182#define KSEL_BYPASS_19 5
183#define KSEL_BYPASS_25 6
184#define KSEL_BYPASS_83_100 7
185
186struct drm_fb_helper;
187struct drm_fb_helper_surface_size;
188
189struct opregion_header;
190struct opregion_acpi;
191struct opregion_swsci;
192struct opregion_asle;
193
194struct psb_intel_opregion {
195	struct opregion_header *header;
196	struct opregion_acpi *acpi;
197	struct opregion_swsci *swsci;
198	struct opregion_asle *asle;
199	void *vbt;
200	u32 __iomem *lid_state;
201	struct work_struct asle_work;
202};
203
204struct sdvo_device_mapping {
205	u8 initialized;
206	u8 dvo_port;
207	u8 target_addr;
208	u8 dvo_wiring;
209	u8 i2c_pin;
210	u8 i2c_speed;
211	u8 ddc_pin;
212};
213
214struct intel_gmbus {
215	struct i2c_adapter adapter;
216	struct i2c_adapter *force_bit;
217	u32 reg0;
218};
219
220/* Register offset maps */
221struct psb_offset {
222	u32	fp0;
223	u32	fp1;
224	u32	cntr;
225	u32	conf;
226	u32	src;
227	u32	dpll;
228	u32	dpll_md;
229	u32	htotal;
230	u32	hblank;
231	u32	hsync;
232	u32	vtotal;
233	u32	vblank;
234	u32	vsync;
235	u32	stride;
236	u32	size;
237	u32	pos;
238	u32	surf;
239	u32	addr;
240	u32	base;
241	u32	status;
242	u32	linoff;
243	u32	tileoff;
244	u32	palette;
245};
246
247/*
248 *	Register save state. This is used to hold the context when the
249 *	device is powered off. In the case of Oaktrail this can (but does not
250 *	yet) include screen blank. Operations occuring during the save
251 *	update the register cache instead.
252 */
253
254/* Common status for pipes */
255struct psb_pipe {
256	u32	fp0;
257	u32	fp1;
258	u32	cntr;
259	u32	conf;
260	u32	src;
261	u32	dpll;
262	u32	dpll_md;
263	u32	htotal;
264	u32	hblank;
265	u32	hsync;
266	u32	vtotal;
267	u32	vblank;
268	u32	vsync;
269	u32	stride;
270	u32	size;
271	u32	pos;
272	u32	base;
273	u32	surf;
274	u32	addr;
275	u32	status;
276	u32	linoff;
277	u32	tileoff;
278	u32	palette[256];
279};
280
281struct psb_state {
282	uint32_t saveVCLK_DIVISOR_VGA0;
283	uint32_t saveVCLK_DIVISOR_VGA1;
284	uint32_t saveVCLK_POST_DIV;
285	uint32_t saveVGACNTRL;
286	uint32_t saveADPA;
287	uint32_t saveLVDS;
288	uint32_t saveDVOA;
289	uint32_t saveDVOB;
290	uint32_t saveDVOC;
291	uint32_t savePP_ON;
292	uint32_t savePP_OFF;
293	uint32_t savePP_CONTROL;
294	uint32_t savePP_CYCLE;
295	uint32_t savePFIT_CONTROL;
296	uint32_t saveCLOCKGATING;
297	uint32_t saveDSPARB;
298	uint32_t savePFIT_AUTO_RATIOS;
299	uint32_t savePFIT_PGM_RATIOS;
300	uint32_t savePP_ON_DELAYS;
301	uint32_t savePP_OFF_DELAYS;
302	uint32_t savePP_DIVISOR;
303	uint32_t saveBCLRPAT_A;
304	uint32_t saveBCLRPAT_B;
305	uint32_t savePERF_MODE;
306	uint32_t saveDSPFW1;
307	uint32_t saveDSPFW2;
308	uint32_t saveDSPFW3;
309	uint32_t saveDSPFW4;
310	uint32_t saveDSPFW5;
311	uint32_t saveDSPFW6;
312	uint32_t saveCHICKENBIT;
313	uint32_t saveDSPACURSOR_CTRL;
314	uint32_t saveDSPBCURSOR_CTRL;
315	uint32_t saveDSPACURSOR_BASE;
316	uint32_t saveDSPBCURSOR_BASE;
317	uint32_t saveDSPACURSOR_POS;
318	uint32_t saveDSPBCURSOR_POS;
319	uint32_t saveOV_OVADD;
320	uint32_t saveOV_OGAMC0;
321	uint32_t saveOV_OGAMC1;
322	uint32_t saveOV_OGAMC2;
323	uint32_t saveOV_OGAMC3;
324	uint32_t saveOV_OGAMC4;
325	uint32_t saveOV_OGAMC5;
326	uint32_t saveOVC_OVADD;
327	uint32_t saveOVC_OGAMC0;
328	uint32_t saveOVC_OGAMC1;
329	uint32_t saveOVC_OGAMC2;
330	uint32_t saveOVC_OGAMC3;
331	uint32_t saveOVC_OGAMC4;
332	uint32_t saveOVC_OGAMC5;
333
334	/* DPST register save */
335	uint32_t saveHISTOGRAM_INT_CONTROL_REG;
336	uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
337	uint32_t savePWM_CONTROL_LOGIC;
338};
339
340struct cdv_state {
341	uint32_t saveDSPCLK_GATE_D;
342	uint32_t saveRAMCLK_GATE_D;
343	uint32_t saveDSPARB;
344	uint32_t saveDSPFW[6];
345	uint32_t saveADPA;
346	uint32_t savePP_CONTROL;
347	uint32_t savePFIT_PGM_RATIOS;
348	uint32_t saveLVDS;
349	uint32_t savePFIT_CONTROL;
350	uint32_t savePP_ON_DELAYS;
351	uint32_t savePP_OFF_DELAYS;
352	uint32_t savePP_CYCLE;
353	uint32_t saveVGACNTRL;
354	uint32_t saveIER;
355	uint32_t saveIMR;
356	u8	 saveLBB;
357};
358
359struct psb_save_area {
360	struct psb_pipe pipe[3];
361	uint32_t saveBSM;
362	uint32_t saveVBT;
363	union {
364	        struct psb_state psb;
365		struct cdv_state cdv;
366	};
367	uint32_t saveBLC_PWM_CTL2;
368	uint32_t saveBLC_PWM_CTL;
369};
370
371struct psb_ops;
372
373#define PSB_NUM_PIPE		3
374
375struct intel_scu_ipc_dev;
376
377struct drm_psb_private {
378	struct drm_device dev;
379
380	struct pci_dev *aux_pdev; /* Currently only used by mrst */
381	struct pci_dev *lpc_pdev; /* Currently only used by mrst */
382	const struct psb_ops *ops;
383	const struct psb_offset *regmap;
384
385	struct child_device_config *child_dev;
386	int child_dev_num;
387
388	struct psb_gtt gtt;
389
390	/* GTT Memory manager */
391	struct psb_gtt_mm *gtt_mm;
392	struct page *scratch_page;
393	u32 __iomem *gtt_map;
394	uint32_t stolen_base;
395	u8 __iomem *vram_addr;
396	unsigned long vram_stolen_size;
397	u16 gmch_ctrl;		/* Saved GTT setup */
398	u32 pge_ctl;
399
400	struct mutex gtt_mutex;
401	struct resource *gtt_mem;	/* Our PCI resource */
402
403	struct mutex mmap_mutex;
404
405	struct psb_mmu_driver *mmu;
406	struct psb_mmu_pd *pf_pd;
407
408	/* Register base */
409	uint8_t __iomem *sgx_reg;
410	uint8_t __iomem *vdc_reg;
411	uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */
412	uint16_t lpc_gpio_base;
413	uint32_t gatt_free_offset;
414
415	/* Fencing / irq */
416	uint32_t vdc_irq_mask;
417	uint32_t pipestat[PSB_NUM_PIPE];
418
419	spinlock_t irqmask_lock;
420	bool irq_enabled;
421
422	/* Power */
423	bool pm_initialized;
424
425	/* Modesetting */
426	struct psb_intel_mode_device mode_dev;
427	bool modeset;	/* true if we have done the mode_device setup */
428
429	struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
430	struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
431	uint32_t num_pipe;
432
433	/* OSPM info (Power management base) (TODO: can go ?) */
434	uint32_t ospm_base;
435
436	/* Sizes info */
437	u32 fuse_reg_value;
438	u32 video_device_fuse;
439
440	/* PCI revision ID for B0:D2:F0 */
441	uint8_t platform_rev_id;
442
443	/* gmbus */
444	struct intel_gmbus *gmbus;
445	uint8_t __iomem *gmbus_reg;
446
447	/* Used by SDVO */
448	int crt_ddc_pin;
449	/* FIXME: The mappings should be parsed from bios but for now we can
450		  pretend there are no mappings available */
451	struct sdvo_device_mapping sdvo_mappings[2];
452	u32 hotplug_supported_mask;
453	struct drm_property *broadcast_rgb_property;
454	struct drm_property *force_audio_property;
455
456	/* LVDS info */
457	int backlight_duty_cycle;	/* restore backlight to this value */
458	bool panel_wants_dither;
459	struct drm_display_mode *panel_fixed_mode;
460	struct drm_display_mode *lfp_lvds_vbt_mode;
461	struct drm_display_mode *sdvo_lvds_vbt_mode;
462
463	struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
464	struct gma_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
465
466	/* Feature bits from the VBIOS */
467	unsigned int int_tv_support:1;
468	unsigned int lvds_dither:1;
469	unsigned int lvds_vbt:1;
470	unsigned int int_crt_support:1;
471	unsigned int lvds_use_ssc:1;
472	int lvds_ssc_freq;
473	bool is_lvds_on;
474	bool is_mipi_on;
475	bool lvds_enabled_in_vbt;
476	u32 mipi_ctrl_display;
477
478	unsigned int core_freq;
479	uint32_t iLVDS_enable;
480
481	/* MID specific */
482	bool use_msi;
483	bool has_gct;
484	struct oaktrail_gct_data gct_data;
485
486	/* Oaktrail HDMI state */
487	struct oaktrail_hdmi_dev *hdmi_priv;
488
489	/* Register state */
490	struct psb_save_area regs;
491
492	/* Hotplug handling */
493	struct work_struct hotplug_work;
494
495	struct psb_intel_opregion opregion;
496
497	/* Watchdog */
498	uint32_t apm_reg;
499	uint16_t apm_base;
500
501	/*
502	 * Used for modifying backlight from
503	 * xrandr -- consider removing and using HAL instead
504	 */
505	struct intel_scu_ipc_dev *scu;
506	struct backlight_device *backlight_device;
507	struct drm_property *backlight_property;
508	bool backlight_enabled;
509	int backlight_level;
510	uint32_t blc_adj1;
511	uint32_t blc_adj2;
512
513	bool dsr_enable;
514	u32 dsr_fb_update;
515	bool dpi_panel_on[3];
516	void *dsi_configs[2];
517	u32 bpp;
518	u32 bpp2;
519
520	u32 pipeconf[3];
521	u32 dspcntr[3];
522
523	bool dplla_96mhz;	/* DPLL data from the VBT */
524
525	struct {
526		int rate;
527		int lanes;
528		int preemphasis;
529		int vswing;
530
531		bool initialized;
532		bool support;
533		int bpp;
534		struct edp_power_seq pps;
535	} edp;
536	uint8_t panel_type;
537};
538
539static inline struct drm_psb_private *to_drm_psb_private(struct drm_device *dev)
540{
541	return container_of(dev, struct drm_psb_private, dev);
542}
543
544/* Operations for each board type */
545struct psb_ops {
546	const char *name;
547	int pipes;		/* Number of output pipes */
548	int crtcs;		/* Number of CRTCs */
549	int sgx_offset;		/* Base offset of SGX device */
550	int hdmi_mask;		/* Mask of HDMI CRTCs */
551	int lvds_mask;		/* Mask of LVDS CRTCs */
552	int sdvo_mask;		/* Mask of SDVO CRTCs */
553	int cursor_needs_phys;  /* If cursor base reg need physical address */
554
555	/* Sub functions */
556	struct drm_crtc_helper_funcs const *crtc_helper;
557	const struct gma_clock_funcs *clock_funcs;
558
559	/* Setup hooks */
560	int (*chip_setup)(struct drm_device *dev);
561	void (*chip_teardown)(struct drm_device *dev);
562	/* Optional helper caller after modeset */
563	void (*errata)(struct drm_device *dev);
564
565	/* Display management hooks */
566	int (*output_init)(struct drm_device *dev);
567	int (*hotplug)(struct drm_device *dev);
568	void (*hotplug_enable)(struct drm_device *dev, bool on);
569	/* Power management hooks */
570	void (*init_pm)(struct drm_device *dev);
571	int (*save_regs)(struct drm_device *dev);
572	int (*restore_regs)(struct drm_device *dev);
573	void (*save_crtc)(struct drm_crtc *crtc);
574	void (*restore_crtc)(struct drm_crtc *crtc);
575	int (*power_up)(struct drm_device *dev);
576	int (*power_down)(struct drm_device *dev);
577	void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc);
578	void (*disable_sr)(struct drm_device *dev);
579
580	void (*lvds_bl_power)(struct drm_device *dev, bool on);
581
582	/* Backlight */
583	int (*backlight_init)(struct drm_device *dev);
584	void (*backlight_set)(struct drm_device *dev, int level);
585	int (*backlight_get)(struct drm_device *dev);
586	const char *backlight_name;
587
588	int i2c_bus;		/* I2C bus identifier for Moorestown */
589};
590
591/* modesetting */
592extern void psb_modeset_init(struct drm_device *dev);
593extern void psb_modeset_cleanup(struct drm_device *dev);
594
595/* framebuffer */
596struct drm_framebuffer *psb_framebuffer_create(struct drm_device *dev,
597					       const struct drm_format_info *info,
598					       const struct drm_mode_fb_cmd2 *mode_cmd,
599					       struct drm_gem_object *obj);
600
601/* fbdev */
602#if defined(CONFIG_DRM_FBDEV_EMULATION)
603int psb_fbdev_driver_fbdev_probe(struct drm_fb_helper *fb_helper,
604				 struct drm_fb_helper_surface_size *sizes);
605#define PSB_FBDEV_DRIVER_OPS \
606	.fbdev_probe = psb_fbdev_driver_fbdev_probe
607#else
608#define PSB_FBDEV_DRIVER_OPS \
609	.fbdev_probe = NULL
610#endif
611
612/* backlight.c */
613int gma_backlight_init(struct drm_device *dev);
614void gma_backlight_exit(struct drm_device *dev);
615void gma_backlight_disable(struct drm_device *dev);
616void gma_backlight_enable(struct drm_device *dev);
617void gma_backlight_set(struct drm_device *dev, int v);
618
619/* oaktrail_crtc.c */
620extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
621
622/* oaktrail_lvds.c */
623extern void oaktrail_lvds_init(struct drm_device *dev,
624		    struct psb_intel_mode_device *mode_dev);
625
626/* psb_intel_display.c */
627extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
628
629/* psb_intel_lvds.c */
630extern const struct drm_connector_helper_funcs
631					psb_intel_lvds_connector_helper_funcs;
632extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
633
634/* gem.c */
635extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
636			struct drm_mode_create_dumb *args);
637
638/* psb_device.c */
639extern const struct psb_ops psb_chip_ops;
640
641/* oaktrail_device.c */
642extern const struct psb_ops oaktrail_chip_ops;
643
644/* cdv_device.c */
645extern const struct psb_ops cdv_chip_ops;
646
647/* Utilities */
648static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
649{
650	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
651	return ioread32(dev_priv->vdc_reg + reg);
652}
653
654static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg)
655{
656	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
657	return ioread32(dev_priv->aux_reg + reg);
658}
659
660#define REG_READ(reg)	       REGISTER_READ(dev, (reg))
661#define REG_READ_AUX(reg)      REGISTER_READ_AUX(dev, (reg))
662
663/* Useful for post reads */
664static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev,
665					      uint32_t reg, int aux)
666{
667	uint32_t val;
668
669	if (aux)
670		val = REG_READ_AUX(reg);
671	else
672		val = REG_READ(reg);
673
674	return val;
675}
676
677#define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux))
678
679static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
680				  uint32_t val)
681{
682	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
683	iowrite32((val), dev_priv->vdc_reg + (reg));
684}
685
686static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg,
687				      uint32_t val)
688{
689	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
690	iowrite32((val), dev_priv->aux_reg + (reg));
691}
692
693#define REG_WRITE(reg, val)	REGISTER_WRITE(dev, (reg), (val))
694#define REG_WRITE_AUX(reg, val)	REGISTER_WRITE_AUX(dev, (reg), (val))
695
696static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg,
697				      uint32_t val, int aux)
698{
699	if (aux)
700		REG_WRITE_AUX(reg, val);
701	else
702		REG_WRITE(reg, val);
703}
704
705#define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux))
706
707static inline void REGISTER_WRITE16(struct drm_device *dev,
708					uint32_t reg, uint32_t val)
709{
710	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
711	iowrite16((val), dev_priv->vdc_reg + (reg));
712}
713
714#define REG_WRITE16(reg, val)	  REGISTER_WRITE16(dev, (reg), (val))
715
716static inline void REGISTER_WRITE8(struct drm_device *dev,
717				       uint32_t reg, uint32_t val)
718{
719	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
720	iowrite8((val), dev_priv->vdc_reg + (reg));
721}
722
723#define REG_WRITE8(reg, val)		REGISTER_WRITE8(dev, (reg), (val))
724
725#define PSB_WVDC32(_val, _offs)		iowrite32(_val, dev_priv->vdc_reg + (_offs))
726#define PSB_RVDC32(_offs)		ioread32(dev_priv->vdc_reg + (_offs))
727
728#define PSB_RSGX32(_offs)		ioread32(dev_priv->sgx_reg + (_offs))
729#define PSB_WSGX32(_val, _offs)		iowrite32(_val, dev_priv->sgx_reg + (_offs))
730
731#define PSB_WMSVDX32(_val, _offs)	iowrite32(_val, dev_priv->msvdx_reg + (_offs))
732#define PSB_RMSVDX32(_offs)		ioread32(dev_priv->msvdx_reg + (_offs))
733
734#endif