oaktrail_crtc.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright © 2009 Intel Corporation
  4 */
  5
  6#include <linux/delay.h>
  7#include <linux/i2c.h>
  8#include <linux/pm_runtime.h>
  9
 10#include <drm/drm_fourcc.h>
 11#include <drm/drm_framebuffer.h>
 12#include <drm/drm_modeset_helper_vtables.h>
 13#include <drm/drm_print.h>
 14
 15#include "framebuffer.h"
 16#include "gem.h"
 17#include "gma_display.h"
 18#include "power.h"
 19#include "psb_drv.h"
 20#include "psb_intel_drv.h"
 21#include "psb_intel_reg.h"
 22
 23#define MRST_LIMIT_LVDS_100L	0
 24#define MRST_LIMIT_LVDS_83	1
 25#define MRST_LIMIT_LVDS_100	2
 26#define MRST_LIMIT_SDVO		3
 27
 28#define MRST_DOT_MIN		  19750
 29#define MRST_DOT_MAX		  120000
 30#define MRST_M_MIN_100L		    20
 31#define MRST_M_MIN_100		    10
 32#define MRST_M_MIN_83		    12
 33#define MRST_M_MAX_100L		    34
 34#define MRST_M_MAX_100		    17
 35#define MRST_M_MAX_83		    20
 36#define MRST_P1_MIN		    2
 37#define MRST_P1_MAX_0		    7
 38#define MRST_P1_MAX_1		    8
 39
 40static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit,
 41				    struct drm_crtc *crtc, int target,
 42				    int refclk, struct gma_clock_t *best_clock);
 43
 44static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit,
 45				    struct drm_crtc *crtc, int target,
 46				    int refclk, struct gma_clock_t *best_clock);
 47
 48static const struct gma_limit_t mrst_limits[] = {
 49	{			/* MRST_LIMIT_LVDS_100L */
 50	 .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
 51	 .m = {.min = MRST_M_MIN_100L, .max = MRST_M_MAX_100L},
 52	 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
 53	 .find_pll = mrst_lvds_find_best_pll,
 54	 },
 55	{			/* MRST_LIMIT_LVDS_83L */
 56	 .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
 57	 .m = {.min = MRST_M_MIN_83, .max = MRST_M_MAX_83},
 58	 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_0},
 59	 .find_pll = mrst_lvds_find_best_pll,
 60	 },
 61	{			/* MRST_LIMIT_LVDS_100 */
 62	 .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
 63	 .m = {.min = MRST_M_MIN_100, .max = MRST_M_MAX_100},
 64	 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
 65	 .find_pll = mrst_lvds_find_best_pll,
 66	 },
 67	{			/* MRST_LIMIT_SDVO */
 68	 .vco = {.min = 1400000, .max = 2800000},
 69	 .n = {.min = 3, .max = 7},
 70	 .m = {.min = 80, .max = 137},
 71	 .p1 = {.min = 1, .max = 2},
 72	 .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 10},
 73	 .find_pll = mrst_sdvo_find_best_pll,
 74	 },
 75};
 76
 77#define MRST_M_MIN	    10
 78static const u32 oaktrail_m_converts[] = {
 79	0x2B, 0x15, 0x2A, 0x35, 0x1A, 0x0D, 0x26, 0x33, 0x19, 0x2C,
 80	0x36, 0x3B, 0x1D, 0x2E, 0x37, 0x1B, 0x2D, 0x16, 0x0B, 0x25,
 81	0x12, 0x09, 0x24, 0x32, 0x39, 0x1c,
 82};
 83
 84static const struct gma_limit_t *mrst_limit(struct drm_crtc *crtc,
 85					    int refclk)
 86{
 87	const struct gma_limit_t *limit = NULL;
 88	struct drm_device *dev = crtc->dev;
 89	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
 90
 91	if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
 92	    || gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) {
 93		switch (dev_priv->core_freq) {
 94		case 100:
 95			limit = &mrst_limits[MRST_LIMIT_LVDS_100L];
 96			break;
 97		case 166:
 98			limit = &mrst_limits[MRST_LIMIT_LVDS_83];
 99			break;
100		case 200:
101			limit = &mrst_limits[MRST_LIMIT_LVDS_100];
102			break;
103		}
104	} else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
105		limit = &mrst_limits[MRST_LIMIT_SDVO];
106	} else {
107		limit = NULL;
108		dev_err(dev->dev, "mrst_limit Wrong display type.\n");
109	}
110
111	return limit;
112}
113
114/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
115static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock)
116{
117	clock->dot = (refclk * clock->m) / (14 * clock->p1);
118}
119
120static void mrst_print_pll(struct gma_clock_t *clock)
121{
122	DRM_DEBUG_DRIVER("dotclock=%d,  m=%d, m1=%d, m2=%d, n=%d, p1=%d, p2=%d\n",
123			 clock->dot, clock->m, clock->m1, clock->m2, clock->n,
124			 clock->p1, clock->p2);
125}
126
127static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit,
128				    struct drm_crtc *crtc, int target,
129				    int refclk, struct gma_clock_t *best_clock)
130{
131	struct gma_clock_t clock;
132	u32 target_vco, actual_freq;
133	s32 freq_error, min_error = 100000;
134
135	memset(best_clock, 0, sizeof(*best_clock));
136	memset(&clock, 0, sizeof(clock));
137
138	for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
139		for (clock.n = limit->n.min; clock.n <= limit->n.max;
140		     clock.n++) {
141			for (clock.p1 = limit->p1.min;
142			     clock.p1 <= limit->p1.max; clock.p1++) {
143				/* p2 value always stored in p2_slow on SDVO */
144				clock.p = clock.p1 * limit->p2.p2_slow;
145				target_vco = target * clock.p;
146
147				/* VCO will increase at this point so break */
148				if (target_vco > limit->vco.max)
149					break;
150
151				if (target_vco < limit->vco.min)
152					continue;
153
154				actual_freq = (refclk * clock.m) /
155					      (clock.n * clock.p);
156				freq_error = 10000 -
157					     ((target * 10000) / actual_freq);
158
159				if (freq_error < -min_error) {
160					/* freq_error will start to decrease at
161					   this point so break */
162					break;
163				}
164
165				if (freq_error < 0)
166					freq_error = -freq_error;
167
168				if (freq_error < min_error) {
169					min_error = freq_error;
170					*best_clock = clock;
171				}
172			}
173		}
174		if (min_error == 0)
175			break;
176	}
177
178	return min_error == 0;
179}
180
181/*
182 * Returns a set of divisors for the desired target clock with the given refclk,
183 * or FALSE.  Divisor values are the actual divisors for
184 */
185static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit,
186				    struct drm_crtc *crtc, int target,
187				    int refclk, struct gma_clock_t *best_clock)
188{
189	struct gma_clock_t clock;
190	int err = target;
191
192	memset(best_clock, 0, sizeof(*best_clock));
193	memset(&clock, 0, sizeof(clock));
194
195	for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
196		for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max;
197		     clock.p1++) {
198			int this_err;
199
200			mrst_lvds_clock(refclk, &clock);
201
202			this_err = abs(clock.dot - target);
203			if (this_err < err) {
204				*best_clock = clock;
205				err = this_err;
206			}
207		}
208	}
209	return err != target;
210}
211
212/*
213 * Sets the power management mode of the pipe and plane.
214 *
215 * This code should probably grow support for turning the cursor off and back
216 * on appropriately at the same time as we're turning the pipe off/on.
217 */
218static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode)
219{
220	struct drm_device *dev = crtc->dev;
221	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
222	struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
223	int pipe = gma_crtc->pipe;
224	const struct psb_offset *map = &dev_priv->regmap[pipe];
225	u32 temp;
226	int i;
227	int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0;
228
229	if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
230		oaktrail_crtc_hdmi_dpms(crtc, mode);
231		return;
232	}
233
234	if (!gma_power_begin(dev, true))
235		return;
236
237	/* XXX: When our outputs are all unaware of DPMS modes other than off
238	 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
239	 */
240	switch (mode) {
241	case DRM_MODE_DPMS_ON:
242	case DRM_MODE_DPMS_STANDBY:
243	case DRM_MODE_DPMS_SUSPEND:
244		for (i = 0; i <= need_aux; i++) {
245			/* Enable the DPLL */
246			temp = REG_READ_WITH_AUX(map->dpll, i);
247			if ((temp & DPLL_VCO_ENABLE) == 0) {
248				REG_WRITE_WITH_AUX(map->dpll, temp, i);
249				REG_READ_WITH_AUX(map->dpll, i);
250				/* Wait for the clocks to stabilize. */
251				udelay(150);
252				REG_WRITE_WITH_AUX(map->dpll,
253						   temp | DPLL_VCO_ENABLE, i);
254				REG_READ_WITH_AUX(map->dpll, i);
255				/* Wait for the clocks to stabilize. */
256				udelay(150);
257				REG_WRITE_WITH_AUX(map->dpll,
258						   temp | DPLL_VCO_ENABLE, i);
259				REG_READ_WITH_AUX(map->dpll, i);
260				/* Wait for the clocks to stabilize. */
261				udelay(150);
262			}
263
264			/* Enable the pipe */
265			temp = REG_READ_WITH_AUX(map->conf, i);
266			if ((temp & PIPEACONF_ENABLE) == 0) {
267				REG_WRITE_WITH_AUX(map->conf,
268						   temp | PIPEACONF_ENABLE, i);
269			}
270
271			/* Enable the plane */
272			temp = REG_READ_WITH_AUX(map->cntr, i);
273			if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
274				REG_WRITE_WITH_AUX(map->cntr,
275						   temp | DISPLAY_PLANE_ENABLE,
276						   i);
277				/* Flush the plane changes */
278				REG_WRITE_WITH_AUX(map->base,
279					REG_READ_WITH_AUX(map->base, i), i);
280			}
281
282		}
283		gma_crtc_load_lut(crtc);
284
285		/* Give the overlay scaler a chance to enable
286		   if it's on this pipe */
287		/* psb_intel_crtc_dpms_video(crtc, true); TODO */
288		break;
289	case DRM_MODE_DPMS_OFF:
290		/* Give the overlay scaler a chance to disable
291		 * if it's on this pipe */
292		/* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
293
294		for (i = 0; i <= need_aux; i++) {
295			/* Disable the VGA plane that we never use */
296			REG_WRITE_WITH_AUX(VGACNTRL, VGA_DISP_DISABLE, i);
297			/* Disable display plane */
298			temp = REG_READ_WITH_AUX(map->cntr, i);
299			if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
300				REG_WRITE_WITH_AUX(map->cntr,
301					temp & ~DISPLAY_PLANE_ENABLE, i);
302				/* Flush the plane changes */
303				REG_WRITE_WITH_AUX(map->base,
304						   REG_READ(map->base), i);
305				REG_READ_WITH_AUX(map->base, i);
306			}
307
308			/* Next, disable display pipes */
309			temp = REG_READ_WITH_AUX(map->conf, i);
310			if ((temp & PIPEACONF_ENABLE) != 0) {
311				REG_WRITE_WITH_AUX(map->conf,
312						   temp & ~PIPEACONF_ENABLE, i);
313				REG_READ_WITH_AUX(map->conf, i);
314			}
315			/* Wait for the pipe disable to take effect. */
316			gma_wait_for_vblank(dev);
317
318			temp = REG_READ_WITH_AUX(map->dpll, i);
319			if ((temp & DPLL_VCO_ENABLE) != 0) {
320				REG_WRITE_WITH_AUX(map->dpll,
321						   temp & ~DPLL_VCO_ENABLE, i);
322				REG_READ_WITH_AUX(map->dpll, i);
323			}
324
325			/* Wait for the clocks to turn off. */
326			udelay(150);
327		}
328		break;
329	}
330
331	/* Set FIFO Watermarks (values taken from EMGD) */
332	REG_WRITE(DSPARB, 0x3f80);
333	REG_WRITE(DSPFW1, 0x3f8f0404);
334	REG_WRITE(DSPFW2, 0x04040f04);
335	REG_WRITE(DSPFW3, 0x0);
336	REG_WRITE(DSPFW4, 0x04040404);
337	REG_WRITE(DSPFW5, 0x04040404);
338	REG_WRITE(DSPFW6, 0x78);
339	REG_WRITE(DSPCHICKENBIT, REG_READ(DSPCHICKENBIT) | 0xc040);
340
341	gma_power_end(dev);
342}
343
344/*
345 * Return the pipe currently connected to the panel fitter,
346 * or -1 if the panel fitter is not present or not in use
347 */
348static int oaktrail_panel_fitter_pipe(struct drm_device *dev)
349{
350	u32 pfit_control;
351
352	pfit_control = REG_READ(PFIT_CONTROL);
353
354	/* See if the panel fitter is in use */
355	if ((pfit_control & PFIT_ENABLE) == 0)
356		return -1;
357	return (pfit_control >> 29) & 3;
358}
359
360static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
361			      struct drm_display_mode *mode,
362			      struct drm_display_mode *adjusted_mode,
363			      int x, int y,
364			      struct drm_framebuffer *old_fb)
365{
366	struct drm_device *dev = crtc->dev;
367	struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
368	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
369	int pipe = gma_crtc->pipe;
370	const struct psb_offset *map = &dev_priv->regmap[pipe];
371	int refclk = 0;
372	struct gma_clock_t clock;
373	const struct gma_limit_t *limit;
374	u32 dpll = 0, fp = 0, dspcntr, pipeconf;
375	bool ok, is_sdvo = false;
376	bool is_lvds = false;
377	bool is_mipi = false;
378	struct gma_encoder *gma_encoder = NULL;
379	uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN;
380	struct drm_connector_list_iter conn_iter;
381	struct drm_connector *connector;
382	int i;
383	int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0;
384
385	if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
386		return oaktrail_crtc_hdmi_mode_set(crtc, mode, adjusted_mode, x, y, old_fb);
387
388	if (!gma_power_begin(dev, true))
389		return 0;
390
391	drm_mode_copy(&gma_crtc->saved_mode, mode);
392	drm_mode_copy(&gma_crtc->saved_adjusted_mode, adjusted_mode);
393
394	drm_connector_list_iter_begin(dev, &conn_iter);
395	drm_for_each_connector_iter(connector, &conn_iter) {
396		if (!connector->encoder || connector->encoder->crtc != crtc)
397			continue;
398
399		gma_encoder = gma_attached_encoder(connector);
400
401		switch (gma_encoder->type) {
402		case INTEL_OUTPUT_LVDS:
403			is_lvds = true;
404			break;
405		case INTEL_OUTPUT_SDVO:
406			is_sdvo = true;
407			break;
408		case INTEL_OUTPUT_MIPI:
409			is_mipi = true;
410			break;
411		}
412
413		break;
414	}
415
416	if (gma_encoder)
417		drm_object_property_get_value(&connector->base,
418			dev->mode_config.scaling_mode_property, &scalingType);
419
420	drm_connector_list_iter_end(&conn_iter);
421
422	/* Disable the VGA plane that we never use */
423	for (i = 0; i <= need_aux; i++)
424		REG_WRITE_WITH_AUX(VGACNTRL, VGA_DISP_DISABLE, i);
425
426	/* Disable the panel fitter if it was on our pipe */
427	if (oaktrail_panel_fitter_pipe(dev) == pipe)
428		REG_WRITE(PFIT_CONTROL, 0);
429
430	for (i = 0; i <= need_aux; i++) {
431		REG_WRITE_WITH_AUX(map->src, ((mode->crtc_hdisplay - 1) << 16) |
432					     (mode->crtc_vdisplay - 1), i);
433	}
434
435	if (scalingType == DRM_MODE_SCALE_NO_SCALE) {
436		/* Moorestown doesn't have register support for centering so
437		 * we need to mess with the h/vblank and h/vsync start and
438		 * ends to get centering */
439		int offsetX = 0, offsetY = 0;
440
441		offsetX = (adjusted_mode->crtc_hdisplay -
442			   mode->crtc_hdisplay) / 2;
443		offsetY = (adjusted_mode->crtc_vdisplay -
444			   mode->crtc_vdisplay) / 2;
445
446		for (i = 0; i <= need_aux; i++) {
447			REG_WRITE_WITH_AUX(map->htotal, (mode->crtc_hdisplay - 1) |
448				((adjusted_mode->crtc_htotal - 1) << 16), i);
449			REG_WRITE_WITH_AUX(map->vtotal, (mode->crtc_vdisplay - 1) |
450				((adjusted_mode->crtc_vtotal - 1) << 16), i);
451			REG_WRITE_WITH_AUX(map->hblank,
452				(adjusted_mode->crtc_hblank_start - offsetX - 1) |
453				((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16), i);
454			REG_WRITE_WITH_AUX(map->hsync,
455				(adjusted_mode->crtc_hsync_start - offsetX - 1) |
456				((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16), i);
457			REG_WRITE_WITH_AUX(map->vblank,
458				(adjusted_mode->crtc_vblank_start - offsetY - 1) |
459				((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16), i);
460			REG_WRITE_WITH_AUX(map->vsync,
461				(adjusted_mode->crtc_vsync_start - offsetY - 1) |
462				((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16), i);
463		}
464	} else {
465		for (i = 0; i <= need_aux; i++) {
466			REG_WRITE_WITH_AUX(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
467				((adjusted_mode->crtc_htotal - 1) << 16), i);
468			REG_WRITE_WITH_AUX(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
469				((adjusted_mode->crtc_vtotal - 1) << 16), i);
470			REG_WRITE_WITH_AUX(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
471				((adjusted_mode->crtc_hblank_end - 1) << 16), i);
472			REG_WRITE_WITH_AUX(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
473				((adjusted_mode->crtc_hsync_end - 1) << 16), i);
474			REG_WRITE_WITH_AUX(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
475				((adjusted_mode->crtc_vblank_end - 1) << 16), i);
476			REG_WRITE_WITH_AUX(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
477				((adjusted_mode->crtc_vsync_end - 1) << 16), i);
478		}
479	}
480
481	/* Flush the plane changes */
482	{
483		const struct drm_crtc_helper_funcs *crtc_funcs =
484		    crtc->helper_private;
485		crtc_funcs->mode_set_base(crtc, x, y, old_fb);
486	}
487
488	/* setup pipeconf */
489	pipeconf = REG_READ(map->conf);
490
491	/* Set up the display plane register */
492	dspcntr = REG_READ(map->cntr);
493	dspcntr |= DISPPLANE_GAMMA_ENABLE;
494
495	if (pipe == 0)
496		dspcntr |= DISPPLANE_SEL_PIPE_A;
497	else
498		dspcntr |= DISPPLANE_SEL_PIPE_B;
499
500	if (is_mipi)
501		goto oaktrail_crtc_mode_set_exit;
502
503
504	dpll = 0;		/*BIT16 = 0 for 100MHz reference */
505
506	refclk = is_sdvo ? 96000 : dev_priv->core_freq * 1000;
507	limit = mrst_limit(crtc, refclk);
508	ok = limit->find_pll(limit, crtc, adjusted_mode->clock,
509			     refclk, &clock);
510
511	if (is_sdvo) {
512		/* Convert calculated values to register values */
513		clock.p1 = (1L << (clock.p1 - 1));
514		clock.m -= 2;
515		clock.n = (1L << (clock.n - 1));
516	}
517
518	if (!ok)
519		DRM_ERROR("Failed to find proper PLL settings");
520
521	mrst_print_pll(&clock);
522
523	if (is_sdvo)
524		fp = clock.n << 16 | clock.m;
525	else
526		fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8;
527
528	dpll |= DPLL_VGA_MODE_DIS;
529
530
531	dpll |= DPLL_VCO_ENABLE;
532
533	if (is_lvds)
534		dpll |= DPLLA_MODE_LVDS;
535	else
536		dpll |= DPLLB_MODE_DAC_SERIAL;
537
538	if (is_sdvo) {
539		int sdvo_pixel_multiply =
540		    adjusted_mode->clock / mode->clock;
541
542		dpll |= DPLL_DVO_HIGH_SPEED;
543		dpll |=
544		    (sdvo_pixel_multiply -
545		     1) << SDVO_MULTIPLIER_SHIFT_HIRES;
546	}
547
548
549	/* compute bitmask from p1 value */
550	if (is_sdvo)
551		dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16;
552	else
553		dpll |= (1 << (clock.p1 - 2)) << 17;
554
555	dpll |= DPLL_VCO_ENABLE;
556
557	if (dpll & DPLL_VCO_ENABLE) {
558		for (i = 0; i <= need_aux; i++) {
559			REG_WRITE_WITH_AUX(map->fp0, fp, i);
560			REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i);
561			REG_READ_WITH_AUX(map->dpll, i);
562			/* Check the DPLLA lock bit PIPEACONF[29] */
563			udelay(150);
564		}
565	}
566
567	for (i = 0; i <= need_aux; i++) {
568		REG_WRITE_WITH_AUX(map->fp0, fp, i);
569		REG_WRITE_WITH_AUX(map->dpll, dpll, i);
570		REG_READ_WITH_AUX(map->dpll, i);
571		/* Wait for the clocks to stabilize. */
572		udelay(150);
573
574		/* write it again -- the BIOS does, after all */
575		REG_WRITE_WITH_AUX(map->dpll, dpll, i);
576		REG_READ_WITH_AUX(map->dpll, i);
577		/* Wait for the clocks to stabilize. */
578		udelay(150);
579
580		REG_WRITE_WITH_AUX(map->conf, pipeconf, i);
581		REG_READ_WITH_AUX(map->conf, i);
582		gma_wait_for_vblank(dev);
583
584		REG_WRITE_WITH_AUX(map->cntr, dspcntr, i);
585		gma_wait_for_vblank(dev);
586	}
587
588oaktrail_crtc_mode_set_exit:
589	gma_power_end(dev);
590	return 0;
591}
592
593static int oaktrail_pipe_set_base(struct drm_crtc *crtc,
594			    int x, int y, struct drm_framebuffer *old_fb)
595{
596	struct drm_device *dev = crtc->dev;
597	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
598	struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
599	struct drm_framebuffer *fb = crtc->primary->fb;
600	int pipe = gma_crtc->pipe;
601	const struct psb_offset *map = &dev_priv->regmap[pipe];
602	unsigned long start, offset;
603
604	u32 dspcntr;
605	int ret = 0;
606
607	/* no fb bound */
608	if (!fb) {
609		dev_dbg(dev->dev, "No FB bound\n");
610		return 0;
611	}
612
613	if (!gma_power_begin(dev, true))
614		return 0;
615
616	start = to_psb_gem_object(fb->obj[0])->offset;
617	offset = y * fb->pitches[0] + x * fb->format->cpp[0];
618
619	REG_WRITE(map->stride, fb->pitches[0]);
620
621	dspcntr = REG_READ(map->cntr);
622	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
623
624	switch (fb->format->cpp[0] * 8) {
625	case 8:
626		dspcntr |= DISPPLANE_8BPP;
627		break;
628	case 16:
629		if (fb->format->depth == 15)
630			dspcntr |= DISPPLANE_15_16BPP;
631		else
632			dspcntr |= DISPPLANE_16BPP;
633		break;
634	case 24:
635	case 32:
636		dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
637		break;
638	default:
639		dev_err(dev->dev, "Unknown color depth\n");
640		ret = -EINVAL;
641		goto pipe_set_base_exit;
642	}
643	REG_WRITE(map->cntr, dspcntr);
644
645	REG_WRITE(map->base, offset);
646	REG_READ(map->base);
647	REG_WRITE(map->surf, start);
648	REG_READ(map->surf);
649
650pipe_set_base_exit:
651	gma_power_end(dev);
652	return ret;
653}
654
655const struct drm_crtc_helper_funcs oaktrail_helper_funcs = {
656	.dpms = oaktrail_crtc_dpms,
657	.mode_set = oaktrail_crtc_mode_set,
658	.mode_set_base = oaktrail_pipe_set_base,
659	.prepare = gma_crtc_prepare,
660	.commit = gma_crtc_commit,
661};