mid_bios.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/**************************************************************************
  3 * Copyright (c) 2011, Intel Corporation.
  4 * All Rights Reserved.
  5 *
  6 **************************************************************************/
  7
  8/* TODO
  9 * - Split functions by vbt type
 10 * - Make them all take drm_device
 11 * - Check ioremap failures
 12 */
 13
 14#include <drm/drm.h>
 15#include <drm/drm_print.h>
 16
 17#include "mid_bios.h"
 18#include "psb_drv.h"
 19
 20static void mid_get_fuse_settings(struct drm_device *dev)
 21{
 22	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
 23	struct pci_dev *pdev = to_pci_dev(dev->dev);
 24	struct pci_dev *pci_root =
 25		pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
 26					    0, 0);
 27	uint32_t fuse_value = 0;
 28	uint32_t fuse_value_tmp = 0;
 29
 30#define FB_REG06 0xD0810600
 31#define FB_MIPI_DISABLE  (1 << 11)
 32#define FB_REG09 0xD0810900
 33#define FB_SKU_MASK  0x7000
 34#define FB_SKU_SHIFT 12
 35#define FB_SKU_100 0
 36#define FB_SKU_100L 1
 37#define FB_SKU_83 2
 38	if (pci_root == NULL) {
 39		WARN_ON(1);
 40		return;
 41	}
 42
 43
 44	pci_write_config_dword(pci_root, 0xD0, FB_REG06);
 45	pci_read_config_dword(pci_root, 0xD4, &fuse_value);
 46
 47	/* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */
 48	if (IS_MRST(dev))
 49		dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
 50
 51	DRM_INFO("internal display is %s\n",
 52		 dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
 53
 54	 /* Prevent runtime suspend at start*/
 55	 if (dev_priv->iLVDS_enable) {
 56		dev_priv->is_lvds_on = true;
 57		dev_priv->is_mipi_on = false;
 58	} else {
 59		dev_priv->is_mipi_on = true;
 60		dev_priv->is_lvds_on = false;
 61	}
 62
 63	dev_priv->video_device_fuse = fuse_value;
 64
 65	pci_write_config_dword(pci_root, 0xD0, FB_REG09);
 66	pci_read_config_dword(pci_root, 0xD4, &fuse_value);
 67
 68	dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value);
 69	fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
 70
 71	dev_priv->fuse_reg_value = fuse_value;
 72
 73	switch (fuse_value_tmp) {
 74	case FB_SKU_100:
 75		dev_priv->core_freq = 200;
 76		break;
 77	case FB_SKU_100L:
 78		dev_priv->core_freq = 100;
 79		break;
 80	case FB_SKU_83:
 81		dev_priv->core_freq = 166;
 82		break;
 83	default:
 84		dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
 85								fuse_value_tmp);
 86		dev_priv->core_freq = 0;
 87	}
 88	dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);
 89	pci_dev_put(pci_root);
 90}
 91
 92/*
 93 *	Get the revison ID, B0:D2:F0;0x08
 94 */
 95static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
 96{
 97	uint32_t platform_rev_id = 0;
 98	struct pci_dev *pdev = to_pci_dev(dev_priv->dev.dev);
 99	int domain = pci_domain_nr(pdev->bus);
100	struct pci_dev *pci_gfx_root =
101		pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(2, 0));
102
103	if (pci_gfx_root == NULL) {
104		WARN_ON(1);
105		return;
106	}
107	pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
108	dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
109	pci_dev_put(pci_gfx_root);
110	dev_dbg(dev_priv->dev.dev, "platform_rev_id is %x\n", dev_priv->platform_rev_id);
111}
112
113struct mid_vbt_header {
114	u32 signature;
115	u8 revision;
116} __packed;
117
118/* The same for r0 and r1 */
119struct vbt_r0 {
120	struct mid_vbt_header vbt_header;
121	u8 size;
122	u8 checksum;
123} __packed;
124
125struct vbt_r10 {
126	struct mid_vbt_header vbt_header;
127	u8 checksum;
128	u16 size;
129	u8 panel_count;
130	u8 primary_panel_idx;
131	u8 secondary_panel_idx;
132	u8 __reserved[5];
133} __packed;
134
135static int read_vbt_r0(u32 addr, struct vbt_r0 *vbt)
136{
137	void __iomem *vbt_virtual;
138
139	vbt_virtual = ioremap(addr, sizeof(*vbt));
140	if (vbt_virtual == NULL)
141		return -1;
142
143	memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
144	iounmap(vbt_virtual);
145
146	return 0;
147}
148
149static int read_vbt_r10(u32 addr, struct vbt_r10 *vbt)
150{
151	void __iomem *vbt_virtual;
152
153	vbt_virtual = ioremap(addr, sizeof(*vbt));
154	if (!vbt_virtual)
155		return -1;
156
157	memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
158	iounmap(vbt_virtual);
159
160	return 0;
161}
162
163static int mid_get_vbt_data_r0(struct drm_psb_private *dev_priv, u32 addr)
164{
165	struct vbt_r0 vbt;
166	void __iomem *gct_virtual;
167	struct gct_r0 gct;
168	u8 bpi;
169
170	if (read_vbt_r0(addr, &vbt))
171		return -1;
172
173	gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
174	if (!gct_virtual)
175		return -1;
176	memcpy_fromio(&gct, gct_virtual, sizeof(gct));
177	iounmap(gct_virtual);
178
179	bpi = gct.PD.BootPanelIndex;
180	dev_priv->gct_data.bpi = bpi;
181	dev_priv->gct_data.pt = gct.PD.PanelType;
182	dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
183	dev_priv->gct_data.Panel_Port_Control =
184		gct.panel[bpi].Panel_Port_Control;
185	dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
186		gct.panel[bpi].Panel_MIPI_Display_Descriptor;
187
188	return 0;
189}
190
191static int mid_get_vbt_data_r1(struct drm_psb_private *dev_priv, u32 addr)
192{
193	struct vbt_r0 vbt;
194	void __iomem *gct_virtual;
195	struct gct_r1 gct;
196	u8 bpi;
197
198	if (read_vbt_r0(addr, &vbt))
199		return -1;
200
201	gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
202	if (!gct_virtual)
203		return -1;
204	memcpy_fromio(&gct, gct_virtual, sizeof(gct));
205	iounmap(gct_virtual);
206
207	bpi = gct.PD.BootPanelIndex;
208	dev_priv->gct_data.bpi = bpi;
209	dev_priv->gct_data.pt = gct.PD.PanelType;
210	dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
211	dev_priv->gct_data.Panel_Port_Control =
212		gct.panel[bpi].Panel_Port_Control;
213	dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
214		gct.panel[bpi].Panel_MIPI_Display_Descriptor;
215
216	return 0;
217}
218
219static int mid_get_vbt_data_r10(struct drm_psb_private *dev_priv, u32 addr)
220{
221	struct vbt_r10 vbt;
222	void __iomem *gct_virtual;
223	struct gct_r10 *gct;
224	struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD;
225	struct gct_r10_timing_info *ti;
226	int ret = -1;
227
228	if (read_vbt_r10(addr, &vbt))
229		return -1;
230
231	gct = kmalloc_array(vbt.panel_count, sizeof(*gct), GFP_KERNEL);
232	if (!gct)
233		return -ENOMEM;
234
235	gct_virtual = ioremap(addr + sizeof(vbt),
236			sizeof(*gct) * vbt.panel_count);
237	if (!gct_virtual)
238		goto out;
239	memcpy_fromio(gct, gct_virtual, sizeof(*gct));
240	iounmap(gct_virtual);
241
242	dev_priv->gct_data.bpi = vbt.primary_panel_idx;
243	dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
244		gct[vbt.primary_panel_idx].Panel_MIPI_Display_Descriptor;
245
246	ti = &gct[vbt.primary_panel_idx].DTD;
247	dp_ti->pixel_clock = ti->pixel_clock;
248	dp_ti->hactive_hi = ti->hactive_hi;
249	dp_ti->hactive_lo = ti->hactive_lo;
250	dp_ti->hblank_hi = ti->hblank_hi;
251	dp_ti->hblank_lo = ti->hblank_lo;
252	dp_ti->hsync_offset_hi = ti->hsync_offset_hi;
253	dp_ti->hsync_offset_lo = ti->hsync_offset_lo;
254	dp_ti->hsync_pulse_width_hi = ti->hsync_pulse_width_hi;
255	dp_ti->hsync_pulse_width_lo = ti->hsync_pulse_width_lo;
256	dp_ti->vactive_hi = ti->vactive_hi;
257	dp_ti->vactive_lo = ti->vactive_lo;
258	dp_ti->vblank_hi = ti->vblank_hi;
259	dp_ti->vblank_lo = ti->vblank_lo;
260	dp_ti->vsync_offset_hi = ti->vsync_offset_hi;
261	dp_ti->vsync_offset_lo = ti->vsync_offset_lo;
262	dp_ti->vsync_pulse_width_hi = ti->vsync_pulse_width_hi;
263	dp_ti->vsync_pulse_width_lo = ti->vsync_pulse_width_lo;
264
265	ret = 0;
266out:
267	kfree(gct);
268	return ret;
269}
270
271static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
272{
273	struct drm_device *dev = &dev_priv->dev;
274	struct pci_dev *pdev = to_pci_dev(dev->dev);
275	u32 addr;
276	u8 __iomem *vbt_virtual;
277	struct mid_vbt_header vbt_header;
278	struct pci_dev *pci_gfx_root =
279		pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
280					    0, PCI_DEVFN(2, 0));
281	int ret = -1;
282
283	if (pci_gfx_root == NULL) {
284		WARN_ON(1);
285		return;
286	}
287
288	/* Get the address of the platform config vbt */
289	pci_read_config_dword(pci_gfx_root, 0xFC, &addr);
290	pci_dev_put(pci_gfx_root);
291
292	dev_dbg(dev->dev, "drm platform config address is %x\n", addr);
293
294	if (!addr)
295		goto out;
296
297	/* get the virtual address of the vbt */
298	vbt_virtual = ioremap(addr, sizeof(vbt_header));
299	if (!vbt_virtual)
300		goto out;
301
302	memcpy_fromio(&vbt_header, vbt_virtual, sizeof(vbt_header));
303	iounmap(vbt_virtual);
304
305	if (memcmp(&vbt_header.signature, "$GCT", 4))
306		goto out;
307
308	dev_dbg(dev->dev, "GCT revision is %02x\n", vbt_header.revision);
309
310	switch (vbt_header.revision) {
311	case 0x00:
312		ret = mid_get_vbt_data_r0(dev_priv, addr);
313		break;
314	case 0x01:
315		ret = mid_get_vbt_data_r1(dev_priv, addr);
316		break;
317	case 0x10:
318		ret = mid_get_vbt_data_r10(dev_priv, addr);
319		break;
320	default:
321		dev_err(dev->dev, "Unknown revision of GCT!\n");
322	}
323
324out:
325	if (ret)
326		dev_err(dev->dev, "Unable to read GCT!");
327	else
328		dev_priv->has_gct = true;
329}
330
331int mid_chip_setup(struct drm_device *dev)
332{
333	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
334	mid_get_fuse_settings(dev);
335	mid_get_vbt_data(dev_priv);
336	mid_get_pci_revID(dev_priv);
337	return 0;
338}