intel_gmbus.c

  1/*
  2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3 * Copyright © 2006-2008,2010 Intel Corporation
  4 *   Jesse Barnes <jesse.barnes@intel.com>
  5 *
  6 * Permission is hereby granted, free of charge, to any person obtaining a
  7 * copy of this software and associated documentation files (the "Software"),
  8 * to deal in the Software without restriction, including without limitation
  9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 10 * and/or sell copies of the Software, and to permit persons to whom the
 11 * Software is furnished to do so, subject to the following conditions:
 12 *
 13 * The above copyright notice and this permission notice (including the next
 14 * paragraph) shall be included in all copies or substantial portions of the
 15 * Software.
 16 *
 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 23 * DEALINGS IN THE SOFTWARE.
 24 *
 25 * Authors:
 26 *	Eric Anholt <eric@anholt.net>
 27 *	Chris Wilson <chris@chris-wilson.co.uk>
 28 */
 29
 30#include <linux/delay.h>
 31#include <linux/i2c-algo-bit.h>
 32#include <linux/i2c.h>
 33#include <linux/module.h>
 34
 35#include <drm/drm_print.h>
 36
 37#include "psb_drv.h"
 38#include "psb_intel_drv.h"
 39#include "psb_intel_reg.h"
 40
 41#define _wait_for(COND, MS, W) ({ \
 42	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);	\
 43	int ret__ = 0;							\
 44	while (! (COND)) {						\
 45		if (time_after(jiffies, timeout__)) {			\
 46			ret__ = -ETIMEDOUT;				\
 47			break;						\
 48		}							\
 49		if (W && !(in_dbg_master()))				\
 50			msleep(W);					\
 51	}								\
 52	ret__;								\
 53})
 54
 55#define wait_for(COND, MS) _wait_for(COND, MS, 1)
 56
 57#define GMBUS_REG_READ(reg) ioread32(dev_priv->gmbus_reg + (reg))
 58#define GMBUS_REG_WRITE(reg, val) iowrite32((val), dev_priv->gmbus_reg + (reg))
 59
 60/* Intel GPIO access functions */
 61
 62#define I2C_RISEFALL_TIME 20
 63
 64static inline struct intel_gmbus *
 65to_intel_gmbus(struct i2c_adapter *i2c)
 66{
 67	return container_of(i2c, struct intel_gmbus, adapter);
 68}
 69
 70struct intel_gpio {
 71	struct i2c_adapter adapter;
 72	struct i2c_algo_bit_data algo;
 73	struct drm_psb_private *dev_priv;
 74	u32 reg;
 75};
 76
 77void
 78gma_intel_i2c_reset(struct drm_device *dev)
 79{
 80	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
 81	GMBUS_REG_WRITE(GMBUS0, 0);
 82}
 83
 84static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable)
 85{
 86	/* When using bit bashing for I2C, this bit needs to be set to 1 */
 87	/* FIXME: We are never Pineview, right?
 88
 89	u32 val;
 90
 91	if (!IS_PINEVIEW(dev_priv->dev))
 92		return;
 93
 94	val = REG_READ(DSPCLK_GATE_D);
 95	if (enable)
 96		val |= DPCUNIT_CLOCK_GATE_DISABLE;
 97	else
 98		val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
 99	REG_WRITE(DSPCLK_GATE_D, val);
100
101	return;
102	*/
103}
104
105static u32 get_reserved(struct intel_gpio *gpio)
106{
107	struct drm_psb_private *dev_priv = gpio->dev_priv;
108	u32 reserved = 0;
109
110	/* On most chips, these bits must be preserved in software. */
111	reserved = GMBUS_REG_READ(gpio->reg) &
112				     (GPIO_DATA_PULLUP_DISABLE |
113				      GPIO_CLOCK_PULLUP_DISABLE);
114
115	return reserved;
116}
117
118static int get_clock(void *data)
119{
120	struct intel_gpio *gpio = data;
121	struct drm_psb_private *dev_priv = gpio->dev_priv;
122	u32 reserved = get_reserved(gpio);
123	GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
124	GMBUS_REG_WRITE(gpio->reg, reserved);
125	return (GMBUS_REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
126}
127
128static int get_data(void *data)
129{
130	struct intel_gpio *gpio = data;
131	struct drm_psb_private *dev_priv = gpio->dev_priv;
132	u32 reserved = get_reserved(gpio);
133	GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
134	GMBUS_REG_WRITE(gpio->reg, reserved);
135	return (GMBUS_REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
136}
137
138static void set_clock(void *data, int state_high)
139{
140	struct intel_gpio *gpio = data;
141	struct drm_psb_private *dev_priv = gpio->dev_priv;
142	u32 reserved = get_reserved(gpio);
143	u32 clock_bits;
144
145	if (state_high)
146		clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
147	else
148		clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
149			GPIO_CLOCK_VAL_MASK;
150
151	GMBUS_REG_WRITE(gpio->reg, reserved | clock_bits);
152	GMBUS_REG_READ(gpio->reg); /* Posting */
153}
154
155static void set_data(void *data, int state_high)
156{
157	struct intel_gpio *gpio = data;
158	struct drm_psb_private *dev_priv = gpio->dev_priv;
159	u32 reserved = get_reserved(gpio);
160	u32 data_bits;
161
162	if (state_high)
163		data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
164	else
165		data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
166			GPIO_DATA_VAL_MASK;
167
168	GMBUS_REG_WRITE(gpio->reg, reserved | data_bits);
169	GMBUS_REG_READ(gpio->reg);
170}
171
172static struct i2c_adapter *
173intel_gpio_create(struct drm_psb_private *dev_priv, u32 pin)
174{
175	static const int map_pin_to_reg[] = {
176		0,
177		GPIOB,
178		GPIOA,
179		GPIOC,
180		GPIOD,
181		GPIOE,
182		0,
183		GPIOF,
184	};
185	struct intel_gpio *gpio;
186
187	if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
188		return NULL;
189
190	gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
191	if (gpio == NULL)
192		return NULL;
193
194	gpio->reg = map_pin_to_reg[pin];
195	gpio->dev_priv = dev_priv;
196
197	snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
198		 "gma500 GPIO%c", "?BACDE?F"[pin]);
199	gpio->adapter.owner = THIS_MODULE;
200	gpio->adapter.algo_data	= &gpio->algo;
201	gpio->adapter.dev.parent = dev_priv->dev.dev;
202	gpio->algo.setsda = set_data;
203	gpio->algo.setscl = set_clock;
204	gpio->algo.getsda = get_data;
205	gpio->algo.getscl = get_clock;
206	gpio->algo.udelay = I2C_RISEFALL_TIME;
207	gpio->algo.timeout = usecs_to_jiffies(2200);
208	gpio->algo.data = gpio;
209
210	if (i2c_bit_add_bus(&gpio->adapter))
211		goto out_free;
212
213	return &gpio->adapter;
214
215out_free:
216	kfree(gpio);
217	return NULL;
218}
219
220static int
221intel_i2c_quirk_xfer(struct drm_psb_private *dev_priv,
222		     struct i2c_adapter *adapter,
223		     struct i2c_msg *msgs,
224		     int num)
225{
226	struct intel_gpio *gpio = container_of(adapter,
227					       struct intel_gpio,
228					       adapter);
229	int ret;
230
231	gma_intel_i2c_reset(&dev_priv->dev);
232
233	intel_i2c_quirk_set(dev_priv, true);
234	set_data(gpio, 1);
235	set_clock(gpio, 1);
236	udelay(I2C_RISEFALL_TIME);
237
238	ret = adapter->algo->master_xfer(adapter, msgs, num);
239
240	set_data(gpio, 1);
241	set_clock(gpio, 1);
242	intel_i2c_quirk_set(dev_priv, false);
243
244	return ret;
245}
246
247static int
248gmbus_xfer(struct i2c_adapter *adapter,
249	   struct i2c_msg *msgs,
250	   int num)
251{
252	struct intel_gmbus *bus = container_of(adapter,
253					       struct intel_gmbus,
254					       adapter);
255	struct drm_psb_private *dev_priv = adapter->algo_data;
256	int i, reg_offset;
257
258	if (bus->force_bit)
259		return intel_i2c_quirk_xfer(dev_priv,
260					    bus->force_bit, msgs, num);
261
262	reg_offset = 0;
263
264	GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0);
265
266	for (i = 0; i < num; i++) {
267		u16 len = msgs[i].len;
268		u8 *buf = msgs[i].buf;
269
270		if (msgs[i].flags & I2C_M_RD) {
271			GMBUS_REG_WRITE(GMBUS1 + reg_offset,
272					GMBUS_CYCLE_WAIT |
273					(i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
274					(len << GMBUS_BYTE_COUNT_SHIFT) |
275					(msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
276					GMBUS_SLAVE_READ | GMBUS_SW_RDY);
277			GMBUS_REG_READ(GMBUS2+reg_offset);
278			do {
279				u32 val, loop = 0;
280
281				if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
282					     (GMBUS_SATOER | GMBUS_HW_RDY), 50))
283					goto timeout;
284				if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
285					goto clear_err;
286
287				val = GMBUS_REG_READ(GMBUS3 + reg_offset);
288				do {
289					*buf++ = val & 0xff;
290					val >>= 8;
291				} while (--len && ++loop < 4);
292			} while (len);
293		} else {
294			u32 val, loop;
295
296			val = loop = 0;
297			do {
298				val |= *buf++ << (8 * loop);
299			} while (--len && ++loop < 4);
300
301			GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
302			GMBUS_REG_WRITE(GMBUS1 + reg_offset,
303				   (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
304				   (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
305				   (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
306				   GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
307			GMBUS_REG_READ(GMBUS2+reg_offset);
308
309			while (len) {
310				if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
311					     (GMBUS_SATOER | GMBUS_HW_RDY), 50))
312					goto timeout;
313				if (GMBUS_REG_READ(GMBUS2 + reg_offset) &
314				    GMBUS_SATOER)
315					goto clear_err;
316
317				val = loop = 0;
318				do {
319					val |= *buf++ << (8 * loop);
320				} while (--len && ++loop < 4);
321
322				GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
323				GMBUS_REG_READ(GMBUS2+reg_offset);
324			}
325		}
326
327		if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
328			goto timeout;
329		if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
330			goto clear_err;
331	}
332
333	goto done;
334
335clear_err:
336	/* Toggle the Software Clear Interrupt bit. This has the effect
337	 * of resetting the GMBUS controller and so clearing the
338	 * BUS_ERROR raised by the target's NAK.
339	 */
340	GMBUS_REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
341	GMBUS_REG_WRITE(GMBUS1 + reg_offset, 0);
342
343done:
344	/* Mark the GMBUS interface as disabled. We will re-enable it at the
345	 * start of the next xfer, till then let it sleep.
346	 */
347	GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
348	return i;
349
350timeout:
351	DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
352		 bus->reg0 & 0xff, bus->adapter.name);
353	GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
354
355	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
356	bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
357	if (!bus->force_bit)
358		return -ENOMEM;
359
360	return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
361}
362
363static u32 gmbus_func(struct i2c_adapter *adapter)
364{
365	struct intel_gmbus *bus = container_of(adapter,
366					       struct intel_gmbus,
367					       adapter);
368
369	if (bus->force_bit)
370		bus->force_bit->algo->functionality(bus->force_bit);
371
372	return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
373		/* I2C_FUNC_10BIT_ADDR | */
374		I2C_FUNC_SMBUS_READ_BLOCK_DATA |
375		I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
376}
377
378static const struct i2c_algorithm gmbus_algorithm = {
379	.master_xfer	= gmbus_xfer,
380	.functionality	= gmbus_func
381};
382
383/**
384 * gma_intel_setup_gmbus() - instantiate all Intel i2c GMBuses
385 * @dev: DRM device
386 */
387int gma_intel_setup_gmbus(struct drm_device *dev)
388{
389	static const char *names[GMBUS_NUM_PORTS] = {
390		"disabled",
391		"ssc",
392		"vga",
393		"panel",
394		"dpc",
395		"dpb",
396		"reserved",
397		"dpd",
398	};
399	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
400	int ret, i;
401
402	dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus),
403				  GFP_KERNEL);
404	if (dev_priv->gmbus == NULL)
405		return -ENOMEM;
406
407	if (IS_MRST(dev))
408		dev_priv->gmbus_reg = dev_priv->aux_reg;
409	else
410		dev_priv->gmbus_reg = dev_priv->vdc_reg;
411
412	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
413		struct intel_gmbus *bus = &dev_priv->gmbus[i];
414
415		bus->adapter.owner = THIS_MODULE;
416		snprintf(bus->adapter.name,
417			 sizeof(bus->adapter.name),
418			 "gma500 gmbus %s",
419			 names[i]);
420
421		bus->adapter.dev.parent = dev->dev;
422		bus->adapter.algo_data	= dev_priv;
423
424		bus->adapter.algo = &gmbus_algorithm;
425		ret = i2c_add_adapter(&bus->adapter);
426		if (ret)
427			goto err;
428
429		/* By default use a conservative clock rate */
430		bus->reg0 = i | GMBUS_RATE_100KHZ;
431
432		/* XXX force bit banging until GMBUS is fully debugged */
433		bus->force_bit = intel_gpio_create(dev_priv, i);
434	}
435
436	gma_intel_i2c_reset(&dev_priv->dev);
437
438	return 0;
439
440err:
441	while (i--) {
442		struct intel_gmbus *bus = &dev_priv->gmbus[i];
443		i2c_del_adapter(&bus->adapter);
444	}
445	kfree(dev_priv->gmbus);
446	dev_priv->gmbus = NULL;
447	return ret;
448}
449
450void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
451{
452	struct intel_gmbus *bus = to_intel_gmbus(adapter);
453
454	/* speed:
455	 * 0x0 = 100 KHz
456	 * 0x1 = 50 KHz
457	 * 0x2 = 400 KHz
458	 * 0x3 = 1000 Khz
459	 */
460	bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
461}
462
463void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
464{
465	struct intel_gmbus *bus = to_intel_gmbus(adapter);
466
467	if (force_bit) {
468		if (bus->force_bit == NULL) {
469			struct drm_psb_private *dev_priv = adapter->algo_data;
470			bus->force_bit = intel_gpio_create(dev_priv,
471							   bus->reg0 & 0xff);
472		}
473	} else {
474		if (bus->force_bit) {
475			i2c_del_adapter(bus->force_bit);
476			kfree(bus->force_bit);
477			bus->force_bit = NULL;
478		}
479	}
480}
481
482void gma_intel_teardown_gmbus(struct drm_device *dev)
483{
484	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
485	int i;
486
487	if (dev_priv->gmbus == NULL)
488		return;
489
490	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
491		struct intel_gmbus *bus = &dev_priv->gmbus[i];
492		if (bus->force_bit) {
493			i2c_del_adapter(bus->force_bit);
494			kfree(bus->force_bit);
495		}
496		i2c_del_adapter(&bus->adapter);
497	}
498
499	dev_priv->gmbus_reg = NULL; /* iounmap is done in driver_unload */
500	kfree(dev_priv->gmbus);
501	dev_priv->gmbus = NULL;
502}