cdv_intel_display.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright © 2006-2011 Intel Corporation
  4 *
  5 * Authors:
  6 *	Eric Anholt <eric@anholt.net>
  7 */
  8
  9#include <linux/delay.h>
 10#include <linux/i2c.h>
 11
 12#include <drm/drm_crtc.h>
 13#include <drm/drm_modeset_helper_vtables.h>
 14#include <drm/drm_print.h>
 15
 16#include "cdv_device.h"
 17#include "framebuffer.h"
 18#include "gma_display.h"
 19#include "power.h"
 20#include "psb_drv.h"
 21#include "psb_intel_drv.h"
 22#include "psb_intel_reg.h"
 23
 24static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
 25				  struct drm_crtc *crtc, int target,
 26				  int refclk, struct gma_clock_t *best_clock);
 27
 28
 29#define CDV_LIMIT_SINGLE_LVDS_96	0
 30#define CDV_LIMIT_SINGLE_LVDS_100	1
 31#define CDV_LIMIT_DAC_HDMI_27		2
 32#define CDV_LIMIT_DAC_HDMI_96		3
 33#define CDV_LIMIT_DP_27			4
 34#define CDV_LIMIT_DP_100		5
 35
 36static const struct gma_limit_t cdv_intel_limits[] = {
 37	{			/* CDV_SINGLE_LVDS_96MHz */
 38	 .dot = {.min = 20000, .max = 115500},
 39	 .vco = {.min = 1800000, .max = 3600000},
 40	 .n = {.min = 2, .max = 6},
 41	 .m = {.min = 60, .max = 160},
 42	 .m1 = {.min = 0, .max = 0},
 43	 .m2 = {.min = 58, .max = 158},
 44	 .p = {.min = 28, .max = 140},
 45	 .p1 = {.min = 2, .max = 10},
 46	 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
 47	 .find_pll = gma_find_best_pll,
 48	 },
 49	{			/* CDV_SINGLE_LVDS_100MHz */
 50	 .dot = {.min = 20000, .max = 115500},
 51	 .vco = {.min = 1800000, .max = 3600000},
 52	 .n = {.min = 2, .max = 6},
 53	 .m = {.min = 60, .max = 160},
 54	 .m1 = {.min = 0, .max = 0},
 55	 .m2 = {.min = 58, .max = 158},
 56	 .p = {.min = 28, .max = 140},
 57	 .p1 = {.min = 2, .max = 10},
 58	 /* The single-channel range is 25-112Mhz, and dual-channel
 59	  * is 80-224Mhz.  Prefer single channel as much as possible.
 60	  */
 61	 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
 62	 .find_pll = gma_find_best_pll,
 63	 },
 64	{			/* CDV_DAC_HDMI_27MHz */
 65	 .dot = {.min = 20000, .max = 400000},
 66	 .vco = {.min = 1809000, .max = 3564000},
 67	 .n = {.min = 1, .max = 1},
 68	 .m = {.min = 67, .max = 132},
 69	 .m1 = {.min = 0, .max = 0},
 70	 .m2 = {.min = 65, .max = 130},
 71	 .p = {.min = 5, .max = 90},
 72	 .p1 = {.min = 1, .max = 9},
 73	 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
 74	 .find_pll = gma_find_best_pll,
 75	 },
 76	{			/* CDV_DAC_HDMI_96MHz */
 77	 .dot = {.min = 20000, .max = 400000},
 78	 .vco = {.min = 1800000, .max = 3600000},
 79	 .n = {.min = 2, .max = 6},
 80	 .m = {.min = 60, .max = 160},
 81	 .m1 = {.min = 0, .max = 0},
 82	 .m2 = {.min = 58, .max = 158},
 83	 .p = {.min = 5, .max = 100},
 84	 .p1 = {.min = 1, .max = 10},
 85	 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
 86	 .find_pll = gma_find_best_pll,
 87	 },
 88	{			/* CDV_DP_27MHz */
 89	 .dot = {.min = 160000, .max = 272000},
 90	 .vco = {.min = 1809000, .max = 3564000},
 91	 .n = {.min = 1, .max = 1},
 92	 .m = {.min = 67, .max = 132},
 93	 .m1 = {.min = 0, .max = 0},
 94	 .m2 = {.min = 65, .max = 130},
 95	 .p = {.min = 5, .max = 90},
 96	 .p1 = {.min = 1, .max = 9},
 97	 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
 98	 .find_pll = cdv_intel_find_dp_pll,
 99	 },
100	{			/* CDV_DP_100MHz */
101	 .dot = {.min = 160000, .max = 272000},
102	 .vco = {.min = 1800000, .max = 3600000},
103	 .n = {.min = 2, .max = 6},
104	 .m = {.min = 60, .max = 164},
105	 .m1 = {.min = 0, .max = 0},
106	 .m2 = {.min = 58, .max = 162},
107	 .p = {.min = 5, .max = 100},
108	 .p1 = {.min = 1, .max = 10},
109	 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
110	 .find_pll = cdv_intel_find_dp_pll,
111	}
112};
113
114#define _wait_for(COND, MS, W) ({ \
115	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);	\
116	int ret__ = 0;							\
117	while (!(COND)) {						\
118		if (time_after(jiffies, timeout__)) {			\
119			ret__ = -ETIMEDOUT;				\
120			break;						\
121		}							\
122		if (W && !in_dbg_master())				\
123			msleep(W);					\
124	}								\
125	ret__;								\
126})
127
128#define wait_for(COND, MS) _wait_for(COND, MS, 1)
129
130
131int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
132{
133	int ret;
134
135	ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
136	if (ret) {
137		DRM_ERROR("timeout waiting for SB to idle before read\n");
138		return ret;
139	}
140
141	REG_WRITE(SB_ADDR, reg);
142	REG_WRITE(SB_PCKT,
143		   SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
144		   SET_FIELD(SB_DEST_DPLL, SB_DEST) |
145		   SET_FIELD(0xf, SB_BYTE_ENABLE));
146
147	ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
148	if (ret) {
149		DRM_ERROR("timeout waiting for SB to idle after read\n");
150		return ret;
151	}
152
153	*val = REG_READ(SB_DATA);
154
155	return 0;
156}
157
158int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
159{
160	int ret;
161	static bool dpio_debug = true;
162	u32 temp;
163
164	if (dpio_debug) {
165		if (cdv_sb_read(dev, reg, &temp) == 0)
166			DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
167		DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
168	}
169
170	ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
171	if (ret) {
172		DRM_ERROR("timeout waiting for SB to idle before write\n");
173		return ret;
174	}
175
176	REG_WRITE(SB_ADDR, reg);
177	REG_WRITE(SB_DATA, val);
178	REG_WRITE(SB_PCKT,
179		   SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
180		   SET_FIELD(SB_DEST_DPLL, SB_DEST) |
181		   SET_FIELD(0xf, SB_BYTE_ENABLE));
182
183	ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
184	if (ret) {
185		DRM_ERROR("timeout waiting for SB to idle after write\n");
186		return ret;
187	}
188
189	if (dpio_debug) {
190		if (cdv_sb_read(dev, reg, &temp) == 0)
191			DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
192	}
193
194	return 0;
195}
196
197/* Reset the DPIO configuration register.  The BIOS does this at every
198 * mode set.
199 */
200void cdv_sb_reset(struct drm_device *dev)
201{
202
203	REG_WRITE(DPIO_CFG, 0);
204	REG_READ(DPIO_CFG);
205	REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
206}
207
208/* Unlike most Intel display engines, on Cedarview the DPLL registers
209 * are behind this sideband bus.  They must be programmed while the
210 * DPLL reference clock is on in the DPLL control register, but before
211 * the DPLL is enabled in the DPLL control register.
212 */
213static int
214cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
215		       struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
216{
217	struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
218	int pipe = gma_crtc->pipe;
219	u32 m, n_vco, p;
220	int ret = 0;
221	int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
222	int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
223	u32 ref_value;
224	u32 lane_reg, lane_value;
225
226	cdv_sb_reset(dev);
227
228	REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
229
230	udelay(100);
231
232	/* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
233	ref_value = 0x68A701;
234
235	cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
236
237	/* We don't know what the other fields of these regs are, so
238	 * leave them in place.
239	 */
240	/*
241	 * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
242	 * for the pipe A/B. Display spec 1.06 has wrong definition.
243	 * Correct definition is like below:
244	 *
245	 * refclka mean use clock from same PLL
246	 *
247	 * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
248	 *
249	 * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
250	 *
251	 */
252	ret = cdv_sb_read(dev, ref_sfr, &ref_value);
253	if (ret)
254		return ret;
255	ref_value &= ~(REF_CLK_MASK);
256
257	/* use DPLL_A for pipeB on CRT/HDMI */
258	if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) {
259		DRM_DEBUG_KMS("use DPLLA for pipe B\n");
260		ref_value |= REF_CLK_DPLLA;
261	} else {
262		DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
263		ref_value |= REF_CLK_DPLL;
264	}
265	ret = cdv_sb_write(dev, ref_sfr, ref_value);
266	if (ret)
267		return ret;
268
269	ret = cdv_sb_read(dev, SB_M(pipe), &m);
270	if (ret)
271		return ret;
272	m &= ~SB_M_DIVIDER_MASK;
273	m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
274	ret = cdv_sb_write(dev, SB_M(pipe), m);
275	if (ret)
276		return ret;
277
278	ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);
279	if (ret)
280		return ret;
281
282	/* Follow the BIOS to program the N_DIVIDER REG */
283	n_vco &= 0xFFFF;
284	n_vco |= 0x107;
285	n_vco &= ~(SB_N_VCO_SEL_MASK |
286		   SB_N_DIVIDER_MASK |
287		   SB_N_CB_TUNE_MASK);
288
289	n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
290
291	if (clock->vco < 2250000) {
292		n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
293		n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
294	} else if (clock->vco < 2750000) {
295		n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
296		n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
297	} else if (clock->vco < 3300000) {
298		n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
299		n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
300	} else {
301		n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
302		n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
303	}
304
305	ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);
306	if (ret)
307		return ret;
308
309	ret = cdv_sb_read(dev, SB_P(pipe), &p);
310	if (ret)
311		return ret;
312	p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
313	p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
314	switch (clock->p2) {
315	case 5:
316		p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
317		break;
318	case 10:
319		p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
320		break;
321	case 14:
322		p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
323		break;
324	case 7:
325		p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
326		break;
327	default:
328		DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
329		return -EINVAL;
330	}
331	ret = cdv_sb_write(dev, SB_P(pipe), p);
332	if (ret)
333		return ret;
334
335	if (ddi_select) {
336		if ((ddi_select & DDI_MASK) == DDI0_SELECT) {
337			lane_reg = PSB_LANE0;
338			cdv_sb_read(dev, lane_reg, &lane_value);
339			lane_value &= ~(LANE_PLL_MASK);
340			lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
341			cdv_sb_write(dev, lane_reg, lane_value);
342
343			lane_reg = PSB_LANE1;
344			cdv_sb_read(dev, lane_reg, &lane_value);
345			lane_value &= ~(LANE_PLL_MASK);
346			lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
347			cdv_sb_write(dev, lane_reg, lane_value);
348		} else {
349			lane_reg = PSB_LANE2;
350			cdv_sb_read(dev, lane_reg, &lane_value);
351			lane_value &= ~(LANE_PLL_MASK);
352			lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
353			cdv_sb_write(dev, lane_reg, lane_value);
354
355			lane_reg = PSB_LANE3;
356			cdv_sb_read(dev, lane_reg, &lane_value);
357			lane_value &= ~(LANE_PLL_MASK);
358			lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
359			cdv_sb_write(dev, lane_reg, lane_value);
360		}
361	}
362	return 0;
363}
364
365static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
366						 int refclk)
367{
368	const struct gma_limit_t *limit;
369	if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
370		/*
371		 * Now only single-channel LVDS is supported on CDV. If it is
372		 * incorrect, please add the dual-channel LVDS.
373		 */
374		if (refclk == 96000)
375			limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
376		else
377			limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
378	} else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
379			gma_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
380		if (refclk == 27000)
381			limit = &cdv_intel_limits[CDV_LIMIT_DP_27];
382		else
383			limit = &cdv_intel_limits[CDV_LIMIT_DP_100];
384	} else {
385		if (refclk == 27000)
386			limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
387		else
388			limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
389	}
390	return limit;
391}
392
393/* m1 is reserved as 0 in CDV, n is a ring counter */
394static void cdv_intel_clock(int refclk, struct gma_clock_t *clock)
395{
396	clock->m = clock->m2 + 2;
397	clock->p = clock->p1 * clock->p2;
398	clock->vco = (refclk * clock->m) / clock->n;
399	clock->dot = clock->vco / clock->p;
400}
401
402static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
403				  struct drm_crtc *crtc, int target,
404				  int refclk,
405				  struct gma_clock_t *best_clock)
406{
407	struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
408	struct gma_clock_t clock;
409
410	memset(&clock, 0, sizeof(clock));
411
412	switch (refclk) {
413	case 27000:
414		if (target < 200000) {
415			clock.p1 = 2;
416			clock.p2 = 10;
417			clock.n = 1;
418			clock.m1 = 0;
419			clock.m2 = 118;
420		} else {
421			clock.p1 = 1;
422			clock.p2 = 10;
423			clock.n = 1;
424			clock.m1 = 0;
425			clock.m2 = 98;
426		}
427		break;
428
429	case 100000:
430		if (target < 200000) {
431			clock.p1 = 2;
432			clock.p2 = 10;
433			clock.n = 5;
434			clock.m1 = 0;
435			clock.m2 = 160;
436		} else {
437			clock.p1 = 1;
438			clock.p2 = 10;
439			clock.n = 5;
440			clock.m1 = 0;
441			clock.m2 = 133;
442		}
443		break;
444
445	default:
446		return false;
447	}
448
449	gma_crtc->clock_funcs->clock(refclk, &clock);
450	memcpy(best_clock, &clock, sizeof(struct gma_clock_t));
451	return true;
452}
453
454#define		FIFO_PIPEA		(1 << 0)
455#define		FIFO_PIPEB		(1 << 1)
456
457static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
458{
459	struct drm_crtc *crtc;
460	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
461	struct gma_crtc *gma_crtc = NULL;
462
463	crtc = dev_priv->pipe_to_crtc_mapping[pipe];
464	gma_crtc = to_gma_crtc(crtc);
465
466	if (crtc->primary->fb == NULL || !gma_crtc->active)
467		return false;
468	return true;
469}
470
471void cdv_disable_sr(struct drm_device *dev)
472{
473	if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
474
475		/* Disable self-refresh before adjust WM */
476		REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
477		REG_READ(FW_BLC_SELF);
478
479		gma_wait_for_vblank(dev);
480
481		/* Cedarview workaround to write ovelay plane, which force to leave
482		 * MAX_FIFO state.
483		 */
484		REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
485		REG_READ(OV_OVADD);
486
487		gma_wait_for_vblank(dev);
488	}
489
490}
491
492void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc)
493{
494	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
495	struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
496
497	/* Is only one pipe enabled? */
498	if (cdv_intel_pipe_enabled(dev, 0) ^ cdv_intel_pipe_enabled(dev, 1)) {
499		u32 fw;
500
501		fw = REG_READ(DSPFW1);
502		fw &= ~DSP_FIFO_SR_WM_MASK;
503		fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);
504		fw &= ~CURSOR_B_FIFO_WM_MASK;
505		fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);
506		REG_WRITE(DSPFW1, fw);
507
508		fw = REG_READ(DSPFW2);
509		fw &= ~CURSOR_A_FIFO_WM_MASK;
510		fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);
511		fw &= ~DSP_PLANE_C_FIFO_WM_MASK;
512		fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);
513		REG_WRITE(DSPFW2, fw);
514
515		REG_WRITE(DSPFW3, 0x36000000);
516
517		/* ignore FW4 */
518
519		/* Is pipe b lvds ? */
520		if (gma_crtc->pipe == 1 &&
521		    gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
522			REG_WRITE(DSPFW5, 0x00040330);
523		} else {
524			fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
525			     (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) |
526			     (3 << CURSOR_B_FIFO_WM1_SHIFT) |
527			     (4 << CURSOR_FIFO_SR_WM1_SHIFT);
528			REG_WRITE(DSPFW5, fw);
529		}
530
531		REG_WRITE(DSPFW6, 0x10);
532
533		gma_wait_for_vblank(dev);
534
535		/* enable self-refresh for single pipe active */
536		REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
537		REG_READ(FW_BLC_SELF);
538		gma_wait_for_vblank(dev);
539
540	} else {
541
542		/* HW team suggested values... */
543		REG_WRITE(DSPFW1, 0x3f880808);
544		REG_WRITE(DSPFW2, 0x0b020202);
545		REG_WRITE(DSPFW3, 0x24000000);
546		REG_WRITE(DSPFW4, 0x08030202);
547		REG_WRITE(DSPFW5, 0x01010101);
548		REG_WRITE(DSPFW6, 0x1d0);
549
550		gma_wait_for_vblank(dev);
551
552		dev_priv->ops->disable_sr(dev);
553	}
554}
555
556/*
557 * Return the pipe currently connected to the panel fitter,
558 * or -1 if the panel fitter is not present or not in use
559 */
560static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
561{
562	u32 pfit_control;
563
564	pfit_control = REG_READ(PFIT_CONTROL);
565
566	/* See if the panel fitter is in use */
567	if ((pfit_control & PFIT_ENABLE) == 0)
568		return -1;
569	return (pfit_control >> 29) & 0x3;
570}
571
572static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
573			       struct drm_display_mode *mode,
574			       struct drm_display_mode *adjusted_mode,
575			       int x, int y,
576			       struct drm_framebuffer *old_fb)
577{
578	struct drm_device *dev = crtc->dev;
579	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
580	struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
581	int pipe = gma_crtc->pipe;
582	const struct psb_offset *map = &dev_priv->regmap[pipe];
583	int refclk;
584	struct gma_clock_t clock;
585	u32 dpll = 0, dspcntr, pipeconf;
586	bool ok;
587	bool is_lvds = false;
588	bool is_dp = false;
589	struct drm_connector_list_iter conn_iter;
590	struct drm_connector *connector;
591	const struct gma_limit_t *limit;
592	u32 ddi_select = 0;
593	bool is_edp = false;
594
595	drm_connector_list_iter_begin(dev, &conn_iter);
596	drm_for_each_connector_iter(connector, &conn_iter) {
597		struct gma_encoder *gma_encoder =
598					gma_attached_encoder(connector);
599
600		if (!connector->encoder
601		    || connector->encoder->crtc != crtc)
602			continue;
603
604		ddi_select = gma_encoder->ddi_select;
605		switch (gma_encoder->type) {
606		case INTEL_OUTPUT_LVDS:
607			is_lvds = true;
608			break;
609		case INTEL_OUTPUT_ANALOG:
610		case INTEL_OUTPUT_HDMI:
611			break;
612		case INTEL_OUTPUT_DISPLAYPORT:
613			is_dp = true;
614			break;
615		case INTEL_OUTPUT_EDP:
616			is_edp = true;
617			break;
618		default:
619			drm_connector_list_iter_end(&conn_iter);
620			DRM_ERROR("invalid output type.\n");
621			return 0;
622		}
623
624		break;
625	}
626	drm_connector_list_iter_end(&conn_iter);
627
628	if (dev_priv->dplla_96mhz)
629		/* low-end sku, 96/100 mhz */
630		refclk = 96000;
631	else
632		/* high-end sku, 27/100 mhz */
633		refclk = 27000;
634	if (is_dp || is_edp) {
635		/*
636		 * Based on the spec the low-end SKU has only CRT/LVDS. So it is
637		 * unnecessary to consider it for DP/eDP.
638		 * On the high-end SKU, it will use the 27/100M reference clk
639		 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise
640		 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose
641		 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz.
642		 */
643		if (pipe == 0)
644			refclk = 27000;
645		else
646			refclk = 100000;
647	}
648
649	if (is_lvds && dev_priv->lvds_use_ssc) {
650		refclk = dev_priv->lvds_ssc_freq * 1000;
651		DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);
652	}
653
654	drm_mode_debug_printmodeline(adjusted_mode);
655
656	limit = gma_crtc->clock_funcs->limit(crtc, refclk);
657
658	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
659				 &clock);
660	if (!ok) {
661		DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
662			  adjusted_mode->clock, clock.dot);
663		return 0;
664	}
665
666	dpll = DPLL_VGA_MODE_DIS;
667
668	if (is_dp || is_edp) {
669		cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode);
670	} else {
671		REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0);
672		REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0);
673		REG_WRITE(PIPE_DP_LINK_M(pipe), 0);
674		REG_WRITE(PIPE_DP_LINK_N(pipe), 0);
675	}
676
677	dpll |= DPLL_SYNCLOCK_ENABLE;
678/*	if (is_lvds)
679		dpll |= DPLLB_MODE_LVDS;
680	else
681		dpll |= DPLLB_MODE_DAC_SERIAL; */
682	/* dpll |= (2 << 11); */
683
684	/* setup pipeconf */
685	pipeconf = REG_READ(map->conf);
686
687	pipeconf &= ~(PIPE_BPC_MASK);
688	if (is_edp) {
689		switch (dev_priv->edp.bpp) {
690		case 24:
691			pipeconf |= PIPE_8BPC;
692			break;
693		case 18:
694			pipeconf |= PIPE_6BPC;
695			break;
696		case 30:
697			pipeconf |= PIPE_10BPC;
698			break;
699		default:
700			pipeconf |= PIPE_8BPC;
701			break;
702		}
703	} else if (is_lvds) {
704		/* the BPC will be 6 if it is 18-bit LVDS panel */
705		if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
706			pipeconf |= PIPE_8BPC;
707		else
708			pipeconf |= PIPE_6BPC;
709	} else
710		pipeconf |= PIPE_8BPC;
711
712	/* Set up the display plane register */
713	dspcntr = DISPPLANE_GAMMA_ENABLE;
714
715	if (pipe == 0)
716		dspcntr |= DISPPLANE_SEL_PIPE_A;
717	else
718		dspcntr |= DISPPLANE_SEL_PIPE_B;
719
720	dspcntr |= DISPLAY_PLANE_ENABLE;
721	pipeconf |= PIPEACONF_ENABLE;
722
723	REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
724	REG_READ(map->dpll);
725
726	cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select);
727
728	udelay(150);
729
730
731	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
732	 * This is an exception to the general rule that mode_set doesn't turn
733	 * things on.
734	 */
735	if (is_lvds) {
736		u32 lvds = REG_READ(LVDS);
737
738		lvds |=
739		    LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
740		    LVDS_PIPEB_SELECT;
741		/* Set the B0-B3 data pairs corresponding to
742		 * whether we're going to
743		 * set the DPLLs for dual-channel mode or not.
744		 */
745		if (clock.p2 == 7)
746			lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
747		else
748			lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
749
750		/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
751		 * appropriately here, but we need to look more
752		 * thoroughly into how panels behave in the two modes.
753		 */
754
755		REG_WRITE(LVDS, lvds);
756		REG_READ(LVDS);
757	}
758
759	dpll |= DPLL_VCO_ENABLE;
760
761	/* Disable the panel fitter if it was on our pipe */
762	if (cdv_intel_panel_fitter_pipe(dev) == pipe)
763		REG_WRITE(PFIT_CONTROL, 0);
764
765	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
766	drm_mode_debug_printmodeline(mode);
767
768	REG_WRITE(map->dpll,
769		(REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
770	REG_READ(map->dpll);
771	/* Wait for the clocks to stabilize. */
772	udelay(150); /* 42 usec w/o calibration, 110 with.  rounded up. */
773
774	if (!(REG_READ(map->dpll) & DPLL_LOCK)) {
775		dev_err(dev->dev, "Failed to get DPLL lock\n");
776		return -EBUSY;
777	}
778
779	{
780		int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
781		REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
782	}
783
784	REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
785		  ((adjusted_mode->crtc_htotal - 1) << 16));
786	REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
787		  ((adjusted_mode->crtc_hblank_end - 1) << 16));
788	REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
789		  ((adjusted_mode->crtc_hsync_end - 1) << 16));
790	REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
791		  ((adjusted_mode->crtc_vtotal - 1) << 16));
792	REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
793		  ((adjusted_mode->crtc_vblank_end - 1) << 16));
794	REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
795		  ((adjusted_mode->crtc_vsync_end - 1) << 16));
796	/* pipesrc and dspsize control the size that is scaled from,
797	 * which should always be the user's requested size.
798	 */
799	REG_WRITE(map->size,
800		  ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
801	REG_WRITE(map->pos, 0);
802	REG_WRITE(map->src,
803		  ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
804	REG_WRITE(map->conf, pipeconf);
805	REG_READ(map->conf);
806
807	gma_wait_for_vblank(dev);
808
809	REG_WRITE(map->cntr, dspcntr);
810
811	/* Flush the plane changes */
812	{
813		const struct drm_crtc_helper_funcs *crtc_funcs =
814		    crtc->helper_private;
815		crtc_funcs->mode_set_base(crtc, x, y, old_fb);
816	}
817
818	gma_wait_for_vblank(dev);
819
820	return 0;
821}
822
823/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
824
825/* FIXME: why are we using this, should it be cdv_ in this tree ? */
826
827static void i8xx_clock(int refclk, struct gma_clock_t *clock)
828{
829	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
830	clock->p = clock->p1 * clock->p2;
831	clock->vco = refclk * clock->m / (clock->n + 2);
832	clock->dot = clock->vco / clock->p;
833}
834
835/* Returns the clock of the currently programmed mode of the given pipe. */
836static int cdv_intel_crtc_clock_get(struct drm_device *dev,
837				struct drm_crtc *crtc)
838{
839	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
840	struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
841	int pipe = gma_crtc->pipe;
842	const struct psb_offset *map = &dev_priv->regmap[pipe];
843	u32 dpll;
844	u32 fp;
845	struct gma_clock_t clock;
846	bool is_lvds;
847	struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
848
849	if (gma_power_begin(dev, false)) {
850		dpll = REG_READ(map->dpll);
851		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
852			fp = REG_READ(map->fp0);
853		else
854			fp = REG_READ(map->fp1);
855		is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
856		gma_power_end(dev);
857	} else {
858		dpll = p->dpll;
859		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
860			fp = p->fp0;
861		else
862			fp = p->fp1;
863
864		is_lvds = (pipe == 1) &&
865				(dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
866	}
867
868	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
869	clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
870	clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
871
872	if (is_lvds) {
873		clock.p1 =
874		    ffs((dpll &
875			 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
876			DPLL_FPA01_P1_POST_DIV_SHIFT);
877		if (clock.p1 == 0) {
878			clock.p1 = 4;
879			dev_err(dev->dev, "PLL %d\n", dpll);
880		}
881		clock.p2 = 14;
882
883		if ((dpll & PLL_REF_INPUT_MASK) ==
884		    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
885			/* XXX: might not be 66MHz */
886			i8xx_clock(66000, &clock);
887		} else
888			i8xx_clock(48000, &clock);
889	} else {
890		if (dpll & PLL_P1_DIVIDE_BY_TWO)
891			clock.p1 = 2;
892		else {
893			clock.p1 =
894			    ((dpll &
895			      DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
896			     DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
897		}
898		if (dpll & PLL_P2_DIVIDE_BY_4)
899			clock.p2 = 4;
900		else
901			clock.p2 = 2;
902
903		i8xx_clock(48000, &clock);
904	}
905
906	/* XXX: It would be nice to validate the clocks, but we can't reuse
907	 * i830PllIsValid() because it relies on the xf86_config connector
908	 * configuration being accurate, which it isn't necessarily.
909	 */
910
911	return clock.dot;
912}
913
914/** Returns the currently programmed mode of the given pipe. */
915struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
916					     struct drm_crtc *crtc)
917{
918	struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
919	int pipe = gma_crtc->pipe;
920	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
921	struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
922	const struct psb_offset *map = &dev_priv->regmap[pipe];
923	struct drm_display_mode *mode;
924	int htot;
925	int hsync;
926	int vtot;
927	int vsync;
928
929	if (gma_power_begin(dev, false)) {
930		htot = REG_READ(map->htotal);
931		hsync = REG_READ(map->hsync);
932		vtot = REG_READ(map->vtotal);
933		vsync = REG_READ(map->vsync);
934		gma_power_end(dev);
935	} else {
936		htot = p->htotal;
937		hsync = p->hsync;
938		vtot = p->vtotal;
939		vsync = p->vsync;
940	}
941
942	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
943	if (!mode)
944		return NULL;
945
946	mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
947	mode->hdisplay = (htot & 0xffff) + 1;
948	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
949	mode->hsync_start = (hsync & 0xffff) + 1;
950	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
951	mode->vdisplay = (vtot & 0xffff) + 1;
952	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
953	mode->vsync_start = (vsync & 0xffff) + 1;
954	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
955
956	drm_mode_set_name(mode);
957	drm_mode_set_crtcinfo(mode, 0);
958
959	return mode;
960}
961
962const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
963	.dpms = gma_crtc_dpms,
964	.mode_set = cdv_intel_crtc_mode_set,
965	.mode_set_base = gma_pipe_set_base,
966	.prepare = gma_crtc_prepare,
967	.commit = gma_crtc_commit,
968	.disable = gma_crtc_disable,
969};
970
971const struct gma_clock_funcs cdv_clock_funcs = {
972	.clock = cdv_intel_clock,
973	.limit = cdv_intel_limit,
974	.pll_is_valid = gma_pll_is_valid,
975};