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cdv_device.c
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linux-6.19.14/drivers/gpu/drm/gma500/cdv_device.c
1// SPDX-License-Identifier: GPL-2.0-only 2/************************************************************************** 3 * Copyright (c) 2011, Intel Corporation. 4 * All Rights Reserved. 5 * 6 **************************************************************************/ 7 8#include <linux/delay.h> 9 10#include <drm/drm.h> 11#include <drm/drm_crtc_helper.h> 12#include <drm/drm_print.h> 13 14#include "cdv_device.h" 15#include "gma_device.h" 16#include "intel_bios.h" 17#include "psb_drv.h" 18#include "psb_intel_reg.h" 19#include "psb_reg.h" 20 21#define VGA_SR_INDEX 0x3c4 22#define VGA_SR_DATA 0x3c5 23 24static void cdv_disable_vga(struct drm_device *dev) 25{ 26 u8 sr1; 27 u32 vga_reg; 28 29 vga_reg = VGACNTRL; 30 31 outb(1, VGA_SR_INDEX); 32 sr1 = inb(VGA_SR_DATA); 33 outb(sr1 | 1<<5, VGA_SR_DATA); 34 udelay(300); 35 36 REG_WRITE(vga_reg, VGA_DISP_DISABLE); 37 REG_READ(vga_reg); 38} 39 40static int cdv_output_init(struct drm_device *dev) 41{ 42 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 43 44 drm_mode_create_scaling_mode_property(dev); 45 46 cdv_disable_vga(dev); 47 48 cdv_intel_crt_init(dev, &dev_priv->mode_dev); 49 cdv_intel_lvds_init(dev, &dev_priv->mode_dev); 50 51 /* These bits indicate HDMI not SDVO on CDV */ 52 if (REG_READ(SDVOB) & SDVO_DETECTED) { 53 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB); 54 if (REG_READ(DP_B) & DP_DETECTED) 55 cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_B); 56 } 57 58 if (REG_READ(SDVOC) & SDVO_DETECTED) { 59 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC); 60 if (REG_READ(DP_C) & DP_DETECTED) 61 cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_C); 62 } 63 return 0; 64} 65 66/* 67 * Cedartrail Backlght Interfaces 68 */ 69 70static int cdv_backlight_combination_mode(struct drm_device *dev) 71{ 72 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; 73} 74 75static u32 cdv_get_max_backlight(struct drm_device *dev) 76{ 77 u32 max = REG_READ(BLC_PWM_CTL); 78 79 if (max == 0) { 80 DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n"); 81 /* i915 does this, I believe which means that we should not 82 * smash PWM control as firmware will take control of it. */ 83 return 1; 84 } 85 86 max >>= 16; 87 if (cdv_backlight_combination_mode(dev)) 88 max *= 0xff; 89 return max; 90} 91 92static int cdv_get_brightness(struct drm_device *dev) 93{ 94 struct pci_dev *pdev = to_pci_dev(dev->dev); 95 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; 96 97 if (cdv_backlight_combination_mode(dev)) { 98 u8 lbpc; 99 100 val &= ~1; 101 pci_read_config_byte(pdev, 0xF4, &lbpc); 102 val *= lbpc; 103 } 104 return (val * 100)/cdv_get_max_backlight(dev); 105} 106 107static void cdv_set_brightness(struct drm_device *dev, int level) 108{ 109 struct pci_dev *pdev = to_pci_dev(dev->dev); 110 u32 blc_pwm_ctl; 111 112 level *= cdv_get_max_backlight(dev); 113 level /= 100; 114 115 if (cdv_backlight_combination_mode(dev)) { 116 u32 max = cdv_get_max_backlight(dev); 117 u8 lbpc; 118 119 lbpc = level * 0xfe / max + 1; 120 level /= lbpc; 121 122 pci_write_config_byte(pdev, 0xF4, lbpc); 123 } 124 125 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; 126 REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | 127 (level << BACKLIGHT_DUTY_CYCLE_SHIFT))); 128} 129 130static int cdv_backlight_init(struct drm_device *dev) 131{ 132 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 133 134 dev_priv->backlight_level = cdv_get_brightness(dev); 135 cdv_set_brightness(dev, dev_priv->backlight_level); 136 137 return 0; 138} 139 140/* 141 * Provide the Cedarview specific chip logic and low level methods 142 * for power management 143 * 144 * FIXME: we need to implement the apm/ospm base management bits 145 * for this and the MID devices. 146 */ 147 148static inline u32 CDV_MSG_READ32(int domain, uint port, uint offset) 149{ 150 int mcr = (0x10<<24) | (port << 16) | (offset << 8); 151 uint32_t ret_val = 0; 152 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 153 pci_write_config_dword(pci_root, 0xD0, mcr); 154 pci_read_config_dword(pci_root, 0xD4, &ret_val); 155 pci_dev_put(pci_root); 156 return ret_val; 157} 158 159static inline void CDV_MSG_WRITE32(int domain, uint port, uint offset, 160 u32 value) 161{ 162 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; 163 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 164 pci_write_config_dword(pci_root, 0xD4, value); 165 pci_write_config_dword(pci_root, 0xD0, mcr); 166 pci_dev_put(pci_root); 167} 168 169#define PSB_PM_SSC 0x20 170#define PSB_PM_SSS 0x30 171#define PSB_PWRGT_GFX_ON 0x02 172#define PSB_PWRGT_GFX_OFF 0x01 173#define PSB_PWRGT_GFX_D0 0x00 174#define PSB_PWRGT_GFX_D3 0x03 175 176static void cdv_init_pm(struct drm_device *dev) 177{ 178 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 179 struct pci_dev *pdev = to_pci_dev(dev->dev); 180 u32 pwr_cnt; 181 int domain = pci_domain_nr(pdev->bus); 182 int i; 183 184 dev_priv->apm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT, 185 PSB_APMBA) & 0xFFFF; 186 dev_priv->ospm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT, 187 PSB_OSPMBA) & 0xFFFF; 188 189 /* Power status */ 190 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 191 192 /* Enable the GPU */ 193 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 194 pwr_cnt |= PSB_PWRGT_GFX_ON; 195 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 196 197 /* Wait for the GPU power */ 198 for (i = 0; i < 5; i++) { 199 u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 200 if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0) 201 return; 202 udelay(10); 203 } 204 dev_err(dev->dev, "GPU: power management timed out.\n"); 205} 206 207static void cdv_errata(struct drm_device *dev) 208{ 209 struct pci_dev *pdev = to_pci_dev(dev->dev); 210 211 /* Disable bonus launch. 212 * CPU and GPU competes for memory and display misses updates and 213 * flickers. Worst with dual core, dual displays. 214 * 215 * Fixes were done to Win 7 gfx driver to disable a feature called 216 * Bonus Launch to work around the issue, by degrading 217 * performance. 218 */ 219 CDV_MSG_WRITE32(pci_domain_nr(pdev->bus), 3, 0x30, 0x08027108); 220} 221 222/** 223 * cdv_save_display_registers - save registers lost on suspend 224 * @dev: our DRM device 225 * 226 * Save the state we need in order to be able to restore the interface 227 * upon resume from suspend 228 */ 229static int cdv_save_display_registers(struct drm_device *dev) 230{ 231 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 232 struct pci_dev *pdev = to_pci_dev(dev->dev); 233 struct psb_save_area *regs = &dev_priv->regs; 234 struct drm_connector_list_iter conn_iter; 235 struct drm_connector *connector; 236 237 dev_dbg(dev->dev, "Saving GPU registers.\n"); 238 239 pci_read_config_byte(pdev, 0xF4, ®s->cdv.saveLBB); 240 241 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); 242 regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D); 243 244 regs->cdv.saveDSPARB = REG_READ(DSPARB); 245 regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1); 246 regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2); 247 regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3); 248 regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4); 249 regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5); 250 regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6); 251 252 regs->cdv.saveADPA = REG_READ(ADPA); 253 254 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); 255 regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS); 256 regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); 257 regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2); 258 regs->cdv.saveLVDS = REG_READ(LVDS); 259 260 regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL); 261 262 regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS); 263 regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS); 264 regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE); 265 266 regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL); 267 268 regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R); 269 regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R); 270 271 drm_connector_list_iter_begin(dev, &conn_iter); 272 drm_for_each_connector_iter(connector, &conn_iter) 273 connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF); 274 drm_connector_list_iter_end(&conn_iter); 275 276 return 0; 277} 278 279/** 280 * cdv_restore_display_registers - restore lost register state 281 * @dev: our DRM device 282 * 283 * Restore register state that was lost during suspend and resume. 284 * 285 * FIXME: review 286 */ 287static int cdv_restore_display_registers(struct drm_device *dev) 288{ 289 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 290 struct pci_dev *pdev = to_pci_dev(dev->dev); 291 struct psb_save_area *regs = &dev_priv->regs; 292 struct drm_connector_list_iter conn_iter; 293 struct drm_connector *connector; 294 u32 temp; 295 296 pci_write_config_byte(pdev, 0xF4, regs->cdv.saveLBB); 297 298 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); 299 REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D); 300 301 /* BIOS does below anyway */ 302 REG_WRITE(DPIO_CFG, 0); 303 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); 304 305 temp = REG_READ(DPLL_A); 306 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { 307 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); 308 REG_READ(DPLL_A); 309 } 310 311 temp = REG_READ(DPLL_B); 312 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { 313 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); 314 REG_READ(DPLL_B); 315 } 316 317 udelay(500); 318 319 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); 320 REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]); 321 REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]); 322 REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]); 323 REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]); 324 REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]); 325 326 REG_WRITE(DSPARB, regs->cdv.saveDSPARB); 327 REG_WRITE(ADPA, regs->cdv.saveADPA); 328 329 REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2); 330 REG_WRITE(LVDS, regs->cdv.saveLVDS); 331 REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL); 332 REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS); 333 REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL); 334 REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS); 335 REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS); 336 REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE); 337 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL); 338 339 REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL); 340 341 REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER); 342 REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR); 343 344 /* Fix arbitration bug */ 345 cdv_errata(dev); 346 347 drm_mode_config_reset(dev); 348 349 drm_connector_list_iter_begin(dev, &conn_iter); 350 drm_for_each_connector_iter(connector, &conn_iter) 351 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); 352 drm_connector_list_iter_end(&conn_iter); 353 354 /* Resume the modeset for every activated CRTC */ 355 drm_helper_resume_force_mode(dev); 356 return 0; 357} 358 359static int cdv_power_down(struct drm_device *dev) 360{ 361 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 362 u32 pwr_cnt, pwr_mask, pwr_sts; 363 int tries = 5; 364 365 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 366 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 367 pwr_cnt |= PSB_PWRGT_GFX_OFF; 368 pwr_mask = PSB_PWRGT_GFX_MASK; 369 370 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 371 372 while (tries--) { 373 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 374 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3) 375 return 0; 376 udelay(10); 377 } 378 return 0; 379} 380 381static int cdv_power_up(struct drm_device *dev) 382{ 383 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 384 u32 pwr_cnt, pwr_mask, pwr_sts; 385 int tries = 5; 386 387 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 388 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 389 pwr_cnt |= PSB_PWRGT_GFX_ON; 390 pwr_mask = PSB_PWRGT_GFX_MASK; 391 392 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 393 394 while (tries--) { 395 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 396 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0) 397 return 0; 398 udelay(10); 399 } 400 return 0; 401} 402 403static void cdv_hotplug_work_func(struct work_struct *work) 404{ 405 struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private, 406 hotplug_work); 407 struct drm_device *dev = &dev_priv->dev; 408 409 /* Just fire off a uevent and let userspace tell us what to do */ 410 drm_helper_hpd_irq_event(dev); 411} 412 413/* The core driver has received a hotplug IRQ. We are in IRQ context 414 so extract the needed information and kick off queued processing */ 415 416static int cdv_hotplug_event(struct drm_device *dev) 417{ 418 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 419 schedule_work(&dev_priv->hotplug_work); 420 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 421 return 1; 422} 423 424static void cdv_hotplug_enable(struct drm_device *dev, bool on) 425{ 426 if (on) { 427 u32 hotplug = REG_READ(PORT_HOTPLUG_EN); 428 hotplug |= HDMIB_HOTPLUG_INT_EN | HDMIC_HOTPLUG_INT_EN | 429 HDMID_HOTPLUG_INT_EN | CRT_HOTPLUG_INT_EN; 430 REG_WRITE(PORT_HOTPLUG_EN, hotplug); 431 } else { 432 REG_WRITE(PORT_HOTPLUG_EN, 0); 433 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 434 } 435} 436 437static const char *force_audio_names[] = { 438 "off", 439 "auto", 440 "on", 441}; 442 443void cdv_intel_attach_force_audio_property(struct drm_connector *connector) 444{ 445 struct drm_device *dev = connector->dev; 446 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 447 struct drm_property *prop; 448 int i; 449 450 prop = dev_priv->force_audio_property; 451 if (prop == NULL) { 452 prop = drm_property_create(dev, DRM_MODE_PROP_ENUM, 453 "audio", 454 ARRAY_SIZE(force_audio_names)); 455 if (prop == NULL) 456 return; 457 458 for (i = 0; i < ARRAY_SIZE(force_audio_names); i++) 459 drm_property_add_enum(prop, i-1, force_audio_names[i]); 460 461 dev_priv->force_audio_property = prop; 462 } 463 drm_object_attach_property(&connector->base, prop, 0); 464} 465 466 467static const char *broadcast_rgb_names[] = { 468 "Full", 469 "Limited 16:235", 470}; 471 472void cdv_intel_attach_broadcast_rgb_property(struct drm_connector *connector) 473{ 474 struct drm_device *dev = connector->dev; 475 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 476 struct drm_property *prop; 477 int i; 478 479 prop = dev_priv->broadcast_rgb_property; 480 if (prop == NULL) { 481 prop = drm_property_create(dev, DRM_MODE_PROP_ENUM, 482 "Broadcast RGB", 483 ARRAY_SIZE(broadcast_rgb_names)); 484 if (prop == NULL) 485 return; 486 487 for (i = 0; i < ARRAY_SIZE(broadcast_rgb_names); i++) 488 drm_property_add_enum(prop, i, broadcast_rgb_names[i]); 489 490 dev_priv->broadcast_rgb_property = prop; 491 } 492 493 drm_object_attach_property(&connector->base, prop, 0); 494} 495 496/* Cedarview */ 497static const struct psb_offset cdv_regmap[2] = { 498 { 499 .fp0 = FPA0, 500 .fp1 = FPA1, 501 .cntr = DSPACNTR, 502 .conf = PIPEACONF, 503 .src = PIPEASRC, 504 .dpll = DPLL_A, 505 .dpll_md = DPLL_A_MD, 506 .htotal = HTOTAL_A, 507 .hblank = HBLANK_A, 508 .hsync = HSYNC_A, 509 .vtotal = VTOTAL_A, 510 .vblank = VBLANK_A, 511 .vsync = VSYNC_A, 512 .stride = DSPASTRIDE, 513 .size = DSPASIZE, 514 .pos = DSPAPOS, 515 .base = DSPABASE, 516 .surf = DSPASURF, 517 .addr = DSPABASE, 518 .status = PIPEASTAT, 519 .linoff = DSPALINOFF, 520 .tileoff = DSPATILEOFF, 521 .palette = PALETTE_A, 522 }, 523 { 524 .fp0 = FPB0, 525 .fp1 = FPB1, 526 .cntr = DSPBCNTR, 527 .conf = PIPEBCONF, 528 .src = PIPEBSRC, 529 .dpll = DPLL_B, 530 .dpll_md = DPLL_B_MD, 531 .htotal = HTOTAL_B, 532 .hblank = HBLANK_B, 533 .hsync = HSYNC_B, 534 .vtotal = VTOTAL_B, 535 .vblank = VBLANK_B, 536 .vsync = VSYNC_B, 537 .stride = DSPBSTRIDE, 538 .size = DSPBSIZE, 539 .pos = DSPBPOS, 540 .base = DSPBBASE, 541 .surf = DSPBSURF, 542 .addr = DSPBBASE, 543 .status = PIPEBSTAT, 544 .linoff = DSPBLINOFF, 545 .tileoff = DSPBTILEOFF, 546 .palette = PALETTE_B, 547 } 548}; 549 550static int cdv_chip_setup(struct drm_device *dev) 551{ 552 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 553 INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func); 554 555 dev_priv->use_msi = true; 556 dev_priv->regmap = cdv_regmap; 557 gma_get_core_freq(dev); 558 psb_intel_opregion_init(dev); 559 psb_intel_init_bios(dev); 560 cdv_hotplug_enable(dev, false); 561 return 0; 562} 563 564/* CDV is much like Poulsbo but has MID like SGX offsets and PM */ 565 566const struct psb_ops cdv_chip_ops = { 567 .name = "GMA3600/3650", 568 .pipes = 2, 569 .crtcs = 2, 570 .hdmi_mask = (1 << 0) | (1 << 1), 571 .lvds_mask = (1 << 1), 572 .sdvo_mask = (1 << 0), 573 .cursor_needs_phys = 0, 574 .sgx_offset = MRST_SGX_OFFSET, 575 .chip_setup = cdv_chip_setup, 576 .errata = cdv_errata, 577 578 .crtc_helper = &cdv_intel_helper_funcs, 579 .clock_funcs = &cdv_clock_funcs, 580 581 .output_init = cdv_output_init, 582 .hotplug = cdv_hotplug_event, 583 .hotplug_enable = cdv_hotplug_enable, 584 585 .backlight_init = cdv_backlight_init, 586 .backlight_get = cdv_get_brightness, 587 .backlight_set = cdv_set_brightness, 588 .backlight_name = "psb-bl", 589 590 .init_pm = cdv_init_pm, 591 .save_regs = cdv_save_display_registers, 592 .restore_regs = cdv_restore_display_registers, 593 .save_crtc = gma_crtc_save, 594 .restore_crtc = gma_crtc_restore, 595 .power_down = cdv_power_down, 596 .power_up = cdv_power_up, 597 .update_wm = cdv_update_wm, 598 .disable_sr = cdv_disable_sr, 599};
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