regs-decon7.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
  4 * Author: Ajay Kumar <ajaykumar.rs@samsung.com>
  5 */
  6
  7#ifndef EXYNOS_REGS_DECON7_H
  8#define EXYNOS_REGS_DECON7_H
  9
 10/* VIDCON0 */
 11#define VIDCON0					0x00
 12
 13#define VIDCON0_SWRESET				(1 << 28)
 14#define VIDCON0_DECON_STOP_STATUS		(1 << 2)
 15#define VIDCON0_ENVID				(1 << 1)
 16#define VIDCON0_ENVID_F				(1 << 0)
 17
 18/* VIDOUTCON0 */
 19#define VIDOUTCON0				0x4
 20
 21#define VIDOUTCON0_DUAL_MASK			(0x3 << 24)
 22#define VIDOUTCON0_DUAL_ON			(0x3 << 24)
 23#define VIDOUTCON0_DISP_IF_1_ON			(0x2 << 24)
 24#define VIDOUTCON0_DISP_IF_0_ON			(0x1 << 24)
 25#define VIDOUTCON0_DUAL_OFF			(0x0 << 24)
 26#define VIDOUTCON0_IF_SHIFT			23
 27#define VIDOUTCON0_IF_MASK			(0x1 << 23)
 28#define VIDOUTCON0_RGBIF			(0x0 << 23)
 29#define VIDOUTCON0_I80IF			(0x1 << 23)
 30
 31/* VIDCON3 */
 32#define VIDCON3					0x8
 33
 34/* VIDCON4 */
 35#define VIDCON4					0xC
 36#define VIDCON4_FIFOCNT_START_EN		(1 << 0)
 37
 38/* VCLKCON0 */
 39#define VCLKCON0				0x10
 40#define VCLKCON0_CLKVALUP			(1 << 8)
 41#define VCLKCON0_VCLKFREE			(1 << 0)
 42
 43/* VCLKCON */
 44#define VCLKCON1				0x14
 45#define VCLKCON1_CLKVAL_NUM_VCLK(val)		(((val) & 0xff) << 0)
 46#define VCLKCON2				0x18
 47
 48/* SHADOWCON */
 49#define SHADOWCON				0x30
 50
 51#define SHADOWCON_WINx_PROTECT(_shf, _win)	(1 << ((_shf) + (_win)))
 52
 53/* WINCONx */
 54#define WINCON(_win)				(0x50 + ((_win) * 4))
 55
 56#define WINCONx_BUFSTATUS			(0x3 << 30)
 57#define WINCONx_BUFSEL_MASK			(0x3 << 28)
 58#define WINCONx_BUFSEL_SHIFT			28
 59#define WINCONx_TRIPLE_BUF_MODE			(0x1 << 18)
 60#define WINCONx_DOUBLE_BUF_MODE			(0x0 << 18)
 61#define WINCONx_BURSTLEN_16WORD(_shf)		(0x0 << (_shf))
 62#define WINCONx_BURSTLEN_8WORD(_shf)		(0x1 << (_shf))
 63#define WINCONx_BURSTLEN_MASK(_shf)		(0x1 << (_shf))
 64#define WINCONx_BLD_PLANE			(0 << 8)
 65#define WINCONx_BLD_PIX				(1 << 8)
 66#define WINCONx_ALPHA_MUL			(1 << 7)
 67
 68#define WINCONx_BPPMODE_MASK			(0xf << 2)
 69#define WINCONx_BPPMODE_SHIFT			2
 70#define WINCONx_BPPMODE_16BPP_565		(0x8 << 2)
 71#define WINCONx_BPPMODE_24BPP_BGRx		(0x7 << 2)
 72#define WINCONx_BPPMODE_24BPP_RGBx		(0x6 << 2)
 73#define WINCONx_BPPMODE_24BPP_xBGR		(0x5 << 2)
 74#define WINCONx_BPPMODE_24BPP_xRGB		(0x4 << 2)
 75#define WINCONx_BPPMODE_32BPP_BGRA		(0x3 << 2)
 76#define WINCONx_BPPMODE_32BPP_RGBA		(0x2 << 2)
 77#define WINCONx_BPPMODE_32BPP_ABGR		(0x1 << 2)
 78#define WINCONx_BPPMODE_32BPP_ARGB		(0x0 << 2)
 79#define WINCONx_ALPHA_SEL			(1 << 1)
 80#define WINCONx_ENWIN				(1 << 0)
 81
 82#define WINCON1_ALPHA_MUL_F			(1 << 7)
 83#define WINCON2_ALPHA_MUL_F			(1 << 7)
 84#define WINCON3_ALPHA_MUL_F			(1 << 7)
 85#define WINCON4_ALPHA_MUL_F			(1 << 7)
 86
 87/*  VIDOSDxH: The height for the OSD image(READ ONLY)*/
 88#define VIDOSD_H(_x)				(0x80 + ((_x) * 4))
 89
 90/* Frame buffer start addresses: VIDWxxADD0n */
 91#define VIDW_BUF_START(_base, _win)		((_base) + ((_win) * 0x10))
 92#define VIDW_BUF_START1(_base, _win)		((_base) + ((_win) * 0x10))
 93#define VIDW_BUF_START2(_base, _win)		((_base) + ((_win) * 0x10))
 94
 95#define VIDW_WHOLE_X(_win)			(0x0130 + ((_win) * 8))
 96#define VIDW_WHOLE_Y(_win)			(0x0134 + ((_win) * 8))
 97#define VIDW_OFFSET_X(_win)			(0x0170 + ((_win) * 8))
 98#define VIDW_OFFSET_Y(_win)			(0x0174 + ((_win) * 8))
 99#define VIDW_BLKOFFSET(_win)			(0x01B0 + ((_win) * 4))
100#define VIDW_BLKSIZE(win)			(0x0200 + ((_win) * 4))
101
102/* Interrupt controls register */
103#define VIDINTCON2				0x228
104
105#define VIDINTCON1_INTEXTRA1_EN			(1 << 1)
106#define VIDINTCON1_INTEXTRA0_EN			(1 << 0)
107
108/* Interrupt controls and status register */
109#define VIDINTCON3				0x22C
110
111#define VIDINTCON1_INTEXTRA1_PEND		(1 << 1)
112#define VIDINTCON1_INTEXTRA0_PEND		(1 << 0)
113
114/* VIDOSDxA ~ VIDOSDxE */
115#define VIDOSD_BASE				0x230
116
117#define OSD_STRIDE				0x20
118
119#define VIDOSD_A(_win)				(VIDOSD_BASE + \
120						((_win) * OSD_STRIDE) + 0x00)
121#define VIDOSD_B(_win)				(VIDOSD_BASE + \
122						((_win) * OSD_STRIDE) + 0x04)
123#define VIDOSD_C(_win)				(VIDOSD_BASE + \
124						((_win) * OSD_STRIDE) + 0x08)
125#define VIDOSD_D(_win)				(VIDOSD_BASE + \
126						((_win) * OSD_STRIDE) + 0x0C)
127#define VIDOSD_E(_win)				(VIDOSD_BASE + \
128						((_win) * OSD_STRIDE) + 0x10)
129
130#define VIDOSDxA_TOPLEFT_X_MASK			(0x1fff << 13)
131#define VIDOSDxA_TOPLEFT_X_SHIFT		13
132#define VIDOSDxA_TOPLEFT_X_LIMIT		0x1fff
133#define VIDOSDxA_TOPLEFT_X(_x)			(((_x) & 0x1fff) << 13)
134
135#define VIDOSDxA_TOPLEFT_Y_MASK			(0x1fff << 0)
136#define VIDOSDxA_TOPLEFT_Y_SHIFT		0
137#define VIDOSDxA_TOPLEFT_Y_LIMIT		0x1fff
138#define VIDOSDxA_TOPLEFT_Y(_x)			(((_x) & 0x1fff) << 0)
139
140#define VIDOSDxB_BOTRIGHT_X_MASK		(0x1fff << 13)
141#define VIDOSDxB_BOTRIGHT_X_SHIFT		13
142#define VIDOSDxB_BOTRIGHT_X_LIMIT		0x1fff
143#define VIDOSDxB_BOTRIGHT_X(_x)			(((_x) & 0x1fff) << 13)
144
145#define VIDOSDxB_BOTRIGHT_Y_MASK		(0x1fff << 0)
146#define VIDOSDxB_BOTRIGHT_Y_SHIFT		0
147#define VIDOSDxB_BOTRIGHT_Y_LIMIT		0x1fff
148#define VIDOSDxB_BOTRIGHT_Y(_x)			(((_x) & 0x1fff) << 0)
149
150#define VIDOSDxC_ALPHA0_R_F(_x)			(((_x) & 0xFF) << 16)
151#define VIDOSDxC_ALPHA0_G_F(_x)			(((_x) & 0xFF) << 8)
152#define VIDOSDxC_ALPHA0_B_F(_x)			(((_x) & 0xFF) << 0)
153
154#define VIDOSDxD_ALPHA1_R_F(_x)			(((_x) & 0xFF) << 16)
155#define VIDOSDxD_ALPHA1_G_F(_x)			(((_x) & 0xFF) << 8)
156#define VIDOSDxD_ALPHA1_B_F(_x)			(((_x) & 0xFF) >> 0)
157
158/* Window MAP (Color map) */
159#define WINxMAP(_win)				(0x340 + ((_win) * 4))
160
161#define WINxMAP_MAP				(1 << 24)
162#define WINxMAP_MAP_COLOUR_MASK			(0xffffff << 0)
163#define WINxMAP_MAP_COLOUR_SHIFT		0
164#define WINxMAP_MAP_COLOUR_LIMIT		0xffffff
165#define WINxMAP_MAP_COLOUR(_x)			((_x) << 0)
166
167/* Window colour-key control registers */
168#define WKEYCON					0x370
169
170#define WKEYCON0				0x00
171#define WKEYCON1				0x04
172#define WxKEYCON0_KEYBL_EN			(1 << 26)
173#define WxKEYCON0_KEYEN_F			(1 << 25)
174#define WxKEYCON0_DIRCON			(1 << 24)
175#define WxKEYCON0_COMPKEY_MASK			(0xffffff << 0)
176#define WxKEYCON0_COMPKEY_SHIFT			0
177#define WxKEYCON0_COMPKEY_LIMIT			0xffffff
178#define WxKEYCON0_COMPKEY(_x)			((_x) << 0)
179#define WxKEYCON1_COLVAL_MASK			(0xffffff << 0)
180#define WxKEYCON1_COLVAL_SHIFT			0
181#define WxKEYCON1_COLVAL_LIMIT			0xffffff
182#define WxKEYCON1_COLVAL(_x)			((_x) << 0)
183
184/* color key control register for hardware window 1 ~ 4. */
185#define WKEYCON0_BASE(x)		((WKEYCON + WKEYCON0) + ((x - 1) * 8))
186/* color key value register for hardware window 1 ~ 4. */
187#define WKEYCON1_BASE(x)		((WKEYCON + WKEYCON1) + ((x - 1) * 8))
188
189/* Window KEY Alpha value */
190#define WxKEYALPHA(_win)			(0x3A0 + (((_win) - 1) * 0x4))
191
192#define Wx_KEYALPHA_R_F_SHIFT			16
193#define Wx_KEYALPHA_G_F_SHIFT			8
194#define Wx_KEYALPHA_B_F_SHIFT			0
195
196/* Blending equation */
197#define BLENDE(_win)				(0x03C0 + ((_win) * 4))
198#define BLENDE_COEF_ZERO			0x0
199#define BLENDE_COEF_ONE				0x1
200#define BLENDE_COEF_ALPHA_A			0x2
201#define BLENDE_COEF_ONE_MINUS_ALPHA_A		0x3
202#define BLENDE_COEF_ALPHA_B			0x4
203#define BLENDE_COEF_ONE_MINUS_ALPHA_B		0x5
204#define BLENDE_COEF_ALPHA0			0x6
205#define BLENDE_COEF_A				0xA
206#define BLENDE_COEF_ONE_MINUS_A			0xB
207#define BLENDE_COEF_B				0xC
208#define BLENDE_COEF_ONE_MINUS_B			0xD
209#define BLENDE_Q_FUNC(_v)			((_v) << 18)
210#define BLENDE_P_FUNC(_v)			((_v) << 12)
211#define BLENDE_B_FUNC(_v)			((_v) << 6)
212#define BLENDE_A_FUNC(_v)			((_v) << 0)
213
214/* Blending equation control */
215#define BLENDCON				0x3D8
216#define BLENDCON_NEW_MASK			(1 << 0)
217#define BLENDCON_NEW_8BIT_ALPHA_VALUE		(1 << 0)
218#define BLENDCON_NEW_4BIT_ALPHA_VALUE		(0 << 0)
219
220/* Interrupt control register */
221#define VIDINTCON0				0x500
222
223#define VIDINTCON0_WAKEUP_MASK			(0x3f << 26)
224#define VIDINTCON0_INTEXTRAEN			(1 << 21)
225
226#define VIDINTCON0_FRAMESEL0_SHIFT		15
227#define VIDINTCON0_FRAMESEL0_MASK		(0x3 << 15)
228#define VIDINTCON0_FRAMESEL0_BACKPORCH		(0x0 << 15)
229#define VIDINTCON0_FRAMESEL0_VSYNC		(0x1 << 15)
230#define VIDINTCON0_FRAMESEL0_ACTIVE		(0x2 << 15)
231#define VIDINTCON0_FRAMESEL0_FRONTPORCH		(0x3 << 15)
232
233#define VIDINTCON0_INT_FRAME			(1 << 11)
234
235#define VIDINTCON0_FIFOLEVEL_MASK		(0x7 << 3)
236#define VIDINTCON0_FIFOLEVEL_SHIFT		3
237#define VIDINTCON0_FIFOLEVEL_EMPTY		(0x0 << 3)
238#define VIDINTCON0_FIFOLEVEL_TO25PC		(0x1 << 3)
239#define VIDINTCON0_FIFOLEVEL_TO50PC		(0x2 << 3)
240#define VIDINTCON0_FIFOLEVEL_FULL		(0x4 << 3)
241
242#define VIDINTCON0_FIFOSEL_MAIN_EN		(1 << 1)
243#define VIDINTCON0_INT_FIFO			(1 << 1)
244
245#define VIDINTCON0_INT_ENABLE			(1 << 0)
246
247/* Interrupt controls and status register */
248#define VIDINTCON1				0x504
249
250#define VIDINTCON1_INT_EXTRA			(1 << 3)
251#define VIDINTCON1_INT_I80			(1 << 2)
252#define VIDINTCON1_INT_FRAME			(1 << 1)
253#define VIDINTCON1_INT_FIFO			(1 << 0)
254
255/* VIDCON1 */
256#define VIDCON1(_x)				(0x0600 + ((_x) * 0x50))
257#define VIDCON1_LINECNT_GET(_v)			(((_v) >> 17) & 0x1fff)
258#define VIDCON1_VCLK_MASK			(0x3 << 9)
259#define VIDCON1_VCLK_HOLD			(0x0 << 9)
260#define VIDCON1_VCLK_RUN			(0x1 << 9)
261#define VIDCON1_VCLK_RUN_VDEN_DISABLE		(0x3 << 9)
262#define VIDCON1_RGB_ORDER_O_MASK		(0x7 << 4)
263#define VIDCON1_RGB_ORDER_O_RGB			(0x0 << 4)
264#define VIDCON1_RGB_ORDER_O_GBR			(0x1 << 4)
265#define VIDCON1_RGB_ORDER_O_BRG			(0x2 << 4)
266#define VIDCON1_RGB_ORDER_O_BGR			(0x4 << 4)
267#define VIDCON1_RGB_ORDER_O_RBG			(0x5 << 4)
268#define VIDCON1_RGB_ORDER_O_GRB			(0x6 << 4)
269
270/* VIDTCON0 */
271#define VIDTCON0				0x610
272
273#define VIDTCON0_VBPD_MASK			(0xffff << 16)
274#define VIDTCON0_VBPD_SHIFT			16
275#define VIDTCON0_VBPD_LIMIT			0xffff
276#define VIDTCON0_VBPD(_x)			((_x) << 16)
277
278#define VIDTCON0_VFPD_MASK			(0xffff << 0)
279#define VIDTCON0_VFPD_SHIFT			0
280#define VIDTCON0_VFPD_LIMIT			0xffff
281#define VIDTCON0_VFPD(_x)			((_x) << 0)
282
283/* VIDTCON1 */
284#define VIDTCON1				0x614
285
286#define VIDTCON1_VSPW_MASK			(0xffff << 16)
287#define VIDTCON1_VSPW_SHIFT			16
288#define VIDTCON1_VSPW_LIMIT			0xffff
289#define VIDTCON1_VSPW(_x)			((_x) << 16)
290
291/* VIDTCON2 */
292#define VIDTCON2				0x618
293
294#define VIDTCON2_HBPD_MASK			(0xffff << 16)
295#define VIDTCON2_HBPD_SHIFT			16
296#define VIDTCON2_HBPD_LIMIT			0xffff
297#define VIDTCON2_HBPD(_x)			((_x) << 16)
298
299#define VIDTCON2_HFPD_MASK			(0xffff << 0)
300#define VIDTCON2_HFPD_SHIFT			0
301#define VIDTCON2_HFPD_LIMIT			0xffff
302#define VIDTCON2_HFPD(_x)			((_x) << 0)
303
304/* VIDTCON3 */
305#define VIDTCON3				0x61C
306
307#define VIDTCON3_HSPW_MASK			(0xffff << 16)
308#define VIDTCON3_HSPW_SHIFT			16
309#define VIDTCON3_HSPW_LIMIT			0xffff
310#define VIDTCON3_HSPW(_x)			((_x) << 16)
311
312/* VIDTCON4 */
313#define VIDTCON4				0x620
314
315#define VIDTCON4_LINEVAL_MASK			(0xfff << 16)
316#define VIDTCON4_LINEVAL_SHIFT			16
317#define VIDTCON4_LINEVAL_LIMIT			0xfff
318#define VIDTCON4_LINEVAL(_x)			(((_x) & 0xfff) << 16)
319
320#define VIDTCON4_HOZVAL_MASK			(0xfff << 0)
321#define VIDTCON4_HOZVAL_SHIFT			0
322#define VIDTCON4_HOZVAL_LIMIT			0xfff
323#define VIDTCON4_HOZVAL(_x)			(((_x) & 0xfff) << 0)
324
325/* LINECNT OP THRSHOLD*/
326#define LINECNT_OP_THRESHOLD			0x630
327
328/* CRCCTRL */
329#define CRCCTRL					0x6C8
330#define CRCCTRL_CRCCLKEN			(0x1 << 2)
331#define CRCCTRL_CRCSTART_F			(0x1 << 1)
332#define CRCCTRL_CRCEN				(0x1 << 0)
333
334/* DECON_CMU */
335#define DECON_CMU				0x704
336
337#define DECON_CMU_ALL_CLKGATE_ENABLE		0x3
338#define DECON_CMU_SE_CLKGATE_ENABLE		(0x1 << 2)
339#define DECON_CMU_SFR_CLKGATE_ENABLE		(0x1 << 1)
340#define DECON_CMU_MEM_CLKGATE_ENABLE		(0x1 << 0)
341
342/* DECON_UPDATE */
343#define DECON_UPDATE				0x710
344
345#define DECON_UPDATE_SLAVE_SYNC			(1 << 4)
346#define DECON_UPDATE_STANDALONE_F		(1 << 0)
347
348#endif /* EXYNOS_REGS_DECON7_H */