exynos7_drm_decon.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/* drivers/gpu/drm/exynos/exynos7_drm_decon.c
  3 *
  4 * Copyright (C) 2014 Samsung Electronics Co.Ltd
  5 * Authors:
  6 *	Akshu Agarwal <akshua@gmail.com>
  7 *	Ajay Kumar <ajaykumar.rs@samsung.com>
  8 */
  9
 10#include <linux/clk.h>
 11#include <linux/component.h>
 12#include <linux/kernel.h>
 13#include <linux/of.h>
 14#include <linux/of_address.h>
 15#include <linux/platform_device.h>
 16#include <linux/pm_runtime.h>
 17
 18#include <video/of_display_timing.h>
 19#include <video/of_videomode.h>
 20
 21#include <drm/drm_fourcc.h>
 22#include <drm/drm_framebuffer.h>
 23#include <drm/drm_print.h>
 24#include <drm/drm_vblank.h>
 25#include <drm/exynos_drm.h>
 26
 27#include "exynos_drm_crtc.h"
 28#include "exynos_drm_drv.h"
 29#include "exynos_drm_fb.h"
 30#include "exynos_drm_plane.h"
 31#include "regs-decon7.h"
 32
 33/*
 34 * DECON stands for Display and Enhancement controller.
 35 */
 36
 37#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
 38
 39#define WINDOWS_NR	2
 40
 41struct decon_data {
 42	unsigned int vidw_buf_start_base;
 43	unsigned int shadowcon_win_protect_shift;
 44	unsigned int wincon_burstlen_shift;
 45};
 46
 47static const struct decon_data exynos7_decon_data = {
 48	.vidw_buf_start_base = 0x80,
 49	.shadowcon_win_protect_shift = 10,
 50	.wincon_burstlen_shift = 11,
 51};
 52
 53static const struct decon_data exynos7870_decon_data = {
 54	.vidw_buf_start_base = 0x880,
 55	.shadowcon_win_protect_shift = 8,
 56	.wincon_burstlen_shift = 10,
 57};
 58
 59struct decon_context {
 60	struct device			*dev;
 61	struct drm_device		*drm_dev;
 62	void				*dma_priv;
 63	struct exynos_drm_crtc		*crtc;
 64	struct exynos_drm_plane		planes[WINDOWS_NR];
 65	struct exynos_drm_plane_config	configs[WINDOWS_NR];
 66	struct clk			*pclk;
 67	struct clk			*aclk;
 68	struct clk			*eclk;
 69	struct clk			*vclk;
 70	void __iomem			*regs;
 71	unsigned long			irq_flags;
 72	bool				i80_if;
 73	wait_queue_head_t		wait_vsync_queue;
 74	atomic_t			wait_vsync_event;
 75
 76	const struct decon_data *data;
 77	struct drm_encoder *encoder;
 78};
 79
 80static const struct of_device_id decon_driver_dt_match[] = {
 81	{
 82		.compatible = "samsung,exynos7-decon",
 83		.data = &exynos7_decon_data,
 84	},
 85	{
 86		.compatible = "samsung,exynos7870-decon",
 87		.data = &exynos7870_decon_data,
 88	},
 89	{},
 90};
 91MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
 92
 93static const uint32_t decon_formats[] = {
 94	DRM_FORMAT_RGB565,
 95	DRM_FORMAT_XRGB8888,
 96	DRM_FORMAT_XBGR8888,
 97	DRM_FORMAT_RGBX8888,
 98	DRM_FORMAT_BGRX8888,
 99	DRM_FORMAT_ARGB8888,
100	DRM_FORMAT_ABGR8888,
101	DRM_FORMAT_RGBA8888,
102	DRM_FORMAT_BGRA8888,
103};
104
105static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
106	DRM_PLANE_TYPE_PRIMARY,
107	DRM_PLANE_TYPE_CURSOR,
108};
109
110/**
111 * decon_shadow_protect_win() - disable updating values from shadow registers at vsync
112 *
113 * @ctx: display and enhancement controller context
114 * @win: window to protect registers for
115 * @protect: 1 to protect (disable updates)
116 */
117static void decon_shadow_protect_win(struct decon_context *ctx,
118				     unsigned int win, bool protect)
119{
120	u32 bits, val;
121	unsigned int shift = ctx->data->shadowcon_win_protect_shift;
122
123	bits = SHADOWCON_WINx_PROTECT(shift, win);
124
125	val = readl(ctx->regs + SHADOWCON);
126	if (protect)
127		val |= bits;
128	else
129		val &= ~bits;
130	writel(val, ctx->regs + SHADOWCON);
131}
132
133static void decon_wait_for_vblank(struct decon_context *ctx)
134{
135	atomic_set(&ctx->wait_vsync_event, 1);
136
137	/*
138	 * wait for DECON to signal VSYNC interrupt or return after
139	 * timeout which is set to 50ms (refresh rate of 20).
140	 */
141	if (!wait_event_timeout(ctx->wait_vsync_queue,
142				!atomic_read(&ctx->wait_vsync_event),
143				HZ/20))
144		DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n");
145}
146
147static void decon_clear_channels(struct decon_context *ctx)
148{
149	unsigned int win, ch_enabled = 0;
150	u32 val;
151
152	/* Check if any channel is enabled. */
153	for (win = 0; win < WINDOWS_NR; win++) {
154		val = readl(ctx->regs + WINCON(win));
155
156		if (val & WINCONx_ENWIN) {
157			decon_shadow_protect_win(ctx, win, true);
158
159			val &= ~WINCONx_ENWIN;
160			writel(val, ctx->regs + WINCON(win));
161			ch_enabled = 1;
162
163			decon_shadow_protect_win(ctx, win, false);
164		}
165	}
166
167	val = readl(ctx->regs + DECON_UPDATE);
168	val |= DECON_UPDATE_STANDALONE_F;
169	writel(val, ctx->regs + DECON_UPDATE);
170
171	/* Wait for vsync, as disable channel takes effect at next vsync */
172	if (ch_enabled)
173		decon_wait_for_vblank(ctx);
174}
175
176static int decon_ctx_initialize(struct decon_context *ctx,
177			struct drm_device *drm_dev)
178{
179	ctx->drm_dev = drm_dev;
180
181	decon_clear_channels(ctx);
182
183	return exynos_drm_register_dma(drm_dev, ctx->dev, &ctx->dma_priv);
184}
185
186static void decon_ctx_remove(struct decon_context *ctx)
187{
188	/* detach this sub driver from iommu mapping if supported. */
189	exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
190}
191
192static u32 decon_calc_clkdiv(struct decon_context *ctx,
193		const struct drm_display_mode *mode)
194{
195	unsigned long ideal_clk = mode->clock * 1000;
196	u32 clkdiv;
197
198	/* Find the clock divider value that gets us closest to ideal_clk */
199	clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
200
201	return (clkdiv < 0x100) ? clkdiv : 0xff;
202}
203
204static void decon_commit(struct exynos_drm_crtc *crtc)
205{
206	struct decon_context *ctx = crtc->ctx;
207	struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
208	u32 val, clkdiv;
209
210	/* nothing to do if we haven't set the mode yet */
211	if (mode->htotal == 0 || mode->vtotal == 0)
212		return;
213
214	if (!ctx->i80_if) {
215		int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
216	      /* setup vertical timing values. */
217		vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
218		vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
219		vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
220
221		val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
222		writel(val, ctx->regs + VIDTCON0);
223
224		val = VIDTCON1_VSPW(vsync_len - 1);
225		writel(val, ctx->regs + VIDTCON1);
226
227		/* setup horizontal timing values.  */
228		hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
229		hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
230		hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
231
232		/* setup horizontal timing values.  */
233		val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
234		writel(val, ctx->regs + VIDTCON2);
235
236		val = VIDTCON3_HSPW(hsync_len - 1);
237		writel(val, ctx->regs + VIDTCON3);
238	}
239
240	/* setup horizontal and vertical display size. */
241	val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
242	       VIDTCON4_HOZVAL(mode->hdisplay - 1);
243	writel(val, ctx->regs + VIDTCON4);
244
245	writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
246
247	/*
248	 * fields of register with prefix '_F' would be updated
249	 * at vsync(same as dma start)
250	 */
251	val = VIDCON0_ENVID | VIDCON0_ENVID_F;
252	writel(val, ctx->regs + VIDCON0);
253
254	clkdiv = decon_calc_clkdiv(ctx, mode);
255	if (clkdiv > 1) {
256		val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
257		writel(val, ctx->regs + VCLKCON1);
258		writel(val, ctx->regs + VCLKCON2);
259	}
260
261	val = readl(ctx->regs + DECON_UPDATE);
262	val |= DECON_UPDATE_STANDALONE_F;
263	writel(val, ctx->regs + DECON_UPDATE);
264}
265
266static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
267{
268	struct decon_context *ctx = crtc->ctx;
269	u32 val;
270
271	if (!test_and_set_bit(0, &ctx->irq_flags)) {
272		val = readl(ctx->regs + VIDINTCON0);
273
274		val |= VIDINTCON0_INT_ENABLE;
275
276		if (!ctx->i80_if) {
277			val |= VIDINTCON0_INT_FRAME;
278			val &= ~VIDINTCON0_FRAMESEL0_MASK;
279			val |= VIDINTCON0_FRAMESEL0_VSYNC;
280		}
281
282		writel(val, ctx->regs + VIDINTCON0);
283	}
284
285	return 0;
286}
287
288static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
289{
290	struct decon_context *ctx = crtc->ctx;
291	u32 val;
292
293	if (test_and_clear_bit(0, &ctx->irq_flags)) {
294		val = readl(ctx->regs + VIDINTCON0);
295
296		val &= ~VIDINTCON0_INT_ENABLE;
297		if (!ctx->i80_if)
298			val &= ~VIDINTCON0_INT_FRAME;
299
300		writel(val, ctx->regs + VIDINTCON0);
301	}
302}
303
304static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
305				 struct drm_framebuffer *fb)
306{
307	unsigned long val;
308	int padding;
309	unsigned int shift = ctx->data->wincon_burstlen_shift;
310
311	val = readl(ctx->regs + WINCON(win));
312	val &= ~WINCONx_BPPMODE_MASK;
313
314	switch (fb->format->format) {
315	case DRM_FORMAT_RGB565:
316		val |= WINCONx_BPPMODE_16BPP_565;
317		val |= WINCONx_BURSTLEN_16WORD(shift);
318		break;
319	case DRM_FORMAT_XRGB8888:
320		val |= WINCONx_BPPMODE_24BPP_xRGB;
321		val |= WINCONx_BURSTLEN_16WORD(shift);
322		break;
323	case DRM_FORMAT_XBGR8888:
324		val |= WINCONx_BPPMODE_24BPP_xBGR;
325		val |= WINCONx_BURSTLEN_16WORD(shift);
326		break;
327	case DRM_FORMAT_RGBX8888:
328		val |= WINCONx_BPPMODE_24BPP_RGBx;
329		val |= WINCONx_BURSTLEN_16WORD(shift);
330		break;
331	case DRM_FORMAT_BGRX8888:
332		val |= WINCONx_BPPMODE_24BPP_BGRx;
333		val |= WINCONx_BURSTLEN_16WORD(shift);
334		break;
335	case DRM_FORMAT_ARGB8888:
336		val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
337			WINCONx_ALPHA_SEL;
338		val |= WINCONx_BURSTLEN_16WORD(shift);
339		break;
340	case DRM_FORMAT_ABGR8888:
341		val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
342			WINCONx_ALPHA_SEL;
343		val |= WINCONx_BURSTLEN_16WORD(shift);
344		break;
345	case DRM_FORMAT_RGBA8888:
346		val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
347			WINCONx_ALPHA_SEL;
348		val |= WINCONx_BURSTLEN_16WORD(shift);
349		break;
350	case DRM_FORMAT_BGRA8888:
351	default:
352		val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
353			WINCONx_ALPHA_SEL;
354		val |= WINCONx_BURSTLEN_16WORD(shift);
355		break;
356	}
357
358	DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %d\n", fb->format->cpp[0]);
359
360	/*
361	 * In case of exynos, setting dma-burst to 16Word causes permanent
362	 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
363	 * switching which is based on plane size is not recommended as
364	 * plane size varies a lot towards the end of the screen and rapid
365	 * movement causes unstable DMA which results into iommu crash/tear.
366	 */
367
368	padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width;
369	if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {
370		val &= ~WINCONx_BURSTLEN_MASK(shift);
371		val |= WINCONx_BURSTLEN_8WORD(shift);
372	}
373
374	writel(val, ctx->regs + WINCON(win));
375}
376
377static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
378{
379	unsigned int keycon0 = 0, keycon1 = 0;
380
381	keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
382			WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
383
384	keycon1 = WxKEYCON1_COLVAL(0xffffffff);
385
386	writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
387	writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
388}
389
390static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
391{
392	struct decon_context *ctx = crtc->ctx;
393	int i;
394
395	for (i = 0; i < WINDOWS_NR; i++)
396		decon_shadow_protect_win(ctx, i, true);
397}
398
399static void decon_update_plane(struct exynos_drm_crtc *crtc,
400			       struct exynos_drm_plane *plane)
401{
402	struct exynos_drm_plane_state *state =
403				to_exynos_plane_state(plane->base.state);
404	struct decon_context *ctx = crtc->ctx;
405	struct drm_framebuffer *fb = state->base.fb;
406	int padding;
407	unsigned long val, alpha;
408	unsigned int last_x;
409	unsigned int last_y;
410	unsigned int win = plane->index;
411	unsigned int cpp = fb->format->cpp[0];
412	unsigned int pitch = fb->pitches[0];
413	unsigned int vidw_addr0_base = ctx->data->vidw_buf_start_base;
414
415	/*
416	 * SHADOWCON/PRTCON register is used for enabling timing.
417	 *
418	 * for example, once only width value of a register is set,
419	 * if the dma is started then decon hardware could malfunction so
420	 * with protect window setting, the register fields with prefix '_F'
421	 * wouldn't be updated at vsync also but updated once unprotect window
422	 * is set.
423	 */
424
425	/* buffer start address */
426	val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0);
427	writel(val, ctx->regs + VIDW_BUF_START(vidw_addr0_base, win));
428
429	padding = (pitch / cpp) - fb->width;
430
431	/* buffer size */
432	writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
433	writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win));
434
435	/* offset from the start of the buffer to read */
436	writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win));
437	writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win));
438
439	DRM_DEV_DEBUG_KMS(ctx->dev, "start addr = 0x%lx\n",
440			(unsigned long)val);
441	DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n",
442			state->crtc.w, state->crtc.h);
443
444	val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
445		VIDOSDxA_TOPLEFT_Y(state->crtc.y);
446	writel(val, ctx->regs + VIDOSD_A(win));
447
448	last_x = state->crtc.x + state->crtc.w;
449	if (last_x)
450		last_x--;
451	last_y = state->crtc.y + state->crtc.h;
452	if (last_y)
453		last_y--;
454
455	val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
456
457	writel(val, ctx->regs + VIDOSD_B(win));
458
459	DRM_DEV_DEBUG_KMS(ctx->dev, "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
460			state->crtc.x, state->crtc.y, last_x, last_y);
461
462	/* OSD alpha */
463	alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
464			VIDOSDxC_ALPHA0_G_F(0x0) |
465			VIDOSDxC_ALPHA0_B_F(0x0);
466
467	writel(alpha, ctx->regs + VIDOSD_C(win));
468
469	alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
470			VIDOSDxD_ALPHA1_G_F(0xff) |
471			VIDOSDxD_ALPHA1_B_F(0xff);
472
473	writel(alpha, ctx->regs + VIDOSD_D(win));
474
475	decon_win_set_pixfmt(ctx, win, fb);
476
477	/* hardware window 0 doesn't support color key. */
478	if (win != 0)
479		decon_win_set_colkey(ctx, win);
480
481	/* wincon */
482	val = readl(ctx->regs + WINCON(win));
483	val |= WINCONx_TRIPLE_BUF_MODE;
484	val |= WINCONx_ENWIN;
485	writel(val, ctx->regs + WINCON(win));
486
487	/* Enable DMA channel and unprotect windows */
488	decon_shadow_protect_win(ctx, win, false);
489
490	val = readl(ctx->regs + DECON_UPDATE);
491	val |= DECON_UPDATE_STANDALONE_F;
492	writel(val, ctx->regs + DECON_UPDATE);
493}
494
495static void decon_disable_plane(struct exynos_drm_crtc *crtc,
496				struct exynos_drm_plane *plane)
497{
498	struct decon_context *ctx = crtc->ctx;
499	unsigned int win = plane->index;
500	u32 val;
501
502	/* protect windows */
503	decon_shadow_protect_win(ctx, win, true);
504
505	/* wincon */
506	val = readl(ctx->regs + WINCON(win));
507	val &= ~WINCONx_ENWIN;
508	writel(val, ctx->regs + WINCON(win));
509
510	val = readl(ctx->regs + DECON_UPDATE);
511	val |= DECON_UPDATE_STANDALONE_F;
512	writel(val, ctx->regs + DECON_UPDATE);
513}
514
515static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
516{
517	struct decon_context *ctx = crtc->ctx;
518	int i;
519
520	for (i = 0; i < WINDOWS_NR; i++)
521		decon_shadow_protect_win(ctx, i, false);
522	exynos_crtc_handle_event(crtc);
523}
524
525static void decon_init(struct decon_context *ctx)
526{
527	u32 val;
528
529	writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
530
531	val = VIDOUTCON0_DISP_IF_0_ON;
532	if (!ctx->i80_if)
533		val |= VIDOUTCON0_RGBIF;
534	writel(val, ctx->regs + VIDOUTCON0);
535
536	writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
537
538	if (!ctx->i80_if)
539		writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
540}
541
542static void decon_atomic_enable(struct exynos_drm_crtc *crtc)
543{
544	struct decon_context *ctx = crtc->ctx;
545	int ret;
546
547	ret = pm_runtime_resume_and_get(ctx->dev);
548	if (ret < 0) {
549		DRM_DEV_ERROR(ctx->dev, "failed to enable DECON device.\n");
550		return;
551	}
552
553	decon_init(ctx);
554
555	/* if vblank was enabled status, enable it again. */
556	if (test_and_clear_bit(0, &ctx->irq_flags))
557		decon_enable_vblank(ctx->crtc);
558
559	decon_commit(ctx->crtc);
560}
561
562static void decon_atomic_disable(struct exynos_drm_crtc *crtc)
563{
564	struct decon_context *ctx = crtc->ctx;
565	int i;
566
567	/*
568	 * We need to make sure that all windows are disabled before we
569	 * suspend that connector. Otherwise we might try to scan from
570	 * a destroyed buffer later.
571	 */
572	for (i = 0; i < WINDOWS_NR; i++)
573		decon_disable_plane(crtc, &ctx->planes[i]);
574
575	pm_runtime_put_sync(ctx->dev);
576}
577
578static const struct exynos_drm_crtc_ops decon_crtc_ops = {
579	.atomic_enable = decon_atomic_enable,
580	.atomic_disable = decon_atomic_disable,
581	.enable_vblank = decon_enable_vblank,
582	.disable_vblank = decon_disable_vblank,
583	.atomic_begin = decon_atomic_begin,
584	.update_plane = decon_update_plane,
585	.disable_plane = decon_disable_plane,
586	.atomic_flush = decon_atomic_flush,
587};
588
589
590static irqreturn_t decon_irq_handler(int irq, void *dev_id)
591{
592	struct decon_context *ctx = (struct decon_context *)dev_id;
593	u32 val, clear_bit;
594
595	val = readl(ctx->regs + VIDINTCON1);
596
597	clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
598	if (val & clear_bit)
599		writel(clear_bit, ctx->regs + VIDINTCON1);
600
601	/* check the crtc is detached already from encoder */
602	if (!ctx->drm_dev)
603		goto out;
604
605	/* check if crtc and vblank have been initialized properly */
606	if (!drm_dev_has_vblank(ctx->drm_dev))
607		goto out;
608
609	if (!ctx->i80_if) {
610		drm_crtc_handle_vblank(&ctx->crtc->base);
611
612		/* set wait vsync event to zero and wake up queue. */
613		if (atomic_read(&ctx->wait_vsync_event)) {
614			atomic_set(&ctx->wait_vsync_event, 0);
615			wake_up(&ctx->wait_vsync_queue);
616		}
617	}
618out:
619	return IRQ_HANDLED;
620}
621
622static int decon_bind(struct device *dev, struct device *master, void *data)
623{
624	struct decon_context *ctx = dev_get_drvdata(dev);
625	struct drm_device *drm_dev = data;
626	struct exynos_drm_plane *exynos_plane;
627	unsigned int i;
628	int ret;
629
630	ret = decon_ctx_initialize(ctx, drm_dev);
631	if (ret) {
632		DRM_DEV_ERROR(dev, "decon_ctx_initialize failed.\n");
633		return ret;
634	}
635
636	for (i = 0; i < WINDOWS_NR; i++) {
637		ctx->configs[i].pixel_formats = decon_formats;
638		ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats);
639		ctx->configs[i].zpos = i;
640		ctx->configs[i].type = decon_win_types[i];
641
642		ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
643					&ctx->configs[i]);
644		if (ret)
645			return ret;
646	}
647
648	exynos_plane = &ctx->planes[DEFAULT_WIN];
649	ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
650			EXYNOS_DISPLAY_TYPE_LCD, &decon_crtc_ops, ctx);
651	if (IS_ERR(ctx->crtc)) {
652		decon_ctx_remove(ctx);
653		return PTR_ERR(ctx->crtc);
654	}
655
656	if (ctx->encoder)
657		exynos_dpi_bind(drm_dev, ctx->encoder);
658
659	return 0;
660
661}
662
663static void decon_unbind(struct device *dev, struct device *master,
664			void *data)
665{
666	struct decon_context *ctx = dev_get_drvdata(dev);
667
668	decon_atomic_disable(ctx->crtc);
669
670	if (ctx->encoder)
671		exynos_dpi_remove(ctx->encoder);
672
673	decon_ctx_remove(ctx);
674}
675
676static const struct component_ops decon_component_ops = {
677	.bind	= decon_bind,
678	.unbind = decon_unbind,
679};
680
681static int decon_probe(struct platform_device *pdev)
682{
683	struct device *dev = &pdev->dev;
684	struct decon_context *ctx;
685	struct device_node *i80_if_timings;
686	int ret;
687
688	if (!dev->of_node)
689		return -ENODEV;
690
691	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
692	if (!ctx)
693		return -ENOMEM;
694
695	ctx->dev = dev;
696	ctx->data = of_device_get_match_data(dev);
697
698	i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
699	if (i80_if_timings)
700		ctx->i80_if = true;
701	of_node_put(i80_if_timings);
702
703	ctx->regs = of_iomap(dev->of_node, 0);
704	if (!ctx->regs)
705		return -ENOMEM;
706
707	ctx->pclk = devm_clk_get(dev, "pclk_decon0");
708	if (IS_ERR(ctx->pclk)) {
709		dev_err(dev, "failed to get bus clock pclk\n");
710		ret = PTR_ERR(ctx->pclk);
711		goto err_iounmap;
712	}
713
714	ctx->aclk = devm_clk_get(dev, "aclk_decon0");
715	if (IS_ERR(ctx->aclk)) {
716		dev_err(dev, "failed to get bus clock aclk\n");
717		ret = PTR_ERR(ctx->aclk);
718		goto err_iounmap;
719	}
720
721	ctx->eclk = devm_clk_get(dev, "decon0_eclk");
722	if (IS_ERR(ctx->eclk)) {
723		dev_err(dev, "failed to get eclock\n");
724		ret = PTR_ERR(ctx->eclk);
725		goto err_iounmap;
726	}
727
728	ctx->vclk = devm_clk_get(dev, "decon0_vclk");
729	if (IS_ERR(ctx->vclk)) {
730		dev_err(dev, "failed to get vclock\n");
731		ret = PTR_ERR(ctx->vclk);
732		goto err_iounmap;
733	}
734
735	ret =  platform_get_irq_byname(pdev, ctx->i80_if ? "lcd_sys" : "vsync");
736	if (ret < 0)
737		goto err_iounmap;
738
739	ret = devm_request_irq(dev, ret, decon_irq_handler, 0, "drm_decon", ctx);
740	if (ret) {
741		dev_err(dev, "irq request failed.\n");
742		goto err_iounmap;
743	}
744
745	init_waitqueue_head(&ctx->wait_vsync_queue);
746	atomic_set(&ctx->wait_vsync_event, 0);
747
748	platform_set_drvdata(pdev, ctx);
749
750	ctx->encoder = exynos_dpi_probe(dev);
751	if (IS_ERR(ctx->encoder)) {
752		ret = PTR_ERR(ctx->encoder);
753		goto err_iounmap;
754	}
755
756	pm_runtime_enable(dev);
757
758	ret = component_add(dev, &decon_component_ops);
759	if (ret)
760		goto err_disable_pm_runtime;
761
762	return ret;
763
764err_disable_pm_runtime:
765	pm_runtime_disable(dev);
766
767err_iounmap:
768	iounmap(ctx->regs);
769
770	return ret;
771}
772
773static void decon_remove(struct platform_device *pdev)
774{
775	struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
776
777	pm_runtime_disable(&pdev->dev);
778
779	iounmap(ctx->regs);
780
781	component_del(&pdev->dev, &decon_component_ops);
782}
783
784static int exynos7_decon_suspend(struct device *dev)
785{
786	struct decon_context *ctx = dev_get_drvdata(dev);
787
788	clk_disable_unprepare(ctx->vclk);
789	clk_disable_unprepare(ctx->eclk);
790	clk_disable_unprepare(ctx->aclk);
791	clk_disable_unprepare(ctx->pclk);
792
793	return 0;
794}
795
796static int exynos7_decon_resume(struct device *dev)
797{
798	struct decon_context *ctx = dev_get_drvdata(dev);
799	int ret;
800
801	ret = clk_prepare_enable(ctx->pclk);
802	if (ret < 0) {
803		DRM_DEV_ERROR(dev, "Failed to prepare_enable the pclk [%d]\n",
804			      ret);
805		goto err_pclk_enable;
806	}
807
808	ret = clk_prepare_enable(ctx->aclk);
809	if (ret < 0) {
810		DRM_DEV_ERROR(dev, "Failed to prepare_enable the aclk [%d]\n",
811			      ret);
812		goto err_aclk_enable;
813	}
814
815	ret = clk_prepare_enable(ctx->eclk);
816	if  (ret < 0) {
817		DRM_DEV_ERROR(dev, "Failed to prepare_enable the eclk [%d]\n",
818			      ret);
819		goto err_eclk_enable;
820	}
821
822	ret = clk_prepare_enable(ctx->vclk);
823	if  (ret < 0) {
824		DRM_DEV_ERROR(dev, "Failed to prepare_enable the vclk [%d]\n",
825			      ret);
826		goto err_vclk_enable;
827	}
828
829	return 0;
830
831err_vclk_enable:
832	clk_disable_unprepare(ctx->eclk);
833err_eclk_enable:
834	clk_disable_unprepare(ctx->aclk);
835err_aclk_enable:
836	clk_disable_unprepare(ctx->pclk);
837err_pclk_enable:
838	return ret;
839}
840
841static DEFINE_RUNTIME_DEV_PM_OPS(exynos7_decon_pm_ops, exynos7_decon_suspend,
842				 exynos7_decon_resume, NULL);
843
844struct platform_driver decon_driver = {
845	.probe		= decon_probe,
846	.remove		= decon_remove,
847	.driver		= {
848		.name	= "exynos-decon",
849		.pm	= pm_ptr(&exynos7_decon_pm_ops),
850		.of_match_table = decon_driver_dt_match,
851	},
852};