etnaviv_gpu.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2015-2018 Etnaviv Project
   4 */
   5
   6#include <linux/clk.h>
   7#include <linux/component.h>
   8#include <linux/delay.h>
   9#include <linux/dma-fence.h>
  10#include <linux/dma-mapping.h>
  11#include <linux/mod_devicetable.h>
  12#include <linux/module.h>
  13#include <linux/platform_device.h>
  14#include <linux/pm_runtime.h>
  15#include <linux/regulator/consumer.h>
  16#include <linux/reset.h>
  17#include <linux/thermal.h>
  18
  19#include <drm/drm_print.h>
  20
  21#include "etnaviv_cmdbuf.h"
  22#include "etnaviv_dump.h"
  23#include "etnaviv_gpu.h"
  24#include "etnaviv_gem.h"
  25#include "etnaviv_mmu.h"
  26#include "etnaviv_perfmon.h"
  27#include "etnaviv_sched.h"
  28#include "common.xml.h"
  29#include "state.xml.h"
  30#include "state_hi.xml.h"
  31#include "cmdstream.xml.h"
  32
  33static const struct platform_device_id gpu_ids[] = {
  34	{ .name = "etnaviv-gpu,2d" },
  35	{ },
  36};
  37
  38/*
  39 * Driver functions:
  40 */
  41
  42int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
  43{
  44	struct etnaviv_drm_private *priv = gpu->drm->dev_private;
  45
  46	switch (param) {
  47	case ETNAVIV_PARAM_GPU_MODEL:
  48		*value = gpu->identity.model;
  49		break;
  50
  51	case ETNAVIV_PARAM_GPU_REVISION:
  52		*value = gpu->identity.revision;
  53		break;
  54
  55	case ETNAVIV_PARAM_GPU_FEATURES_0:
  56		*value = gpu->identity.features;
  57		break;
  58
  59	case ETNAVIV_PARAM_GPU_FEATURES_1:
  60		*value = gpu->identity.minor_features0;
  61		break;
  62
  63	case ETNAVIV_PARAM_GPU_FEATURES_2:
  64		*value = gpu->identity.minor_features1;
  65		break;
  66
  67	case ETNAVIV_PARAM_GPU_FEATURES_3:
  68		*value = gpu->identity.minor_features2;
  69		break;
  70
  71	case ETNAVIV_PARAM_GPU_FEATURES_4:
  72		*value = gpu->identity.minor_features3;
  73		break;
  74
  75	case ETNAVIV_PARAM_GPU_FEATURES_5:
  76		*value = gpu->identity.minor_features4;
  77		break;
  78
  79	case ETNAVIV_PARAM_GPU_FEATURES_6:
  80		*value = gpu->identity.minor_features5;
  81		break;
  82
  83	case ETNAVIV_PARAM_GPU_FEATURES_7:
  84		*value = gpu->identity.minor_features6;
  85		break;
  86
  87	case ETNAVIV_PARAM_GPU_FEATURES_8:
  88		*value = gpu->identity.minor_features7;
  89		break;
  90
  91	case ETNAVIV_PARAM_GPU_FEATURES_9:
  92		*value = gpu->identity.minor_features8;
  93		break;
  94
  95	case ETNAVIV_PARAM_GPU_FEATURES_10:
  96		*value = gpu->identity.minor_features9;
  97		break;
  98
  99	case ETNAVIV_PARAM_GPU_FEATURES_11:
 100		*value = gpu->identity.minor_features10;
 101		break;
 102
 103	case ETNAVIV_PARAM_GPU_FEATURES_12:
 104		*value = gpu->identity.minor_features11;
 105		break;
 106
 107	case ETNAVIV_PARAM_GPU_STREAM_COUNT:
 108		*value = gpu->identity.stream_count;
 109		break;
 110
 111	case ETNAVIV_PARAM_GPU_REGISTER_MAX:
 112		*value = gpu->identity.register_max;
 113		break;
 114
 115	case ETNAVIV_PARAM_GPU_THREAD_COUNT:
 116		*value = gpu->identity.thread_count;
 117		break;
 118
 119	case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
 120		*value = gpu->identity.vertex_cache_size;
 121		break;
 122
 123	case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
 124		*value = gpu->identity.shader_core_count;
 125		break;
 126
 127	case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
 128		*value = gpu->identity.pixel_pipes;
 129		break;
 130
 131	case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
 132		*value = gpu->identity.vertex_output_buffer_size;
 133		break;
 134
 135	case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
 136		*value = gpu->identity.buffer_size;
 137		break;
 138
 139	case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
 140		*value = gpu->identity.instruction_count;
 141		break;
 142
 143	case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
 144		*value = gpu->identity.num_constants;
 145		break;
 146
 147	case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
 148		*value = gpu->identity.varyings_count;
 149		break;
 150
 151	case ETNAVIV_PARAM_SOFTPIN_START_ADDR:
 152		if (priv->mmu_global->version == ETNAVIV_IOMMU_V2)
 153			*value = ETNAVIV_SOFTPIN_START_ADDRESS;
 154		else
 155			*value = ~0ULL;
 156		break;
 157
 158	case ETNAVIV_PARAM_GPU_PRODUCT_ID:
 159		*value = gpu->identity.product_id;
 160		break;
 161
 162	case ETNAVIV_PARAM_GPU_CUSTOMER_ID:
 163		*value = gpu->identity.customer_id;
 164		break;
 165
 166	case ETNAVIV_PARAM_GPU_ECO_ID:
 167		*value = gpu->identity.eco_id;
 168		break;
 169
 170	default:
 171		DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
 172		return -EINVAL;
 173	}
 174
 175	return 0;
 176}
 177
 178static int etnaviv_gpu_reset_deassert(struct etnaviv_gpu *gpu)
 179{
 180	int ret;
 181
 182	/*
 183	 * 32 core clock cycles (slowest clock) required before deassertion
 184	 * 1 microsecond might match all implementations without computation
 185	 */
 186	usleep_range(1, 2);
 187
 188	ret = reset_control_deassert(gpu->rst);
 189	if (ret)
 190		return ret;
 191
 192	/*
 193	 * 128 core clock cycles (slowest clock) required before any activity on AHB
 194	 * 1 microsecond might match all implementations without computation
 195	 */
 196	usleep_range(1, 2);
 197
 198	return 0;
 199}
 200
 201static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision)
 202{
 203	return gpu->identity.model == model &&
 204	       gpu->identity.revision == revision;
 205}
 206
 207#define etnaviv_field(val, field) \
 208	(((val) & field##__MASK) >> field##__SHIFT)
 209
 210static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
 211{
 212	if (gpu->identity.minor_features0 &
 213	    chipMinorFeatures0_MORE_MINOR_FEATURES) {
 214		u32 specs[4];
 215		unsigned int streams;
 216
 217		specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
 218		specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
 219		specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
 220		specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
 221
 222		gpu->identity.stream_count = etnaviv_field(specs[0],
 223					VIVS_HI_CHIP_SPECS_STREAM_COUNT);
 224		gpu->identity.register_max = etnaviv_field(specs[0],
 225					VIVS_HI_CHIP_SPECS_REGISTER_MAX);
 226		gpu->identity.thread_count = etnaviv_field(specs[0],
 227					VIVS_HI_CHIP_SPECS_THREAD_COUNT);
 228		gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
 229					VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
 230		gpu->identity.shader_core_count = etnaviv_field(specs[0],
 231					VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
 232		gpu->identity.pixel_pipes = etnaviv_field(specs[0],
 233					VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
 234		gpu->identity.vertex_output_buffer_size =
 235			etnaviv_field(specs[0],
 236				VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
 237
 238		gpu->identity.buffer_size = etnaviv_field(specs[1],
 239					VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
 240		gpu->identity.instruction_count = etnaviv_field(specs[1],
 241					VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
 242		gpu->identity.num_constants = etnaviv_field(specs[1],
 243					VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
 244
 245		gpu->identity.varyings_count = etnaviv_field(specs[2],
 246					VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
 247
 248		/* This overrides the value from older register if non-zero */
 249		streams = etnaviv_field(specs[3],
 250					VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
 251		if (streams)
 252			gpu->identity.stream_count = streams;
 253	}
 254
 255	/* Fill in the stream count if not specified */
 256	if (gpu->identity.stream_count == 0) {
 257		if (gpu->identity.model >= 0x1000)
 258			gpu->identity.stream_count = 4;
 259		else
 260			gpu->identity.stream_count = 1;
 261	}
 262
 263	/* Convert the register max value */
 264	if (gpu->identity.register_max)
 265		gpu->identity.register_max = 1 << gpu->identity.register_max;
 266	else if (gpu->identity.model == chipModel_GC400)
 267		gpu->identity.register_max = 32;
 268	else
 269		gpu->identity.register_max = 64;
 270
 271	/* Convert thread count */
 272	if (gpu->identity.thread_count)
 273		gpu->identity.thread_count = 1 << gpu->identity.thread_count;
 274	else if (gpu->identity.model == chipModel_GC400)
 275		gpu->identity.thread_count = 64;
 276	else if (gpu->identity.model == chipModel_GC500 ||
 277		 gpu->identity.model == chipModel_GC530)
 278		gpu->identity.thread_count = 128;
 279	else
 280		gpu->identity.thread_count = 256;
 281
 282	if (gpu->identity.vertex_cache_size == 0)
 283		gpu->identity.vertex_cache_size = 8;
 284
 285	if (gpu->identity.shader_core_count == 0) {
 286		if (gpu->identity.model >= 0x1000)
 287			gpu->identity.shader_core_count = 2;
 288		else
 289			gpu->identity.shader_core_count = 1;
 290	}
 291
 292	if (gpu->identity.pixel_pipes == 0)
 293		gpu->identity.pixel_pipes = 1;
 294
 295	/* Convert virtex buffer size */
 296	if (gpu->identity.vertex_output_buffer_size) {
 297		gpu->identity.vertex_output_buffer_size =
 298			1 << gpu->identity.vertex_output_buffer_size;
 299	} else if (gpu->identity.model == chipModel_GC400) {
 300		if (gpu->identity.revision < 0x4000)
 301			gpu->identity.vertex_output_buffer_size = 512;
 302		else if (gpu->identity.revision < 0x4200)
 303			gpu->identity.vertex_output_buffer_size = 256;
 304		else
 305			gpu->identity.vertex_output_buffer_size = 128;
 306	} else {
 307		gpu->identity.vertex_output_buffer_size = 512;
 308	}
 309
 310	switch (gpu->identity.instruction_count) {
 311	case 0:
 312		if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
 313		    gpu->identity.model == chipModel_GC880)
 314			gpu->identity.instruction_count = 512;
 315		else
 316			gpu->identity.instruction_count = 256;
 317		break;
 318
 319	case 1:
 320		gpu->identity.instruction_count = 1024;
 321		break;
 322
 323	case 2:
 324		gpu->identity.instruction_count = 2048;
 325		break;
 326
 327	default:
 328		gpu->identity.instruction_count = 256;
 329		break;
 330	}
 331
 332	if (gpu->identity.num_constants == 0)
 333		gpu->identity.num_constants = 168;
 334
 335	if (gpu->identity.varyings_count == 0) {
 336		if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
 337			gpu->identity.varyings_count = 12;
 338		else
 339			gpu->identity.varyings_count = 8;
 340	}
 341
 342	/*
 343	 * For some cores, two varyings are consumed for position, so the
 344	 * maximum varying count needs to be reduced by one.
 345	 */
 346	if (etnaviv_is_model_rev(gpu, 0x5000, 0x5434) ||
 347	    etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
 348	    etnaviv_is_model_rev(gpu, 0x4000, 0x5245) ||
 349	    etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
 350	    etnaviv_is_model_rev(gpu, 0x3000, 0x5435) ||
 351	    etnaviv_is_model_rev(gpu, 0x2200, 0x5244) ||
 352	    etnaviv_is_model_rev(gpu, 0x2100, 0x5108) ||
 353	    etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
 354	    etnaviv_is_model_rev(gpu, 0x1500, 0x5246) ||
 355	    etnaviv_is_model_rev(gpu, 0x880, 0x5107) ||
 356	    etnaviv_is_model_rev(gpu, 0x880, 0x5106))
 357		gpu->identity.varyings_count -= 1;
 358}
 359
 360static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
 361{
 362	u32 chipIdentity;
 363
 364	chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
 365
 366	/* Special case for older graphic cores. */
 367	if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
 368		gpu->identity.model    = chipModel_GC500;
 369		gpu->identity.revision = etnaviv_field(chipIdentity,
 370					 VIVS_HI_CHIP_IDENTITY_REVISION);
 371	} else {
 372		u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
 373
 374		gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
 375		gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
 376		gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
 377
 378		/*
 379		 * Reading these two registers on GC600 rev 0x19 result in a
 380		 * unhandled fault: external abort on non-linefetch
 381		 */
 382		if (!etnaviv_is_model_rev(gpu, 0x600, 0x19)) {
 383			gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
 384			gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
 385		}
 386
 387		/*
 388		 * !!!! HACK ALERT !!!!
 389		 * Because people change device IDs without letting software
 390		 * know about it - here is the hack to make it all look the
 391		 * same.  Only for GC400 family.
 392		 */
 393		if ((gpu->identity.model & 0xff00) == 0x0400 &&
 394		    gpu->identity.model != chipModel_GC420) {
 395			gpu->identity.model = gpu->identity.model & 0x0400;
 396		}
 397
 398		/* Another special case */
 399		if (etnaviv_is_model_rev(gpu, 0x300, 0x2201)) {
 400			u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
 401
 402			if (chipDate == 0x20080814 && chipTime == 0x12051100) {
 403				/*
 404				 * This IP has an ECO; put the correct
 405				 * revision in it.
 406				 */
 407				gpu->identity.revision = 0x1051;
 408			}
 409		}
 410
 411		/*
 412		 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
 413		 * reality it's just a re-branded GC3000. We can identify this
 414		 * core by the upper half of the revision register being all 1.
 415		 * Fix model/rev here, so all other places can refer to this
 416		 * core by its real identity.
 417		 */
 418		if (etnaviv_is_model_rev(gpu, 0x2000, 0xffff5450)) {
 419			gpu->identity.model = chipModel_GC3000;
 420			gpu->identity.revision &= 0xffff;
 421		}
 422
 423		if (etnaviv_is_model_rev(gpu, 0x1000, 0x5037) && (chipDate == 0x20120617))
 424			gpu->identity.eco_id = 1;
 425
 426		if (etnaviv_is_model_rev(gpu, 0x320, 0x5303) && (chipDate == 0x20140511))
 427			gpu->identity.eco_id = 1;
 428	}
 429
 430	dev_info(gpu->dev, "model: GC%x, revision: %x\n",
 431		 gpu->identity.model, gpu->identity.revision);
 432
 433	gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
 434	/*
 435	 * If there is a match in the HWDB, we aren't interested in the
 436	 * remaining register values, as they might be wrong.
 437	 */
 438	if (etnaviv_fill_identity_from_hwdb(gpu))
 439		return;
 440
 441	gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
 442
 443	/* Disable fast clear on GC700. */
 444	if (gpu->identity.model == chipModel_GC700)
 445		gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 446
 447	/* These models/revisions don't have the 2D pipe bit */
 448	if ((gpu->identity.model == chipModel_GC500 &&
 449	     gpu->identity.revision <= 2) ||
 450	    gpu->identity.model == chipModel_GC300)
 451		gpu->identity.features |= chipFeatures_PIPE_2D;
 452
 453	if ((gpu->identity.model == chipModel_GC500 &&
 454	     gpu->identity.revision < 2) ||
 455	    (gpu->identity.model == chipModel_GC300 &&
 456	     gpu->identity.revision < 0x2000)) {
 457
 458		/*
 459		 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
 460		 * registers.
 461		 */
 462		gpu->identity.minor_features0 = 0;
 463		gpu->identity.minor_features1 = 0;
 464		gpu->identity.minor_features2 = 0;
 465		gpu->identity.minor_features3 = 0;
 466		gpu->identity.minor_features4 = 0;
 467		gpu->identity.minor_features5 = 0;
 468	} else
 469		gpu->identity.minor_features0 =
 470				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
 471
 472	if (gpu->identity.minor_features0 &
 473	    chipMinorFeatures0_MORE_MINOR_FEATURES) {
 474		gpu->identity.minor_features1 =
 475				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
 476		gpu->identity.minor_features2 =
 477				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
 478		gpu->identity.minor_features3 =
 479				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
 480		gpu->identity.minor_features4 =
 481				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
 482		gpu->identity.minor_features5 =
 483				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
 484	}
 485
 486	/* GC600/300 idle register reports zero bits where modules aren't present */
 487	if (gpu->identity.model == chipModel_GC600 ||
 488	    gpu->identity.model == chipModel_GC300)
 489		gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
 490				 VIVS_HI_IDLE_STATE_RA |
 491				 VIVS_HI_IDLE_STATE_SE |
 492				 VIVS_HI_IDLE_STATE_PA |
 493				 VIVS_HI_IDLE_STATE_SH |
 494				 VIVS_HI_IDLE_STATE_PE |
 495				 VIVS_HI_IDLE_STATE_DE |
 496				 VIVS_HI_IDLE_STATE_FE;
 497
 498	etnaviv_hw_specs(gpu);
 499}
 500
 501static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
 502{
 503	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
 504		  VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
 505	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
 506}
 507
 508static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
 509{
 510	if (gpu->identity.minor_features2 &
 511	    chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
 512		clk_set_rate(gpu->clk_core,
 513			     gpu->base_rate_core >> gpu->freq_scale);
 514		clk_set_rate(gpu->clk_shader,
 515			     gpu->base_rate_shader >> gpu->freq_scale);
 516	} else {
 517		unsigned int fscale = 1 << (6 - gpu->freq_scale);
 518		u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 519
 520		clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
 521		clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 522		etnaviv_gpu_load_clock(gpu, clock);
 523	}
 524
 525	/*
 526	 * Choose number of wait cycles to target a ~30us (1/32768) max latency
 527	 * until new work is picked up by the FE when it polls in the idle loop.
 528	 * If the GPU base frequency is unknown use 200 wait cycles.
 529	 */
 530	gpu->fe_waitcycles = clamp(gpu->base_rate_core >> (15 - gpu->freq_scale),
 531				   200UL, 0xffffUL);
 532}
 533
 534static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
 535{
 536	u32 control, idle;
 537	unsigned long timeout;
 538	bool failed = true;
 539
 540	/* We hope that the GPU resets in under one second */
 541	timeout = jiffies + msecs_to_jiffies(1000);
 542
 543	while (time_is_after_jiffies(timeout)) {
 544		unsigned int fscale = 1 << (6 - gpu->freq_scale);
 545		u32 pulse_eater = 0x01590880;
 546
 547		/* disable clock gating */
 548		gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, 0x0);
 549
 550		/* disable pulse eater */
 551		pulse_eater |= BIT(17);
 552		gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
 553		pulse_eater |= BIT(0);
 554		gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
 555
 556		/* enable clock */
 557		control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 558		etnaviv_gpu_load_clock(gpu, control);
 559
 560		/* isolate the GPU. */
 561		control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 562		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 563
 564		if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 565			gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
 566			          VIVS_MMUv2_AHB_CONTROL_RESET);
 567		} else {
 568			/* set soft reset. */
 569			control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 570			gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 571		}
 572
 573		/* wait for reset. */
 574		usleep_range(10, 20);
 575
 576		/* reset soft reset bit. */
 577		control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 578		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 579
 580		/* reset GPU isolation. */
 581		control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 582		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 583
 584		/* read idle register. */
 585		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 586
 587		/* try resetting again if FE is not idle */
 588		if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
 589			dev_dbg(gpu->dev, "FE is not idle\n");
 590			continue;
 591		}
 592
 593		/* read reset register. */
 594		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 595
 596		/* is the GPU idle? */
 597		if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
 598		    ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
 599			dev_dbg(gpu->dev, "GPU is not idle\n");
 600			continue;
 601		}
 602
 603		/* enable debug register access */
 604		control &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
 605		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 606
 607		failed = false;
 608		break;
 609	}
 610
 611	if (failed) {
 612		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 613		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 614
 615		dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
 616			idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
 617			control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
 618			control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
 619
 620		return -EBUSY;
 621	}
 622
 623	/* We rely on the GPU running, so program the clock */
 624	etnaviv_gpu_update_clock(gpu);
 625
 626	gpu->state = ETNA_GPU_STATE_RESET;
 627	gpu->exec_state = -1;
 628	if (gpu->mmu_context)
 629		etnaviv_iommu_context_put(gpu->mmu_context);
 630	gpu->mmu_context = NULL;
 631
 632	return 0;
 633}
 634
 635static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
 636{
 637	u32 pmc, ppc;
 638
 639	/* enable clock gating */
 640	ppc = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
 641	ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
 642
 643	/* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
 644	if (gpu->identity.revision == 0x4301 ||
 645	    gpu->identity.revision == 0x4302)
 646		ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
 647
 648	gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, ppc);
 649
 650	pmc = gpu_read_power(gpu, VIVS_PM_MODULE_CONTROLS);
 651
 652	/* Disable PA clock gating for GC400+ without bugfix except for GC420 */
 653	if (gpu->identity.model >= chipModel_GC400 &&
 654	    gpu->identity.model != chipModel_GC420 &&
 655	    !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
 656		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
 657
 658	/*
 659	 * Disable PE clock gating on revs < 5.0.0.0 when HZ is
 660	 * present without a bug fix.
 661	 */
 662	if (gpu->identity.revision < 0x5000 &&
 663	    gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
 664	    !(gpu->identity.minor_features1 &
 665	      chipMinorFeatures1_DISABLE_PE_GATING))
 666		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
 667
 668	if (gpu->identity.revision < 0x5422)
 669		pmc |= BIT(15); /* Unknown bit */
 670
 671	/* Disable TX clock gating on affected core revisions. */
 672	if (etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
 673	    etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
 674	    etnaviv_is_model_rev(gpu, 0x7000, 0x6202) ||
 675	    etnaviv_is_model_rev(gpu, 0x7000, 0x6203))
 676		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
 677
 678	/* Disable SE and RA clock gating on affected core revisions. */
 679	if (etnaviv_is_model_rev(gpu, 0x7000, 0x6202))
 680		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
 681		       VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;
 682
 683	/* Disable SH_EU clock gating on affected core revisions. */
 684	if (etnaviv_is_model_rev(gpu, 0x8000, 0x7200) ||
 685	    etnaviv_is_model_rev(gpu, 0x8000, 0x8002) ||
 686	    etnaviv_is_model_rev(gpu, 0x9200, 0x6304))
 687		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU;
 688
 689	pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
 690	pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
 691
 692	gpu_write_power(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
 693}
 694
 695void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
 696{
 697	gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
 698	gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
 699		  VIVS_FE_COMMAND_CONTROL_ENABLE |
 700		  VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
 701
 702	if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 703		gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
 704			  VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
 705			  VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
 706	}
 707}
 708
 709static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu,
 710					  struct etnaviv_iommu_context *context)
 711{
 712	u16 prefetch;
 713	u32 address;
 714
 715	WARN_ON(gpu->state != ETNA_GPU_STATE_INITIALIZED);
 716
 717	/* setup the MMU */
 718	etnaviv_iommu_restore(gpu, context);
 719
 720	/* Start command processor */
 721	prefetch = etnaviv_buffer_init(gpu);
 722	address = etnaviv_cmdbuf_get_va(&gpu->buffer,
 723					&gpu->mmu_context->cmdbuf_mapping);
 724
 725	etnaviv_gpu_start_fe(gpu, address, prefetch);
 726
 727	gpu->state = ETNA_GPU_STATE_RUNNING;
 728}
 729
 730static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
 731{
 732	/*
 733	 * Base value for VIVS_PM_PULSE_EATER register on models where it
 734	 * cannot be read, extracted from vivante kernel driver.
 735	 */
 736	u32 pulse_eater = 0x01590880;
 737
 738	if (etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
 739	    etnaviv_is_model_rev(gpu, 0x4000, 0x5222)) {
 740		pulse_eater |= BIT(23);
 741
 742	}
 743
 744	if (etnaviv_is_model_rev(gpu, 0x1000, 0x5039) ||
 745	    etnaviv_is_model_rev(gpu, 0x1000, 0x5040)) {
 746		pulse_eater &= ~BIT(16);
 747		pulse_eater |= BIT(17);
 748	}
 749
 750	if ((gpu->identity.revision > 0x5420) &&
 751	    (gpu->identity.features & chipFeatures_PIPE_3D))
 752	{
 753		/* Performance fix: disable internal DFS */
 754		pulse_eater = gpu_read_power(gpu, VIVS_PM_PULSE_EATER);
 755		pulse_eater |= BIT(18);
 756	}
 757
 758	gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
 759}
 760
 761static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
 762{
 763	WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED ||
 764		  gpu->state == ETNA_GPU_STATE_RESET));
 765
 766	if ((etnaviv_is_model_rev(gpu, 0x320, 0x5007) ||
 767	     etnaviv_is_model_rev(gpu, 0x320, 0x5220)) &&
 768	    gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
 769		u32 mc_memory_debug;
 770
 771		mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
 772
 773		if (gpu->identity.revision == 0x5007)
 774			mc_memory_debug |= 0x0c;
 775		else
 776			mc_memory_debug |= 0x08;
 777
 778		gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
 779	}
 780
 781	/* enable module-level clock gating */
 782	etnaviv_gpu_enable_mlcg(gpu);
 783
 784	/*
 785	 * Update GPU AXI cache atttribute to "cacheable, no allocate".
 786	 * This is necessary to prevent the iMX6 SoC locking up.
 787	 */
 788	gpu_write(gpu, VIVS_HI_AXI_CONFIG,
 789		  VIVS_HI_AXI_CONFIG_AWCACHE(2) |
 790		  VIVS_HI_AXI_CONFIG_ARCACHE(2));
 791
 792	/* GC2000 rev 5108 needs a special bus config */
 793	if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108)) {
 794		u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
 795		bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
 796				VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
 797		bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
 798			      VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
 799		gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
 800	}
 801
 802	if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 803		u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
 804		val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
 805		gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
 806	}
 807
 808	/* setup the pulse eater */
 809	etnaviv_gpu_setup_pulse_eater(gpu);
 810
 811	gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
 812
 813	gpu->state = ETNA_GPU_STATE_INITIALIZED;
 814}
 815
 816int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
 817{
 818	struct etnaviv_drm_private *priv = gpu->drm->dev_private;
 819	dma_addr_t cmdbuf_paddr;
 820	int ret, i;
 821
 822	ret = pm_runtime_get_sync(gpu->dev);
 823	if (ret < 0) {
 824		dev_err(gpu->dev, "Failed to enable GPU power domain\n");
 825		goto pm_put;
 826	}
 827
 828	ret = etnaviv_gpu_reset_deassert(gpu);
 829	if (ret) {
 830		dev_err(gpu->dev, "GPU reset deassert failed\n");
 831		goto fail;
 832	}
 833
 834	etnaviv_hw_identify(gpu);
 835
 836	if (gpu->identity.model == 0) {
 837		dev_err(gpu->dev, "Unknown GPU model\n");
 838		ret = -ENXIO;
 839		goto fail;
 840	}
 841
 842	if (gpu->identity.nn_core_count > 0)
 843		dev_warn(gpu->dev, "etnaviv has been instantiated on a NPU, "
 844                                   "for which the UAPI is still experimental\n");
 845
 846	/* Exclude VG cores with FE2.0 */
 847	if (gpu->identity.features & chipFeatures_PIPE_VG &&
 848	    gpu->identity.features & chipFeatures_FE20) {
 849		dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
 850		ret = -ENXIO;
 851		goto fail;
 852	}
 853
 854	/*
 855	 * On cores with security features supported, we claim control over the
 856	 * security states.
 857	 */
 858	if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
 859	    (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
 860		gpu->sec_mode = ETNA_SEC_KERNEL;
 861
 862	gpu->state = ETNA_GPU_STATE_IDENTIFIED;
 863
 864	ret = etnaviv_hw_reset(gpu);
 865	if (ret) {
 866		dev_err(gpu->dev, "GPU reset failed\n");
 867		goto fail;
 868	}
 869
 870	ret = etnaviv_iommu_global_init(gpu);
 871	if (ret)
 872		goto fail;
 873
 874	/* Create buffer: */
 875	ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, SZ_4K);
 876	if (ret) {
 877		dev_err(gpu->dev, "could not create command buffer\n");
 878		goto fail;
 879	}
 880
 881	/*
 882	 * Set the GPU linear window to cover the cmdbuf region, as the GPU
 883	 * won't be able to start execution otherwise. The alignment to 128M is
 884	 * chosen arbitrarily but helps in debugging, as the MMU offset
 885	 * calculations are much more straight forward this way.
 886	 *
 887	 * On MC1.0 cores the linear window offset is ignored by the TS engine,
 888	 * leading to inconsistent memory views. Avoid using the offset on those
 889	 * cores if possible, otherwise disable the TS feature. MMUv2 doesn't
 890	 * expose this issue, as all TS accesses are MMU translated, so the
 891	 * linear window offset won't be used.
 892	 */
 893	cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M);
 894
 895	if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
 896	    (gpu->identity.minor_features0 & chipMinorFeatures0_MC20) ||
 897	    (gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION)) {
 898		if (cmdbuf_paddr >= SZ_2G)
 899			priv->mmu_global->memory_base = SZ_2G;
 900		else
 901			priv->mmu_global->memory_base = cmdbuf_paddr;
 902	} else if (cmdbuf_paddr + SZ_128M >= SZ_2G) {
 903		dev_info(gpu->dev,
 904			 "Need to move linear window on MC1.0, disabling TS\n");
 905		gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 906		priv->mmu_global->memory_base = SZ_2G;
 907	}
 908
 909	/* Setup event management */
 910	spin_lock_init(&gpu->event_spinlock);
 911	init_completion(&gpu->event_free);
 912	bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
 913	for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
 914		complete(&gpu->event_free);
 915
 916	/* Now program the hardware */
 917	mutex_lock(&gpu->lock);
 918	etnaviv_gpu_hw_init(gpu);
 919	mutex_unlock(&gpu->lock);
 920
 921	pm_runtime_mark_last_busy(gpu->dev);
 922	pm_runtime_put_autosuspend(gpu->dev);
 923
 924	return 0;
 925
 926fail:
 927	pm_runtime_mark_last_busy(gpu->dev);
 928pm_put:
 929	pm_runtime_put_autosuspend(gpu->dev);
 930
 931	return ret;
 932}
 933
 934#ifdef CONFIG_DEBUG_FS
 935struct dma_debug {
 936	u32 address[2];
 937	u32 state[2];
 938};
 939
 940static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
 941{
 942	u32 i;
 943
 944	debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 945	debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 946
 947	for (i = 0; i < 500; i++) {
 948		debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 949		debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 950
 951		if (debug->address[0] != debug->address[1])
 952			break;
 953
 954		if (debug->state[0] != debug->state[1])
 955			break;
 956	}
 957}
 958
 959int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
 960{
 961	struct dma_debug debug;
 962	u32 dma_lo, dma_hi, axi, idle;
 963	int ret;
 964
 965	seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
 966
 967	ret = pm_runtime_get_sync(gpu->dev);
 968	if (ret < 0)
 969		goto pm_put;
 970
 971	dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
 972	dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
 973	axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
 974	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 975
 976	verify_dma(gpu, &debug);
 977
 978	seq_puts(m, "\tidentity\n");
 979	seq_printf(m, "\t model: 0x%x\n", gpu->identity.model);
 980	seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision);
 981	seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id);
 982	seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id);
 983	seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id);
 984
 985	seq_puts(m, "\tfeatures\n");
 986	seq_printf(m, "\t major_features: 0x%08x\n",
 987		   gpu->identity.features);
 988	seq_printf(m, "\t minor_features0: 0x%08x\n",
 989		   gpu->identity.minor_features0);
 990	seq_printf(m, "\t minor_features1: 0x%08x\n",
 991		   gpu->identity.minor_features1);
 992	seq_printf(m, "\t minor_features2: 0x%08x\n",
 993		   gpu->identity.minor_features2);
 994	seq_printf(m, "\t minor_features3: 0x%08x\n",
 995		   gpu->identity.minor_features3);
 996	seq_printf(m, "\t minor_features4: 0x%08x\n",
 997		   gpu->identity.minor_features4);
 998	seq_printf(m, "\t minor_features5: 0x%08x\n",
 999		   gpu->identity.minor_features5);
1000	seq_printf(m, "\t minor_features6: 0x%08x\n",
1001		   gpu->identity.minor_features6);
1002	seq_printf(m, "\t minor_features7: 0x%08x\n",
1003		   gpu->identity.minor_features7);
1004	seq_printf(m, "\t minor_features8: 0x%08x\n",
1005		   gpu->identity.minor_features8);
1006	seq_printf(m, "\t minor_features9: 0x%08x\n",
1007		   gpu->identity.minor_features9);
1008	seq_printf(m, "\t minor_features10: 0x%08x\n",
1009		   gpu->identity.minor_features10);
1010	seq_printf(m, "\t minor_features11: 0x%08x\n",
1011		   gpu->identity.minor_features11);
1012
1013	seq_puts(m, "\tspecs\n");
1014	seq_printf(m, "\t stream_count:  %d\n",
1015			gpu->identity.stream_count);
1016	seq_printf(m, "\t register_max: %d\n",
1017			gpu->identity.register_max);
1018	seq_printf(m, "\t thread_count: %d\n",
1019			gpu->identity.thread_count);
1020	seq_printf(m, "\t vertex_cache_size: %d\n",
1021			gpu->identity.vertex_cache_size);
1022	seq_printf(m, "\t shader_core_count: %d\n",
1023			gpu->identity.shader_core_count);
1024	seq_printf(m, "\t nn_core_count: %d\n",
1025			gpu->identity.nn_core_count);
1026	seq_printf(m, "\t pixel_pipes: %d\n",
1027			gpu->identity.pixel_pipes);
1028	seq_printf(m, "\t vertex_output_buffer_size: %d\n",
1029			gpu->identity.vertex_output_buffer_size);
1030	seq_printf(m, "\t buffer_size: %d\n",
1031			gpu->identity.buffer_size);
1032	seq_printf(m, "\t instruction_count: %d\n",
1033			gpu->identity.instruction_count);
1034	seq_printf(m, "\t num_constants: %d\n",
1035			gpu->identity.num_constants);
1036	seq_printf(m, "\t varyings_count: %d\n",
1037			gpu->identity.varyings_count);
1038
1039	seq_printf(m, "\taxi: 0x%08x\n", axi);
1040	seq_printf(m, "\tidle: 0x%08x\n", idle);
1041	idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
1042	if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
1043		seq_puts(m, "\t FE is not idle\n");
1044	if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
1045		seq_puts(m, "\t DE is not idle\n");
1046	if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
1047		seq_puts(m, "\t PE is not idle\n");
1048	if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
1049		seq_puts(m, "\t SH is not idle\n");
1050	if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
1051		seq_puts(m, "\t PA is not idle\n");
1052	if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
1053		seq_puts(m, "\t SE is not idle\n");
1054	if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
1055		seq_puts(m, "\t RA is not idle\n");
1056	if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
1057		seq_puts(m, "\t TX is not idle\n");
1058	if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
1059		seq_puts(m, "\t VG is not idle\n");
1060	if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
1061		seq_puts(m, "\t IM is not idle\n");
1062	if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
1063		seq_puts(m, "\t FP is not idle\n");
1064	if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
1065		seq_puts(m, "\t TS is not idle\n");
1066	if ((idle & VIVS_HI_IDLE_STATE_BL) == 0)
1067		seq_puts(m, "\t BL is not idle\n");
1068	if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0)
1069		seq_puts(m, "\t ASYNCFE is not idle\n");
1070	if ((idle & VIVS_HI_IDLE_STATE_MC) == 0)
1071		seq_puts(m, "\t MC is not idle\n");
1072	if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0)
1073		seq_puts(m, "\t PPA is not idle\n");
1074	if ((idle & VIVS_HI_IDLE_STATE_WD) == 0)
1075		seq_puts(m, "\t WD is not idle\n");
1076	if ((idle & VIVS_HI_IDLE_STATE_NN) == 0)
1077		seq_puts(m, "\t NN is not idle\n");
1078	if ((idle & VIVS_HI_IDLE_STATE_TP) == 0)
1079		seq_puts(m, "\t TP is not idle\n");
1080	if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
1081		seq_puts(m, "\t AXI low power mode\n");
1082
1083	if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
1084		u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
1085		u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
1086		u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
1087
1088		seq_puts(m, "\tMC\n");
1089		seq_printf(m, "\t read0: 0x%08x\n", read0);
1090		seq_printf(m, "\t read1: 0x%08x\n", read1);
1091		seq_printf(m, "\t write: 0x%08x\n", write);
1092	}
1093
1094	seq_puts(m, "\tDMA ");
1095
1096	if (debug.address[0] == debug.address[1] &&
1097	    debug.state[0] == debug.state[1]) {
1098		seq_puts(m, "seems to be stuck\n");
1099	} else if (debug.address[0] == debug.address[1]) {
1100		seq_puts(m, "address is constant\n");
1101	} else {
1102		seq_puts(m, "is running\n");
1103	}
1104
1105	seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
1106	seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
1107	seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
1108	seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
1109	seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
1110		   dma_lo, dma_hi);
1111
1112	ret = 0;
1113
1114	pm_runtime_mark_last_busy(gpu->dev);
1115pm_put:
1116	pm_runtime_put_autosuspend(gpu->dev);
1117
1118	return ret;
1119}
1120#endif
1121
1122/* fence object management */
1123struct etnaviv_fence {
1124	struct etnaviv_gpu *gpu;
1125	struct dma_fence base;
1126};
1127
1128static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1129{
1130	return container_of(fence, struct etnaviv_fence, base);
1131}
1132
1133static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1134{
1135	return "etnaviv";
1136}
1137
1138static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1139{
1140	struct etnaviv_fence *f = to_etnaviv_fence(fence);
1141
1142	return dev_name(f->gpu->dev);
1143}
1144
1145static bool etnaviv_fence_signaled(struct dma_fence *fence)
1146{
1147	struct etnaviv_fence *f = to_etnaviv_fence(fence);
1148
1149	return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1150}
1151
1152static void etnaviv_fence_release(struct dma_fence *fence)
1153{
1154	struct etnaviv_fence *f = to_etnaviv_fence(fence);
1155
1156	kfree_rcu(f, base.rcu);
1157}
1158
1159static const struct dma_fence_ops etnaviv_fence_ops = {
1160	.get_driver_name = etnaviv_fence_get_driver_name,
1161	.get_timeline_name = etnaviv_fence_get_timeline_name,
1162	.signaled = etnaviv_fence_signaled,
1163	.release = etnaviv_fence_release,
1164};
1165
1166static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1167{
1168	struct etnaviv_fence *f;
1169
1170	/*
1171	 * GPU lock must already be held, otherwise fence completion order might
1172	 * not match the seqno order assigned here.
1173	 */
1174	lockdep_assert_held(&gpu->lock);
1175
1176	f = kzalloc(sizeof(*f), GFP_KERNEL);
1177	if (!f)
1178		return NULL;
1179
1180	f->gpu = gpu;
1181
1182	dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1183		       gpu->fence_context, ++gpu->next_fence);
1184
1185	return &f->base;
1186}
1187
1188/* returns true if fence a comes after fence b */
1189static inline bool fence_after(u32 a, u32 b)
1190{
1191	return (s32)(a - b) > 0;
1192}
1193
1194/*
1195 * event management:
1196 */
1197
1198static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1199	unsigned int *events)
1200{
1201	unsigned long timeout = msecs_to_jiffies(10 * 10000);
1202	unsigned i, acquired = 0, rpm_count = 0;
1203	int ret;
1204
1205	for (i = 0; i < nr_events; i++) {
1206		unsigned long remaining;
1207
1208		remaining = wait_for_completion_timeout(&gpu->event_free, timeout);
1209
1210		if (!remaining) {
1211			dev_err(gpu->dev, "wait_for_completion_timeout failed");
1212			ret = -EBUSY;
1213			goto out;
1214		}
1215
1216		acquired++;
1217		timeout = remaining;
1218	}
1219
1220	spin_lock(&gpu->event_spinlock);
1221
1222	for (i = 0; i < nr_events; i++) {
1223		int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1224
1225		events[i] = event;
1226		memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1227		set_bit(event, gpu->event_bitmap);
1228	}
1229
1230	spin_unlock(&gpu->event_spinlock);
1231
1232	for (i = 0; i < nr_events; i++) {
1233		ret = pm_runtime_resume_and_get(gpu->dev);
1234		if (ret)
1235			goto out_rpm;
1236		rpm_count++;
1237	}
1238
1239	return 0;
1240
1241out_rpm:
1242	for (i = 0; i < rpm_count; i++)
1243		pm_runtime_put_autosuspend(gpu->dev);
1244out:
1245	for (i = 0; i < acquired; i++)
1246		complete(&gpu->event_free);
1247
1248	return ret;
1249}
1250
1251static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1252{
1253	if (!test_bit(event, gpu->event_bitmap)) {
1254		dev_warn(gpu->dev, "event %u is already marked as free",
1255			 event);
1256	} else {
1257		clear_bit(event, gpu->event_bitmap);
1258		complete(&gpu->event_free);
1259	}
1260
1261	pm_runtime_put_autosuspend(gpu->dev);
1262}
1263
1264/*
1265 * Cmdstream submission/retirement:
1266 */
1267int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1268	u32 id, struct drm_etnaviv_timespec *timeout)
1269{
1270	struct dma_fence *fence;
1271	int ret;
1272
1273	/*
1274	 * Look up the fence and take a reference. We might still find a fence
1275	 * whose refcount has already dropped to zero. dma_fence_get_rcu
1276	 * pretends we didn't find a fence in that case.
1277	 */
1278	rcu_read_lock();
1279	fence = xa_load(&gpu->user_fences, id);
1280	if (fence)
1281		fence = dma_fence_get_rcu(fence);
1282	rcu_read_unlock();
1283
1284	if (!fence)
1285		return 0;
1286
1287	if (!timeout) {
1288		/* No timeout was requested: just test for completion */
1289		ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1290	} else {
1291		unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1292
1293		ret = dma_fence_wait_timeout(fence, true, remaining);
1294		if (ret == 0)
1295			ret = -ETIMEDOUT;
1296		else if (ret != -ERESTARTSYS)
1297			ret = 0;
1298
1299	}
1300
1301	dma_fence_put(fence);
1302	return ret;
1303}
1304
1305/*
1306 * Wait for an object to become inactive.  This, on it's own, is not race
1307 * free: the object is moved by the scheduler off the active list, and
1308 * then the iova is put.  Moreover, the object could be re-submitted just
1309 * after we notice that it's become inactive.
1310 *
1311 * Although the retirement happens under the gpu lock, we don't want to hold
1312 * that lock in this function while waiting.
1313 */
1314int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1315	struct etnaviv_gem_object *etnaviv_obj,
1316	struct drm_etnaviv_timespec *timeout)
1317{
1318	unsigned long remaining;
1319	long ret;
1320
1321	if (!timeout)
1322		return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1323
1324	remaining = etnaviv_timeout_to_jiffies(timeout);
1325
1326	ret = wait_event_interruptible_timeout(gpu->fence_event,
1327					       !is_active(etnaviv_obj),
1328					       remaining);
1329	if (ret > 0)
1330		return 0;
1331	else if (ret == -ERESTARTSYS)
1332		return -ERESTARTSYS;
1333	else
1334		return -ETIMEDOUT;
1335}
1336
1337static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1338	struct etnaviv_event *event, unsigned int flags)
1339{
1340	const struct etnaviv_gem_submit *submit = event->submit;
1341	unsigned int i;
1342
1343	for (i = 0; i < submit->nr_pmrs; i++) {
1344		const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1345
1346		if (pmr->flags == flags)
1347			etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1348	}
1349}
1350
1351static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1352	struct etnaviv_event *event)
1353{
1354	u32 val;
1355
1356	mutex_lock(&gpu->lock);
1357
1358	/* disable clock gating */
1359	val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
1360	val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1361	gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
1362
1363	sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1364
1365	mutex_unlock(&gpu->lock);
1366}
1367
1368static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1369	struct etnaviv_event *event)
1370{
1371	const struct etnaviv_gem_submit *submit = event->submit;
1372	unsigned int i;
1373	u32 val;
1374
1375	mutex_lock(&gpu->lock);
1376
1377	sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1378
1379	/* enable clock gating */
1380	val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
1381	val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1382	gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
1383
1384	mutex_unlock(&gpu->lock);
1385
1386	for (i = 0; i < submit->nr_pmrs; i++) {
1387		const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1388
1389		*pmr->bo_vma = pmr->sequence;
1390	}
1391}
1392
1393
1394/* add bo's to gpu's ring, and kick gpu: */
1395struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1396{
1397	struct etnaviv_gpu *gpu = submit->gpu;
1398	struct dma_fence *gpu_fence;
1399	unsigned int i, nr_events = 1, event[3];
1400	int ret;
1401
1402	/*
1403	 * if there are performance monitor requests we need to have
1404	 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1405	 *   requests.
1406	 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1407	 *   and update the sequence number for userspace.
1408	 */
1409	if (submit->nr_pmrs)
1410		nr_events = 3;
1411
1412	ret = event_alloc(gpu, nr_events, event);
1413	if (ret) {
1414		DRM_ERROR("no free events\n");
1415		pm_runtime_put_noidle(gpu->dev);
1416		return NULL;
1417	}
1418
1419	mutex_lock(&gpu->lock);
1420
1421	gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1422	if (!gpu_fence) {
1423		for (i = 0; i < nr_events; i++)
1424			event_free(gpu, event[i]);
1425
1426		goto out_unlock;
1427	}
1428
1429	if (gpu->state == ETNA_GPU_STATE_INITIALIZED)
1430		etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context);
1431
1432	if (submit->prev_mmu_context)
1433		etnaviv_iommu_context_put(submit->prev_mmu_context);
1434	submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context);
1435
1436	if (submit->nr_pmrs) {
1437		gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1438		kref_get(&submit->refcount);
1439		gpu->event[event[1]].submit = submit;
1440		etnaviv_sync_point_queue(gpu, event[1]);
1441	}
1442
1443	gpu->event[event[0]].fence = gpu_fence;
1444	submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1445	etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context,
1446			     event[0], &submit->cmdbuf);
1447
1448	if (submit->nr_pmrs) {
1449		gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1450		kref_get(&submit->refcount);
1451		gpu->event[event[2]].submit = submit;
1452		etnaviv_sync_point_queue(gpu, event[2]);
1453	}
1454
1455out_unlock:
1456	mutex_unlock(&gpu->lock);
1457
1458	return gpu_fence;
1459}
1460
1461static void sync_point_worker(struct work_struct *work)
1462{
1463	struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1464					       sync_point_work);
1465	struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1466	u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1467
1468	event->sync_point(gpu, event);
1469	etnaviv_submit_put(event->submit);
1470	event_free(gpu, gpu->sync_point_event);
1471
1472	/* restart FE last to avoid GPU and IRQ racing against this worker */
1473	etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1474}
1475
1476void etnaviv_gpu_recover_hang(struct etnaviv_gem_submit *submit)
1477{
1478	struct etnaviv_gpu *gpu = submit->gpu;
1479	char *comm = NULL, *cmd = NULL;
1480	struct task_struct *task;
1481	unsigned int i;
1482
1483	dev_err(gpu->dev, "recover hung GPU!\n");
1484
1485	task = get_pid_task(submit->pid, PIDTYPE_PID);
1486	if (task) {
1487		comm = kstrdup(task->comm, GFP_KERNEL);
1488		cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
1489		put_task_struct(task);
1490	}
1491
1492	if (comm && cmd)
1493		dev_err(gpu->dev, "offending task: %s (%s)\n", comm, cmd);
1494
1495	kfree(cmd);
1496	kfree(comm);
1497
1498	if (pm_runtime_get_sync(gpu->dev) < 0)
1499		goto pm_put;
1500
1501	mutex_lock(&gpu->lock);
1502
1503	etnaviv_hw_reset(gpu);
1504
1505	/* complete all events, the GPU won't do it after the reset */
1506	spin_lock(&gpu->event_spinlock);
1507	for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS)
1508		event_free(gpu, i);
1509	spin_unlock(&gpu->event_spinlock);
1510
1511	etnaviv_gpu_hw_init(gpu);
1512
1513	mutex_unlock(&gpu->lock);
1514	pm_runtime_mark_last_busy(gpu->dev);
1515pm_put:
1516	pm_runtime_put_autosuspend(gpu->dev);
1517}
1518
1519static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1520{
1521	static const char *fault_reasons[] = {
1522		"slave not present",
1523		"page not present",
1524		"write violation",
1525		"out of bounds",
1526		"read security violation",
1527		"write security violation",
1528	};
1529
1530	u32 status_reg, status;
1531	int i;
1532
1533	if (gpu->sec_mode == ETNA_SEC_NONE)
1534		status_reg = VIVS_MMUv2_STATUS;
1535	else
1536		status_reg = VIVS_MMUv2_SEC_STATUS;
1537
1538	status = gpu_read(gpu, status_reg);
1539	dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1540
1541	for (i = 0; i < 4; i++) {
1542		const char *reason = "unknown";
1543		u32 address_reg;
1544		u32 mmu_status;
1545
1546		mmu_status = (status >> (i * 4)) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK;
1547		if (!mmu_status)
1548			continue;
1549
1550		if ((mmu_status - 1) < ARRAY_SIZE(fault_reasons))
1551			reason = fault_reasons[mmu_status - 1];
1552
1553		if (gpu->sec_mode == ETNA_SEC_NONE)
1554			address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1555		else
1556			address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1557
1558		dev_err_ratelimited(gpu->dev,
1559				    "MMU %d fault (%s) addr 0x%08x\n",
1560				    i, reason, gpu_read(gpu, address_reg));
1561	}
1562}
1563
1564static irqreturn_t irq_handler(int irq, void *data)
1565{
1566	struct etnaviv_gpu *gpu = data;
1567	irqreturn_t ret = IRQ_NONE;
1568
1569	u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1570
1571	if (intr != 0) {
1572		ktime_t now = ktime_get();
1573		int event;
1574
1575		pm_runtime_mark_last_busy(gpu->dev);
1576
1577		dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1578
1579		if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1580			dev_err(gpu->dev, "AXI bus error\n");
1581			intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1582		}
1583
1584		if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1585			dump_mmu_fault(gpu);
1586			gpu->state = ETNA_GPU_STATE_FAULT;
1587			drm_sched_fault(&gpu->sched);
1588			intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1589		}
1590
1591		while ((event = ffs(intr)) != 0) {
1592			struct dma_fence *fence;
1593
1594			event -= 1;
1595
1596			intr &= ~(1 << event);
1597
1598			dev_dbg(gpu->dev, "event %u\n", event);
1599
1600			if (gpu->event[event].sync_point) {
1601				gpu->sync_point_event = event;
1602				queue_work(gpu->wq, &gpu->sync_point_work);
1603			}
1604
1605			fence = gpu->event[event].fence;
1606			if (!fence)
1607				continue;
1608
1609			gpu->event[event].fence = NULL;
1610
1611			/*
1612			 * Events can be processed out of order.  Eg,
1613			 * - allocate and queue event 0
1614			 * - allocate event 1
1615			 * - event 0 completes, we process it
1616			 * - allocate and queue event 0
1617			 * - event 1 and event 0 complete
1618			 * we can end up processing event 0 first, then 1.
1619			 */
1620			if (fence_after(fence->seqno, gpu->completed_fence))
1621				gpu->completed_fence = fence->seqno;
1622			dma_fence_signal_timestamp(fence, now);
1623
1624			event_free(gpu, event);
1625		}
1626
1627		ret = IRQ_HANDLED;
1628	}
1629
1630	return ret;
1631}
1632
1633static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1634{
1635	int ret;
1636
1637	ret = clk_prepare_enable(gpu->clk_reg);
1638	if (ret)
1639		return ret;
1640
1641	ret = clk_prepare_enable(gpu->clk_bus);
1642	if (ret)
1643		goto disable_clk_reg;
1644
1645	ret = clk_prepare_enable(gpu->clk_core);
1646	if (ret)
1647		goto disable_clk_bus;
1648
1649	ret = clk_prepare_enable(gpu->clk_shader);
1650	if (ret)
1651		goto disable_clk_core;
1652
1653	return 0;
1654
1655disable_clk_core:
1656	clk_disable_unprepare(gpu->clk_core);
1657disable_clk_bus:
1658	clk_disable_unprepare(gpu->clk_bus);
1659disable_clk_reg:
1660	clk_disable_unprepare(gpu->clk_reg);
1661
1662	return ret;
1663}
1664
1665static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1666{
1667	clk_disable_unprepare(gpu->clk_shader);
1668	clk_disable_unprepare(gpu->clk_core);
1669	clk_disable_unprepare(gpu->clk_bus);
1670	clk_disable_unprepare(gpu->clk_reg);
1671
1672	return 0;
1673}
1674
1675int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1676{
1677	unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1678
1679	do {
1680		u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1681
1682		if ((idle & gpu->idle_mask) == gpu->idle_mask)
1683			return 0;
1684
1685		if (time_is_before_jiffies(timeout)) {
1686			dev_warn(gpu->dev,
1687				 "timed out waiting for idle: idle=0x%x\n",
1688				 idle);
1689			return -ETIMEDOUT;
1690		}
1691
1692		udelay(5);
1693	} while (1);
1694}
1695
1696static void etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1697{
1698	if (gpu->state == ETNA_GPU_STATE_RUNNING) {
1699		/* Replace the last WAIT with END */
1700		mutex_lock(&gpu->lock);
1701		etnaviv_buffer_end(gpu);
1702		mutex_unlock(&gpu->lock);
1703
1704		/*
1705		 * We know that only the FE is busy here, this should
1706		 * happen quickly (as the WAIT is only 200 cycles).  If
1707		 * we fail, just warn and continue.
1708		 */
1709		etnaviv_gpu_wait_idle(gpu, 100);
1710
1711		gpu->state = ETNA_GPU_STATE_INITIALIZED;
1712	}
1713
1714	gpu->exec_state = -1;
1715}
1716
1717static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1718{
1719	int ret;
1720
1721	ret = mutex_lock_killable(&gpu->lock);
1722	if (ret)
1723		return ret;
1724
1725	etnaviv_gpu_update_clock(gpu);
1726	etnaviv_gpu_hw_init(gpu);
1727
1728	mutex_unlock(&gpu->lock);
1729
1730	return 0;
1731}
1732
1733static int
1734etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1735				  unsigned long *state)
1736{
1737	*state = 6;
1738
1739	return 0;
1740}
1741
1742static int
1743etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1744				  unsigned long *state)
1745{
1746	struct etnaviv_gpu *gpu = cdev->devdata;
1747
1748	*state = gpu->freq_scale;
1749
1750	return 0;
1751}
1752
1753static int
1754etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1755				  unsigned long state)
1756{
1757	struct etnaviv_gpu *gpu = cdev->devdata;
1758
1759	mutex_lock(&gpu->lock);
1760	gpu->freq_scale = state;
1761	if (!pm_runtime_suspended(gpu->dev))
1762		etnaviv_gpu_update_clock(gpu);
1763	mutex_unlock(&gpu->lock);
1764
1765	return 0;
1766}
1767
1768static const struct thermal_cooling_device_ops cooling_ops = {
1769	.get_max_state = etnaviv_gpu_cooling_get_max_state,
1770	.get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1771	.set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1772};
1773
1774static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1775	void *data)
1776{
1777	struct drm_device *drm = data;
1778	struct etnaviv_drm_private *priv = drm->dev_private;
1779	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1780	int ret;
1781
1782	if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1783		gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1784				(char *)dev_name(dev), gpu, &cooling_ops);
1785		if (IS_ERR(gpu->cooling))
1786			return PTR_ERR(gpu->cooling);
1787	}
1788
1789	gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1790	if (!gpu->wq) {
1791		ret = -ENOMEM;
1792		goto out_thermal;
1793	}
1794
1795	ret = etnaviv_sched_init(gpu);
1796	if (ret)
1797		goto out_workqueue;
1798
1799	if (!IS_ENABLED(CONFIG_PM)) {
1800		ret = etnaviv_gpu_clk_enable(gpu);
1801		if (ret < 0)
1802			goto out_sched;
1803	}
1804
1805	gpu->drm = drm;
1806	gpu->fence_context = dma_fence_context_alloc(1);
1807	xa_init_flags(&gpu->user_fences, XA_FLAGS_ALLOC);
1808	spin_lock_init(&gpu->fence_spinlock);
1809
1810	INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1811	init_waitqueue_head(&gpu->fence_event);
1812
1813	priv->gpu[priv->num_gpus++] = gpu;
1814
1815	return 0;
1816
1817out_sched:
1818	etnaviv_sched_fini(gpu);
1819
1820out_workqueue:
1821	destroy_workqueue(gpu->wq);
1822
1823out_thermal:
1824	if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1825		thermal_cooling_device_unregister(gpu->cooling);
1826
1827	return ret;
1828}
1829
1830static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1831	void *data)
1832{
1833	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1834
1835	DBG("%s", dev_name(gpu->dev));
1836
1837	destroy_workqueue(gpu->wq);
1838
1839	etnaviv_sched_fini(gpu);
1840
1841	if (IS_ENABLED(CONFIG_PM)) {
1842		pm_runtime_get_sync(gpu->dev);
1843		pm_runtime_put_sync_suspend(gpu->dev);
1844	} else {
1845		etnaviv_gpu_hw_suspend(gpu);
1846		etnaviv_gpu_clk_disable(gpu);
1847	}
1848
1849	if (gpu->mmu_context)
1850		etnaviv_iommu_context_put(gpu->mmu_context);
1851
1852	etnaviv_cmdbuf_free(&gpu->buffer);
1853	etnaviv_iommu_global_fini(gpu);
1854
1855	gpu->drm = NULL;
1856	xa_destroy(&gpu->user_fences);
1857
1858	if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1859		thermal_cooling_device_unregister(gpu->cooling);
1860	gpu->cooling = NULL;
1861}
1862
1863static const struct component_ops gpu_ops = {
1864	.bind = etnaviv_gpu_bind,
1865	.unbind = etnaviv_gpu_unbind,
1866};
1867
1868static const struct of_device_id etnaviv_gpu_match[] = {
1869	{
1870		.compatible = "vivante,gc"
1871	},
1872	{ /* sentinel */ }
1873};
1874MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1875
1876static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1877{
1878	struct device *dev = &pdev->dev;
1879	struct etnaviv_gpu *gpu;
1880	int err;
1881
1882	gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1883	if (!gpu)
1884		return -ENOMEM;
1885
1886	gpu->dev = dev;
1887	mutex_init(&gpu->lock);
1888	mutex_init(&gpu->sched_lock);
1889
1890	/* Map registers: */
1891	gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
1892	if (IS_ERR(gpu->mmio))
1893		return PTR_ERR(gpu->mmio);
1894
1895
1896	/* Get Reset: */
1897	gpu->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1898	if (IS_ERR(gpu->rst))
1899		return dev_err_probe(dev, PTR_ERR(gpu->rst),
1900				     "failed to get reset\n");
1901
1902	err = reset_control_assert(gpu->rst);
1903	if (err)
1904		return dev_err_probe(dev, err, "failed to assert reset\n");
1905
1906	/* Get Interrupt: */
1907	gpu->irq = platform_get_irq(pdev, 0);
1908	if (gpu->irq < 0)
1909		return gpu->irq;
1910
1911	err = devm_request_irq(dev, gpu->irq, irq_handler, 0,
1912			       dev_name(dev), gpu);
1913	if (err) {
1914		dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1915		return err;
1916	}
1917
1918	/* Get Clocks: */
1919	gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg");
1920	DBG("clk_reg: %p", gpu->clk_reg);
1921	if (IS_ERR(gpu->clk_reg))
1922		return PTR_ERR(gpu->clk_reg);
1923
1924	gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus");
1925	DBG("clk_bus: %p", gpu->clk_bus);
1926	if (IS_ERR(gpu->clk_bus))
1927		return PTR_ERR(gpu->clk_bus);
1928
1929	gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1930	DBG("clk_core: %p", gpu->clk_core);
1931	if (IS_ERR(gpu->clk_core))
1932		return PTR_ERR(gpu->clk_core);
1933	gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1934
1935	gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader");
1936	DBG("clk_shader: %p", gpu->clk_shader);
1937	if (IS_ERR(gpu->clk_shader))
1938		return PTR_ERR(gpu->clk_shader);
1939	gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1940
1941	/* TODO: figure out max mapped size */
1942	dev_set_drvdata(dev, gpu);
1943
1944	/*
1945	 * We treat the device as initially suspended.  The runtime PM
1946	 * autosuspend delay is rather arbitary: no measurements have
1947	 * yet been performed to determine an appropriate value.
1948	 */
1949	pm_runtime_use_autosuspend(dev);
1950	pm_runtime_set_autosuspend_delay(dev, 200);
1951	pm_runtime_enable(dev);
1952
1953	err = component_add(dev, &gpu_ops);
1954	if (err < 0) {
1955		dev_err(dev, "failed to register component: %d\n", err);
1956		return err;
1957	}
1958
1959	return 0;
1960}
1961
1962static void etnaviv_gpu_platform_remove(struct platform_device *pdev)
1963{
1964	struct etnaviv_gpu *gpu = dev_get_drvdata(&pdev->dev);
1965
1966	component_del(&pdev->dev, &gpu_ops);
1967	pm_runtime_disable(&pdev->dev);
1968
1969	mutex_destroy(&gpu->lock);
1970	mutex_destroy(&gpu->sched_lock);
1971}
1972
1973static int etnaviv_gpu_rpm_suspend(struct device *dev)
1974{
1975	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1976	u32 idle, mask;
1977
1978	/* If there are any jobs in the HW queue, we're not idle */
1979	if (atomic_read(&gpu->sched.credit_count))
1980		return -EBUSY;
1981
1982	/* Check whether the hardware (except FE and MC) is idle */
1983	mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE |
1984				  VIVS_HI_IDLE_STATE_MC);
1985	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1986	if (idle != mask) {
1987		dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n",
1988				     idle);
1989		return -EBUSY;
1990	}
1991
1992	etnaviv_gpu_hw_suspend(gpu);
1993
1994	gpu->state = ETNA_GPU_STATE_IDENTIFIED;
1995
1996	return etnaviv_gpu_clk_disable(gpu);
1997}
1998
1999static int etnaviv_gpu_rpm_resume(struct device *dev)
2000{
2001	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
2002	int ret;
2003
2004	ret = etnaviv_gpu_clk_enable(gpu);
2005	if (ret)
2006		return ret;
2007
2008	/* Re-initialise the basic hardware state */
2009	if (gpu->state == ETNA_GPU_STATE_IDENTIFIED) {
2010		ret = etnaviv_gpu_hw_resume(gpu);
2011		if (ret) {
2012			etnaviv_gpu_clk_disable(gpu);
2013			return ret;
2014		}
2015	}
2016
2017	return 0;
2018}
2019
2020static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
2021	RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, NULL)
2022};
2023
2024struct platform_driver etnaviv_gpu_driver = {
2025	.driver = {
2026		.name = "etnaviv-gpu",
2027		.pm = pm_ptr(&etnaviv_gpu_pm_ops),
2028		.of_match_table = etnaviv_gpu_match,
2029	},
2030	.probe = etnaviv_gpu_platform_probe,
2031	.remove = etnaviv_gpu_platform_remove,
2032	.id_table = gpu_ids,
2033};