drm_mipi_dbi.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * MIPI Display Bus Interface (DBI) LCD controller support
   4 *
   5 * Copyright 2016 Noralf Trønnes
   6 */
   7
   8#include <linux/backlight.h>
   9#include <linux/debugfs.h>
  10#include <linux/delay.h>
  11#include <linux/export.h>
  12#include <linux/gpio/consumer.h>
  13#include <linux/module.h>
  14#include <linux/regulator/consumer.h>
  15#include <linux/spi/spi.h>
  16
  17#include <drm/drm_connector.h>
  18#include <drm/drm_damage_helper.h>
  19#include <drm/drm_drv.h>
  20#include <drm/drm_file.h>
  21#include <drm/drm_format_helper.h>
  22#include <drm/drm_fourcc.h>
  23#include <drm/drm_framebuffer.h>
  24#include <drm/drm_gem.h>
  25#include <drm/drm_gem_atomic_helper.h>
  26#include <drm/drm_gem_framebuffer_helper.h>
  27#include <drm/drm_mipi_dbi.h>
  28#include <drm/drm_modes.h>
  29#include <drm/drm_print.h>
  30#include <drm/drm_probe_helper.h>
  31#include <drm/drm_rect.h>
  32#include <video/mipi_display.h>
  33
  34#define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */
  35
  36#define DCS_POWER_MODE_DISPLAY			BIT(2)
  37#define DCS_POWER_MODE_DISPLAY_NORMAL_MODE	BIT(3)
  38#define DCS_POWER_MODE_SLEEP_MODE		BIT(4)
  39#define DCS_POWER_MODE_PARTIAL_MODE		BIT(5)
  40#define DCS_POWER_MODE_IDLE_MODE		BIT(6)
  41#define DCS_POWER_MODE_RESERVED_MASK		(BIT(0) | BIT(1) | BIT(7))
  42
  43/**
  44 * DOC: overview
  45 *
  46 * This library provides helpers for MIPI Display Bus Interface (DBI)
  47 * compatible display controllers.
  48 *
  49 * Many controllers for tiny lcd displays are MIPI compliant and can use this
  50 * library. If a controller uses registers 0x2A and 0x2B to set the area to
  51 * update and uses register 0x2C to write to frame memory, it is most likely
  52 * MIPI compliant.
  53 *
  54 * Only MIPI Type 1 displays are supported since a full frame memory is needed.
  55 *
  56 * There are 3 MIPI DBI implementation types:
  57 *
  58 * A. Motorola 6800 type parallel bus
  59 *
  60 * B. Intel 8080 type parallel bus
  61 *
  62 * C. SPI type with 3 options:
  63 *
  64 *    1. 9-bit with the Data/Command signal as the ninth bit
  65 *    2. Same as above except it's sent as 16 bits
  66 *    3. 8-bit with the Data/Command signal as a separate D/CX pin
  67 *
  68 * Currently mipi_dbi only supports Type C options 1 and 3 with
  69 * mipi_dbi_spi_init().
  70 */
  71
  72#define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \
  73({ \
  74	if (!len) \
  75		DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \
  76	else if (len <= 32) \
  77		DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\
  78	else \
  79		DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \
  80})
  81
  82static const u8 mipi_dbi_dcs_read_commands[] = {
  83	MIPI_DCS_GET_DISPLAY_ID,
  84	MIPI_DCS_GET_RED_CHANNEL,
  85	MIPI_DCS_GET_GREEN_CHANNEL,
  86	MIPI_DCS_GET_BLUE_CHANNEL,
  87	MIPI_DCS_GET_DISPLAY_STATUS,
  88	MIPI_DCS_GET_POWER_MODE,
  89	MIPI_DCS_GET_ADDRESS_MODE,
  90	MIPI_DCS_GET_PIXEL_FORMAT,
  91	MIPI_DCS_GET_DISPLAY_MODE,
  92	MIPI_DCS_GET_SIGNAL_MODE,
  93	MIPI_DCS_GET_DIAGNOSTIC_RESULT,
  94	MIPI_DCS_READ_MEMORY_START,
  95	MIPI_DCS_READ_MEMORY_CONTINUE,
  96	MIPI_DCS_GET_SCANLINE,
  97	MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
  98	MIPI_DCS_GET_CONTROL_DISPLAY,
  99	MIPI_DCS_GET_POWER_SAVE,
 100	MIPI_DCS_GET_CABC_MIN_BRIGHTNESS,
 101	MIPI_DCS_READ_DDB_START,
 102	MIPI_DCS_READ_DDB_CONTINUE,
 103	0, /* sentinel */
 104};
 105
 106static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd)
 107{
 108	unsigned int i;
 109
 110	if (!dbi->read_commands)
 111		return false;
 112
 113	for (i = 0; i < 0xff; i++) {
 114		if (!dbi->read_commands[i])
 115			return false;
 116		if (cmd == dbi->read_commands[i])
 117			return true;
 118	}
 119
 120	return false;
 121}
 122
 123/**
 124 * mipi_dbi_command_read - MIPI DCS read command
 125 * @dbi: MIPI DBI structure
 126 * @cmd: Command
 127 * @val: Value read
 128 *
 129 * Send MIPI DCS read command to the controller.
 130 *
 131 * Returns:
 132 * Zero on success, negative error code on failure.
 133 */
 134int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val)
 135{
 136	if (!dbi->read_commands)
 137		return -EACCES;
 138
 139	if (!mipi_dbi_command_is_read(dbi, cmd))
 140		return -EINVAL;
 141
 142	return mipi_dbi_command_buf(dbi, cmd, val, 1);
 143}
 144EXPORT_SYMBOL(mipi_dbi_command_read);
 145
 146/**
 147 * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array
 148 * @dbi: MIPI DBI structure
 149 * @cmd: Command
 150 * @data: Parameter buffer
 151 * @len: Buffer length
 152 *
 153 * Returns:
 154 * Zero on success, negative error code on failure.
 155 */
 156int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
 157{
 158	u8 *cmdbuf;
 159	int ret;
 160
 161	/* SPI requires dma-safe buffers */
 162	cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL);
 163	if (!cmdbuf)
 164		return -ENOMEM;
 165
 166	mutex_lock(&dbi->cmdlock);
 167	ret = dbi->command(dbi, cmdbuf, data, len);
 168	mutex_unlock(&dbi->cmdlock);
 169
 170	kfree(cmdbuf);
 171
 172	return ret;
 173}
 174EXPORT_SYMBOL(mipi_dbi_command_buf);
 175
 176/* This should only be used by mipi_dbi_command() */
 177int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, const u8 *data,
 178			      size_t len)
 179{
 180	u8 *buf;
 181	int ret;
 182
 183	buf = kmemdup(data, len, GFP_KERNEL);
 184	if (!buf)
 185		return -ENOMEM;
 186
 187	ret = mipi_dbi_command_buf(dbi, cmd, buf, len);
 188
 189	kfree(buf);
 190
 191	return ret;
 192}
 193EXPORT_SYMBOL(mipi_dbi_command_stackbuf);
 194
 195/**
 196 * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary
 197 * @dst: The destination buffer
 198 * @src: The source buffer
 199 * @fb: The source framebuffer
 200 * @clip: Clipping rectangle of the area to be copied
 201 * @swap: When true, swap MSB/LSB of 16-bit values
 202 * @fmtcnv_state: Format-conversion state
 203 *
 204 * Returns:
 205 * Zero on success, negative error code on failure.
 206 */
 207int mipi_dbi_buf_copy(void *dst, struct iosys_map *src, struct drm_framebuffer *fb,
 208		      struct drm_rect *clip, bool swap,
 209		      struct drm_format_conv_state *fmtcnv_state)
 210{
 211	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
 212	struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
 213	struct iosys_map dst_map = IOSYS_MAP_INIT_VADDR(dst);
 214	int ret;
 215
 216	ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
 217	if (ret)
 218		return ret;
 219
 220	switch (fb->format->format) {
 221	case DRM_FORMAT_RGB565:
 222		if (swap)
 223			drm_fb_swab(&dst_map, NULL, src, fb, clip, !drm_gem_is_imported(gem),
 224				    fmtcnv_state);
 225		else
 226			drm_fb_memcpy(&dst_map, NULL, src, fb, clip);
 227		break;
 228	case DRM_FORMAT_RGB888:
 229		drm_fb_memcpy(&dst_map, NULL, src, fb, clip);
 230		break;
 231	case DRM_FORMAT_XRGB8888:
 232		switch (dbidev->pixel_format) {
 233		case DRM_FORMAT_RGB565:
 234			if (swap) {
 235				drm_fb_xrgb8888_to_rgb565be(&dst_map, NULL, src, fb, clip,
 236							    fmtcnv_state);
 237			} else {
 238				drm_fb_xrgb8888_to_rgb565(&dst_map, NULL, src, fb, clip,
 239							  fmtcnv_state);
 240			}
 241			break;
 242		case DRM_FORMAT_RGB888:
 243			drm_fb_xrgb8888_to_rgb888(&dst_map, NULL, src, fb, clip, fmtcnv_state);
 244			break;
 245		}
 246		break;
 247	default:
 248		drm_err_once(fb->dev, "Format is not supported: %p4cc\n",
 249			     &fb->format->format);
 250		ret = -EINVAL;
 251	}
 252
 253	drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
 254
 255	return ret;
 256}
 257EXPORT_SYMBOL(mipi_dbi_buf_copy);
 258
 259static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev,
 260					unsigned int xs, unsigned int xe,
 261					unsigned int ys, unsigned int ye)
 262{
 263	struct mipi_dbi *dbi = &dbidev->dbi;
 264
 265	xs += dbidev->left_offset;
 266	xe += dbidev->left_offset;
 267	ys += dbidev->top_offset;
 268	ye += dbidev->top_offset;
 269
 270	mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff,
 271			 xs & 0xff, (xe >> 8) & 0xff, xe & 0xff);
 272	mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff,
 273			 ys & 0xff, (ye >> 8) & 0xff, ye & 0xff);
 274}
 275
 276static void mipi_dbi_fb_dirty(struct iosys_map *src, struct drm_framebuffer *fb,
 277			      struct drm_rect *rect, struct drm_format_conv_state *fmtcnv_state)
 278{
 279	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
 280	unsigned int height = rect->y2 - rect->y1;
 281	unsigned int width = rect->x2 - rect->x1;
 282	const struct drm_format_info *dst_format;
 283	struct mipi_dbi *dbi = &dbidev->dbi;
 284	bool swap = dbi->swap_bytes;
 285	int ret = 0;
 286	size_t len;
 287	bool full;
 288	void *tr;
 289
 290	full = width == fb->width && height == fb->height;
 291
 292	DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
 293
 294	if (!dbi->dc || !full || swap ||
 295	    fb->format->format == DRM_FORMAT_XRGB8888) {
 296		tr = dbidev->tx_buf;
 297		ret = mipi_dbi_buf_copy(tr, src, fb, rect, swap, fmtcnv_state);
 298		if (ret)
 299			goto err_msg;
 300	} else {
 301		tr = src->vaddr; /* TODO: Use mapping abstraction properly */
 302	}
 303
 304	mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1,
 305				    rect->y2 - 1);
 306
 307	if (fb->format->format == DRM_FORMAT_XRGB8888)
 308		dst_format = drm_format_info(dbidev->pixel_format);
 309	else
 310		dst_format = fb->format;
 311	len = drm_format_info_min_pitch(dst_format, 0, width) * height;
 312
 313	ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr, len);
 314err_msg:
 315	if (ret)
 316		drm_err_once(fb->dev, "Failed to update display %d\n", ret);
 317}
 318
 319/**
 320 * mipi_dbi_pipe_mode_valid - MIPI DBI mode-valid helper
 321 * @pipe: Simple display pipe
 322 * @mode: The mode to test
 323 *
 324 * This function validates a given display mode against the MIPI DBI's hardware
 325 * display. Drivers can use this as their &drm_simple_display_pipe_funcs->mode_valid
 326 * callback.
 327 */
 328enum drm_mode_status mipi_dbi_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
 329					      const struct drm_display_mode *mode)
 330{
 331	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
 332
 333	return drm_crtc_helper_mode_valid_fixed(&pipe->crtc, mode, &dbidev->mode);
 334}
 335EXPORT_SYMBOL(mipi_dbi_pipe_mode_valid);
 336
 337/**
 338 * mipi_dbi_pipe_update - Display pipe update helper
 339 * @pipe: Simple display pipe
 340 * @old_state: Old plane state
 341 *
 342 * This function handles framebuffer flushing and vblank events. Drivers can use
 343 * this as their &drm_simple_display_pipe_funcs->update callback.
 344 */
 345void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
 346			  struct drm_plane_state *old_state)
 347{
 348	struct drm_plane_state *state = pipe->plane.state;
 349	struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state);
 350	struct drm_framebuffer *fb = state->fb;
 351	struct drm_rect rect;
 352	int idx;
 353
 354	if (!pipe->crtc.state->active)
 355		return;
 356
 357	if (WARN_ON(!fb))
 358		return;
 359
 360	if (!drm_dev_enter(fb->dev, &idx))
 361		return;
 362
 363	if (drm_atomic_helper_damage_merged(old_state, state, &rect))
 364		mipi_dbi_fb_dirty(&shadow_plane_state->data[0], fb, &rect,
 365				  &shadow_plane_state->fmtcnv_state);
 366
 367	drm_dev_exit(idx);
 368}
 369EXPORT_SYMBOL(mipi_dbi_pipe_update);
 370
 371/**
 372 * mipi_dbi_enable_flush - MIPI DBI enable helper
 373 * @dbidev: MIPI DBI device structure
 374 * @crtc_state: CRTC state
 375 * @plane_state: Plane state
 376 *
 377 * Flushes the whole framebuffer and enables the backlight. Drivers can use this
 378 * in their &drm_simple_display_pipe_funcs->enable callback.
 379 *
 380 * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom
 381 * framebuffer flushing, can't use this function since they both use the same
 382 * flushing code.
 383 */
 384void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev,
 385			   struct drm_crtc_state *crtc_state,
 386			   struct drm_plane_state *plane_state)
 387{
 388	struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
 389	struct drm_framebuffer *fb = plane_state->fb;
 390	struct drm_rect rect = {
 391		.x1 = 0,
 392		.x2 = fb->width,
 393		.y1 = 0,
 394		.y2 = fb->height,
 395	};
 396	int idx;
 397
 398	if (!drm_dev_enter(&dbidev->drm, &idx))
 399		return;
 400
 401	mipi_dbi_fb_dirty(&shadow_plane_state->data[0], fb, &rect,
 402			  &shadow_plane_state->fmtcnv_state);
 403	backlight_enable(dbidev->backlight);
 404
 405	drm_dev_exit(idx);
 406}
 407EXPORT_SYMBOL(mipi_dbi_enable_flush);
 408
 409static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev)
 410{
 411	struct drm_device *drm = &dbidev->drm;
 412	u16 height = drm->mode_config.min_height;
 413	u16 width = drm->mode_config.min_width;
 414	struct mipi_dbi *dbi = &dbidev->dbi;
 415	const struct drm_format_info *dst_format;
 416	size_t len;
 417	int idx;
 418
 419	if (!drm_dev_enter(drm, &idx))
 420		return;
 421
 422	dst_format = drm_format_info(dbidev->pixel_format);
 423	len = drm_format_info_min_pitch(dst_format, 0, width) * height;
 424
 425	memset(dbidev->tx_buf, 0, len);
 426
 427	mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1);
 428	mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
 429			     (u8 *)dbidev->tx_buf, len);
 430
 431	drm_dev_exit(idx);
 432}
 433
 434/**
 435 * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper
 436 * @pipe: Display pipe
 437 *
 438 * This function disables backlight if present, if not the display memory is
 439 * blanked. The regulator is disabled if in use. Drivers can use this as their
 440 * &drm_simple_display_pipe_funcs->disable callback.
 441 */
 442void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe)
 443{
 444	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
 445
 446	DRM_DEBUG_KMS("\n");
 447
 448	if (dbidev->backlight)
 449		backlight_disable(dbidev->backlight);
 450	else
 451		mipi_dbi_blank(dbidev);
 452
 453	if (dbidev->regulator)
 454		regulator_disable(dbidev->regulator);
 455	if (dbidev->io_regulator)
 456		regulator_disable(dbidev->io_regulator);
 457}
 458EXPORT_SYMBOL(mipi_dbi_pipe_disable);
 459
 460/**
 461 * mipi_dbi_pipe_begin_fb_access - MIPI DBI pipe begin-access helper
 462 * @pipe: Display pipe
 463 * @plane_state: Plane state
 464 *
 465 * This function implements struct &drm_simple_display_funcs.begin_fb_access.
 466 *
 467 * See drm_gem_begin_shadow_fb_access() for details and mipi_dbi_pipe_cleanup_fb()
 468 * for cleanup.
 469 *
 470 * Returns:
 471 * 0 on success, or a negative errno code otherwise.
 472 */
 473int mipi_dbi_pipe_begin_fb_access(struct drm_simple_display_pipe *pipe,
 474				  struct drm_plane_state *plane_state)
 475{
 476	return drm_gem_begin_shadow_fb_access(&pipe->plane, plane_state);
 477}
 478EXPORT_SYMBOL(mipi_dbi_pipe_begin_fb_access);
 479
 480/**
 481 * mipi_dbi_pipe_end_fb_access - MIPI DBI pipe end-access helper
 482 * @pipe: Display pipe
 483 * @plane_state: Plane state
 484 *
 485 * This function implements struct &drm_simple_display_funcs.end_fb_access.
 486 *
 487 * See mipi_dbi_pipe_begin_fb_access().
 488 */
 489void mipi_dbi_pipe_end_fb_access(struct drm_simple_display_pipe *pipe,
 490				 struct drm_plane_state *plane_state)
 491{
 492	drm_gem_end_shadow_fb_access(&pipe->plane, plane_state);
 493}
 494EXPORT_SYMBOL(mipi_dbi_pipe_end_fb_access);
 495
 496/**
 497 * mipi_dbi_pipe_reset_plane - MIPI DBI plane-reset helper
 498 * @pipe: Display pipe
 499 *
 500 * This function implements struct &drm_simple_display_funcs.reset_plane
 501 * for MIPI DBI planes.
 502 */
 503void mipi_dbi_pipe_reset_plane(struct drm_simple_display_pipe *pipe)
 504{
 505	drm_gem_reset_shadow_plane(&pipe->plane);
 506}
 507EXPORT_SYMBOL(mipi_dbi_pipe_reset_plane);
 508
 509/**
 510 * mipi_dbi_pipe_duplicate_plane_state - duplicates MIPI DBI plane state
 511 * @pipe: Display pipe
 512 *
 513 * This function implements struct &drm_simple_display_funcs.duplicate_plane_state
 514 * for MIPI DBI planes.
 515 *
 516 * See drm_gem_duplicate_shadow_plane_state() for additional details.
 517 *
 518 * Returns:
 519 * A pointer to a new plane state on success, or NULL otherwise.
 520 */
 521struct drm_plane_state *mipi_dbi_pipe_duplicate_plane_state(struct drm_simple_display_pipe *pipe)
 522{
 523	return drm_gem_duplicate_shadow_plane_state(&pipe->plane);
 524}
 525EXPORT_SYMBOL(mipi_dbi_pipe_duplicate_plane_state);
 526
 527/**
 528 * mipi_dbi_pipe_destroy_plane_state - cleans up MIPI DBI plane state
 529 * @pipe: Display pipe
 530 * @plane_state: Plane state
 531 *
 532 * This function implements struct drm_simple_display_funcs.destroy_plane_state
 533 * for MIPI DBI planes.
 534 *
 535 * See drm_gem_destroy_shadow_plane_state() for additional details.
 536 */
 537void mipi_dbi_pipe_destroy_plane_state(struct drm_simple_display_pipe *pipe,
 538				       struct drm_plane_state *plane_state)
 539{
 540	drm_gem_destroy_shadow_plane_state(&pipe->plane, plane_state);
 541}
 542EXPORT_SYMBOL(mipi_dbi_pipe_destroy_plane_state);
 543
 544static int mipi_dbi_connector_get_modes(struct drm_connector *connector)
 545{
 546	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev);
 547
 548	return drm_connector_helper_get_modes_fixed(connector, &dbidev->mode);
 549}
 550
 551static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = {
 552	.get_modes = mipi_dbi_connector_get_modes,
 553};
 554
 555static const struct drm_connector_funcs mipi_dbi_connector_funcs = {
 556	.reset = drm_atomic_helper_connector_reset,
 557	.fill_modes = drm_helper_probe_single_connector_modes,
 558	.destroy = drm_connector_cleanup,
 559	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 560	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 561};
 562
 563static int mipi_dbi_rotate_mode(struct drm_display_mode *mode,
 564				unsigned int rotation)
 565{
 566	if (rotation == 0 || rotation == 180) {
 567		return 0;
 568	} else if (rotation == 90 || rotation == 270) {
 569		swap(mode->hdisplay, mode->vdisplay);
 570		swap(mode->hsync_start, mode->vsync_start);
 571		swap(mode->hsync_end, mode->vsync_end);
 572		swap(mode->htotal, mode->vtotal);
 573		swap(mode->width_mm, mode->height_mm);
 574		return 0;
 575	} else {
 576		return -EINVAL;
 577	}
 578}
 579
 580static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = {
 581	.fb_create = drm_gem_fb_create_with_dirty,
 582	.atomic_check = drm_atomic_helper_check,
 583	.atomic_commit = drm_atomic_helper_commit,
 584};
 585
 586static const uint32_t mipi_dbi_formats[] = {
 587	DRM_FORMAT_RGB565,
 588	DRM_FORMAT_XRGB8888,
 589};
 590
 591/**
 592 * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats
 593 * @dbidev: MIPI DBI device structure to initialize
 594 * @funcs: Display pipe functions
 595 * @formats: Array of supported formats (DRM_FORMAT\_\*).
 596 * @format_count: Number of elements in @formats
 597 * @mode: Display mode
 598 * @rotation: Initial rotation in degrees Counter Clock Wise
 599 * @tx_buf_size: Allocate a transmit buffer of this size.
 600 *
 601 * This function sets up a &drm_simple_display_pipe with a &drm_connector that
 602 * has one fixed &drm_display_mode which is rotated according to @rotation.
 603 * This mode is used to set the mode config min/max width/height properties.
 604 *
 605 * Use mipi_dbi_dev_init() if you want native RGB565 and emulated XRGB8888 format.
 606 *
 607 * Note:
 608 * Some of the helper functions expects RGB565 to be the default format and the
 609 * transmit buffer sized to fit that.
 610 *
 611 * Returns:
 612 * Zero on success, negative error code on failure.
 613 */
 614int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev,
 615				   const struct drm_simple_display_pipe_funcs *funcs,
 616				   const uint32_t *formats, unsigned int format_count,
 617				   const struct drm_display_mode *mode,
 618				   unsigned int rotation, size_t tx_buf_size)
 619{
 620	static const uint64_t modifiers[] = {
 621		DRM_FORMAT_MOD_LINEAR,
 622		DRM_FORMAT_MOD_INVALID
 623	};
 624	struct drm_device *drm = &dbidev->drm;
 625	int ret;
 626
 627	if (!dbidev->dbi.command)
 628		return -EINVAL;
 629
 630	ret = drmm_mode_config_init(drm);
 631	if (ret)
 632		return ret;
 633
 634	dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL);
 635	if (!dbidev->tx_buf)
 636		return -ENOMEM;
 637
 638	drm_mode_copy(&dbidev->mode, mode);
 639	ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation);
 640	if (ret) {
 641		DRM_ERROR("Illegal rotation value %u\n", rotation);
 642		return -EINVAL;
 643	}
 644
 645	drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs);
 646	ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs,
 647				 DRM_MODE_CONNECTOR_SPI);
 648	if (ret)
 649		return ret;
 650
 651	ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count,
 652					   modifiers, &dbidev->connector);
 653	if (ret)
 654		return ret;
 655
 656	drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane);
 657
 658	drm->mode_config.funcs = &mipi_dbi_mode_config_funcs;
 659	drm->mode_config.min_width = dbidev->mode.hdisplay;
 660	drm->mode_config.max_width = dbidev->mode.hdisplay;
 661	drm->mode_config.min_height = dbidev->mode.vdisplay;
 662	drm->mode_config.max_height = dbidev->mode.vdisplay;
 663	dbidev->rotation = rotation;
 664	dbidev->pixel_format = formats[0];
 665	if (formats[0] == DRM_FORMAT_RGB888)
 666		dbidev->dbi.write_memory_bpw = 8;
 667
 668	DRM_DEBUG_KMS("rotation = %u\n", rotation);
 669
 670	return 0;
 671}
 672EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats);
 673
 674/**
 675 * mipi_dbi_dev_init - MIPI DBI device initialization
 676 * @dbidev: MIPI DBI device structure to initialize
 677 * @funcs: Display pipe functions
 678 * @mode: Display mode
 679 * @rotation: Initial rotation in degrees Counter Clock Wise
 680 *
 681 * This function sets up a &drm_simple_display_pipe with a &drm_connector that
 682 * has one fixed &drm_display_mode which is rotated according to @rotation.
 683 * This mode is used to set the mode config min/max width/height properties.
 684 * Additionally &mipi_dbi.tx_buf is allocated.
 685 *
 686 * Supported formats: Native RGB565 and emulated XRGB8888.
 687 *
 688 * Returns:
 689 * Zero on success, negative error code on failure.
 690 */
 691int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev,
 692		      const struct drm_simple_display_pipe_funcs *funcs,
 693		      const struct drm_display_mode *mode, unsigned int rotation)
 694{
 695	size_t bufsize = (u32)mode->vdisplay * mode->hdisplay * sizeof(u16);
 696
 697	dbidev->drm.mode_config.preferred_depth = 16;
 698
 699	return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats,
 700					      ARRAY_SIZE(mipi_dbi_formats), mode,
 701					      rotation, bufsize);
 702}
 703EXPORT_SYMBOL(mipi_dbi_dev_init);
 704
 705/**
 706 * mipi_dbi_hw_reset - Hardware reset of controller
 707 * @dbi: MIPI DBI structure
 708 *
 709 * Reset controller if the &mipi_dbi->reset gpio is set.
 710 */
 711void mipi_dbi_hw_reset(struct mipi_dbi *dbi)
 712{
 713	if (!dbi->reset)
 714		return;
 715
 716	gpiod_set_value_cansleep(dbi->reset, 0);
 717	usleep_range(20, 1000);
 718	gpiod_set_value_cansleep(dbi->reset, 1);
 719	msleep(120);
 720}
 721EXPORT_SYMBOL(mipi_dbi_hw_reset);
 722
 723/**
 724 * mipi_dbi_display_is_on - Check if display is on
 725 * @dbi: MIPI DBI structure
 726 *
 727 * This function checks the Power Mode register (if readable) to see if
 728 * display output is turned on. This can be used to see if the bootloader
 729 * has already turned on the display avoiding flicker when the pipeline is
 730 * enabled.
 731 *
 732 * Returns:
 733 * true if the display can be verified to be on, false otherwise.
 734 */
 735bool mipi_dbi_display_is_on(struct mipi_dbi *dbi)
 736{
 737	u8 val;
 738
 739	if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val))
 740		return false;
 741
 742	val &= ~DCS_POWER_MODE_RESERVED_MASK;
 743
 744	/* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */
 745	if (val != (DCS_POWER_MODE_DISPLAY |
 746	    DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE))
 747		return false;
 748
 749	DRM_DEBUG_DRIVER("Display is ON\n");
 750
 751	return true;
 752}
 753EXPORT_SYMBOL(mipi_dbi_display_is_on);
 754
 755static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond)
 756{
 757	struct device *dev = dbidev->drm.dev;
 758	struct mipi_dbi *dbi = &dbidev->dbi;
 759	int ret;
 760
 761	if (dbidev->regulator) {
 762		ret = regulator_enable(dbidev->regulator);
 763		if (ret) {
 764			DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret);
 765			return ret;
 766		}
 767	}
 768
 769	if (dbidev->io_regulator) {
 770		ret = regulator_enable(dbidev->io_regulator);
 771		if (ret) {
 772			DRM_DEV_ERROR(dev, "Failed to enable I/O regulator (%d)\n", ret);
 773			if (dbidev->regulator)
 774				regulator_disable(dbidev->regulator);
 775			return ret;
 776		}
 777	}
 778
 779	if (cond && mipi_dbi_display_is_on(dbi))
 780		return 1;
 781
 782	mipi_dbi_hw_reset(dbi);
 783	ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET);
 784	if (ret) {
 785		DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret);
 786		if (dbidev->regulator)
 787			regulator_disable(dbidev->regulator);
 788		if (dbidev->io_regulator)
 789			regulator_disable(dbidev->io_regulator);
 790		return ret;
 791	}
 792
 793	/*
 794	 * If we did a hw reset, we know the controller is in Sleep mode and
 795	 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't,
 796	 * we assume worst case and wait 120ms.
 797	 */
 798	if (dbi->reset)
 799		usleep_range(5000, 20000);
 800	else
 801		msleep(120);
 802
 803	return 0;
 804}
 805
 806/**
 807 * mipi_dbi_poweron_reset - MIPI DBI poweron and reset
 808 * @dbidev: MIPI DBI device structure
 809 *
 810 * This function enables the regulator if used and does a hardware and software
 811 * reset.
 812 *
 813 * Returns:
 814 * Zero on success, or a negative error code.
 815 */
 816int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev)
 817{
 818	return mipi_dbi_poweron_reset_conditional(dbidev, false);
 819}
 820EXPORT_SYMBOL(mipi_dbi_poweron_reset);
 821
 822/**
 823 * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset
 824 * @dbidev: MIPI DBI device structure
 825 *
 826 * This function enables the regulator if used and if the display is off, it
 827 * does a hardware and software reset. If mipi_dbi_display_is_on() determines
 828 * that the display is on, no reset is performed.
 829 *
 830 * Returns:
 831 * Zero if the controller was reset, 1 if the display was already on, or a
 832 * negative error code.
 833 */
 834int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev)
 835{
 836	return mipi_dbi_poweron_reset_conditional(dbidev, true);
 837}
 838EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset);
 839
 840#if IS_ENABLED(CONFIG_SPI)
 841
 842/**
 843 * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed
 844 * @spi: SPI device
 845 * @len: The transfer buffer length.
 846 *
 847 * Many controllers have a max speed of 10MHz, but can be pushed way beyond
 848 * that. Increase reliability by running pixel data at max speed and the rest
 849 * at 10MHz, preventing transfer glitches from messing up the init settings.
 850 */
 851u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
 852{
 853	if (len > 64)
 854		return 0; /* use default */
 855
 856	return min_t(u32, 10000000, spi->max_speed_hz);
 857}
 858EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
 859
 860/*
 861 * MIPI DBI Type C Option 1
 862 *
 863 * If the SPI controller doesn't have 9 bits per word support,
 864 * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer.
 865 * Pad partial blocks with MIPI_DCS_NOP (zero).
 866 * This is how the D/C bit (x) is added:
 867 *     x7654321
 868 *     0x765432
 869 *     10x76543
 870 *     210x7654
 871 *     3210x765
 872 *     43210x76
 873 *     543210x7
 874 *     6543210x
 875 *     76543210
 876 */
 877
 878static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc,
 879				   const void *buf, size_t len,
 880				   unsigned int bpw)
 881{
 882	bool swap_bytes = (bpw == 16);
 883	size_t chunk, max_chunk = dbi->tx_buf9_len;
 884	struct spi_device *spi = dbi->spi;
 885	struct spi_transfer tr = {
 886		.tx_buf = dbi->tx_buf9,
 887		.bits_per_word = 8,
 888	};
 889	struct spi_message m;
 890	const u8 *src = buf;
 891	int i, ret;
 892	u8 *dst;
 893
 894	if (drm_debug_enabled(DRM_UT_DRIVER))
 895		pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
 896			 __func__, dc, max_chunk);
 897
 898	tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
 899	spi_message_init_with_transfers(&m, &tr, 1);
 900
 901	if (!dc) {
 902		if (WARN_ON_ONCE(len != 1))
 903			return -EINVAL;
 904
 905		/* Command: pad no-op's (zeroes) at beginning of block */
 906		dst = dbi->tx_buf9;
 907		memset(dst, 0, 9);
 908		dst[8] = *src;
 909		tr.len = 9;
 910
 911		return spi_sync(spi, &m);
 912	}
 913
 914	/* max with room for adding one bit per byte */
 915	max_chunk = max_chunk / 9 * 8;
 916	/* but no bigger than len */
 917	max_chunk = min(max_chunk, len);
 918	/* 8 byte blocks */
 919	max_chunk = max_t(size_t, 8, max_chunk & ~0x7);
 920
 921	while (len) {
 922		size_t added = 0;
 923
 924		chunk = min(len, max_chunk);
 925		len -= chunk;
 926		dst = dbi->tx_buf9;
 927
 928		if (chunk < 8) {
 929			u8 val, carry = 0;
 930
 931			/* Data: pad no-op's (zeroes) at end of block */
 932			memset(dst, 0, 9);
 933
 934			if (swap_bytes) {
 935				for (i = 1; i < (chunk + 1); i++) {
 936					val = src[1];
 937					*dst++ = carry | BIT(8 - i) | (val >> i);
 938					carry = val << (8 - i);
 939					i++;
 940					val = src[0];
 941					*dst++ = carry | BIT(8 - i) | (val >> i);
 942					carry = val << (8 - i);
 943					src += 2;
 944				}
 945				*dst++ = carry;
 946			} else {
 947				for (i = 1; i < (chunk + 1); i++) {
 948					val = *src++;
 949					*dst++ = carry | BIT(8 - i) | (val >> i);
 950					carry = val << (8 - i);
 951				}
 952				*dst++ = carry;
 953			}
 954
 955			chunk = 8;
 956			added = 1;
 957		} else {
 958			for (i = 0; i < chunk; i += 8) {
 959				if (swap_bytes) {
 960					*dst++ =                 BIT(7) | (src[1] >> 1);
 961					*dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2);
 962					*dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3);
 963					*dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4);
 964					*dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5);
 965					*dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6);
 966					*dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7);
 967					*dst++ = (src[7] << 1) | BIT(0);
 968					*dst++ = src[6];
 969				} else {
 970					*dst++ =                 BIT(7) | (src[0] >> 1);
 971					*dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2);
 972					*dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3);
 973					*dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4);
 974					*dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5);
 975					*dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6);
 976					*dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7);
 977					*dst++ = (src[6] << 1) | BIT(0);
 978					*dst++ = src[7];
 979				}
 980
 981				src += 8;
 982				added++;
 983			}
 984		}
 985
 986		tr.len = chunk + added;
 987
 988		ret = spi_sync(spi, &m);
 989		if (ret)
 990			return ret;
 991	}
 992
 993	return 0;
 994}
 995
 996static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc,
 997				  const void *buf, size_t len,
 998				  unsigned int bpw)
 999{
1000	struct spi_device *spi = dbi->spi;
1001	struct spi_transfer tr = {
1002		.bits_per_word = 9,
1003	};
1004	const u16 *src16 = buf;
1005	const u8 *src8 = buf;
1006	struct spi_message m;
1007	size_t max_chunk;
1008	u16 *dst16;
1009	int ret;
1010
1011	if (!spi_is_bpw_supported(spi, 9))
1012		return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw);
1013
1014	tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
1015	max_chunk = dbi->tx_buf9_len;
1016	dst16 = dbi->tx_buf9;
1017
1018	if (drm_debug_enabled(DRM_UT_DRIVER))
1019		pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
1020			 __func__, dc, max_chunk);
1021
1022	max_chunk = min(max_chunk / 2, len);
1023
1024	spi_message_init_with_transfers(&m, &tr, 1);
1025	tr.tx_buf = dst16;
1026
1027	while (len) {
1028		size_t chunk = min(len, max_chunk);
1029		unsigned int i;
1030
1031		if (bpw == 16) {
1032			for (i = 0; i < (chunk * 2); i += 2) {
1033				dst16[i]     = *src16 >> 8;
1034				dst16[i + 1] = *src16++ & 0xFF;
1035				if (dc) {
1036					dst16[i]     |= 0x0100;
1037					dst16[i + 1] |= 0x0100;
1038				}
1039			}
1040		} else {
1041			for (i = 0; i < chunk; i++) {
1042				dst16[i] = *src8++;
1043				if (dc)
1044					dst16[i] |= 0x0100;
1045			}
1046		}
1047
1048		tr.len = chunk * 2;
1049		len -= chunk;
1050
1051		ret = spi_sync(spi, &m);
1052		if (ret)
1053			return ret;
1054	}
1055
1056	return 0;
1057}
1058
1059static int mipi_dbi_typec1_command_read(struct mipi_dbi *dbi, u8 *cmd,
1060					u8 *data, size_t len)
1061{
1062	struct spi_device *spi = dbi->spi;
1063	u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
1064			     spi->max_speed_hz / 2);
1065	struct spi_transfer tr[2] = {
1066		{
1067			.speed_hz = speed_hz,
1068			.bits_per_word = 9,
1069			.tx_buf = dbi->tx_buf9,
1070			.len = 2,
1071		}, {
1072			.speed_hz = speed_hz,
1073			.bits_per_word = 8,
1074			.len = len,
1075			.rx_buf = data,
1076		},
1077	};
1078	struct spi_message m;
1079	u16 *dst16;
1080	int ret;
1081
1082	if (!len)
1083		return -EINVAL;
1084
1085	if (!spi_is_bpw_supported(spi, 9)) {
1086		/*
1087		 * FIXME: implement something like mipi_dbi_spi1e_transfer() but
1088		 * for reads using emulation.
1089		 */
1090		dev_err(&spi->dev,
1091			"reading on host not supporting 9 bpw not yet implemented\n");
1092		return -EOPNOTSUPP;
1093	}
1094
1095	/*
1096	 * Turn the 8bit command into a 16bit version of the command in the
1097	 * buffer. Only 9 bits of this will be used when executing the actual
1098	 * transfer.
1099	 */
1100	dst16 = dbi->tx_buf9;
1101	dst16[0] = *cmd;
1102
1103	spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
1104	ret = spi_sync(spi, &m);
1105
1106	if (!ret)
1107		MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
1108
1109	return ret;
1110}
1111
1112static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,
1113				   u8 *parameters, size_t num)
1114{
1115	unsigned int bpw = 8;
1116	int ret;
1117
1118	if (mipi_dbi_command_is_read(dbi, *cmd))
1119		return mipi_dbi_typec1_command_read(dbi, cmd, parameters, num);
1120
1121	MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num);
1122
1123	ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8);
1124	if (ret || !num)
1125		return ret;
1126
1127	if (*cmd == MIPI_DCS_WRITE_MEMORY_START)
1128		bpw = dbi->write_memory_bpw;
1129
1130	return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);
1131}
1132
1133/* MIPI DBI Type C Option 3 */
1134
1135static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd,
1136					u8 *data, size_t len)
1137{
1138	struct spi_device *spi = dbi->spi;
1139	u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
1140			     spi->max_speed_hz / 2);
1141	struct spi_transfer tr[2] = {
1142		{
1143			.speed_hz = speed_hz,
1144			.tx_buf = cmd,
1145			.len = 1,
1146		}, {
1147			.speed_hz = speed_hz,
1148			.len = len,
1149		},
1150	};
1151	struct spi_message m;
1152	u8 *buf;
1153	int ret;
1154
1155	if (!len)
1156		return -EINVAL;
1157
1158	/*
1159	 * Support non-standard 24-bit and 32-bit Nokia read commands which
1160	 * start with a dummy clock, so we need to read an extra byte.
1161	 */
1162	if (*cmd == MIPI_DCS_GET_DISPLAY_ID ||
1163	    *cmd == MIPI_DCS_GET_DISPLAY_STATUS) {
1164		if (!(len == 3 || len == 4))
1165			return -EINVAL;
1166
1167		tr[1].len = len + 1;
1168	}
1169
1170	buf = kmalloc(tr[1].len, GFP_KERNEL);
1171	if (!buf)
1172		return -ENOMEM;
1173
1174	tr[1].rx_buf = buf;
1175
1176	spi_bus_lock(spi->controller);
1177	gpiod_set_value_cansleep(dbi->dc, 0);
1178
1179	spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
1180	ret = spi_sync_locked(spi, &m);
1181	spi_bus_unlock(spi->controller);
1182	if (ret)
1183		goto err_free;
1184
1185	if (tr[1].len == len) {
1186		memcpy(data, buf, len);
1187	} else {
1188		unsigned int i;
1189
1190		for (i = 0; i < len; i++)
1191			data[i] = (buf[i] << 1) | (buf[i + 1] >> 7);
1192	}
1193
1194	MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
1195
1196err_free:
1197	kfree(buf);
1198
1199	return ret;
1200}
1201
1202static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd,
1203				   u8 *par, size_t num)
1204{
1205	struct spi_device *spi = dbi->spi;
1206	unsigned int bpw = 8;
1207	u32 speed_hz;
1208	int ret;
1209
1210	if (mipi_dbi_command_is_read(dbi, *cmd))
1211		return mipi_dbi_typec3_command_read(dbi, cmd, par, num);
1212
1213	MIPI_DBI_DEBUG_COMMAND(*cmd, par, num);
1214
1215	spi_bus_lock(spi->controller);
1216	gpiod_set_value_cansleep(dbi->dc, 0);
1217	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
1218	ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1);
1219	spi_bus_unlock(spi->controller);
1220	if (ret || !num)
1221		return ret;
1222
1223	if (*cmd == MIPI_DCS_WRITE_MEMORY_START)
1224		bpw = dbi->write_memory_bpw;
1225
1226	spi_bus_lock(spi->controller);
1227	gpiod_set_value_cansleep(dbi->dc, 1);
1228	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
1229	ret = mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num);
1230	spi_bus_unlock(spi->controller);
1231
1232	return ret;
1233}
1234
1235/**
1236 * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface
1237 * @spi: SPI device
1238 * @dbi: MIPI DBI structure to initialize
1239 * @dc: D/C gpio (optional)
1240 *
1241 * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the
1242 * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or
1243 * a driver-specific init.
1244 *
1245 * If @dc is set, a Type C Option 3 interface is assumed, if not
1246 * Type C Option 1.
1247 *
1248 * If the command is %MIPI_DCS_WRITE_MEMORY_START and the pixel format is RGB565, endianness has
1249 * to be taken into account. The MIPI DBI serial interface is big endian and framebuffers are
1250 * assumed stored in memory as little endian (%DRM_FORMAT_BIG_ENDIAN is not supported).
1251 *
1252 * This is how endianness is handled:
1253 *
1254 * Option 1 (D/C as a bit): The buffer is sent on the wire byte by byte so the 16-bit buffer is
1255 *                          byteswapped before transfer.
1256 *
1257 * Option 3 (D/C as a gpio): If the SPI controller supports 16 bits per word the buffer can be
1258 *                           sent as-is. If not the caller is responsible for swapping the bytes
1259 *                           before calling mipi_dbi_command_buf() and the buffer is sent 8 bpw.
1260 *
1261 * This handling is optimised for %DRM_FORMAT_RGB565 framebuffers.
1262 *
1263 * If the interface is Option 1 and the SPI controller doesn't support 9 bits per word,
1264 * the buffer is sent as 9x 8-bit words, padded with MIPI DCS no-op commands if necessary.
1265 *
1266 * Returns:
1267 * Zero on success, negative error code on failure.
1268 */
1269int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
1270		      struct gpio_desc *dc)
1271{
1272	struct device *dev = &spi->dev;
1273	int ret;
1274
1275	/*
1276	 * Even though it's not the SPI device that does DMA (the master does),
1277	 * the dma mask is necessary for the dma_alloc_wc() in the GEM code
1278	 * (e.g., drm_gem_dma_create()). The dma_addr returned will be a physical
1279	 * address which might be different from the bus address, but this is
1280	 * not a problem since the address will not be used.
1281	 * The virtual address is used in the transfer and the SPI core
1282	 * re-maps it on the SPI master device using the DMA streaming API
1283	 * (spi_map_buf()).
1284	 */
1285	if (!dev->coherent_dma_mask) {
1286		ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
1287		if (ret) {
1288			dev_warn(dev, "Failed to set dma mask %d\n", ret);
1289			return ret;
1290		}
1291	}
1292
1293	dbi->spi = spi;
1294	dbi->read_commands = mipi_dbi_dcs_read_commands;
1295	dbi->write_memory_bpw = 16;
1296
1297	if (dc) {
1298		dbi->command = mipi_dbi_typec3_command;
1299		dbi->dc = dc;
1300		if (!spi_is_bpw_supported(spi, 16)) {
1301			dbi->write_memory_bpw = 8;
1302			dbi->swap_bytes = true;
1303		}
1304	} else {
1305		dbi->command = mipi_dbi_typec1_command;
1306		dbi->tx_buf9_len = SZ_16K;
1307		dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL);
1308		if (!dbi->tx_buf9)
1309			return -ENOMEM;
1310	}
1311
1312	mutex_init(&dbi->cmdlock);
1313
1314	DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
1315
1316	return 0;
1317}
1318EXPORT_SYMBOL(mipi_dbi_spi_init);
1319
1320/**
1321 * mipi_dbi_spi_transfer - SPI transfer helper
1322 * @spi: SPI device
1323 * @speed_hz: Override speed (optional)
1324 * @bpw: Bits per word
1325 * @buf: Buffer to transfer
1326 * @len: Buffer length
1327 *
1328 * This SPI transfer helper breaks up the transfer of @buf into chunks which
1329 * the SPI controller driver can handle. The SPI bus must be locked when
1330 * calling this.
1331 *
1332 * Returns:
1333 * Zero on success, negative error code on failure.
1334 */
1335int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
1336			  u8 bpw, const void *buf, size_t len)
1337{
1338	size_t max_chunk = spi_max_transfer_size(spi);
1339	struct spi_transfer tr = {
1340		.bits_per_word = bpw,
1341		.speed_hz = speed_hz,
1342	};
1343	struct spi_message m;
1344	size_t chunk;
1345	int ret;
1346
1347	/* In __spi_validate, there's a validation that no partial transfers
1348	 * are accepted (xfer->len % w_size must be zero).
1349	 * Here we align max_chunk to multiple of 2 (16bits),
1350	 * to prevent transfers from being rejected.
1351	 */
1352	max_chunk = ALIGN_DOWN(max_chunk, 2);
1353
1354	spi_message_init_with_transfers(&m, &tr, 1);
1355
1356	while (len) {
1357		chunk = min(len, max_chunk);
1358
1359		tr.tx_buf = buf;
1360		tr.len = chunk;
1361		buf += chunk;
1362		len -= chunk;
1363
1364		ret = spi_sync_locked(spi, &m);
1365		if (ret)
1366			return ret;
1367	}
1368
1369	return 0;
1370}
1371EXPORT_SYMBOL(mipi_dbi_spi_transfer);
1372
1373#endif /* CONFIG_SPI */
1374
1375#ifdef CONFIG_DEBUG_FS
1376
1377static ssize_t mipi_dbi_debugfs_command_write(struct file *file,
1378					      const char __user *ubuf,
1379					      size_t count, loff_t *ppos)
1380{
1381	struct seq_file *m = file->private_data;
1382	struct mipi_dbi_dev *dbidev = m->private;
1383	u8 val, cmd = 0, parameters[64];
1384	char *buf, *pos, *token;
1385	int i, ret, idx;
1386
1387	if (!drm_dev_enter(&dbidev->drm, &idx))
1388		return -ENODEV;
1389
1390	buf = memdup_user_nul(ubuf, count);
1391	if (IS_ERR(buf)) {
1392		ret = PTR_ERR(buf);
1393		goto err_exit;
1394	}
1395
1396	/* strip trailing whitespace */
1397	for (i = count - 1; i > 0; i--)
1398		if (isspace(buf[i]))
1399			buf[i] = '\0';
1400		else
1401			break;
1402	i = 0;
1403	pos = buf;
1404	while (pos) {
1405		token = strsep(&pos, " ");
1406		if (!token) {
1407			ret = -EINVAL;
1408			goto err_free;
1409		}
1410
1411		ret = kstrtou8(token, 16, &val);
1412		if (ret < 0)
1413			goto err_free;
1414
1415		if (token == buf)
1416			cmd = val;
1417		else
1418			parameters[i++] = val;
1419
1420		if (i == 64) {
1421			ret = -E2BIG;
1422			goto err_free;
1423		}
1424	}
1425
1426	ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i);
1427
1428err_free:
1429	kfree(buf);
1430err_exit:
1431	drm_dev_exit(idx);
1432
1433	return ret < 0 ? ret : count;
1434}
1435
1436static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused)
1437{
1438	struct mipi_dbi_dev *dbidev = m->private;
1439	struct mipi_dbi *dbi = &dbidev->dbi;
1440	u8 cmd, val[4];
1441	int ret, idx;
1442	size_t len;
1443
1444	if (!drm_dev_enter(&dbidev->drm, &idx))
1445		return -ENODEV;
1446
1447	for (cmd = 0; cmd < 255; cmd++) {
1448		if (!mipi_dbi_command_is_read(dbi, cmd))
1449			continue;
1450
1451		switch (cmd) {
1452		case MIPI_DCS_READ_MEMORY_START:
1453		case MIPI_DCS_READ_MEMORY_CONTINUE:
1454			len = 2;
1455			break;
1456		case MIPI_DCS_GET_DISPLAY_ID:
1457			len = 3;
1458			break;
1459		case MIPI_DCS_GET_DISPLAY_STATUS:
1460			len = 4;
1461			break;
1462		default:
1463			len = 1;
1464			break;
1465		}
1466
1467		seq_printf(m, "%02x: ", cmd);
1468		ret = mipi_dbi_command_buf(dbi, cmd, val, len);
1469		if (ret) {
1470			seq_puts(m, "XX\n");
1471			continue;
1472		}
1473		seq_printf(m, "%*phN\n", (int)len, val);
1474	}
1475
1476	drm_dev_exit(idx);
1477
1478	return 0;
1479}
1480
1481static int mipi_dbi_debugfs_command_open(struct inode *inode,
1482					 struct file *file)
1483{
1484	return single_open(file, mipi_dbi_debugfs_command_show,
1485			   inode->i_private);
1486}
1487
1488static const struct file_operations mipi_dbi_debugfs_command_fops = {
1489	.owner = THIS_MODULE,
1490	.open = mipi_dbi_debugfs_command_open,
1491	.read = seq_read,
1492	.llseek = seq_lseek,
1493	.release = single_release,
1494	.write = mipi_dbi_debugfs_command_write,
1495};
1496
1497/**
1498 * mipi_dbi_debugfs_init - Create debugfs entries
1499 * @minor: DRM minor
1500 *
1501 * This function creates a 'command' debugfs file for sending commands to the
1502 * controller or getting the read command values.
1503 * Drivers can use this as their &drm_driver->debugfs_init callback.
1504 *
1505 */
1506void mipi_dbi_debugfs_init(struct drm_minor *minor)
1507{
1508	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev);
1509	umode_t mode = S_IFREG | S_IWUSR;
1510
1511	if (dbidev->dbi.read_commands)
1512		mode |= S_IRUGO;
1513	debugfs_create_file("command", mode, minor->debugfs_root, dbidev,
1514			    &mipi_dbi_debugfs_command_fops);
1515}
1516EXPORT_SYMBOL(mipi_dbi_debugfs_init);
1517
1518#endif
1519
1520MODULE_DESCRIPTION("MIPI Display Bus Interface (DBI) LCD controller support");
1521MODULE_LICENSE("GPL");