FILE
drm_edid.c
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linux-6.19.14/drivers/gpu/drm/drm_edid.c
1/* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31#include <linux/bitfield.h> 32#include <linux/byteorder/generic.h> 33#include <linux/cec.h> 34#include <linux/export.h> 35#include <linux/hdmi.h> 36#include <linux/i2c.h> 37#include <linux/kernel.h> 38#include <linux/module.h> 39#include <linux/pci.h> 40#include <linux/seq_buf.h> 41#include <linux/slab.h> 42#include <linux/vga_switcheroo.h> 43 44#include <drm/drm_drv.h> 45#include <drm/drm_edid.h> 46#include <drm/drm_eld.h> 47#include <drm/drm_encoder.h> 48#include <drm/drm_print.h> 49 50#include "drm_crtc_internal.h" 51#include "drm_displayid_internal.h" 52#include "drm_internal.h" 53 54static int oui(u8 first, u8 second, u8 third) 55{ 56 return (first << 16) | (second << 8) | third; 57} 58 59#define EDID_EST_TIMINGS 16 60#define EDID_STD_TIMINGS 8 61#define EDID_DETAILED_TIMINGS 4 62 63/* 64 * EDID blocks out in the wild have a variety of bugs, try to collect 65 * them here (note that userspace may work around broken monitors first, 66 * but fixes should make their way here so that the kernel "just works" 67 * on as many displays as possible). 68 */ 69 70enum drm_edid_internal_quirk { 71 /* First detailed mode wrong, use largest 60Hz mode */ 72 EDID_QUIRK_PREFER_LARGE_60 = DRM_EDID_QUIRK_NUM, 73 /* Reported 135MHz pixel clock is too high, needs adjustment */ 74 EDID_QUIRK_135_CLOCK_TOO_HIGH, 75 /* Prefer the largest mode at 75 Hz */ 76 EDID_QUIRK_PREFER_LARGE_75, 77 /* Detail timing is in cm not mm */ 78 EDID_QUIRK_DETAILED_IN_CM, 79 /* Detailed timing descriptors have bogus size values, so just take the 80 * maximum size and use that. 81 */ 82 EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE, 83 /* use +hsync +vsync for detailed mode */ 84 EDID_QUIRK_DETAILED_SYNC_PP, 85 /* Force reduced-blanking timings for detailed modes */ 86 EDID_QUIRK_FORCE_REDUCED_BLANKING, 87 /* Force 8bpc */ 88 EDID_QUIRK_FORCE_8BPC, 89 /* Force 12bpc */ 90 EDID_QUIRK_FORCE_12BPC, 91 /* Force 6bpc */ 92 EDID_QUIRK_FORCE_6BPC, 93 /* Force 10bpc */ 94 EDID_QUIRK_FORCE_10BPC, 95 /* Non desktop display (i.e. HMD) */ 96 EDID_QUIRK_NON_DESKTOP, 97 /* Cap the DSC target bitrate to 15bpp */ 98 EDID_QUIRK_CAP_DSC_15BPP, 99}; 100 101#define MICROSOFT_IEEE_OUI 0xca125c 102 103struct detailed_mode_closure { 104 struct drm_connector *connector; 105 const struct drm_edid *drm_edid; 106 bool preferred; 107 int modes; 108}; 109 110struct drm_edid_match_closure { 111 const struct drm_edid_ident *ident; 112 bool matched; 113}; 114 115#define LEVEL_DMT 0 116#define LEVEL_GTF 1 117#define LEVEL_GTF2 2 118#define LEVEL_CVT 3 119 120#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 121{ \ 122 .ident = { \ 123 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, \ 124 vend_chr_2, product_id), \ 125 }, \ 126 .quirks = _quirks \ 127} 128 129static const struct edid_quirk { 130 const struct drm_edid_ident ident; 131 u32 quirks; 132} edid_quirk_list[] = { 133 /* Acer AL1706 */ 134 EDID_QUIRK('A', 'C', 'R', 44358, BIT(EDID_QUIRK_PREFER_LARGE_60)), 135 /* Acer F51 */ 136 EDID_QUIRK('A', 'P', 'I', 0x7602, BIT(EDID_QUIRK_PREFER_LARGE_60)), 137 138 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 139 EDID_QUIRK('A', 'E', 'O', 0, BIT(EDID_QUIRK_FORCE_6BPC)), 140 141 /* BenQ GW2765 */ 142 EDID_QUIRK('B', 'N', 'Q', 0x78d6, BIT(EDID_QUIRK_FORCE_8BPC)), 143 144 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 145 EDID_QUIRK('B', 'O', 'E', 0x78b, BIT(EDID_QUIRK_FORCE_6BPC)), 146 147 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 148 EDID_QUIRK('C', 'P', 'T', 0x17df, BIT(EDID_QUIRK_FORCE_6BPC)), 149 150 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 151 EDID_QUIRK('S', 'D', 'C', 0x3652, BIT(EDID_QUIRK_FORCE_6BPC)), 152 153 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 154 EDID_QUIRK('B', 'O', 'E', 0x0771, BIT(EDID_QUIRK_FORCE_6BPC)), 155 156 /* Belinea 10 15 55 */ 157 EDID_QUIRK('M', 'A', 'X', 1516, BIT(EDID_QUIRK_PREFER_LARGE_60)), 158 EDID_QUIRK('M', 'A', 'X', 0x77e, BIT(EDID_QUIRK_PREFER_LARGE_60)), 159 160 /* Envision Peripherals, Inc. EN-7100e */ 161 EDID_QUIRK('E', 'P', 'I', 59264, BIT(EDID_QUIRK_135_CLOCK_TOO_HIGH)), 162 /* Envision EN2028 */ 163 EDID_QUIRK('E', 'P', 'I', 8232, BIT(EDID_QUIRK_PREFER_LARGE_60)), 164 165 /* Funai Electronics PM36B */ 166 EDID_QUIRK('F', 'C', 'M', 13600, BIT(EDID_QUIRK_PREFER_LARGE_75) | 167 BIT(EDID_QUIRK_DETAILED_IN_CM)), 168 169 /* LG 27GP950 */ 170 EDID_QUIRK('G', 'S', 'M', 0x5bbf, BIT(EDID_QUIRK_CAP_DSC_15BPP)), 171 172 /* LG 27GN950 */ 173 EDID_QUIRK('G', 'S', 'M', 0x5b9a, BIT(EDID_QUIRK_CAP_DSC_15BPP)), 174 175 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 176 EDID_QUIRK('L', 'G', 'D', 764, BIT(EDID_QUIRK_FORCE_10BPC)), 177 178 /* LG Philips LCD LP154W01-A5 */ 179 EDID_QUIRK('L', 'P', 'L', 0, BIT(EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)), 180 EDID_QUIRK('L', 'P', 'L', 0x2a00, BIT(EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)), 181 182 /* Samsung SyncMaster 205BW. Note: irony */ 183 EDID_QUIRK('S', 'A', 'M', 541, BIT(EDID_QUIRK_DETAILED_SYNC_PP)), 184 /* Samsung SyncMaster 22[5-6]BW */ 185 EDID_QUIRK('S', 'A', 'M', 596, BIT(EDID_QUIRK_PREFER_LARGE_60)), 186 EDID_QUIRK('S', 'A', 'M', 638, BIT(EDID_QUIRK_PREFER_LARGE_60)), 187 188 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 189 EDID_QUIRK('S', 'N', 'Y', 0x2541, BIT(EDID_QUIRK_FORCE_12BPC)), 190 191 /* ViewSonic VA2026w */ 192 EDID_QUIRK('V', 'S', 'C', 5020, BIT(EDID_QUIRK_FORCE_REDUCED_BLANKING)), 193 194 /* Medion MD 30217 PG */ 195 EDID_QUIRK('M', 'E', 'D', 0x7b8, BIT(EDID_QUIRK_PREFER_LARGE_75)), 196 197 /* Lenovo G50 */ 198 EDID_QUIRK('S', 'D', 'C', 18514, BIT(EDID_QUIRK_FORCE_6BPC)), 199 200 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 201 EDID_QUIRK('S', 'E', 'C', 0xd033, BIT(EDID_QUIRK_FORCE_8BPC)), 202 203 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 204 EDID_QUIRK('E', 'T', 'R', 13896, BIT(EDID_QUIRK_FORCE_8BPC)), 205 206 /* Valve Index Headset */ 207 EDID_QUIRK('V', 'L', 'V', 0x91a8, BIT(EDID_QUIRK_NON_DESKTOP)), 208 EDID_QUIRK('V', 'L', 'V', 0x91b0, BIT(EDID_QUIRK_NON_DESKTOP)), 209 EDID_QUIRK('V', 'L', 'V', 0x91b1, BIT(EDID_QUIRK_NON_DESKTOP)), 210 EDID_QUIRK('V', 'L', 'V', 0x91b2, BIT(EDID_QUIRK_NON_DESKTOP)), 211 EDID_QUIRK('V', 'L', 'V', 0x91b3, BIT(EDID_QUIRK_NON_DESKTOP)), 212 EDID_QUIRK('V', 'L', 'V', 0x91b4, BIT(EDID_QUIRK_NON_DESKTOP)), 213 EDID_QUIRK('V', 'L', 'V', 0x91b5, BIT(EDID_QUIRK_NON_DESKTOP)), 214 EDID_QUIRK('V', 'L', 'V', 0x91b6, BIT(EDID_QUIRK_NON_DESKTOP)), 215 EDID_QUIRK('V', 'L', 'V', 0x91b7, BIT(EDID_QUIRK_NON_DESKTOP)), 216 EDID_QUIRK('V', 'L', 'V', 0x91b8, BIT(EDID_QUIRK_NON_DESKTOP)), 217 EDID_QUIRK('V', 'L', 'V', 0x91b9, BIT(EDID_QUIRK_NON_DESKTOP)), 218 EDID_QUIRK('V', 'L', 'V', 0x91ba, BIT(EDID_QUIRK_NON_DESKTOP)), 219 EDID_QUIRK('V', 'L', 'V', 0x91bb, BIT(EDID_QUIRK_NON_DESKTOP)), 220 EDID_QUIRK('V', 'L', 'V', 0x91bc, BIT(EDID_QUIRK_NON_DESKTOP)), 221 EDID_QUIRK('V', 'L', 'V', 0x91bd, BIT(EDID_QUIRK_NON_DESKTOP)), 222 EDID_QUIRK('V', 'L', 'V', 0x91be, BIT(EDID_QUIRK_NON_DESKTOP)), 223 EDID_QUIRK('V', 'L', 'V', 0x91bf, BIT(EDID_QUIRK_NON_DESKTOP)), 224 225 /* HTC Vive and Vive Pro VR Headsets */ 226 EDID_QUIRK('H', 'V', 'R', 0xaa01, BIT(EDID_QUIRK_NON_DESKTOP)), 227 EDID_QUIRK('H', 'V', 'R', 0xaa02, BIT(EDID_QUIRK_NON_DESKTOP)), 228 229 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 230 EDID_QUIRK('O', 'V', 'R', 0x0001, BIT(EDID_QUIRK_NON_DESKTOP)), 231 EDID_QUIRK('O', 'V', 'R', 0x0003, BIT(EDID_QUIRK_NON_DESKTOP)), 232 EDID_QUIRK('O', 'V', 'R', 0x0004, BIT(EDID_QUIRK_NON_DESKTOP)), 233 EDID_QUIRK('O', 'V', 'R', 0x0012, BIT(EDID_QUIRK_NON_DESKTOP)), 234 235 /* Windows Mixed Reality Headsets */ 236 EDID_QUIRK('A', 'C', 'R', 0x7fce, BIT(EDID_QUIRK_NON_DESKTOP)), 237 EDID_QUIRK('L', 'E', 'N', 0x0408, BIT(EDID_QUIRK_NON_DESKTOP)), 238 EDID_QUIRK('F', 'U', 'J', 0x1970, BIT(EDID_QUIRK_NON_DESKTOP)), 239 EDID_QUIRK('D', 'E', 'L', 0x7fce, BIT(EDID_QUIRK_NON_DESKTOP)), 240 EDID_QUIRK('S', 'E', 'C', 0x144a, BIT(EDID_QUIRK_NON_DESKTOP)), 241 EDID_QUIRK('A', 'U', 'S', 0xc102, BIT(EDID_QUIRK_NON_DESKTOP)), 242 243 /* Sony PlayStation VR Headset */ 244 EDID_QUIRK('S', 'N', 'Y', 0x0704, BIT(EDID_QUIRK_NON_DESKTOP)), 245 246 /* Sensics VR Headsets */ 247 EDID_QUIRK('S', 'E', 'N', 0x1019, BIT(EDID_QUIRK_NON_DESKTOP)), 248 249 /* OSVR HDK and HDK2 VR Headsets */ 250 EDID_QUIRK('S', 'V', 'R', 0x1019, BIT(EDID_QUIRK_NON_DESKTOP)), 251 EDID_QUIRK('A', 'U', 'O', 0x1111, BIT(EDID_QUIRK_NON_DESKTOP)), 252 253 /* LQ116M1JW10 displays noise when 8 bpc, but display fine as 6 bpc */ 254 EDID_QUIRK('S', 'H', 'P', 0x154c, BIT(EDID_QUIRK_FORCE_6BPC)), 255 256 /* 257 * @drm_edid_internal_quirk entries end here, following with the 258 * @drm_edid_quirk entries. 259 */ 260 261 /* HP ZR24w DP AUX DPCD access requires probing to prevent corruption. */ 262 EDID_QUIRK('H', 'W', 'P', 0x2869, BIT(DRM_EDID_QUIRK_DP_DPCD_PROBE)), 263}; 264 265/* 266 * Autogenerated from the DMT spec. 267 * This table is copied from xfree86/modes/xf86EdidModes.c. 268 */ 269static const struct drm_display_mode drm_dmt_modes[] = { 270 /* 0x01 - 640x350@85Hz */ 271 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 272 736, 832, 0, 350, 382, 385, 445, 0, 273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 274 /* 0x02 - 640x400@85Hz */ 275 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 276 736, 832, 0, 400, 401, 404, 445, 0, 277 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 278 /* 0x03 - 720x400@85Hz */ 279 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 280 828, 936, 0, 400, 401, 404, 446, 0, 281 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 282 /* 0x04 - 640x480@60Hz */ 283 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 284 752, 800, 0, 480, 490, 492, 525, 0, 285 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 286 /* 0x05 - 640x480@72Hz */ 287 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 288 704, 832, 0, 480, 489, 492, 520, 0, 289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 290 /* 0x06 - 640x480@75Hz */ 291 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 292 720, 840, 0, 480, 481, 484, 500, 0, 293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 294 /* 0x07 - 640x480@85Hz */ 295 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 296 752, 832, 0, 480, 481, 484, 509, 0, 297 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 298 /* 0x08 - 800x600@56Hz */ 299 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 300 896, 1024, 0, 600, 601, 603, 625, 0, 301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 302 /* 0x09 - 800x600@60Hz */ 303 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 304 968, 1056, 0, 600, 601, 605, 628, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 306 /* 0x0a - 800x600@72Hz */ 307 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 308 976, 1040, 0, 600, 637, 643, 666, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x0b - 800x600@75Hz */ 311 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 312 896, 1056, 0, 600, 601, 604, 625, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 314 /* 0x0c - 800x600@85Hz */ 315 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 316 896, 1048, 0, 600, 601, 604, 631, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 318 /* 0x0d - 800x600@120Hz RB */ 319 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 320 880, 960, 0, 600, 603, 607, 636, 0, 321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 322 /* 0x0e - 848x480@60Hz */ 323 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 324 976, 1088, 0, 480, 486, 494, 517, 0, 325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x0f - 1024x768@43Hz, interlace */ 327 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 328 1208, 1264, 0, 768, 768, 776, 817, 0, 329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 330 DRM_MODE_FLAG_INTERLACE) }, 331 /* 0x10 - 1024x768@60Hz */ 332 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 333 1184, 1344, 0, 768, 771, 777, 806, 0, 334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 335 /* 0x11 - 1024x768@70Hz */ 336 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 337 1184, 1328, 0, 768, 771, 777, 806, 0, 338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 339 /* 0x12 - 1024x768@75Hz */ 340 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 341 1136, 1312, 0, 768, 769, 772, 800, 0, 342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 343 /* 0x13 - 1024x768@85Hz */ 344 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 345 1168, 1376, 0, 768, 769, 772, 808, 0, 346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 347 /* 0x14 - 1024x768@120Hz RB */ 348 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 349 1104, 1184, 0, 768, 771, 775, 813, 0, 350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 351 /* 0x15 - 1152x864@75Hz */ 352 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 353 1344, 1600, 0, 864, 865, 868, 900, 0, 354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 355 /* 0x55 - 1280x720@60Hz */ 356 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 357 1430, 1650, 0, 720, 725, 730, 750, 0, 358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 359 /* 0x16 - 1280x768@60Hz RB */ 360 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 361 1360, 1440, 0, 768, 771, 778, 790, 0, 362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 363 /* 0x17 - 1280x768@60Hz */ 364 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 365 1472, 1664, 0, 768, 771, 778, 798, 0, 366 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 367 /* 0x18 - 1280x768@75Hz */ 368 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 369 1488, 1696, 0, 768, 771, 778, 805, 0, 370 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 371 /* 0x19 - 1280x768@85Hz */ 372 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 373 1496, 1712, 0, 768, 771, 778, 809, 0, 374 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 375 /* 0x1a - 1280x768@120Hz RB */ 376 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 377 1360, 1440, 0, 768, 771, 778, 813, 0, 378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 379 /* 0x1b - 1280x800@60Hz RB */ 380 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 381 1360, 1440, 0, 800, 803, 809, 823, 0, 382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 383 /* 0x1c - 1280x800@60Hz */ 384 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 385 1480, 1680, 0, 800, 803, 809, 831, 0, 386 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 387 /* 0x1d - 1280x800@75Hz */ 388 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 389 1488, 1696, 0, 800, 803, 809, 838, 0, 390 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 391 /* 0x1e - 1280x800@85Hz */ 392 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 393 1496, 1712, 0, 800, 803, 809, 843, 0, 394 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 395 /* 0x1f - 1280x800@120Hz RB */ 396 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 397 1360, 1440, 0, 800, 803, 809, 847, 0, 398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 399 /* 0x20 - 1280x960@60Hz */ 400 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 401 1488, 1800, 0, 960, 961, 964, 1000, 0, 402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 403 /* 0x21 - 1280x960@85Hz */ 404 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 405 1504, 1728, 0, 960, 961, 964, 1011, 0, 406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 407 /* 0x22 - 1280x960@120Hz RB */ 408 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 409 1360, 1440, 0, 960, 963, 967, 1017, 0, 410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 411 /* 0x23 - 1280x1024@60Hz */ 412 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 413 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 415 /* 0x24 - 1280x1024@75Hz */ 416 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 417 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 419 /* 0x25 - 1280x1024@85Hz */ 420 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 421 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 423 /* 0x26 - 1280x1024@120Hz RB */ 424 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 425 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 427 /* 0x27 - 1360x768@60Hz */ 428 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 429 1536, 1792, 0, 768, 771, 777, 795, 0, 430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 431 /* 0x28 - 1360x768@120Hz RB */ 432 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 433 1440, 1520, 0, 768, 771, 776, 813, 0, 434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 435 /* 0x51 - 1366x768@60Hz */ 436 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 437 1579, 1792, 0, 768, 771, 774, 798, 0, 438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 439 /* 0x56 - 1366x768@60Hz */ 440 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 441 1436, 1500, 0, 768, 769, 772, 800, 0, 442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 443 /* 0x29 - 1400x1050@60Hz RB */ 444 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 445 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 447 /* 0x2a - 1400x1050@60Hz */ 448 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 449 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 451 /* 0x2b - 1400x1050@75Hz */ 452 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 453 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 454 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 455 /* 0x2c - 1400x1050@85Hz */ 456 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 457 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 459 /* 0x2d - 1400x1050@120Hz RB */ 460 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 461 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 463 /* 0x2e - 1440x900@60Hz RB */ 464 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 465 1520, 1600, 0, 900, 903, 909, 926, 0, 466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 467 /* 0x2f - 1440x900@60Hz */ 468 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 469 1672, 1904, 0, 900, 903, 909, 934, 0, 470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 471 /* 0x30 - 1440x900@75Hz */ 472 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 473 1688, 1936, 0, 900, 903, 909, 942, 0, 474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 475 /* 0x31 - 1440x900@85Hz */ 476 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 477 1696, 1952, 0, 900, 903, 909, 948, 0, 478 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 479 /* 0x32 - 1440x900@120Hz RB */ 480 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 481 1520, 1600, 0, 900, 903, 909, 953, 0, 482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 483 /* 0x53 - 1600x900@60Hz */ 484 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 485 1704, 1800, 0, 900, 901, 904, 1000, 0, 486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 487 /* 0x33 - 1600x1200@60Hz */ 488 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 489 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 491 /* 0x34 - 1600x1200@65Hz */ 492 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 493 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 495 /* 0x35 - 1600x1200@70Hz */ 496 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 497 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 499 /* 0x36 - 1600x1200@75Hz */ 500 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 501 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 503 /* 0x37 - 1600x1200@85Hz */ 504 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 505 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 507 /* 0x38 - 1600x1200@120Hz RB */ 508 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 509 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 511 /* 0x39 - 1680x1050@60Hz RB */ 512 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 513 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 515 /* 0x3a - 1680x1050@60Hz */ 516 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 517 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 518 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 519 /* 0x3b - 1680x1050@75Hz */ 520 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 521 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 522 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 523 /* 0x3c - 1680x1050@85Hz */ 524 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 525 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 526 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 527 /* 0x3d - 1680x1050@120Hz RB */ 528 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 529 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 531 /* 0x3e - 1792x1344@60Hz */ 532 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 533 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 535 /* 0x3f - 1792x1344@75Hz */ 536 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 537 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 539 /* 0x40 - 1792x1344@120Hz RB */ 540 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 541 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 543 /* 0x41 - 1856x1392@60Hz */ 544 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 545 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 546 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 547 /* 0x42 - 1856x1392@75Hz */ 548 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 549 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 550 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 551 /* 0x43 - 1856x1392@120Hz RB */ 552 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 553 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 555 /* 0x52 - 1920x1080@60Hz */ 556 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 557 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 559 /* 0x44 - 1920x1200@60Hz RB */ 560 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 561 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 563 /* 0x45 - 1920x1200@60Hz */ 564 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 565 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 566 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 567 /* 0x46 - 1920x1200@75Hz */ 568 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 569 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 570 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 571 /* 0x47 - 1920x1200@85Hz */ 572 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 573 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 574 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 575 /* 0x48 - 1920x1200@120Hz RB */ 576 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 577 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 578 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 579 /* 0x49 - 1920x1440@60Hz */ 580 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 581 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 582 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 583 /* 0x4a - 1920x1440@75Hz */ 584 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 585 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 586 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 587 /* 0x4b - 1920x1440@120Hz RB */ 588 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 589 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 591 /* 0x54 - 2048x1152@60Hz */ 592 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 593 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 595 /* 0x4c - 2560x1600@60Hz RB */ 596 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 597 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 598 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 599 /* 0x4d - 2560x1600@60Hz */ 600 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 601 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 602 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 603 /* 0x4e - 2560x1600@75Hz */ 604 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 605 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 607 /* 0x4f - 2560x1600@85Hz */ 608 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 609 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 611 /* 0x50 - 2560x1600@120Hz RB */ 612 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 613 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 615 /* 0x57 - 4096x2160@60Hz RB */ 616 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 617 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 619 /* 0x58 - 4096x2160@59.94Hz RB */ 620 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 621 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 622 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 623}; 624 625/* 626 * These more or less come from the DMT spec. The 720x400 modes are 627 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 628 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 629 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 630 * mode. 631 * 632 * The DMT modes have been fact-checked; the rest are mild guesses. 633 */ 634static const struct drm_display_mode edid_est_modes[] = { 635 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 636 968, 1056, 0, 600, 601, 605, 628, 0, 637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 638 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 639 896, 1024, 0, 600, 601, 603, 625, 0, 640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 641 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 642 720, 840, 0, 480, 481, 484, 500, 0, 643 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 644 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 645 704, 832, 0, 480, 489, 492, 520, 0, 646 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 647 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 648 768, 864, 0, 480, 483, 486, 525, 0, 649 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 650 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 651 752, 800, 0, 480, 490, 492, 525, 0, 652 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 653 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 654 846, 900, 0, 400, 421, 423, 449, 0, 655 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 656 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 657 846, 900, 0, 400, 412, 414, 449, 0, 658 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 659 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 660 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 661 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 662 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 663 1136, 1312, 0, 768, 769, 772, 800, 0, 664 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 665 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 666 1184, 1328, 0, 768, 771, 777, 806, 0, 667 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 668 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 669 1184, 1344, 0, 768, 771, 777, 806, 0, 670 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 671 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 672 1208, 1264, 0, 768, 768, 776, 817, 0, 673 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 674 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 675 928, 1152, 0, 624, 625, 628, 667, 0, 676 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 677 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 678 896, 1056, 0, 600, 601, 604, 625, 0, 679 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 680 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 681 976, 1040, 0, 600, 637, 643, 666, 0, 682 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 683 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 684 1344, 1600, 0, 864, 865, 868, 900, 0, 685 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 686}; 687 688struct minimode { 689 short w; 690 short h; 691 short r; 692 short rb; 693}; 694 695static const struct minimode est3_modes[] = { 696 /* byte 6 */ 697 { 640, 350, 85, 0 }, 698 { 640, 400, 85, 0 }, 699 { 720, 400, 85, 0 }, 700 { 640, 480, 85, 0 }, 701 { 848, 480, 60, 0 }, 702 { 800, 600, 85, 0 }, 703 { 1024, 768, 85, 0 }, 704 { 1152, 864, 75, 0 }, 705 /* byte 7 */ 706 { 1280, 768, 60, 1 }, 707 { 1280, 768, 60, 0 }, 708 { 1280, 768, 75, 0 }, 709 { 1280, 768, 85, 0 }, 710 { 1280, 960, 60, 0 }, 711 { 1280, 960, 85, 0 }, 712 { 1280, 1024, 60, 0 }, 713 { 1280, 1024, 85, 0 }, 714 /* byte 8 */ 715 { 1360, 768, 60, 0 }, 716 { 1440, 900, 60, 1 }, 717 { 1440, 900, 60, 0 }, 718 { 1440, 900, 75, 0 }, 719 { 1440, 900, 85, 0 }, 720 { 1400, 1050, 60, 1 }, 721 { 1400, 1050, 60, 0 }, 722 { 1400, 1050, 75, 0 }, 723 /* byte 9 */ 724 { 1400, 1050, 85, 0 }, 725 { 1680, 1050, 60, 1 }, 726 { 1680, 1050, 60, 0 }, 727 { 1680, 1050, 75, 0 }, 728 { 1680, 1050, 85, 0 }, 729 { 1600, 1200, 60, 0 }, 730 { 1600, 1200, 65, 0 }, 731 { 1600, 1200, 70, 0 }, 732 /* byte 10 */ 733 { 1600, 1200, 75, 0 }, 734 { 1600, 1200, 85, 0 }, 735 { 1792, 1344, 60, 0 }, 736 { 1792, 1344, 75, 0 }, 737 { 1856, 1392, 60, 0 }, 738 { 1856, 1392, 75, 0 }, 739 { 1920, 1200, 60, 1 }, 740 { 1920, 1200, 60, 0 }, 741 /* byte 11 */ 742 { 1920, 1200, 75, 0 }, 743 { 1920, 1200, 85, 0 }, 744 { 1920, 1440, 60, 0 }, 745 { 1920, 1440, 75, 0 }, 746}; 747 748static const struct minimode extra_modes[] = { 749 { 1024, 576, 60, 0 }, 750 { 1366, 768, 60, 0 }, 751 { 1600, 900, 60, 0 }, 752 { 1680, 945, 60, 0 }, 753 { 1920, 1080, 60, 0 }, 754 { 2048, 1152, 60, 0 }, 755 { 2048, 1536, 60, 0 }, 756}; 757 758/* 759 * From CEA/CTA-861 spec. 760 * 761 * Do not access directly, instead always use cea_mode_for_vic(). 762 */ 763static const struct drm_display_mode edid_cea_modes_1[] = { 764 /* 1 - 640x480@60Hz 4:3 */ 765 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 766 752, 800, 0, 480, 490, 492, 525, 0, 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 768 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 769 /* 2 - 720x480@60Hz 4:3 */ 770 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 771 798, 858, 0, 480, 489, 495, 525, 0, 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 773 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 774 /* 3 - 720x480@60Hz 16:9 */ 775 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 776 798, 858, 0, 480, 489, 495, 525, 0, 777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 778 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 779 /* 4 - 1280x720@60Hz 16:9 */ 780 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 781 1430, 1650, 0, 720, 725, 730, 750, 0, 782 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 783 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 784 /* 5 - 1920x1080i@60Hz 16:9 */ 785 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 786 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 787 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 788 DRM_MODE_FLAG_INTERLACE), 789 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 790 /* 6 - 720(1440)x480i@60Hz 4:3 */ 791 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 792 801, 858, 0, 480, 488, 494, 525, 0, 793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 794 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 795 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 796 /* 7 - 720(1440)x480i@60Hz 16:9 */ 797 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 798 801, 858, 0, 480, 488, 494, 525, 0, 799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 800 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 801 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 802 /* 8 - 720(1440)x240@60Hz 4:3 */ 803 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 804 801, 858, 0, 240, 244, 247, 262, 0, 805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 806 DRM_MODE_FLAG_DBLCLK), 807 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 808 /* 9 - 720(1440)x240@60Hz 16:9 */ 809 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 810 801, 858, 0, 240, 244, 247, 262, 0, 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 812 DRM_MODE_FLAG_DBLCLK), 813 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 814 /* 10 - 2880x480i@60Hz 4:3 */ 815 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 816 3204, 3432, 0, 480, 488, 494, 525, 0, 817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 818 DRM_MODE_FLAG_INTERLACE), 819 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 820 /* 11 - 2880x480i@60Hz 16:9 */ 821 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 822 3204, 3432, 0, 480, 488, 494, 525, 0, 823 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 824 DRM_MODE_FLAG_INTERLACE), 825 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 826 /* 12 - 2880x240@60Hz 4:3 */ 827 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 828 3204, 3432, 0, 240, 244, 247, 262, 0, 829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 830 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 831 /* 13 - 2880x240@60Hz 16:9 */ 832 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 833 3204, 3432, 0, 240, 244, 247, 262, 0, 834 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 835 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 836 /* 14 - 1440x480@60Hz 4:3 */ 837 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 838 1596, 1716, 0, 480, 489, 495, 525, 0, 839 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 840 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 841 /* 15 - 1440x480@60Hz 16:9 */ 842 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 843 1596, 1716, 0, 480, 489, 495, 525, 0, 844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 846 /* 16 - 1920x1080@60Hz 16:9 */ 847 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 848 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 850 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 851 /* 17 - 720x576@50Hz 4:3 */ 852 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 853 796, 864, 0, 576, 581, 586, 625, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 855 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 856 /* 18 - 720x576@50Hz 16:9 */ 857 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 858 796, 864, 0, 576, 581, 586, 625, 0, 859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 860 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 861 /* 19 - 1280x720@50Hz 16:9 */ 862 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 863 1760, 1980, 0, 720, 725, 730, 750, 0, 864 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 865 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 866 /* 20 - 1920x1080i@50Hz 16:9 */ 867 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 868 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 869 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 870 DRM_MODE_FLAG_INTERLACE), 871 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 872 /* 21 - 720(1440)x576i@50Hz 4:3 */ 873 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 874 795, 864, 0, 576, 580, 586, 625, 0, 875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 876 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 877 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 878 /* 22 - 720(1440)x576i@50Hz 16:9 */ 879 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 880 795, 864, 0, 576, 580, 586, 625, 0, 881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 882 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 883 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 884 /* 23 - 720(1440)x288@50Hz 4:3 */ 885 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 886 795, 864, 0, 288, 290, 293, 312, 0, 887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 888 DRM_MODE_FLAG_DBLCLK), 889 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 890 /* 24 - 720(1440)x288@50Hz 16:9 */ 891 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 892 795, 864, 0, 288, 290, 293, 312, 0, 893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 894 DRM_MODE_FLAG_DBLCLK), 895 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 896 /* 25 - 2880x576i@50Hz 4:3 */ 897 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 898 3180, 3456, 0, 576, 580, 586, 625, 0, 899 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 900 DRM_MODE_FLAG_INTERLACE), 901 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 902 /* 26 - 2880x576i@50Hz 16:9 */ 903 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 904 3180, 3456, 0, 576, 580, 586, 625, 0, 905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 906 DRM_MODE_FLAG_INTERLACE), 907 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 908 /* 27 - 2880x288@50Hz 4:3 */ 909 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 910 3180, 3456, 0, 288, 290, 293, 312, 0, 911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 913 /* 28 - 2880x288@50Hz 16:9 */ 914 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 915 3180, 3456, 0, 288, 290, 293, 312, 0, 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 917 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 918 /* 29 - 1440x576@50Hz 4:3 */ 919 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 920 1592, 1728, 0, 576, 581, 586, 625, 0, 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 922 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 923 /* 30 - 1440x576@50Hz 16:9 */ 924 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 925 1592, 1728, 0, 576, 581, 586, 625, 0, 926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 927 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 928 /* 31 - 1920x1080@50Hz 16:9 */ 929 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 930 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 931 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 932 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 933 /* 32 - 1920x1080@24Hz 16:9 */ 934 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 935 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 936 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 937 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 938 /* 33 - 1920x1080@25Hz 16:9 */ 939 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 940 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 941 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 942 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 943 /* 34 - 1920x1080@30Hz 16:9 */ 944 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 945 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 948 /* 35 - 2880x480@60Hz 4:3 */ 949 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 950 3192, 3432, 0, 480, 489, 495, 525, 0, 951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 952 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 953 /* 36 - 2880x480@60Hz 16:9 */ 954 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 955 3192, 3432, 0, 480, 489, 495, 525, 0, 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 957 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 958 /* 37 - 2880x576@50Hz 4:3 */ 959 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 960 3184, 3456, 0, 576, 581, 586, 625, 0, 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 962 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 963 /* 38 - 2880x576@50Hz 16:9 */ 964 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 965 3184, 3456, 0, 576, 581, 586, 625, 0, 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 967 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 968 /* 39 - 1920x1080i@50Hz 16:9 */ 969 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 970 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 972 DRM_MODE_FLAG_INTERLACE), 973 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 974 /* 40 - 1920x1080i@100Hz 16:9 */ 975 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 976 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 978 DRM_MODE_FLAG_INTERLACE), 979 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 980 /* 41 - 1280x720@100Hz 16:9 */ 981 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 982 1760, 1980, 0, 720, 725, 730, 750, 0, 983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 984 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 985 /* 42 - 720x576@100Hz 4:3 */ 986 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 987 796, 864, 0, 576, 581, 586, 625, 0, 988 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 989 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 990 /* 43 - 720x576@100Hz 16:9 */ 991 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 992 796, 864, 0, 576, 581, 586, 625, 0, 993 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 995 /* 44 - 720(1440)x576i@100Hz 4:3 */ 996 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 997 795, 864, 0, 576, 580, 586, 625, 0, 998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 999 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1000 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1001 /* 45 - 720(1440)x576i@100Hz 16:9 */ 1002 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 1003 795, 864, 0, 576, 580, 586, 625, 0, 1004 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1005 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1006 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1007 /* 46 - 1920x1080i@120Hz 16:9 */ 1008 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1009 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 1010 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1011 DRM_MODE_FLAG_INTERLACE), 1012 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1013 /* 47 - 1280x720@120Hz 16:9 */ 1014 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1015 1430, 1650, 0, 720, 725, 730, 750, 0, 1016 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1017 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1018 /* 48 - 720x480@120Hz 4:3 */ 1019 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 1020 798, 858, 0, 480, 489, 495, 525, 0, 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1022 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1023 /* 49 - 720x480@120Hz 16:9 */ 1024 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 1025 798, 858, 0, 480, 489, 495, 525, 0, 1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1027 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1028 /* 50 - 720(1440)x480i@120Hz 4:3 */ 1029 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1030 801, 858, 0, 480, 488, 494, 525, 0, 1031 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1032 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1033 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1034 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1035 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1036 801, 858, 0, 480, 488, 494, 525, 0, 1037 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1038 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1039 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1040 /* 52 - 720x576@200Hz 4:3 */ 1041 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1042 796, 864, 0, 576, 581, 586, 625, 0, 1043 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1044 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1045 /* 53 - 720x576@200Hz 16:9 */ 1046 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1047 796, 864, 0, 576, 581, 586, 625, 0, 1048 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1049 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1050 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1051 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1052 795, 864, 0, 576, 580, 586, 625, 0, 1053 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1054 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1055 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1056 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1057 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1058 795, 864, 0, 576, 580, 586, 625, 0, 1059 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1060 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1061 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1062 /* 56 - 720x480@240Hz 4:3 */ 1063 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1064 798, 858, 0, 480, 489, 495, 525, 0, 1065 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1066 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1067 /* 57 - 720x480@240Hz 16:9 */ 1068 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1069 798, 858, 0, 480, 489, 495, 525, 0, 1070 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1071 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1072 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1073 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1074 801, 858, 0, 480, 488, 494, 525, 0, 1075 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1076 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1077 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1078 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1079 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1080 801, 858, 0, 480, 488, 494, 525, 0, 1081 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1082 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1083 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1084 /* 60 - 1280x720@24Hz 16:9 */ 1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1086 3080, 3300, 0, 720, 725, 730, 750, 0, 1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1088 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1089 /* 61 - 1280x720@25Hz 16:9 */ 1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1091 3740, 3960, 0, 720, 725, 730, 750, 0, 1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1093 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1094 /* 62 - 1280x720@30Hz 16:9 */ 1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1096 3080, 3300, 0, 720, 725, 730, 750, 0, 1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1098 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1099 /* 63 - 1920x1080@120Hz 16:9 */ 1100 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1101 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1103 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1104 /* 64 - 1920x1080@100Hz 16:9 */ 1105 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1106 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1108 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1109 /* 65 - 1280x720@24Hz 64:27 */ 1110 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1111 3080, 3300, 0, 720, 725, 730, 750, 0, 1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1113 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1114 /* 66 - 1280x720@25Hz 64:27 */ 1115 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1116 3740, 3960, 0, 720, 725, 730, 750, 0, 1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1118 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1119 /* 67 - 1280x720@30Hz 64:27 */ 1120 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1121 3080, 3300, 0, 720, 725, 730, 750, 0, 1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1123 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1124 /* 68 - 1280x720@50Hz 64:27 */ 1125 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1126 1760, 1980, 0, 720, 725, 730, 750, 0, 1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1128 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1129 /* 69 - 1280x720@60Hz 64:27 */ 1130 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1131 1430, 1650, 0, 720, 725, 730, 750, 0, 1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1133 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1134 /* 70 - 1280x720@100Hz 64:27 */ 1135 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1136 1760, 1980, 0, 720, 725, 730, 750, 0, 1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1138 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1139 /* 71 - 1280x720@120Hz 64:27 */ 1140 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1141 1430, 1650, 0, 720, 725, 730, 750, 0, 1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1143 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1144 /* 72 - 1920x1080@24Hz 64:27 */ 1145 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1146 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1148 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1149 /* 73 - 1920x1080@25Hz 64:27 */ 1150 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1151 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1153 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1154 /* 74 - 1920x1080@30Hz 64:27 */ 1155 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1156 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1158 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1159 /* 75 - 1920x1080@50Hz 64:27 */ 1160 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1161 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1163 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1164 /* 76 - 1920x1080@60Hz 64:27 */ 1165 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1166 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1168 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1169 /* 77 - 1920x1080@100Hz 64:27 */ 1170 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1171 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1173 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1174 /* 78 - 1920x1080@120Hz 64:27 */ 1175 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1176 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1178 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1179 /* 79 - 1680x720@24Hz 64:27 */ 1180 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1181 3080, 3300, 0, 720, 725, 730, 750, 0, 1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1183 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1184 /* 80 - 1680x720@25Hz 64:27 */ 1185 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1186 2948, 3168, 0, 720, 725, 730, 750, 0, 1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1188 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1189 /* 81 - 1680x720@30Hz 64:27 */ 1190 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1191 2420, 2640, 0, 720, 725, 730, 750, 0, 1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1193 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1194 /* 82 - 1680x720@50Hz 64:27 */ 1195 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1196 1980, 2200, 0, 720, 725, 730, 750, 0, 1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1198 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1199 /* 83 - 1680x720@60Hz 64:27 */ 1200 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1201 1980, 2200, 0, 720, 725, 730, 750, 0, 1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1203 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1204 /* 84 - 1680x720@100Hz 64:27 */ 1205 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1206 1780, 2000, 0, 720, 725, 730, 825, 0, 1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1208 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1209 /* 85 - 1680x720@120Hz 64:27 */ 1210 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1211 1780, 2000, 0, 720, 725, 730, 825, 0, 1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1213 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1214 /* 86 - 2560x1080@24Hz 64:27 */ 1215 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1216 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1218 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1219 /* 87 - 2560x1080@25Hz 64:27 */ 1220 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1221 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1223 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1224 /* 88 - 2560x1080@30Hz 64:27 */ 1225 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1226 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1228 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1229 /* 89 - 2560x1080@50Hz 64:27 */ 1230 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1231 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1233 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1234 /* 90 - 2560x1080@60Hz 64:27 */ 1235 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1236 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1238 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1239 /* 91 - 2560x1080@100Hz 64:27 */ 1240 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1241 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1243 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1244 /* 92 - 2560x1080@120Hz 64:27 */ 1245 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1246 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1248 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1249 /* 93 - 3840x2160@24Hz 16:9 */ 1250 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1251 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1253 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1254 /* 94 - 3840x2160@25Hz 16:9 */ 1255 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1256 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1258 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1259 /* 95 - 3840x2160@30Hz 16:9 */ 1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1261 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1263 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1264 /* 96 - 3840x2160@50Hz 16:9 */ 1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1266 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1268 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1269 /* 97 - 3840x2160@60Hz 16:9 */ 1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1271 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1273 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1274 /* 98 - 4096x2160@24Hz 256:135 */ 1275 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1276 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1278 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1279 /* 99 - 4096x2160@25Hz 256:135 */ 1280 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1281 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1283 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1284 /* 100 - 4096x2160@30Hz 256:135 */ 1285 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1286 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1288 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1289 /* 101 - 4096x2160@50Hz 256:135 */ 1290 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1291 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1293 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1294 /* 102 - 4096x2160@60Hz 256:135 */ 1295 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1296 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1298 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1299 /* 103 - 3840x2160@24Hz 64:27 */ 1300 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1301 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1303 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1304 /* 104 - 3840x2160@25Hz 64:27 */ 1305 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1306 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1308 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1309 /* 105 - 3840x2160@30Hz 64:27 */ 1310 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1311 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1313 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1314 /* 106 - 3840x2160@50Hz 64:27 */ 1315 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1316 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1318 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1319 /* 107 - 3840x2160@60Hz 64:27 */ 1320 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1321 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1324 /* 108 - 1280x720@48Hz 16:9 */ 1325 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1326 2280, 2500, 0, 720, 725, 730, 750, 0, 1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1328 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1329 /* 109 - 1280x720@48Hz 64:27 */ 1330 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1331 2280, 2500, 0, 720, 725, 730, 750, 0, 1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1333 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1334 /* 110 - 1680x720@48Hz 64:27 */ 1335 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1336 2530, 2750, 0, 720, 725, 730, 750, 0, 1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1338 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1339 /* 111 - 1920x1080@48Hz 16:9 */ 1340 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1341 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1343 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1344 /* 112 - 1920x1080@48Hz 64:27 */ 1345 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1346 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1348 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1349 /* 113 - 2560x1080@48Hz 64:27 */ 1350 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1351 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1354 /* 114 - 3840x2160@48Hz 16:9 */ 1355 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1356 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1359 /* 115 - 4096x2160@48Hz 256:135 */ 1360 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1361 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1363 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1364 /* 116 - 3840x2160@48Hz 64:27 */ 1365 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1366 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1368 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1369 /* 117 - 3840x2160@100Hz 16:9 */ 1370 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1371 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1373 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1374 /* 118 - 3840x2160@120Hz 16:9 */ 1375 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1376 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1378 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1379 /* 119 - 3840x2160@100Hz 64:27 */ 1380 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1381 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1383 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1384 /* 120 - 3840x2160@120Hz 64:27 */ 1385 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1386 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1388 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1389 /* 121 - 5120x2160@24Hz 64:27 */ 1390 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1391 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1393 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1394 /* 122 - 5120x2160@25Hz 64:27 */ 1395 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1396 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1398 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1399 /* 123 - 5120x2160@30Hz 64:27 */ 1400 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1401 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1403 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1404 /* 124 - 5120x2160@48Hz 64:27 */ 1405 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1406 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1408 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1409 /* 125 - 5120x2160@50Hz 64:27 */ 1410 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1411 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1413 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1414 /* 126 - 5120x2160@60Hz 64:27 */ 1415 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1416 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1418 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1419 /* 127 - 5120x2160@100Hz 64:27 */ 1420 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1421 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1423 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1424}; 1425 1426/* 1427 * From CEA/CTA-861 spec. 1428 * 1429 * Do not access directly, instead always use cea_mode_for_vic(). 1430 */ 1431static const struct drm_display_mode edid_cea_modes_193[] = { 1432 /* 193 - 5120x2160@120Hz 64:27 */ 1433 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1434 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1437 /* 194 - 7680x4320@24Hz 16:9 */ 1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1439 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1442 /* 195 - 7680x4320@25Hz 16:9 */ 1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1444 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1447 /* 196 - 7680x4320@30Hz 16:9 */ 1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1449 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1451 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1452 /* 197 - 7680x4320@48Hz 16:9 */ 1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1454 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1456 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1457 /* 198 - 7680x4320@50Hz 16:9 */ 1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1459 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1461 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1462 /* 199 - 7680x4320@60Hz 16:9 */ 1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1464 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1466 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1467 /* 200 - 7680x4320@100Hz 16:9 */ 1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1469 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1471 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1472 /* 201 - 7680x4320@120Hz 16:9 */ 1473 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1474 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1476 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1477 /* 202 - 7680x4320@24Hz 64:27 */ 1478 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1479 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1481 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1482 /* 203 - 7680x4320@25Hz 64:27 */ 1483 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1484 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1486 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1487 /* 204 - 7680x4320@30Hz 64:27 */ 1488 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1489 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1491 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1492 /* 205 - 7680x4320@48Hz 64:27 */ 1493 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1494 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1496 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1497 /* 206 - 7680x4320@50Hz 64:27 */ 1498 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1499 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1501 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1502 /* 207 - 7680x4320@60Hz 64:27 */ 1503 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1504 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1506 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1507 /* 208 - 7680x4320@100Hz 64:27 */ 1508 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1509 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1511 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1512 /* 209 - 7680x4320@120Hz 64:27 */ 1513 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1514 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1516 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1517 /* 210 - 10240x4320@24Hz 64:27 */ 1518 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1519 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1521 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1522 /* 211 - 10240x4320@25Hz 64:27 */ 1523 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1524 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1526 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1527 /* 212 - 10240x4320@30Hz 64:27 */ 1528 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1529 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1531 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1532 /* 213 - 10240x4320@48Hz 64:27 */ 1533 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1534 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1536 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1537 /* 214 - 10240x4320@50Hz 64:27 */ 1538 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1539 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1541 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1542 /* 215 - 10240x4320@60Hz 64:27 */ 1543 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1544 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1546 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1547 /* 216 - 10240x4320@100Hz 64:27 */ 1548 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1549 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1551 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1552 /* 217 - 10240x4320@120Hz 64:27 */ 1553 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1554 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1556 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1557 /* 218 - 4096x2160@100Hz 256:135 */ 1558 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1559 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1561 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1562 /* 219 - 4096x2160@120Hz 256:135 */ 1563 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1564 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1567}; 1568 1569/* 1570 * HDMI 1.4 4k modes. Index using the VIC. 1571 */ 1572static const struct drm_display_mode edid_4k_modes[] = { 1573 /* 0 - dummy, VICs start at 1 */ 1574 { }, 1575 /* 1 - 3840x2160@30Hz */ 1576 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1577 3840, 4016, 4104, 4400, 0, 1578 2160, 2168, 2178, 2250, 0, 1579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1580 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1581 /* 2 - 3840x2160@25Hz */ 1582 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1583 3840, 4896, 4984, 5280, 0, 1584 2160, 2168, 2178, 2250, 0, 1585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1586 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1587 /* 3 - 3840x2160@24Hz */ 1588 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1589 3840, 5116, 5204, 5500, 0, 1590 2160, 2168, 2178, 2250, 0, 1591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1592 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1593 /* 4 - 4096x2160@24Hz (SMPTE) */ 1594 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1595 4096, 5116, 5204, 5500, 0, 1596 2160, 2168, 2178, 2250, 0, 1597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1598 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1599}; 1600 1601/*** DDC fetch and block validation ***/ 1602 1603/* 1604 * The opaque EDID type, internal to drm_edid.c. 1605 */ 1606struct drm_edid { 1607 /* Size allocated for edid */ 1608 size_t size; 1609 const struct edid *edid; 1610}; 1611 1612static int edid_hfeeodb_extension_block_count(const struct edid *edid); 1613 1614static int edid_hfeeodb_block_count(const struct edid *edid) 1615{ 1616 int eeodb = edid_hfeeodb_extension_block_count(edid); 1617 1618 return eeodb ? eeodb + 1 : 0; 1619} 1620 1621static int edid_extension_block_count(const struct edid *edid) 1622{ 1623 return edid->extensions; 1624} 1625 1626static int edid_block_count(const struct edid *edid) 1627{ 1628 return edid_extension_block_count(edid) + 1; 1629} 1630 1631static int edid_size_by_blocks(int num_blocks) 1632{ 1633 return num_blocks * EDID_LENGTH; 1634} 1635 1636static int edid_size(const struct edid *edid) 1637{ 1638 return edid_size_by_blocks(edid_block_count(edid)); 1639} 1640 1641static const void *edid_block_data(const struct edid *edid, int index) 1642{ 1643 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1644 1645 return edid + index; 1646} 1647 1648static const void *edid_extension_block_data(const struct edid *edid, int index) 1649{ 1650 return edid_block_data(edid, index + 1); 1651} 1652 1653/* EDID block count indicated in EDID, may exceed allocated size */ 1654static int __drm_edid_block_count(const struct drm_edid *drm_edid) 1655{ 1656 int num_blocks; 1657 1658 /* Starting point */ 1659 num_blocks = edid_block_count(drm_edid->edid); 1660 1661 /* HF-EEODB override */ 1662 if (drm_edid->size >= edid_size_by_blocks(2)) { 1663 int eeodb; 1664 1665 /* 1666 * Note: HF-EEODB may specify a smaller extension count than the 1667 * regular one. Unlike in buffer allocation, here we can use it. 1668 */ 1669 eeodb = edid_hfeeodb_block_count(drm_edid->edid); 1670 if (eeodb) 1671 num_blocks = eeodb; 1672 } 1673 1674 return num_blocks; 1675} 1676 1677/* EDID block count, limited by allocated size */ 1678static int drm_edid_block_count(const struct drm_edid *drm_edid) 1679{ 1680 /* Limit by allocated size */ 1681 return min(__drm_edid_block_count(drm_edid), 1682 (int)drm_edid->size / EDID_LENGTH); 1683} 1684 1685/* EDID extension block count, limited by allocated size */ 1686static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1687{ 1688 return drm_edid_block_count(drm_edid) - 1; 1689} 1690 1691static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1692{ 1693 return edid_block_data(drm_edid->edid, index); 1694} 1695 1696static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1697 int index) 1698{ 1699 return edid_extension_block_data(drm_edid->edid, index); 1700} 1701 1702/* 1703 * Initializer helper for legacy interfaces, where we have no choice but to 1704 * trust edid size. Not for general purpose use. 1705 */ 1706static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1707 const struct edid *edid) 1708{ 1709 if (!edid) 1710 return NULL; 1711 1712 memset(drm_edid, 0, sizeof(*drm_edid)); 1713 1714 drm_edid->edid = edid; 1715 drm_edid->size = edid_size(edid); 1716 1717 return drm_edid; 1718} 1719 1720/* 1721 * EDID base and extension block iterator. 1722 * 1723 * struct drm_edid_iter iter; 1724 * const u8 *block; 1725 * 1726 * drm_edid_iter_begin(drm_edid, &iter); 1727 * drm_edid_iter_for_each(block, &iter) { 1728 * // do stuff with block 1729 * } 1730 * drm_edid_iter_end(&iter); 1731 */ 1732struct drm_edid_iter { 1733 const struct drm_edid *drm_edid; 1734 1735 /* Current block index. */ 1736 int index; 1737}; 1738 1739static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1740 struct drm_edid_iter *iter) 1741{ 1742 memset(iter, 0, sizeof(*iter)); 1743 1744 iter->drm_edid = drm_edid; 1745} 1746 1747static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1748{ 1749 const void *block = NULL; 1750 1751 if (!iter->drm_edid) 1752 return NULL; 1753 1754 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1755 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1756 1757 return block; 1758} 1759 1760#define drm_edid_iter_for_each(__block, __iter) \ 1761 while (((__block) = __drm_edid_iter_next(__iter))) 1762 1763static void drm_edid_iter_end(struct drm_edid_iter *iter) 1764{ 1765 memset(iter, 0, sizeof(*iter)); 1766} 1767 1768static const u8 edid_header[] = { 1769 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1770}; 1771 1772static void edid_header_fix(void *edid) 1773{ 1774 memcpy(edid, edid_header, sizeof(edid_header)); 1775} 1776 1777/** 1778 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1779 * @_edid: pointer to raw base EDID block 1780 * 1781 * Sanity check the header of the base EDID block. 1782 * 1783 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1784 */ 1785int drm_edid_header_is_valid(const void *_edid) 1786{ 1787 const struct edid *edid = _edid; 1788 int i, score = 0; 1789 1790 for (i = 0; i < sizeof(edid_header); i++) { 1791 if (edid->header[i] == edid_header[i]) 1792 score++; 1793 } 1794 1795 return score; 1796} 1797EXPORT_SYMBOL(drm_edid_header_is_valid); 1798 1799static int edid_fixup __read_mostly = 6; 1800module_param_named(edid_fixup, edid_fixup, int, 0400); 1801MODULE_PARM_DESC(edid_fixup, 1802 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1803 1804static int edid_block_compute_checksum(const void *_block) 1805{ 1806 const u8 *block = _block; 1807 int i; 1808 u8 csum = 0, crc = 0; 1809 1810 for (i = 0; i < EDID_LENGTH - 1; i++) 1811 csum += block[i]; 1812 1813 crc = 0x100 - csum; 1814 1815 return crc; 1816} 1817 1818static int edid_block_get_checksum(const void *_block) 1819{ 1820 const struct edid *block = _block; 1821 1822 return block->checksum; 1823} 1824 1825static int edid_block_tag(const void *_block) 1826{ 1827 const u8 *block = _block; 1828 1829 return block[0]; 1830} 1831 1832static bool edid_block_is_zero(const void *edid) 1833{ 1834 return mem_is_zero(edid, EDID_LENGTH); 1835} 1836 1837static bool drm_edid_eq(const struct drm_edid *drm_edid, 1838 const void *raw_edid, size_t raw_edid_size) 1839{ 1840 bool edid1_present = drm_edid && drm_edid->edid && drm_edid->size; 1841 bool edid2_present = raw_edid && raw_edid_size; 1842 1843 if (edid1_present != edid2_present) 1844 return false; 1845 1846 if (edid1_present) { 1847 if (drm_edid->size != raw_edid_size) 1848 return false; 1849 1850 if (memcmp(drm_edid->edid, raw_edid, drm_edid->size)) 1851 return false; 1852 } 1853 1854 return true; 1855} 1856 1857enum edid_block_status { 1858 EDID_BLOCK_OK = 0, 1859 EDID_BLOCK_READ_FAIL, 1860 EDID_BLOCK_NULL, 1861 EDID_BLOCK_ZERO, 1862 EDID_BLOCK_HEADER_CORRUPT, 1863 EDID_BLOCK_HEADER_REPAIR, 1864 EDID_BLOCK_HEADER_FIXED, 1865 EDID_BLOCK_CHECKSUM, 1866 EDID_BLOCK_VERSION, 1867}; 1868 1869static enum edid_block_status edid_block_check(const void *_block, 1870 bool is_base_block) 1871{ 1872 const struct edid *block = _block; 1873 1874 if (!block) 1875 return EDID_BLOCK_NULL; 1876 1877 if (is_base_block) { 1878 int score = drm_edid_header_is_valid(block); 1879 1880 if (score < clamp(edid_fixup, 0, 8)) { 1881 if (edid_block_is_zero(block)) 1882 return EDID_BLOCK_ZERO; 1883 else 1884 return EDID_BLOCK_HEADER_CORRUPT; 1885 } 1886 1887 if (score < 8) 1888 return EDID_BLOCK_HEADER_REPAIR; 1889 } 1890 1891 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1892 if (edid_block_is_zero(block)) 1893 return EDID_BLOCK_ZERO; 1894 else 1895 return EDID_BLOCK_CHECKSUM; 1896 } 1897 1898 if (is_base_block) { 1899 if (block->version != 1) 1900 return EDID_BLOCK_VERSION; 1901 } 1902 1903 return EDID_BLOCK_OK; 1904} 1905 1906static bool edid_block_status_valid(enum edid_block_status status, int tag) 1907{ 1908 return status == EDID_BLOCK_OK || 1909 status == EDID_BLOCK_HEADER_FIXED || 1910 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1911} 1912 1913static bool edid_block_valid(const void *block, bool base) 1914{ 1915 return edid_block_status_valid(edid_block_check(block, base), 1916 edid_block_tag(block)); 1917} 1918 1919static void edid_block_status_print(enum edid_block_status status, 1920 const struct edid *block, 1921 int block_num) 1922{ 1923 switch (status) { 1924 case EDID_BLOCK_OK: 1925 break; 1926 case EDID_BLOCK_READ_FAIL: 1927 pr_debug("EDID block %d read failed\n", block_num); 1928 break; 1929 case EDID_BLOCK_NULL: 1930 pr_debug("EDID block %d pointer is NULL\n", block_num); 1931 break; 1932 case EDID_BLOCK_ZERO: 1933 pr_notice("EDID block %d is all zeroes\n", block_num); 1934 break; 1935 case EDID_BLOCK_HEADER_CORRUPT: 1936 pr_notice("EDID has corrupt header\n"); 1937 break; 1938 case EDID_BLOCK_HEADER_REPAIR: 1939 pr_debug("EDID corrupt header needs repair\n"); 1940 break; 1941 case EDID_BLOCK_HEADER_FIXED: 1942 pr_debug("EDID corrupt header fixed\n"); 1943 break; 1944 case EDID_BLOCK_CHECKSUM: 1945 if (edid_block_status_valid(status, edid_block_tag(block))) { 1946 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1947 block_num, edid_block_tag(block), 1948 edid_block_compute_checksum(block)); 1949 } else { 1950 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1951 block_num, edid_block_tag(block), 1952 edid_block_compute_checksum(block)); 1953 } 1954 break; 1955 case EDID_BLOCK_VERSION: 1956 pr_notice("EDID has major version %d, instead of 1\n", 1957 block->version); 1958 break; 1959 default: 1960 WARN(1, "EDID block %d unknown edid block status code %d\n", 1961 block_num, status); 1962 break; 1963 } 1964} 1965 1966static void edid_block_dump(const char *level, const void *block, int block_num) 1967{ 1968 enum edid_block_status status; 1969 char prefix[20]; 1970 1971 status = edid_block_check(block, block_num == 0); 1972 if (status == EDID_BLOCK_ZERO) 1973 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1974 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1975 sprintf(prefix, "\t[%02x] BAD ", block_num); 1976 else 1977 sprintf(prefix, "\t[%02x] GOOD ", block_num); 1978 1979 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1980 block, EDID_LENGTH, false); 1981} 1982 1983/* 1984 * Validate a base or extension EDID block and optionally dump bad blocks to 1985 * the console. 1986 */ 1987static bool drm_edid_block_valid(void *_block, int block_num, bool print_bad_edid, 1988 bool *edid_corrupt) 1989{ 1990 struct edid *block = _block; 1991 enum edid_block_status status; 1992 bool is_base_block = block_num == 0; 1993 bool valid; 1994 1995 if (WARN_ON(!block)) 1996 return false; 1997 1998 status = edid_block_check(block, is_base_block); 1999 if (status == EDID_BLOCK_HEADER_REPAIR) { 2000 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n"); 2001 edid_header_fix(block); 2002 2003 /* Retry with fixed header, update status if that worked. */ 2004 status = edid_block_check(block, is_base_block); 2005 if (status == EDID_BLOCK_OK) 2006 status = EDID_BLOCK_HEADER_FIXED; 2007 } 2008 2009 if (edid_corrupt) { 2010 /* 2011 * Unknown major version isn't corrupt but we can't use it. Only 2012 * the base block can reset edid_corrupt to false. 2013 */ 2014 if (is_base_block && 2015 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 2016 *edid_corrupt = false; 2017 else if (status != EDID_BLOCK_OK) 2018 *edid_corrupt = true; 2019 } 2020 2021 edid_block_status_print(status, block, block_num); 2022 2023 /* Determine whether we can use this block with this status. */ 2024 valid = edid_block_status_valid(status, edid_block_tag(block)); 2025 2026 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 2027 pr_notice("Raw EDID:\n"); 2028 edid_block_dump(KERN_NOTICE, block, block_num); 2029 } 2030 2031 return valid; 2032} 2033 2034/** 2035 * drm_edid_is_valid - sanity check EDID data 2036 * @edid: EDID data 2037 * 2038 * Sanity-check an entire EDID record (including extensions) 2039 * 2040 * Return: True if the EDID data is valid, false otherwise. 2041 */ 2042bool drm_edid_is_valid(struct edid *edid) 2043{ 2044 int i; 2045 2046 if (!edid) 2047 return false; 2048 2049 for (i = 0; i < edid_block_count(edid); i++) { 2050 void *block = (void *)edid_block_data(edid, i); 2051 2052 if (!drm_edid_block_valid(block, i, true, NULL)) 2053 return false; 2054 } 2055 2056 return true; 2057} 2058EXPORT_SYMBOL(drm_edid_is_valid); 2059 2060/** 2061 * drm_edid_valid - sanity check EDID data 2062 * @drm_edid: EDID data 2063 * 2064 * Sanity check an EDID. Cross check block count against allocated size and 2065 * checksum the blocks. 2066 * 2067 * Return: True if the EDID data is valid, false otherwise. 2068 */ 2069bool drm_edid_valid(const struct drm_edid *drm_edid) 2070{ 2071 int i; 2072 2073 if (!drm_edid) 2074 return false; 2075 2076 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size) 2077 return false; 2078 2079 for (i = 0; i < drm_edid_block_count(drm_edid); i++) { 2080 const void *block = drm_edid_block_data(drm_edid, i); 2081 2082 if (!edid_block_valid(block, i == 0)) 2083 return false; 2084 } 2085 2086 return true; 2087} 2088EXPORT_SYMBOL(drm_edid_valid); 2089 2090static struct edid *edid_filter_invalid_blocks(struct edid *edid, 2091 size_t *alloc_size) 2092{ 2093 struct edid *new; 2094 int i, valid_blocks = 0; 2095 2096 /* 2097 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert 2098 * back to regular extension count here. We don't want to start 2099 * modifying the HF-EEODB extension too. 2100 */ 2101 for (i = 0; i < edid_block_count(edid); i++) { 2102 const void *src_block = edid_block_data(edid, i); 2103 2104 if (edid_block_valid(src_block, i == 0)) { 2105 void *dst_block = (void *)edid_block_data(edid, valid_blocks); 2106 2107 memmove(dst_block, src_block, EDID_LENGTH); 2108 valid_blocks++; 2109 } 2110 } 2111 2112 /* We already trusted the base block to be valid here... */ 2113 if (WARN_ON(!valid_blocks)) { 2114 kfree(edid); 2115 return NULL; 2116 } 2117 2118 edid->extensions = valid_blocks - 1; 2119 edid->checksum = edid_block_compute_checksum(edid); 2120 2121 *alloc_size = edid_size_by_blocks(valid_blocks); 2122 2123 new = krealloc(edid, *alloc_size, GFP_KERNEL); 2124 if (!new) 2125 kfree(edid); 2126 2127 return new; 2128} 2129 2130#define DDC_SEGMENT_ADDR 0x30 2131/** 2132 * drm_do_probe_ddc_edid() - get EDID information via I2C 2133 * @data: I2C device adapter 2134 * @buf: EDID data buffer to be filled 2135 * @block: 128 byte EDID block to start fetching from 2136 * @len: EDID data buffer length to fetch 2137 * 2138 * Try to fetch EDID information by calling I2C driver functions. 2139 * 2140 * Return: 0 on success or -1 on failure. 2141 */ 2142static int 2143drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2144{ 2145 struct i2c_adapter *adapter = data; 2146 unsigned char start = block * EDID_LENGTH; 2147 unsigned char segment = block >> 1; 2148 unsigned char xfers = segment ? 3 : 2; 2149 int ret, retries = 5; 2150 2151 /* 2152 * The core I2C driver will automatically retry the transfer if the 2153 * adapter reports EAGAIN. However, we find that bit-banging transfers 2154 * are susceptible to errors under a heavily loaded machine and 2155 * generate spurious NAKs and timeouts. Retrying the transfer 2156 * of the individual block a few times seems to overcome this. 2157 */ 2158 do { 2159 struct i2c_msg msgs[] = { 2160 { 2161 .addr = DDC_SEGMENT_ADDR, 2162 .flags = 0, 2163 .len = 1, 2164 .buf = &segment, 2165 }, { 2166 .addr = DDC_ADDR, 2167 .flags = 0, 2168 .len = 1, 2169 .buf = &start, 2170 }, { 2171 .addr = DDC_ADDR, 2172 .flags = I2C_M_RD, 2173 .len = len, 2174 .buf = buf, 2175 } 2176 }; 2177 2178 /* 2179 * Avoid sending the segment addr to not upset non-compliant 2180 * DDC monitors. 2181 */ 2182 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2183 2184 if (ret == -ENXIO) { 2185 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2186 adapter->name); 2187 break; 2188 } 2189 } while (ret != xfers && --retries); 2190 2191 return ret == xfers ? 0 : -1; 2192} 2193 2194static void connector_bad_edid(struct drm_connector *connector, 2195 const struct edid *edid, int num_blocks) 2196{ 2197 int i; 2198 u8 last_block; 2199 2200 /* 2201 * 0x7e in the EDID is the number of extension blocks. The EDID 2202 * is 1 (base block) + num_ext_blocks big. That means we can think 2203 * of 0x7e in the EDID of the _index_ of the last block in the 2204 * combined chunk of memory. 2205 */ 2206 last_block = edid->extensions; 2207 2208 /* Calculate real checksum for the last edid extension block data */ 2209 if (last_block < num_blocks) 2210 connector->real_edid_checksum = 2211 edid_block_compute_checksum(edid + last_block); 2212 2213 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2214 return; 2215 2216 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n", 2217 connector->base.id, connector->name); 2218 for (i = 0; i < num_blocks; i++) 2219 edid_block_dump(KERN_DEBUG, edid + i, i); 2220} 2221 2222/* Get override or firmware EDID */ 2223static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector) 2224{ 2225 const struct drm_edid *override = NULL; 2226 2227 mutex_lock(&connector->edid_override_mutex); 2228 2229 if (connector->edid_override) 2230 override = drm_edid_dup(connector->edid_override); 2231 2232 mutex_unlock(&connector->edid_override_mutex); 2233 2234 if (!override) 2235 override = drm_edid_load_firmware(connector); 2236 2237 return IS_ERR(override) ? NULL : override; 2238} 2239 2240/* For debugfs edid_override implementation */ 2241int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m) 2242{ 2243 const struct drm_edid *drm_edid; 2244 2245 mutex_lock(&connector->edid_override_mutex); 2246 2247 drm_edid = connector->edid_override; 2248 if (drm_edid) 2249 seq_write(m, drm_edid->edid, drm_edid->size); 2250 2251 mutex_unlock(&connector->edid_override_mutex); 2252 2253 return 0; 2254} 2255 2256/* For debugfs edid_override implementation */ 2257int drm_edid_override_set(struct drm_connector *connector, const void *edid, 2258 size_t size) 2259{ 2260 const struct drm_edid *drm_edid; 2261 2262 drm_edid = drm_edid_alloc(edid, size); 2263 if (!drm_edid_valid(drm_edid)) { 2264 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n", 2265 connector->base.id, connector->name); 2266 drm_edid_free(drm_edid); 2267 return -EINVAL; 2268 } 2269 2270 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n", 2271 connector->base.id, connector->name); 2272 2273 mutex_lock(&connector->edid_override_mutex); 2274 2275 drm_edid_free(connector->edid_override); 2276 connector->edid_override = drm_edid; 2277 2278 mutex_unlock(&connector->edid_override_mutex); 2279 2280 return 0; 2281} 2282 2283/* For debugfs edid_override implementation */ 2284int drm_edid_override_reset(struct drm_connector *connector) 2285{ 2286 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n", 2287 connector->base.id, connector->name); 2288 2289 mutex_lock(&connector->edid_override_mutex); 2290 2291 drm_edid_free(connector->edid_override); 2292 connector->edid_override = NULL; 2293 2294 mutex_unlock(&connector->edid_override_mutex); 2295 2296 return 0; 2297} 2298 2299/** 2300 * drm_edid_override_connector_update - add modes from override/firmware EDID 2301 * @connector: connector we're probing 2302 * 2303 * Add modes from the override/firmware EDID, if available. Only to be used from 2304 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2305 * failed during drm_get_edid() and caused the override/firmware EDID to be 2306 * skipped. 2307 * 2308 * Return: The number of modes added or 0 if we couldn't find any. 2309 */ 2310int drm_edid_override_connector_update(struct drm_connector *connector) 2311{ 2312 const struct drm_edid *override; 2313 int num_modes = 0; 2314 2315 override = drm_edid_override_get(connector); 2316 if (override) { 2317 if (drm_edid_connector_update(connector, override) == 0) 2318 num_modes = drm_edid_connector_add_modes(connector); 2319 2320 drm_edid_free(override); 2321 2322 drm_dbg_kms(connector->dev, 2323 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2324 connector->base.id, connector->name, num_modes); 2325 } 2326 2327 return num_modes; 2328} 2329EXPORT_SYMBOL(drm_edid_override_connector_update); 2330 2331typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2332 2333static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2334 read_block_fn read_block, 2335 void *context) 2336{ 2337 enum edid_block_status status; 2338 bool is_base_block = block_num == 0; 2339 int try; 2340 2341 for (try = 0; try < 4; try++) { 2342 if (read_block(context, block, block_num, EDID_LENGTH)) 2343 return EDID_BLOCK_READ_FAIL; 2344 2345 status = edid_block_check(block, is_base_block); 2346 if (status == EDID_BLOCK_HEADER_REPAIR) { 2347 edid_header_fix(block); 2348 2349 /* Retry with fixed header, update status if that worked. */ 2350 status = edid_block_check(block, is_base_block); 2351 if (status == EDID_BLOCK_OK) 2352 status = EDID_BLOCK_HEADER_FIXED; 2353 } 2354 2355 if (edid_block_status_valid(status, edid_block_tag(block))) 2356 break; 2357 2358 /* Fail early for unrepairable base block all zeros. */ 2359 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2360 break; 2361 } 2362 2363 return status; 2364} 2365 2366static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2367 read_block_fn read_block, void *context, 2368 size_t *size) 2369{ 2370 enum edid_block_status status; 2371 int i, num_blocks, invalid_blocks = 0; 2372 const struct drm_edid *override; 2373 struct edid *edid, *new; 2374 size_t alloc_size = EDID_LENGTH; 2375 2376 override = drm_edid_override_get(connector); 2377 if (override) { 2378 alloc_size = override->size; 2379 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL); 2380 drm_edid_free(override); 2381 if (!edid) 2382 return NULL; 2383 goto ok; 2384 } 2385 2386 edid = kmalloc(alloc_size, GFP_KERNEL); 2387 if (!edid) 2388 return NULL; 2389 2390 status = edid_block_read(edid, 0, read_block, context); 2391 2392 edid_block_status_print(status, edid, 0); 2393 2394 if (status == EDID_BLOCK_READ_FAIL) 2395 goto fail; 2396 2397 /* FIXME: Clarify what a corrupt EDID actually means. */ 2398 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2399 connector->edid_corrupt = false; 2400 else 2401 connector->edid_corrupt = true; 2402 2403 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2404 if (status == EDID_BLOCK_ZERO) 2405 connector->null_edid_counter++; 2406 2407 connector_bad_edid(connector, edid, 1); 2408 goto fail; 2409 } 2410 2411 if (!edid_extension_block_count(edid)) 2412 goto ok; 2413 2414 alloc_size = edid_size(edid); 2415 new = krealloc(edid, alloc_size, GFP_KERNEL); 2416 if (!new) 2417 goto fail; 2418 edid = new; 2419 2420 num_blocks = edid_block_count(edid); 2421 for (i = 1; i < num_blocks; i++) { 2422 void *block = (void *)edid_block_data(edid, i); 2423 2424 status = edid_block_read(block, i, read_block, context); 2425 2426 edid_block_status_print(status, block, i); 2427 2428 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2429 if (status == EDID_BLOCK_READ_FAIL) 2430 goto fail; 2431 invalid_blocks++; 2432 } else if (i == 1) { 2433 /* 2434 * If the first EDID extension is a CTA extension, and 2435 * the first Data Block is HF-EEODB, override the 2436 * extension block count. 2437 * 2438 * Note: HF-EEODB could specify a smaller extension 2439 * count too, but we can't risk allocating a smaller 2440 * amount. 2441 */ 2442 int eeodb = edid_hfeeodb_block_count(edid); 2443 2444 if (eeodb > num_blocks) { 2445 num_blocks = eeodb; 2446 alloc_size = edid_size_by_blocks(num_blocks); 2447 new = krealloc(edid, alloc_size, GFP_KERNEL); 2448 if (!new) 2449 goto fail; 2450 edid = new; 2451 } 2452 } 2453 } 2454 2455 if (invalid_blocks) { 2456 connector_bad_edid(connector, edid, num_blocks); 2457 2458 edid = edid_filter_invalid_blocks(edid, &alloc_size); 2459 } 2460 2461ok: 2462 if (size) 2463 *size = alloc_size; 2464 2465 return edid; 2466 2467fail: 2468 kfree(edid); 2469 return NULL; 2470} 2471 2472/** 2473 * drm_edid_raw - Get a pointer to the raw EDID data. 2474 * @drm_edid: drm_edid container 2475 * 2476 * Get a pointer to the raw EDID data. 2477 * 2478 * This is for transition only. Avoid using this like the plague. 2479 * 2480 * Return: Pointer to raw EDID data. 2481 */ 2482const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) 2483{ 2484 if (!drm_edid || !drm_edid->size) 2485 return NULL; 2486 2487 /* 2488 * Do not return pointers where relying on EDID extension count would 2489 * lead to buffer overflow. 2490 */ 2491 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) 2492 return NULL; 2493 2494 return drm_edid->edid; 2495} 2496EXPORT_SYMBOL(drm_edid_raw); 2497 2498/* Allocate struct drm_edid container *without* duplicating the edid data */ 2499static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2500{ 2501 struct drm_edid *drm_edid; 2502 2503 if (!edid || !size || size < EDID_LENGTH) 2504 return NULL; 2505 2506 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); 2507 if (drm_edid) { 2508 drm_edid->edid = edid; 2509 drm_edid->size = size; 2510 } 2511 2512 return drm_edid; 2513} 2514 2515/** 2516 * drm_edid_alloc - Allocate a new drm_edid container 2517 * @edid: Pointer to raw EDID data 2518 * @size: Size of memory allocated for EDID 2519 * 2520 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2521 * the actual size that has been allocated for the data. There is no validation 2522 * of the raw EDID data against the size, but at least the EDID base block must 2523 * fit in the buffer. 2524 * 2525 * The returned pointer must be freed using drm_edid_free(). 2526 * 2527 * Return: drm_edid container, or NULL on errors 2528 */ 2529const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2530{ 2531 const struct drm_edid *drm_edid; 2532 2533 if (!edid || !size || size < EDID_LENGTH) 2534 return NULL; 2535 2536 edid = kmemdup(edid, size, GFP_KERNEL); 2537 if (!edid) 2538 return NULL; 2539 2540 drm_edid = _drm_edid_alloc(edid, size); 2541 if (!drm_edid) 2542 kfree(edid); 2543 2544 return drm_edid; 2545} 2546EXPORT_SYMBOL(drm_edid_alloc); 2547 2548/** 2549 * drm_edid_dup - Duplicate a drm_edid container 2550 * @drm_edid: EDID to duplicate 2551 * 2552 * The returned pointer must be freed using drm_edid_free(). 2553 * 2554 * Returns: drm_edid container copy, or NULL on errors 2555 */ 2556const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2557{ 2558 if (!drm_edid) 2559 return NULL; 2560 2561 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2562} 2563EXPORT_SYMBOL(drm_edid_dup); 2564 2565/** 2566 * drm_edid_free - Free the drm_edid container 2567 * @drm_edid: EDID to free 2568 */ 2569void drm_edid_free(const struct drm_edid *drm_edid) 2570{ 2571 if (!drm_edid) 2572 return; 2573 2574 kfree(drm_edid->edid); 2575 kfree(drm_edid); 2576} 2577EXPORT_SYMBOL(drm_edid_free); 2578 2579/** 2580 * drm_probe_ddc() - probe DDC presence 2581 * @adapter: I2C adapter to probe 2582 * 2583 * Return: True on success, false on failure. 2584 */ 2585bool 2586drm_probe_ddc(struct i2c_adapter *adapter) 2587{ 2588 unsigned char out; 2589 2590 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2591} 2592EXPORT_SYMBOL(drm_probe_ddc); 2593 2594/** 2595 * drm_get_edid - get EDID data, if available 2596 * @connector: connector we're probing 2597 * @adapter: I2C adapter to use for DDC 2598 * 2599 * Poke the given I2C channel to grab EDID data if possible. If found, 2600 * attach it to the connector. 2601 * 2602 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2603 */ 2604struct edid *drm_get_edid(struct drm_connector *connector, 2605 struct i2c_adapter *adapter) 2606{ 2607 struct edid *edid; 2608 2609 if (connector->force == DRM_FORCE_OFF) 2610 return NULL; 2611 2612 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2613 return NULL; 2614 2615 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2616 drm_connector_update_edid_property(connector, edid); 2617 return edid; 2618} 2619EXPORT_SYMBOL(drm_get_edid); 2620 2621/** 2622 * drm_edid_read_custom - Read EDID data using given EDID block read function 2623 * @connector: Connector to use 2624 * @read_block: EDID block read function 2625 * @context: Private data passed to the block read function 2626 * 2627 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2628 * exposes a different interface to read EDID blocks this function can be used 2629 * to get EDID data using a custom block read function. 2630 * 2631 * As in the general case the DDC bus is accessible by the kernel at the I2C 2632 * level, drivers must make all reasonable efforts to expose it as an I2C 2633 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2634 * this function. 2635 * 2636 * The EDID may be overridden using debugfs override_edid or firmware EDID 2637 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2638 * order. Having either of them bypasses actual EDID reads. 2639 * 2640 * The returned pointer must be freed using drm_edid_free(). 2641 * 2642 * Return: Pointer to EDID, or NULL if probe/read failed. 2643 */ 2644const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2645 read_block_fn read_block, 2646 void *context) 2647{ 2648 const struct drm_edid *drm_edid; 2649 struct edid *edid; 2650 size_t size = 0; 2651 2652 edid = _drm_do_get_edid(connector, read_block, context, &size); 2653 if (!edid) 2654 return NULL; 2655 2656 /* Sanity check for now */ 2657 drm_WARN_ON(connector->dev, !size); 2658 2659 drm_edid = _drm_edid_alloc(edid, size); 2660 if (!drm_edid) 2661 kfree(edid); 2662 2663 return drm_edid; 2664} 2665EXPORT_SYMBOL(drm_edid_read_custom); 2666 2667/** 2668 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2669 * @connector: Connector to use 2670 * @adapter: I2C adapter to use for DDC 2671 * 2672 * Read EDID using the given I2C adapter. 2673 * 2674 * The EDID may be overridden using debugfs override_edid or firmware EDID 2675 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2676 * order. Having either of them bypasses actual EDID reads. 2677 * 2678 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2679 * using drm_edid_read() instead of this function. 2680 * 2681 * The returned pointer must be freed using drm_edid_free(). 2682 * 2683 * Return: Pointer to EDID, or NULL if probe/read failed. 2684 */ 2685const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2686 struct i2c_adapter *adapter) 2687{ 2688 const struct drm_edid *drm_edid; 2689 2690 if (connector->force == DRM_FORCE_OFF) 2691 return NULL; 2692 2693 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2694 return NULL; 2695 2696 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2697 2698 /* Note: Do *not* call connector updates here. */ 2699 2700 return drm_edid; 2701} 2702EXPORT_SYMBOL(drm_edid_read_ddc); 2703 2704/** 2705 * drm_edid_read - Read EDID data using connector's I2C adapter 2706 * @connector: Connector to use 2707 * 2708 * Read EDID using the connector's I2C adapter. 2709 * 2710 * The EDID may be overridden using debugfs override_edid or firmware EDID 2711 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2712 * order. Having either of them bypasses actual EDID reads. 2713 * 2714 * The returned pointer must be freed using drm_edid_free(). 2715 * 2716 * Return: Pointer to EDID, or NULL if probe/read failed. 2717 */ 2718const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2719{ 2720 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2721 return NULL; 2722 2723 return drm_edid_read_ddc(connector, connector->ddc); 2724} 2725EXPORT_SYMBOL(drm_edid_read); 2726 2727/** 2728 * drm_edid_get_product_id - Get the vendor and product identification 2729 * @drm_edid: EDID 2730 * @id: Where to place the product id 2731 */ 2732void drm_edid_get_product_id(const struct drm_edid *drm_edid, 2733 struct drm_edid_product_id *id) 2734{ 2735 if (drm_edid && drm_edid->edid && drm_edid->size >= EDID_LENGTH) 2736 memcpy(id, &drm_edid->edid->product_id, sizeof(*id)); 2737 else 2738 memset(id, 0, sizeof(*id)); 2739} 2740EXPORT_SYMBOL(drm_edid_get_product_id); 2741 2742static void decode_date(struct seq_buf *s, const struct drm_edid_product_id *id) 2743{ 2744 int week = id->week_of_manufacture; 2745 int year = id->year_of_manufacture + 1990; 2746 2747 if (week == 0xff) 2748 seq_buf_printf(s, "model year: %d", year); 2749 else if (!week) 2750 seq_buf_printf(s, "year of manufacture: %d", year); 2751 else 2752 seq_buf_printf(s, "week/year of manufacture: %d/%d", week, year); 2753} 2754 2755/** 2756 * drm_edid_print_product_id - Print decoded product id to printer 2757 * @p: drm printer 2758 * @id: EDID product id 2759 * @raw: If true, also print the raw hex 2760 * 2761 * See VESA E-EDID 1.4 section 3.4. 2762 */ 2763void drm_edid_print_product_id(struct drm_printer *p, 2764 const struct drm_edid_product_id *id, bool raw) 2765{ 2766 DECLARE_SEQ_BUF(date, 40); 2767 char vend[4]; 2768 2769 drm_edid_decode_mfg_id(be16_to_cpu(id->manufacturer_name), vend); 2770 2771 decode_date(&date, id); 2772 2773 drm_printf(p, "manufacturer name: %s, product code: %u, serial number: %u, %s\n", 2774 vend, le16_to_cpu(id->product_code), 2775 le32_to_cpu(id->serial_number), seq_buf_str(&date)); 2776 2777 if (raw) 2778 drm_printf(p, "raw product id: %*ph\n", (int)sizeof(*id), id); 2779 2780 WARN_ON(seq_buf_has_overflowed(&date)); 2781} 2782EXPORT_SYMBOL(drm_edid_print_product_id); 2783 2784/** 2785 * drm_edid_get_panel_id - Get a panel's ID from EDID 2786 * @drm_edid: EDID that contains panel ID. 2787 * 2788 * This function uses the first block of the EDID of a panel and (assuming 2789 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2790 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2791 * supposed to be different for each different modem of panel. 2792 * 2793 * Return: A 32-bit ID that should be different for each make/model of panel. 2794 * See the functions drm_edid_encode_panel_id() and 2795 * drm_edid_decode_panel_id() for some details on the structure of this 2796 * ID. Return 0 if the EDID size is less than a base block. 2797 */ 2798u32 drm_edid_get_panel_id(const struct drm_edid *drm_edid) 2799{ 2800 const struct edid *edid = drm_edid->edid; 2801 2802 if (drm_edid->size < EDID_LENGTH) 2803 return 0; 2804 2805 /* 2806 * We represent the ID as a 32-bit number so it can easily be compared 2807 * with "==". 2808 * 2809 * NOTE that we deal with endianness differently for the top half 2810 * of this ID than for the bottom half. The bottom half (the product 2811 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2812 * that's how everyone seems to interpret it. The top half (the mfg_id) 2813 * gets stored as big endian because that makes 2814 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2815 * to write (it's easier to extract the ASCII). It doesn't really 2816 * matter, though, as long as the number here is unique. 2817 */ 2818 return (u32)edid->mfg_id[0] << 24 | 2819 (u32)edid->mfg_id[1] << 16 | 2820 (u32)EDID_PRODUCT_ID(edid); 2821} 2822EXPORT_SYMBOL(drm_edid_get_panel_id); 2823 2824/** 2825 * drm_edid_read_base_block - Get a panel's EDID base block 2826 * @adapter: I2C adapter to use for DDC 2827 * 2828 * This function returns the drm_edid containing the first block of the EDID of 2829 * a panel. 2830 * 2831 * This function is intended to be used during early probing on devices where 2832 * more than one panel might be present. Because of its intended use it must 2833 * assume that the EDID of the panel is correct, at least as far as the base 2834 * block is concerned (in other words, we don't process any overrides here). 2835 * 2836 * Caller should call drm_edid_free() after use. 2837 * 2838 * NOTE: it's expected that this function and drm_do_get_edid() will both 2839 * be read the EDID, but there is no caching between them. Since we're only 2840 * reading the first block, hopefully this extra overhead won't be too big. 2841 * 2842 * WARNING: Only use this function when the connector is unknown. For example, 2843 * during the early probe of panel. The EDID read from the function is temporary 2844 * and should be replaced by the full EDID returned from other drm_edid_read. 2845 * 2846 * Return: Pointer to allocated EDID base block, or NULL on any failure. 2847 */ 2848const struct drm_edid *drm_edid_read_base_block(struct i2c_adapter *adapter) 2849{ 2850 enum edid_block_status status; 2851 void *base_block; 2852 2853 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL); 2854 if (!base_block) 2855 return NULL; 2856 2857 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2858 2859 edid_block_status_print(status, base_block, 0); 2860 2861 if (!edid_block_status_valid(status, edid_block_tag(base_block))) { 2862 edid_block_dump(KERN_NOTICE, base_block, 0); 2863 kfree(base_block); 2864 return NULL; 2865 } 2866 2867 return _drm_edid_alloc(base_block, EDID_LENGTH); 2868} 2869EXPORT_SYMBOL(drm_edid_read_base_block); 2870 2871/** 2872 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2873 * @connector: connector we're probing 2874 * @adapter: I2C adapter to use for DDC 2875 * 2876 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2877 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2878 * switch DDC to the GPU which is retrieving EDID. 2879 * 2880 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2881 */ 2882struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2883 struct i2c_adapter *adapter) 2884{ 2885 struct drm_device *dev = connector->dev; 2886 struct pci_dev *pdev = to_pci_dev(dev->dev); 2887 struct edid *edid; 2888 2889 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2890 return NULL; 2891 2892 vga_switcheroo_lock_ddc(pdev); 2893 edid = drm_get_edid(connector, adapter); 2894 vga_switcheroo_unlock_ddc(pdev); 2895 2896 return edid; 2897} 2898EXPORT_SYMBOL(drm_get_edid_switcheroo); 2899 2900/** 2901 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output 2902 * @connector: connector we're probing 2903 * @adapter: I2C adapter to use for DDC 2904 * 2905 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set 2906 * of outputs. The wrapper adds the requisite vga_switcheroo calls to 2907 * temporarily switch DDC to the GPU which is retrieving EDID. 2908 * 2909 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2910 */ 2911const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, 2912 struct i2c_adapter *adapter) 2913{ 2914 struct drm_device *dev = connector->dev; 2915 struct pci_dev *pdev = to_pci_dev(dev->dev); 2916 const struct drm_edid *drm_edid; 2917 2918 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2919 return NULL; 2920 2921 vga_switcheroo_lock_ddc(pdev); 2922 drm_edid = drm_edid_read_ddc(connector, adapter); 2923 vga_switcheroo_unlock_ddc(pdev); 2924 2925 return drm_edid; 2926} 2927EXPORT_SYMBOL(drm_edid_read_switcheroo); 2928 2929/** 2930 * drm_edid_duplicate - duplicate an EDID and the extensions 2931 * @edid: EDID to duplicate 2932 * 2933 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2934 */ 2935struct edid *drm_edid_duplicate(const struct edid *edid) 2936{ 2937 if (!edid) 2938 return NULL; 2939 2940 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2941} 2942EXPORT_SYMBOL(drm_edid_duplicate); 2943 2944/*** EDID parsing ***/ 2945 2946/** 2947 * edid_get_quirks - return quirk flags for a given EDID 2948 * @drm_edid: EDID to process 2949 * 2950 * This tells subsequent routines what fixes they need to apply. 2951 * 2952 * Return: A u32 represents the quirks to apply. 2953 */ 2954static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2955{ 2956 const struct edid_quirk *quirk; 2957 int i; 2958 2959 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2960 quirk = &edid_quirk_list[i]; 2961 if (drm_edid_match(drm_edid, &quirk->ident)) 2962 return quirk->quirks; 2963 } 2964 2965 return 0; 2966} 2967 2968static bool drm_edid_has_internal_quirk(struct drm_connector *connector, 2969 enum drm_edid_internal_quirk quirk) 2970{ 2971 return connector->display_info.quirks & BIT(quirk); 2972} 2973 2974bool drm_edid_has_quirk(struct drm_connector *connector, enum drm_edid_quirk quirk) 2975{ 2976 return connector->display_info.quirks & BIT(quirk); 2977} 2978EXPORT_SYMBOL(drm_edid_has_quirk); 2979 2980#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2981#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2982 2983/* 2984 * Walk the mode list for connector, clearing the preferred status on existing 2985 * modes and setting it anew for the right mode ala quirks. 2986 */ 2987static void edid_fixup_preferred(struct drm_connector *connector) 2988{ 2989 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2990 int target_refresh = 0; 2991 int cur_vrefresh, preferred_vrefresh; 2992 2993 if (list_empty(&connector->probed_modes)) 2994 return; 2995 2996 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_60)) 2997 target_refresh = 60; 2998 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_75)) 2999 target_refresh = 75; 3000 3001 preferred_mode = list_first_entry(&connector->probed_modes, 3002 struct drm_display_mode, head); 3003 3004 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 3005 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 3006 3007 if (cur_mode == preferred_mode) 3008 continue; 3009 3010 /* Largest mode is preferred */ 3011 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 3012 preferred_mode = cur_mode; 3013 3014 cur_vrefresh = drm_mode_vrefresh(cur_mode); 3015 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 3016 /* At a given size, try to get closest to target refresh */ 3017 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 3018 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 3019 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 3020 preferred_mode = cur_mode; 3021 } 3022 } 3023 3024 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 3025} 3026 3027static bool 3028mode_is_rb(const struct drm_display_mode *mode) 3029{ 3030 return (mode->htotal - mode->hdisplay == 160) && 3031 (mode->hsync_end - mode->hdisplay == 80) && 3032 (mode->hsync_end - mode->hsync_start == 32) && 3033 (mode->vsync_start - mode->vdisplay == 3); 3034} 3035 3036/* 3037 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 3038 * @dev: Device to duplicate against 3039 * @hsize: Mode width 3040 * @vsize: Mode height 3041 * @fresh: Mode refresh rate 3042 * @rb: Mode reduced-blanking-ness 3043 * 3044 * Walk the DMT mode list looking for a match for the given parameters. 3045 * 3046 * Return: A newly allocated copy of the mode, or NULL if not found. 3047 */ 3048struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 3049 int hsize, int vsize, int fresh, 3050 bool rb) 3051{ 3052 int i; 3053 3054 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3055 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3056 3057 if (hsize != ptr->hdisplay) 3058 continue; 3059 if (vsize != ptr->vdisplay) 3060 continue; 3061 if (fresh != drm_mode_vrefresh(ptr)) 3062 continue; 3063 if (rb != mode_is_rb(ptr)) 3064 continue; 3065 3066 return drm_mode_duplicate(dev, ptr); 3067 } 3068 3069 return NULL; 3070} 3071EXPORT_SYMBOL(drm_mode_find_dmt); 3072 3073static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 3074{ 3075 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3076 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 3077 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 3078 3079 return descriptor->pixel_clock == 0 && 3080 descriptor->data.other_data.pad1 == 0 && 3081 descriptor->data.other_data.type == type; 3082} 3083 3084static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 3085{ 3086 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3087 3088 return descriptor->pixel_clock != 0; 3089} 3090 3091typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 3092 3093static void 3094cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3095{ 3096 int i, n; 3097 u8 d = ext[0x02]; 3098 const u8 *det_base = ext + d; 3099 3100 if (d < 4 || d > 127) 3101 return; 3102 3103 n = (127 - d) / 18; 3104 for (i = 0; i < n; i++) 3105 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3106} 3107 3108static void 3109vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3110{ 3111 unsigned int i, n = min((int)ext[0x02], 6); 3112 const u8 *det_base = ext + 5; 3113 3114 if (ext[0x01] != 1) 3115 return; /* unknown version */ 3116 3117 for (i = 0; i < n; i++) 3118 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3119} 3120 3121static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 3122 detailed_cb *cb, void *closure) 3123{ 3124 struct drm_edid_iter edid_iter; 3125 const u8 *ext; 3126 int i; 3127 3128 if (!drm_edid) 3129 return; 3130 3131 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3132 cb(&drm_edid->edid->detailed_timings[i], closure); 3133 3134 drm_edid_iter_begin(drm_edid, &edid_iter); 3135 drm_edid_iter_for_each(ext, &edid_iter) { 3136 switch (*ext) { 3137 case CEA_EXT: 3138 cea_for_each_detailed_block(ext, cb, closure); 3139 break; 3140 case VTB_EXT: 3141 vtb_for_each_detailed_block(ext, cb, closure); 3142 break; 3143 default: 3144 break; 3145 } 3146 } 3147 drm_edid_iter_end(&edid_iter); 3148} 3149 3150static void 3151is_rb(const struct detailed_timing *descriptor, void *data) 3152{ 3153 bool *res = data; 3154 3155 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3156 return; 3157 3158 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3159 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 3160 3161 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 3162 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING) 3163 *res = true; 3164} 3165 3166/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3167static bool 3168drm_monitor_supports_rb(const struct drm_edid *drm_edid) 3169{ 3170 if (drm_edid->edid->revision >= 4) { 3171 bool ret = false; 3172 3173 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 3174 return ret; 3175 } 3176 3177 return drm_edid_is_digital(drm_edid); 3178} 3179 3180static void 3181find_gtf2(const struct detailed_timing *descriptor, void *data) 3182{ 3183 const struct detailed_timing **res = data; 3184 3185 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3186 return; 3187 3188 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3189 3190 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG) 3191 *res = descriptor; 3192} 3193 3194/* Secondary GTF curve kicks in above some break frequency */ 3195static int 3196drm_gtf2_hbreak(const struct drm_edid *drm_edid) 3197{ 3198 const struct detailed_timing *descriptor = NULL; 3199 3200 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3201 3202 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 3203 3204 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 3205} 3206 3207static int 3208drm_gtf2_2c(const struct drm_edid *drm_edid) 3209{ 3210 const struct detailed_timing *descriptor = NULL; 3211 3212 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3213 3214 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 3215 3216 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 3217} 3218 3219static int 3220drm_gtf2_m(const struct drm_edid *drm_edid) 3221{ 3222 const struct detailed_timing *descriptor = NULL; 3223 3224 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3225 3226 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 3227 3228 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 3229} 3230 3231static int 3232drm_gtf2_k(const struct drm_edid *drm_edid) 3233{ 3234 const struct detailed_timing *descriptor = NULL; 3235 3236 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3237 3238 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 3239 3240 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 3241} 3242 3243static int 3244drm_gtf2_2j(const struct drm_edid *drm_edid) 3245{ 3246 const struct detailed_timing *descriptor = NULL; 3247 3248 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3249 3250 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 3251 3252 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 3253} 3254 3255static void 3256get_timing_level(const struct detailed_timing *descriptor, void *data) 3257{ 3258 int *res = data; 3259 3260 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3261 return; 3262 3263 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3264 3265 switch (descriptor->data.other_data.data.range.flags) { 3266 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3267 *res = LEVEL_GTF; 3268 break; 3269 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3270 *res = LEVEL_GTF2; 3271 break; 3272 case DRM_EDID_CVT_SUPPORT_FLAG: 3273 *res = LEVEL_CVT; 3274 break; 3275 default: 3276 break; 3277 } 3278} 3279 3280/* Get standard timing level (CVT/GTF/DMT). */ 3281static int standard_timing_level(const struct drm_edid *drm_edid) 3282{ 3283 const struct edid *edid = drm_edid->edid; 3284 3285 if (edid->revision >= 4) { 3286 /* 3287 * If the range descriptor doesn't 3288 * indicate otherwise default to CVT 3289 */ 3290 int ret = LEVEL_CVT; 3291 3292 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret); 3293 3294 return ret; 3295 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) { 3296 return LEVEL_GTF2; 3297 } else if (edid->revision >= 2) { 3298 return LEVEL_GTF; 3299 } else { 3300 return LEVEL_DMT; 3301 } 3302} 3303 3304/* 3305 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3306 * monitors fill with ascii space (0x20) instead. 3307 */ 3308static int 3309bad_std_timing(u8 a, u8 b) 3310{ 3311 return (a == 0x00 && b == 0x00) || 3312 (a == 0x01 && b == 0x01) || 3313 (a == 0x20 && b == 0x20); 3314} 3315 3316static int drm_mode_hsync(const struct drm_display_mode *mode) 3317{ 3318 if (mode->htotal <= 0) 3319 return 0; 3320 3321 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3322} 3323 3324static struct drm_display_mode * 3325drm_gtf2_mode(struct drm_device *dev, 3326 const struct drm_edid *drm_edid, 3327 int hsize, int vsize, int vrefresh_rate) 3328{ 3329 struct drm_display_mode *mode; 3330 3331 /* 3332 * This is potentially wrong if there's ever a monitor with 3333 * more than one ranges section, each claiming a different 3334 * secondary GTF curve. Please don't do that. 3335 */ 3336 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3337 if (!mode) 3338 return NULL; 3339 3340 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3341 drm_mode_destroy(dev, mode); 3342 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3343 vrefresh_rate, 0, 0, 3344 drm_gtf2_m(drm_edid), 3345 drm_gtf2_2c(drm_edid), 3346 drm_gtf2_k(drm_edid), 3347 drm_gtf2_2j(drm_edid)); 3348 } 3349 3350 return mode; 3351} 3352 3353/* 3354 * Take the standard timing params (in this case width, aspect, and refresh) 3355 * and convert them into a real mode using CVT/GTF/DMT. 3356 */ 3357static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3358 const struct drm_edid *drm_edid, 3359 const struct std_timing *t) 3360{ 3361 struct drm_device *dev = connector->dev; 3362 struct drm_display_mode *m, *mode = NULL; 3363 int hsize, vsize; 3364 int vrefresh_rate; 3365 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3366 >> EDID_TIMING_ASPECT_SHIFT; 3367 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3368 >> EDID_TIMING_VFREQ_SHIFT; 3369 int timing_level = standard_timing_level(drm_edid); 3370 3371 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3372 return NULL; 3373 3374 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3375 hsize = t->hsize * 8 + 248; 3376 /* vrefresh_rate = vfreq + 60 */ 3377 vrefresh_rate = vfreq + 60; 3378 /* the vdisplay is calculated based on the aspect ratio */ 3379 if (aspect_ratio == 0) { 3380 if (drm_edid->edid->revision < 3) 3381 vsize = hsize; 3382 else 3383 vsize = (hsize * 10) / 16; 3384 } else if (aspect_ratio == 1) 3385 vsize = (hsize * 3) / 4; 3386 else if (aspect_ratio == 2) 3387 vsize = (hsize * 4) / 5; 3388 else 3389 vsize = (hsize * 9) / 16; 3390 3391 /* HDTV hack, part 1 */ 3392 if (vrefresh_rate == 60 && 3393 ((hsize == 1360 && vsize == 765) || 3394 (hsize == 1368 && vsize == 769))) { 3395 hsize = 1366; 3396 vsize = 768; 3397 } 3398 3399 /* 3400 * If this connector already has a mode for this size and refresh 3401 * rate (because it came from detailed or CVT info), use that 3402 * instead. This way we don't have to guess at interlace or 3403 * reduced blanking. 3404 */ 3405 list_for_each_entry(m, &connector->probed_modes, head) 3406 if (m->hdisplay == hsize && m->vdisplay == vsize && 3407 drm_mode_vrefresh(m) == vrefresh_rate) 3408 return NULL; 3409 3410 /* HDTV hack, part 2 */ 3411 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3412 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3413 false); 3414 if (!mode) 3415 return NULL; 3416 mode->hdisplay = 1366; 3417 mode->hsync_start = mode->hsync_start - 1; 3418 mode->hsync_end = mode->hsync_end - 1; 3419 return mode; 3420 } 3421 3422 /* check whether it can be found in default mode table */ 3423 if (drm_monitor_supports_rb(drm_edid)) { 3424 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3425 true); 3426 if (mode) 3427 return mode; 3428 } 3429 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3430 if (mode) 3431 return mode; 3432 3433 /* okay, generate it */ 3434 switch (timing_level) { 3435 case LEVEL_DMT: 3436 break; 3437 case LEVEL_GTF: 3438 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3439 break; 3440 case LEVEL_GTF2: 3441 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate); 3442 break; 3443 case LEVEL_CVT: 3444 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3445 false); 3446 break; 3447 } 3448 return mode; 3449} 3450 3451/* 3452 * EDID is delightfully ambiguous about how interlaced modes are to be 3453 * encoded. Our internal representation is of frame height, but some 3454 * HDTV detailed timings are encoded as field height. 3455 * 3456 * The format list here is from CEA, in frame size. Technically we 3457 * should be checking refresh rate too. Whatever. 3458 */ 3459static void 3460drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3461 const struct detailed_pixel_timing *pt) 3462{ 3463 int i; 3464 static const struct { 3465 int w, h; 3466 } cea_interlaced[] = { 3467 { 1920, 1080 }, 3468 { 720, 480 }, 3469 { 1440, 480 }, 3470 { 2880, 480 }, 3471 { 720, 576 }, 3472 { 1440, 576 }, 3473 { 2880, 576 }, 3474 }; 3475 3476 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3477 return; 3478 3479 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3480 if ((mode->hdisplay == cea_interlaced[i].w) && 3481 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3482 mode->vdisplay *= 2; 3483 mode->vsync_start *= 2; 3484 mode->vsync_end *= 2; 3485 mode->vtotal *= 2; 3486 mode->vtotal |= 1; 3487 } 3488 } 3489 3490 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3491} 3492 3493/* 3494 * Create a new mode from an EDID detailed timing section. An EDID detailed 3495 * timing block contains enough info for us to create and return a new struct 3496 * drm_display_mode. 3497 */ 3498static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector, 3499 const struct drm_edid *drm_edid, 3500 const struct detailed_timing *timing) 3501{ 3502 struct drm_device *dev = connector->dev; 3503 struct drm_display_mode *mode; 3504 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3505 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3506 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3507 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3508 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3509 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3510 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3511 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3512 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3513 3514 /* ignore tiny modes */ 3515 if (hactive < 64 || vactive < 64) 3516 return NULL; 3517 3518 if (pt->misc & DRM_EDID_PT_STEREO) { 3519 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n", 3520 connector->base.id, connector->name); 3521 return NULL; 3522 } 3523 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 3524 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n", 3525 connector->base.id, connector->name); 3526 } 3527 3528 /* it is incorrect if hsync/vsync width is zero */ 3529 if (!hsync_pulse_width || !vsync_pulse_width) { 3530 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n", 3531 connector->base.id, connector->name); 3532 return NULL; 3533 } 3534 3535 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_REDUCED_BLANKING)) { 3536 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3537 if (!mode) 3538 return NULL; 3539 3540 goto set_size; 3541 } 3542 3543 mode = drm_mode_create(dev); 3544 if (!mode) 3545 return NULL; 3546 3547 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_135_CLOCK_TOO_HIGH)) 3548 mode->clock = 1088 * 10; 3549 else 3550 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3551 3552 mode->hdisplay = hactive; 3553 mode->hsync_start = mode->hdisplay + hsync_offset; 3554 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3555 mode->htotal = mode->hdisplay + hblank; 3556 3557 mode->vdisplay = vactive; 3558 mode->vsync_start = mode->vdisplay + vsync_offset; 3559 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3560 mode->vtotal = mode->vdisplay + vblank; 3561 3562 /* Some EDIDs have bogus h/vsync_end values */ 3563 if (mode->hsync_end > mode->htotal) { 3564 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n", 3565 connector->base.id, connector->name, 3566 mode->hsync_end, mode->htotal); 3567 mode->hsync_end = mode->htotal; 3568 } 3569 if (mode->vsync_end > mode->vtotal) { 3570 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n", 3571 connector->base.id, connector->name, 3572 mode->vsync_end, mode->vtotal); 3573 mode->vsync_end = mode->vtotal; 3574 } 3575 3576 drm_mode_do_interlace_quirk(mode, pt); 3577 3578 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_DETAILED_SYNC_PP)) { 3579 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3580 } else { 3581 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3582 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3583 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3584 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3585 } 3586 3587set_size: 3588 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3589 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3590 3591 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_DETAILED_IN_CM)) { 3592 mode->width_mm *= 10; 3593 mode->height_mm *= 10; 3594 } 3595 3596 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE)) { 3597 mode->width_mm = drm_edid->edid->width_cm * 10; 3598 mode->height_mm = drm_edid->edid->height_cm * 10; 3599 } 3600 3601 mode->type = DRM_MODE_TYPE_DRIVER; 3602 drm_mode_set_name(mode); 3603 3604 return mode; 3605} 3606 3607static bool 3608mode_in_hsync_range(const struct drm_display_mode *mode, 3609 const struct edid *edid, const u8 *t) 3610{ 3611 int hsync, hmin, hmax; 3612 3613 hmin = t[7]; 3614 if (edid->revision >= 4) 3615 hmin += ((t[4] & 0x04) ? 255 : 0); 3616 hmax = t[8]; 3617 if (edid->revision >= 4) 3618 hmax += ((t[4] & 0x08) ? 255 : 0); 3619 hsync = drm_mode_hsync(mode); 3620 3621 return (hsync <= hmax && hsync >= hmin); 3622} 3623 3624static bool 3625mode_in_vsync_range(const struct drm_display_mode *mode, 3626 const struct edid *edid, const u8 *t) 3627{ 3628 int vsync, vmin, vmax; 3629 3630 vmin = t[5]; 3631 if (edid->revision >= 4) 3632 vmin += ((t[4] & 0x01) ? 255 : 0); 3633 vmax = t[6]; 3634 if (edid->revision >= 4) 3635 vmax += ((t[4] & 0x02) ? 255 : 0); 3636 vsync = drm_mode_vrefresh(mode); 3637 3638 return (vsync <= vmax && vsync >= vmin); 3639} 3640 3641static u32 3642range_pixel_clock(const struct edid *edid, const u8 *t) 3643{ 3644 /* unspecified */ 3645 if (t[9] == 0 || t[9] == 255) 3646 return 0; 3647 3648 /* 1.4 with CVT support gives us real precision, yay */ 3649 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3650 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3651 3652 /* 1.3 is pathetic, so fuzz up a bit */ 3653 return t[9] * 10000 + 5001; 3654} 3655 3656static bool mode_in_range(const struct drm_display_mode *mode, 3657 const struct drm_edid *drm_edid, 3658 const struct detailed_timing *timing) 3659{ 3660 const struct edid *edid = drm_edid->edid; 3661 u32 max_clock; 3662 const u8 *t = (const u8 *)timing; 3663 3664 if (!mode_in_hsync_range(mode, edid, t)) 3665 return false; 3666 3667 if (!mode_in_vsync_range(mode, edid, t)) 3668 return false; 3669 3670 max_clock = range_pixel_clock(edid, t); 3671 if (max_clock) 3672 if (mode->clock > max_clock) 3673 return false; 3674 3675 /* 1.4 max horizontal check */ 3676 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3677 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3678 return false; 3679 3680 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3681 return false; 3682 3683 return true; 3684} 3685 3686static bool valid_inferred_mode(const struct drm_connector *connector, 3687 const struct drm_display_mode *mode) 3688{ 3689 const struct drm_display_mode *m; 3690 bool ok = false; 3691 3692 list_for_each_entry(m, &connector->probed_modes, head) { 3693 if (mode->hdisplay == m->hdisplay && 3694 mode->vdisplay == m->vdisplay && 3695 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3696 return false; /* duplicated */ 3697 if (mode->hdisplay <= m->hdisplay && 3698 mode->vdisplay <= m->vdisplay) 3699 ok = true; 3700 } 3701 return ok; 3702} 3703 3704static int drm_dmt_modes_for_range(struct drm_connector *connector, 3705 const struct drm_edid *drm_edid, 3706 const struct detailed_timing *timing) 3707{ 3708 int i, modes = 0; 3709 struct drm_display_mode *newmode; 3710 struct drm_device *dev = connector->dev; 3711 3712 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3713 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3714 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3715 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3716 if (newmode) { 3717 drm_mode_probed_add(connector, newmode); 3718 modes++; 3719 } 3720 } 3721 } 3722 3723 return modes; 3724} 3725 3726/* fix up 1366x768 mode from 1368x768; 3727 * GFT/CVT can't express 1366 width which isn't dividable by 8 3728 */ 3729void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3730{ 3731 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3732 mode->hdisplay = 1366; 3733 mode->hsync_start--; 3734 mode->hsync_end--; 3735 drm_mode_set_name(mode); 3736 } 3737} 3738 3739static int drm_gtf_modes_for_range(struct drm_connector *connector, 3740 const struct drm_edid *drm_edid, 3741 const struct detailed_timing *timing) 3742{ 3743 int i, modes = 0; 3744 struct drm_display_mode *newmode; 3745 struct drm_device *dev = connector->dev; 3746 3747 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3748 const struct minimode *m = &extra_modes[i]; 3749 3750 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3751 if (!newmode) 3752 return modes; 3753 3754 drm_mode_fixup_1366x768(newmode); 3755 if (!mode_in_range(newmode, drm_edid, timing) || 3756 !valid_inferred_mode(connector, newmode)) { 3757 drm_mode_destroy(dev, newmode); 3758 continue; 3759 } 3760 3761 drm_mode_probed_add(connector, newmode); 3762 modes++; 3763 } 3764 3765 return modes; 3766} 3767 3768static int drm_gtf2_modes_for_range(struct drm_connector *connector, 3769 const struct drm_edid *drm_edid, 3770 const struct detailed_timing *timing) 3771{ 3772 int i, modes = 0; 3773 struct drm_display_mode *newmode; 3774 struct drm_device *dev = connector->dev; 3775 3776 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3777 const struct minimode *m = &extra_modes[i]; 3778 3779 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r); 3780 if (!newmode) 3781 return modes; 3782 3783 drm_mode_fixup_1366x768(newmode); 3784 if (!mode_in_range(newmode, drm_edid, timing) || 3785 !valid_inferred_mode(connector, newmode)) { 3786 drm_mode_destroy(dev, newmode); 3787 continue; 3788 } 3789 3790 drm_mode_probed_add(connector, newmode); 3791 modes++; 3792 } 3793 3794 return modes; 3795} 3796 3797static int drm_cvt_modes_for_range(struct drm_connector *connector, 3798 const struct drm_edid *drm_edid, 3799 const struct detailed_timing *timing) 3800{ 3801 int i, modes = 0; 3802 struct drm_display_mode *newmode; 3803 struct drm_device *dev = connector->dev; 3804 bool rb = drm_monitor_supports_rb(drm_edid); 3805 3806 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3807 const struct minimode *m = &extra_modes[i]; 3808 3809 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3810 if (!newmode) 3811 return modes; 3812 3813 drm_mode_fixup_1366x768(newmode); 3814 if (!mode_in_range(newmode, drm_edid, timing) || 3815 !valid_inferred_mode(connector, newmode)) { 3816 drm_mode_destroy(dev, newmode); 3817 continue; 3818 } 3819 3820 drm_mode_probed_add(connector, newmode); 3821 modes++; 3822 } 3823 3824 return modes; 3825} 3826 3827static void 3828do_inferred_modes(const struct detailed_timing *timing, void *c) 3829{ 3830 struct detailed_mode_closure *closure = c; 3831 const struct detailed_non_pixel *data = &timing->data.other_data; 3832 const struct detailed_data_monitor_range *range = &data->data.range; 3833 3834 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3835 return; 3836 3837 closure->modes += drm_dmt_modes_for_range(closure->connector, 3838 closure->drm_edid, 3839 timing); 3840 3841 if (closure->drm_edid->edid->revision < 2) 3842 return; /* GTF not defined yet */ 3843 3844 switch (range->flags) { 3845 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3846 closure->modes += drm_gtf2_modes_for_range(closure->connector, 3847 closure->drm_edid, 3848 timing); 3849 break; 3850 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3851 closure->modes += drm_gtf_modes_for_range(closure->connector, 3852 closure->drm_edid, 3853 timing); 3854 break; 3855 case DRM_EDID_CVT_SUPPORT_FLAG: 3856 if (closure->drm_edid->edid->revision < 4) 3857 break; 3858 3859 closure->modes += drm_cvt_modes_for_range(closure->connector, 3860 closure->drm_edid, 3861 timing); 3862 break; 3863 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG: 3864 default: 3865 break; 3866 } 3867} 3868 3869static int add_inferred_modes(struct drm_connector *connector, 3870 const struct drm_edid *drm_edid) 3871{ 3872 struct detailed_mode_closure closure = { 3873 .connector = connector, 3874 .drm_edid = drm_edid, 3875 }; 3876 3877 if (drm_edid->edid->revision >= 1) 3878 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3879 3880 return closure.modes; 3881} 3882 3883static int 3884drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3885{ 3886 int i, j, m, modes = 0; 3887 struct drm_display_mode *mode; 3888 const u8 *est = ((const u8 *)timing) + 6; 3889 3890 for (i = 0; i < 6; i++) { 3891 for (j = 7; j >= 0; j--) { 3892 m = (i * 8) + (7 - j); 3893 if (m >= ARRAY_SIZE(est3_modes)) 3894 break; 3895 if (est[i] & (1 << j)) { 3896 mode = drm_mode_find_dmt(connector->dev, 3897 est3_modes[m].w, 3898 est3_modes[m].h, 3899 est3_modes[m].r, 3900 est3_modes[m].rb); 3901 if (mode) { 3902 drm_mode_probed_add(connector, mode); 3903 modes++; 3904 } 3905 } 3906 } 3907 } 3908 3909 return modes; 3910} 3911 3912static void 3913do_established_modes(const struct detailed_timing *timing, void *c) 3914{ 3915 struct detailed_mode_closure *closure = c; 3916 3917 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3918 return; 3919 3920 closure->modes += drm_est3_modes(closure->connector, timing); 3921} 3922 3923/* 3924 * Get established modes from EDID and add them. Each EDID block contains a 3925 * bitmap of the supported "established modes" list (defined above). Tease them 3926 * out and add them to the global modes list. 3927 */ 3928static int add_established_modes(struct drm_connector *connector, 3929 const struct drm_edid *drm_edid) 3930{ 3931 struct drm_device *dev = connector->dev; 3932 const struct edid *edid = drm_edid->edid; 3933 unsigned long est_bits = edid->established_timings.t1 | 3934 (edid->established_timings.t2 << 8) | 3935 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3936 int i, modes = 0; 3937 struct detailed_mode_closure closure = { 3938 .connector = connector, 3939 .drm_edid = drm_edid, 3940 }; 3941 3942 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3943 if (est_bits & (1<<i)) { 3944 struct drm_display_mode *newmode; 3945 3946 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3947 if (newmode) { 3948 drm_mode_probed_add(connector, newmode); 3949 modes++; 3950 } 3951 } 3952 } 3953 3954 if (edid->revision >= 1) 3955 drm_for_each_detailed_block(drm_edid, do_established_modes, 3956 &closure); 3957 3958 return modes + closure.modes; 3959} 3960 3961static void 3962do_standard_modes(const struct detailed_timing *timing, void *c) 3963{ 3964 struct detailed_mode_closure *closure = c; 3965 const struct detailed_non_pixel *data = &timing->data.other_data; 3966 struct drm_connector *connector = closure->connector; 3967 int i; 3968 3969 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3970 return; 3971 3972 for (i = 0; i < 6; i++) { 3973 const struct std_timing *std = &data->data.timings[i]; 3974 struct drm_display_mode *newmode; 3975 3976 newmode = drm_mode_std(connector, closure->drm_edid, std); 3977 if (newmode) { 3978 drm_mode_probed_add(connector, newmode); 3979 closure->modes++; 3980 } 3981 } 3982} 3983 3984/* 3985 * Get standard modes from EDID and add them. Standard modes can be calculated 3986 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3987 * add them to the list. 3988 */ 3989static int add_standard_modes(struct drm_connector *connector, 3990 const struct drm_edid *drm_edid) 3991{ 3992 int i, modes = 0; 3993 struct detailed_mode_closure closure = { 3994 .connector = connector, 3995 .drm_edid = drm_edid, 3996 }; 3997 3998 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3999 struct drm_display_mode *newmode; 4000 4001 newmode = drm_mode_std(connector, drm_edid, 4002 &drm_edid->edid->standard_timings[i]); 4003 if (newmode) { 4004 drm_mode_probed_add(connector, newmode); 4005 modes++; 4006 } 4007 } 4008 4009 if (drm_edid->edid->revision >= 1) 4010 drm_for_each_detailed_block(drm_edid, do_standard_modes, 4011 &closure); 4012 4013 /* XXX should also look for standard codes in VTB blocks */ 4014 4015 return modes + closure.modes; 4016} 4017 4018static int drm_cvt_modes(struct drm_connector *connector, 4019 const struct detailed_timing *timing) 4020{ 4021 int i, j, modes = 0; 4022 struct drm_display_mode *newmode; 4023 struct drm_device *dev = connector->dev; 4024 const struct cvt_timing *cvt; 4025 static const int rates[] = { 60, 85, 75, 60, 50 }; 4026 const u8 empty[3] = { 0, 0, 0 }; 4027 4028 for (i = 0; i < 4; i++) { 4029 int width, height; 4030 4031 cvt = &(timing->data.other_data.data.cvt[i]); 4032 4033 if (!memcmp(cvt->code, empty, 3)) 4034 continue; 4035 4036 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 4037 switch (cvt->code[1] & 0x0c) { 4038 /* default - because compiler doesn't see that we've enumerated all cases */ 4039 default: 4040 case 0x00: 4041 width = height * 4 / 3; 4042 break; 4043 case 0x04: 4044 width = height * 16 / 9; 4045 break; 4046 case 0x08: 4047 width = height * 16 / 10; 4048 break; 4049 case 0x0c: 4050 width = height * 15 / 9; 4051 break; 4052 } 4053 4054 for (j = 1; j < 5; j++) { 4055 if (cvt->code[2] & (1 << j)) { 4056 newmode = drm_cvt_mode(dev, width, height, 4057 rates[j], j == 0, 4058 false, false); 4059 if (newmode) { 4060 drm_mode_probed_add(connector, newmode); 4061 modes++; 4062 } 4063 } 4064 } 4065 } 4066 4067 return modes; 4068} 4069 4070static void 4071do_cvt_mode(const struct detailed_timing *timing, void *c) 4072{ 4073 struct detailed_mode_closure *closure = c; 4074 4075 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 4076 return; 4077 4078 closure->modes += drm_cvt_modes(closure->connector, timing); 4079} 4080 4081static int 4082add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 4083{ 4084 struct detailed_mode_closure closure = { 4085 .connector = connector, 4086 .drm_edid = drm_edid, 4087 }; 4088 4089 if (drm_edid->edid->revision >= 3) 4090 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 4091 4092 /* XXX should also look for CVT codes in VTB blocks */ 4093 4094 return closure.modes; 4095} 4096 4097static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 4098 struct drm_display_mode *mode); 4099 4100static void 4101do_detailed_mode(const struct detailed_timing *timing, void *c) 4102{ 4103 struct detailed_mode_closure *closure = c; 4104 struct drm_display_mode *newmode; 4105 4106 if (!is_detailed_timing_descriptor(timing)) 4107 return; 4108 4109 newmode = drm_mode_detailed(closure->connector, 4110 closure->drm_edid, timing); 4111 if (!newmode) 4112 return; 4113 4114 if (closure->preferred) 4115 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4116 4117 /* 4118 * Detailed modes are limited to 10kHz pixel clock resolution, 4119 * so fix up anything that looks like CEA/HDMI mode, but the clock 4120 * is just slightly off. 4121 */ 4122 fixup_detailed_cea_mode_clock(closure->connector, newmode); 4123 4124 drm_mode_probed_add(closure->connector, newmode); 4125 closure->modes++; 4126 closure->preferred = false; 4127} 4128 4129/* 4130 * add_detailed_modes - Add modes from detailed timings 4131 * @connector: attached connector 4132 * @drm_edid: EDID block to scan 4133 */ 4134static int add_detailed_modes(struct drm_connector *connector, 4135 const struct drm_edid *drm_edid) 4136{ 4137 struct detailed_mode_closure closure = { 4138 .connector = connector, 4139 .drm_edid = drm_edid, 4140 }; 4141 4142 if (drm_edid->edid->revision >= 4) 4143 closure.preferred = true; /* first detailed timing is always preferred */ 4144 else 4145 closure.preferred = 4146 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING; 4147 4148 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 4149 4150 return closure.modes; 4151} 4152 4153/* CTA-861-H Table 60 - CTA Tag Codes */ 4154#define CTA_DB_AUDIO 1 4155#define CTA_DB_VIDEO 2 4156#define CTA_DB_VENDOR 3 4157#define CTA_DB_SPEAKER 4 4158#define CTA_DB_EXTENDED_TAG 7 4159 4160/* CTA-861-H Table 62 - CTA Extended Tag Codes */ 4161#define CTA_EXT_DB_VIDEO_CAP 0 4162#define CTA_EXT_DB_VENDOR 1 4163#define CTA_EXT_DB_HDR_STATIC_METADATA 6 4164#define CTA_EXT_DB_420_VIDEO_DATA 14 4165#define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 4166#define CTA_EXT_DB_HF_EEODB 0x78 4167#define CTA_EXT_DB_HF_SCDB 0x79 4168 4169#define EDID_BASIC_AUDIO (1 << 6) 4170#define EDID_CEA_YCRCB444 (1 << 5) 4171#define EDID_CEA_YCRCB422 (1 << 4) 4172#define EDID_CEA_VCDB_QS (1 << 6) 4173 4174/* 4175 * Search EDID for CEA extension block. 4176 * 4177 * FIXME: Prefer not returning pointers to raw EDID data. 4178 */ 4179const u8 *drm_edid_find_extension(const struct drm_edid *drm_edid, 4180 int ext_id, int *ext_index) 4181{ 4182 const u8 *edid_ext = NULL; 4183 int i; 4184 4185 /* No EDID or EDID extensions */ 4186 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 4187 return NULL; 4188 4189 /* Find CEA extension */ 4190 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 4191 edid_ext = drm_edid_extension_block_data(drm_edid, i); 4192 if (edid_block_tag(edid_ext) == ext_id) 4193 break; 4194 } 4195 4196 if (i >= drm_edid_extension_block_count(drm_edid)) 4197 return NULL; 4198 4199 *ext_index = i + 1; 4200 4201 return edid_ext; 4202} 4203 4204/* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 4205static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 4206{ 4207 const struct displayid_block *block; 4208 struct displayid_iter iter; 4209 struct drm_edid_iter edid_iter; 4210 const u8 *ext; 4211 bool found = false; 4212 4213 /* Look for a top level CEA extension block */ 4214 drm_edid_iter_begin(drm_edid, &edid_iter); 4215 drm_edid_iter_for_each(ext, &edid_iter) { 4216 if (ext[0] == CEA_EXT) { 4217 found = true; 4218 break; 4219 } 4220 } 4221 drm_edid_iter_end(&edid_iter); 4222 4223 if (found) 4224 return true; 4225 4226 /* CEA blocks can also be found embedded in a DisplayID block */ 4227 displayid_iter_edid_begin(drm_edid, &iter); 4228 displayid_iter_for_each(block, &iter) { 4229 if (block->tag == DATA_BLOCK_CTA) { 4230 found = true; 4231 break; 4232 } 4233 } 4234 displayid_iter_end(&iter); 4235 4236 return found; 4237} 4238 4239static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 4240{ 4241 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 4242 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 4243 4244 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 4245 return &edid_cea_modes_1[vic - 1]; 4246 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 4247 return &edid_cea_modes_193[vic - 193]; 4248 return NULL; 4249} 4250 4251static u8 cea_num_vics(void) 4252{ 4253 return 193 + ARRAY_SIZE(edid_cea_modes_193); 4254} 4255 4256static u8 cea_next_vic(u8 vic) 4257{ 4258 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 4259 vic = 193; 4260 return vic; 4261} 4262 4263/* 4264 * Calculate the alternate clock for the CEA mode 4265 * (60Hz vs. 59.94Hz etc.) 4266 */ 4267static unsigned int 4268cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 4269{ 4270 unsigned int clock = cea_mode->clock; 4271 4272 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 4273 return clock; 4274 4275 /* 4276 * edid_cea_modes contains the 59.94Hz 4277 * variant for 240 and 480 line modes, 4278 * and the 60Hz variant otherwise. 4279 */ 4280 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 4281 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 4282 else 4283 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 4284 4285 return clock; 4286} 4287 4288static bool 4289cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 4290{ 4291 /* 4292 * For certain VICs the spec allows the vertical 4293 * front porch to vary by one or two lines. 4294 * 4295 * cea_modes[] stores the variant with the shortest 4296 * vertical front porch. We can adjust the mode to 4297 * get the other variants by simply increasing the 4298 * vertical front porch length. 4299 */ 4300 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 4301 cea_mode_for_vic(9)->vtotal != 262 || 4302 cea_mode_for_vic(12)->vtotal != 262 || 4303 cea_mode_for_vic(13)->vtotal != 262 || 4304 cea_mode_for_vic(23)->vtotal != 312 || 4305 cea_mode_for_vic(24)->vtotal != 312 || 4306 cea_mode_for_vic(27)->vtotal != 312 || 4307 cea_mode_for_vic(28)->vtotal != 312); 4308 4309 if (((vic == 8 || vic == 9 || 4310 vic == 12 || vic == 13) && mode->vtotal < 263) || 4311 ((vic == 23 || vic == 24 || 4312 vic == 27 || vic == 28) && mode->vtotal < 314)) { 4313 mode->vsync_start++; 4314 mode->vsync_end++; 4315 mode->vtotal++; 4316 4317 return true; 4318 } 4319 4320 return false; 4321} 4322 4323static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4324 unsigned int clock_tolerance) 4325{ 4326 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4327 u8 vic; 4328 4329 if (!to_match->clock) 4330 return 0; 4331 4332 if (to_match->picture_aspect_ratio) 4333 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4334 4335 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4336 struct drm_display_mode cea_mode; 4337 unsigned int clock1, clock2; 4338 4339 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4340 4341 /* Check both 60Hz and 59.94Hz */ 4342 clock1 = cea_mode.clock; 4343 clock2 = cea_mode_alternate_clock(&cea_mode); 4344 4345 if (abs(to_match->clock - clock1) > clock_tolerance && 4346 abs(to_match->clock - clock2) > clock_tolerance) 4347 continue; 4348 4349 do { 4350 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4351 return vic; 4352 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4353 } 4354 4355 return 0; 4356} 4357 4358/** 4359 * drm_match_cea_mode - look for a CEA mode matching given mode 4360 * @to_match: display mode 4361 * 4362 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 4363 * mode. 4364 */ 4365u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 4366{ 4367 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4368 u8 vic; 4369 4370 if (!to_match->clock) 4371 return 0; 4372 4373 if (to_match->picture_aspect_ratio) 4374 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4375 4376 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4377 struct drm_display_mode cea_mode; 4378 unsigned int clock1, clock2; 4379 4380 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4381 4382 /* Check both 60Hz and 59.94Hz */ 4383 clock1 = cea_mode.clock; 4384 clock2 = cea_mode_alternate_clock(&cea_mode); 4385 4386 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4387 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4388 continue; 4389 4390 do { 4391 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4392 return vic; 4393 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4394 } 4395 4396 return 0; 4397} 4398EXPORT_SYMBOL(drm_match_cea_mode); 4399 4400static bool drm_valid_cea_vic(u8 vic) 4401{ 4402 return cea_mode_for_vic(vic) != NULL; 4403} 4404 4405static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4406{ 4407 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4408 4409 if (mode) 4410 return mode->picture_aspect_ratio; 4411 4412 return HDMI_PICTURE_ASPECT_NONE; 4413} 4414 4415static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4416{ 4417 return edid_4k_modes[video_code].picture_aspect_ratio; 4418} 4419 4420/* 4421 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4422 * specific block). 4423 */ 4424static unsigned int 4425hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4426{ 4427 return cea_mode_alternate_clock(hdmi_mode); 4428} 4429 4430static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4431 unsigned int clock_tolerance) 4432{ 4433 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4434 u8 vic; 4435 4436 if (!to_match->clock) 4437 return 0; 4438 4439 if (to_match->picture_aspect_ratio) 4440 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4441 4442 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4443 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4444 unsigned int clock1, clock2; 4445 4446 /* Make sure to also match alternate clocks */ 4447 clock1 = hdmi_mode->clock; 4448 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4449 4450 if (abs(to_match->clock - clock1) > clock_tolerance && 4451 abs(to_match->clock - clock2) > clock_tolerance) 4452 continue; 4453 4454 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4455 return vic; 4456 } 4457 4458 return 0; 4459} 4460 4461/* 4462 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4463 * @to_match: display mode 4464 * 4465 * An HDMI mode is one defined in the HDMI vendor specific block. 4466 * 4467 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4468 */ 4469static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4470{ 4471 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4472 u8 vic; 4473 4474 if (!to_match->clock) 4475 return 0; 4476 4477 if (to_match->picture_aspect_ratio) 4478 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4479 4480 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4481 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4482 unsigned int clock1, clock2; 4483 4484 /* Make sure to also match alternate clocks */ 4485 clock1 = hdmi_mode->clock; 4486 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4487 4488 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4489 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4490 drm_mode_match(to_match, hdmi_mode, match_flags)) 4491 return vic; 4492 } 4493 return 0; 4494} 4495 4496static bool drm_valid_hdmi_vic(u8 vic) 4497{ 4498 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4499} 4500 4501static int add_alternate_cea_modes(struct drm_connector *connector, 4502 const struct drm_edid *drm_edid) 4503{ 4504 struct drm_device *dev = connector->dev; 4505 struct drm_display_mode *mode, *tmp; 4506 LIST_HEAD(list); 4507 int modes = 0; 4508 4509 /* Don't add CTA modes if the CTA extension block is missing */ 4510 if (!drm_edid_has_cta_extension(drm_edid)) 4511 return 0; 4512 4513 /* 4514 * Go through all probed modes and create a new mode 4515 * with the alternate clock for certain CEA modes. 4516 */ 4517 list_for_each_entry(mode, &connector->probed_modes, head) { 4518 const struct drm_display_mode *cea_mode = NULL; 4519 struct drm_display_mode *newmode; 4520 u8 vic = drm_match_cea_mode(mode); 4521 unsigned int clock1, clock2; 4522 4523 if (drm_valid_cea_vic(vic)) { 4524 cea_mode = cea_mode_for_vic(vic); 4525 clock2 = cea_mode_alternate_clock(cea_mode); 4526 } else { 4527 vic = drm_match_hdmi_mode(mode); 4528 if (drm_valid_hdmi_vic(vic)) { 4529 cea_mode = &edid_4k_modes[vic]; 4530 clock2 = hdmi_mode_alternate_clock(cea_mode); 4531 } 4532 } 4533 4534 if (!cea_mode) 4535 continue; 4536 4537 clock1 = cea_mode->clock; 4538 4539 if (clock1 == clock2) 4540 continue; 4541 4542 if (mode->clock != clock1 && mode->clock != clock2) 4543 continue; 4544 4545 newmode = drm_mode_duplicate(dev, cea_mode); 4546 if (!newmode) 4547 continue; 4548 4549 /* Carry over the stereo flags */ 4550 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4551 4552 /* 4553 * The current mode could be either variant. Make 4554 * sure to pick the "other" clock for the new mode. 4555 */ 4556 if (mode->clock != clock1) 4557 newmode->clock = clock1; 4558 else 4559 newmode->clock = clock2; 4560 4561 list_add_tail(&newmode->head, &list); 4562 } 4563 4564 list_for_each_entry_safe(mode, tmp, &list, head) { 4565 list_del(&mode->head); 4566 drm_mode_probed_add(connector, mode); 4567 modes++; 4568 } 4569 4570 return modes; 4571} 4572 4573static u8 svd_to_vic(u8 svd) 4574{ 4575 /* 0-6 bit vic, 7th bit native mode indicator */ 4576 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4577 return svd & 127; 4578 4579 return svd; 4580} 4581 4582/* 4583 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in 4584 * the EDID, or NULL on errors. 4585 */ 4586static struct drm_display_mode * 4587drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index) 4588{ 4589 const struct drm_display_info *info = &connector->display_info; 4590 struct drm_device *dev = connector->dev; 4591 4592 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index]) 4593 return NULL; 4594 4595 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]); 4596} 4597 4598/* 4599 * do_y420vdb_modes - Parse YCBCR 420 only modes 4600 * @connector: connector corresponding to the HDMI sink 4601 * @svds: start of the data block of CEA YCBCR 420 VDB 4602 * @len: length of the CEA YCBCR 420 VDB 4603 * 4604 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4605 * which contains modes which can be supported in YCBCR 420 4606 * output format only. 4607 */ 4608static int do_y420vdb_modes(struct drm_connector *connector, 4609 const u8 *svds, u8 svds_len) 4610{ 4611 struct drm_device *dev = connector->dev; 4612 int modes = 0, i; 4613 4614 for (i = 0; i < svds_len; i++) { 4615 u8 vic = svd_to_vic(svds[i]); 4616 struct drm_display_mode *newmode; 4617 4618 if (!drm_valid_cea_vic(vic)) 4619 continue; 4620 4621 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4622 if (!newmode) 4623 break; 4624 drm_mode_probed_add(connector, newmode); 4625 modes++; 4626 } 4627 4628 return modes; 4629} 4630 4631/** 4632 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4633 * @dev: DRM device 4634 * @video_code: CEA VIC of the mode 4635 * 4636 * Creates a new mode matching the specified CEA VIC. 4637 * 4638 * Returns: A new drm_display_mode on success or NULL on failure 4639 */ 4640struct drm_display_mode * 4641drm_display_mode_from_cea_vic(struct drm_device *dev, 4642 u8 video_code) 4643{ 4644 const struct drm_display_mode *cea_mode; 4645 struct drm_display_mode *newmode; 4646 4647 cea_mode = cea_mode_for_vic(video_code); 4648 if (!cea_mode) 4649 return NULL; 4650 4651 newmode = drm_mode_duplicate(dev, cea_mode); 4652 if (!newmode) 4653 return NULL; 4654 4655 return newmode; 4656} 4657EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4658 4659/* Add modes based on VICs parsed in parse_cta_vdb() */ 4660static int add_cta_vdb_modes(struct drm_connector *connector) 4661{ 4662 const struct drm_display_info *info = &connector->display_info; 4663 int i, modes = 0; 4664 4665 if (!info->vics) 4666 return 0; 4667 4668 for (i = 0; i < info->vics_len; i++) { 4669 struct drm_display_mode *mode; 4670 4671 mode = drm_display_mode_from_vic_index(connector, i); 4672 if (mode) { 4673 drm_mode_probed_add(connector, mode); 4674 modes++; 4675 } 4676 } 4677 4678 return modes; 4679} 4680 4681struct stereo_mandatory_mode { 4682 int width, height, vrefresh; 4683 unsigned int flags; 4684}; 4685 4686static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4687 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4688 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4689 { 1920, 1080, 50, 4690 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4691 { 1920, 1080, 60, 4692 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4693 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4694 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4695 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4696 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4697}; 4698 4699static bool 4700stereo_match_mandatory(const struct drm_display_mode *mode, 4701 const struct stereo_mandatory_mode *stereo_mode) 4702{ 4703 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4704 4705 return mode->hdisplay == stereo_mode->width && 4706 mode->vdisplay == stereo_mode->height && 4707 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4708 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4709} 4710 4711static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4712{ 4713 struct drm_device *dev = connector->dev; 4714 const struct drm_display_mode *mode; 4715 struct list_head stereo_modes; 4716 int modes = 0, i; 4717 4718 INIT_LIST_HEAD(&stereo_modes); 4719 4720 list_for_each_entry(mode, &connector->probed_modes, head) { 4721 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4722 const struct stereo_mandatory_mode *mandatory; 4723 struct drm_display_mode *new_mode; 4724 4725 if (!stereo_match_mandatory(mode, 4726 &stereo_mandatory_modes[i])) 4727 continue; 4728 4729 mandatory = &stereo_mandatory_modes[i]; 4730 new_mode = drm_mode_duplicate(dev, mode); 4731 if (!new_mode) 4732 continue; 4733 4734 new_mode->flags |= mandatory->flags; 4735 list_add_tail(&new_mode->head, &stereo_modes); 4736 modes++; 4737 } 4738 } 4739 4740 list_splice_tail(&stereo_modes, &connector->probed_modes); 4741 4742 return modes; 4743} 4744 4745static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4746{ 4747 struct drm_device *dev = connector->dev; 4748 struct drm_display_mode *newmode; 4749 4750 if (!drm_valid_hdmi_vic(vic)) { 4751 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n", 4752 connector->base.id, connector->name, vic); 4753 return 0; 4754 } 4755 4756 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4757 if (!newmode) 4758 return 0; 4759 4760 drm_mode_probed_add(connector, newmode); 4761 4762 return 1; 4763} 4764 4765static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4766 int vic_index) 4767{ 4768 struct drm_display_mode *newmode; 4769 int modes = 0; 4770 4771 if (structure & (1 << 0)) { 4772 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4773 if (newmode) { 4774 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4775 drm_mode_probed_add(connector, newmode); 4776 modes++; 4777 } 4778 } 4779 if (structure & (1 << 6)) { 4780 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4781 if (newmode) { 4782 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4783 drm_mode_probed_add(connector, newmode); 4784 modes++; 4785 } 4786 } 4787 if (structure & (1 << 8)) { 4788 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4789 if (newmode) { 4790 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4791 drm_mode_probed_add(connector, newmode); 4792 modes++; 4793 } 4794 } 4795 4796 return modes; 4797} 4798 4799static bool hdmi_vsdb_latency_present(const u8 *db) 4800{ 4801 return db[8] & BIT(7); 4802} 4803 4804static bool hdmi_vsdb_i_latency_present(const u8 *db) 4805{ 4806 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6); 4807} 4808 4809static int hdmi_vsdb_latency_length(const u8 *db) 4810{ 4811 if (hdmi_vsdb_i_latency_present(db)) 4812 return 4; 4813 else if (hdmi_vsdb_latency_present(db)) 4814 return 2; 4815 else 4816 return 0; 4817} 4818 4819/* 4820 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4821 * @connector: connector corresponding to the HDMI sink 4822 * @db: start of the CEA vendor specific block 4823 * @len: length of the CEA block payload, ie. one can access up to db[len] 4824 * 4825 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4826 * also adds the stereo 3d modes when applicable. 4827 */ 4828static int 4829do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len) 4830{ 4831 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4832 u8 vic_len, hdmi_3d_len = 0; 4833 u16 mask; 4834 u16 structure_all; 4835 4836 if (len < 8) 4837 goto out; 4838 4839 /* no HDMI_Video_Present */ 4840 if (!(db[8] & (1 << 5))) 4841 goto out; 4842 4843 offset += hdmi_vsdb_latency_length(db); 4844 4845 /* the declared length is not long enough for the 2 first bytes 4846 * of additional video format capabilities */ 4847 if (len < (8 + offset + 2)) 4848 goto out; 4849 4850 /* 3D_Present */ 4851 offset++; 4852 if (db[8 + offset] & (1 << 7)) { 4853 modes += add_hdmi_mandatory_stereo_modes(connector); 4854 4855 /* 3D_Multi_present */ 4856 multi_present = (db[8 + offset] & 0x60) >> 5; 4857 } 4858 4859 offset++; 4860 vic_len = db[8 + offset] >> 5; 4861 hdmi_3d_len = db[8 + offset] & 0x1f; 4862 4863 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4864 u8 vic; 4865 4866 vic = db[9 + offset + i]; 4867 modes += add_hdmi_mode(connector, vic); 4868 } 4869 offset += 1 + vic_len; 4870 4871 if (multi_present == 1) 4872 multi_len = 2; 4873 else if (multi_present == 2) 4874 multi_len = 4; 4875 else 4876 multi_len = 0; 4877 4878 if (len < (8 + offset + hdmi_3d_len - 1)) 4879 goto out; 4880 4881 if (hdmi_3d_len < multi_len) 4882 goto out; 4883 4884 if (multi_present == 1 || multi_present == 2) { 4885 /* 3D_Structure_ALL */ 4886 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4887 4888 /* check if 3D_MASK is present */ 4889 if (multi_present == 2) 4890 mask = (db[10 + offset] << 8) | db[11 + offset]; 4891 else 4892 mask = 0xffff; 4893 4894 for (i = 0; i < 16; i++) { 4895 if (mask & (1 << i)) 4896 modes += add_3d_struct_modes(connector, 4897 structure_all, i); 4898 } 4899 } 4900 4901 offset += multi_len; 4902 4903 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4904 int vic_index; 4905 struct drm_display_mode *newmode = NULL; 4906 unsigned int newflag = 0; 4907 bool detail_present; 4908 4909 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4910 4911 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4912 break; 4913 4914 /* 2D_VIC_order_X */ 4915 vic_index = db[8 + offset + i] >> 4; 4916 4917 /* 3D_Structure_X */ 4918 switch (db[8 + offset + i] & 0x0f) { 4919 case 0: 4920 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4921 break; 4922 case 6: 4923 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4924 break; 4925 case 8: 4926 /* 3D_Detail_X */ 4927 if ((db[9 + offset + i] >> 4) == 1) 4928 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4929 break; 4930 } 4931 4932 if (newflag != 0) { 4933 newmode = drm_display_mode_from_vic_index(connector, 4934 vic_index); 4935 4936 if (newmode) { 4937 newmode->flags |= newflag; 4938 drm_mode_probed_add(connector, newmode); 4939 modes++; 4940 } 4941 } 4942 4943 if (detail_present) 4944 i++; 4945 } 4946 4947out: 4948 return modes; 4949} 4950 4951static int 4952cea_revision(const u8 *cea) 4953{ 4954 /* 4955 * FIXME is this correct for the DispID variant? 4956 * The DispID spec doesn't really specify whether 4957 * this is the revision of the CEA extension or 4958 * the DispID CEA data block. And the only value 4959 * given as an example is 0. 4960 */ 4961 return cea[1]; 4962} 4963 4964/* 4965 * CTA Data Block iterator. 4966 * 4967 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4968 * CTA Data Blocks. 4969 * 4970 * struct cea_db *db: 4971 * struct cea_db_iter iter; 4972 * 4973 * cea_db_iter_edid_begin(edid, &iter); 4974 * cea_db_iter_for_each(db, &iter) { 4975 * // do stuff with db 4976 * } 4977 * cea_db_iter_end(&iter); 4978 */ 4979struct cea_db_iter { 4980 struct drm_edid_iter edid_iter; 4981 struct displayid_iter displayid_iter; 4982 4983 /* Current Data Block Collection. */ 4984 const u8 *collection; 4985 4986 /* Current Data Block index in current collection. */ 4987 int index; 4988 4989 /* End index in current collection. */ 4990 int end; 4991}; 4992 4993/* CTA-861-H section 7.4 CTA Data BLock Collection */ 4994struct cea_db { 4995 u8 tag_length; 4996 u8 data[]; 4997} __packed; 4998 4999static int cea_db_tag(const struct cea_db *db) 5000{ 5001 return db->tag_length >> 5; 5002} 5003 5004static int cea_db_payload_len(const void *_db) 5005{ 5006 /* FIXME: Transition to passing struct cea_db * everywhere. */ 5007 const struct cea_db *db = _db; 5008 5009 return db->tag_length & 0x1f; 5010} 5011 5012static const void *cea_db_data(const struct cea_db *db) 5013{ 5014 return db->data; 5015} 5016 5017static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 5018{ 5019 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 5020 cea_db_payload_len(db) >= 1 && 5021 db->data[0] == tag; 5022} 5023 5024static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 5025{ 5026 const u8 *data = cea_db_data(db); 5027 5028 return cea_db_tag(db) == CTA_DB_VENDOR && 5029 cea_db_payload_len(db) >= 3 && 5030 oui(data[2], data[1], data[0]) == vendor_oui; 5031} 5032 5033static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 5034 struct cea_db_iter *iter) 5035{ 5036 memset(iter, 0, sizeof(*iter)); 5037 5038 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 5039 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 5040} 5041 5042static const struct cea_db * 5043__cea_db_iter_current_block(const struct cea_db_iter *iter) 5044{ 5045 const struct cea_db *db; 5046 5047 if (!iter->collection) 5048 return NULL; 5049 5050 db = (const struct cea_db *)&iter->collection[iter->index]; 5051 5052 if (iter->index + sizeof(*db) <= iter->end && 5053 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 5054 return db; 5055 5056 return NULL; 5057} 5058 5059/* 5060 * References: 5061 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5062 */ 5063static int cea_db_collection_size(const u8 *cta) 5064{ 5065 u8 d = cta[2]; 5066 5067 if (d < 4 || d > 127) 5068 return 0; 5069 5070 return d - 4; 5071} 5072 5073/* 5074 * References: 5075 * - VESA E-EDID v1.4 5076 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5077 */ 5078static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 5079{ 5080 const u8 *ext; 5081 5082 drm_edid_iter_for_each(ext, &iter->edid_iter) { 5083 int size; 5084 5085 /* Only support CTA Extension revision 3+ */ 5086 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 5087 continue; 5088 5089 size = cea_db_collection_size(ext); 5090 if (!size) 5091 continue; 5092 5093 iter->index = 4; 5094 iter->end = iter->index + size; 5095 5096 return ext; 5097 } 5098 5099 return NULL; 5100} 5101 5102/* 5103 * References: 5104 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 5105 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 5106 * 5107 * Note that the above do not specify any connection between DisplayID Data 5108 * Block revision and CTA Extension versions. 5109 */ 5110static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 5111{ 5112 const struct displayid_block *block; 5113 5114 displayid_iter_for_each(block, &iter->displayid_iter) { 5115 if (block->tag != DATA_BLOCK_CTA) 5116 continue; 5117 5118 /* 5119 * The displayid iterator has already verified the block bounds 5120 * in displayid_iter_block(). 5121 */ 5122 iter->index = sizeof(*block); 5123 iter->end = iter->index + block->num_bytes; 5124 5125 return block; 5126 } 5127 5128 return NULL; 5129} 5130 5131static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 5132{ 5133 const struct cea_db *db; 5134 5135 if (iter->collection) { 5136 /* Current collection should always be valid. */ 5137 db = __cea_db_iter_current_block(iter); 5138 if (WARN_ON(!db)) { 5139 iter->collection = NULL; 5140 return NULL; 5141 } 5142 5143 /* Next block in CTA Data Block Collection */ 5144 iter->index += sizeof(*db) + cea_db_payload_len(db); 5145 5146 db = __cea_db_iter_current_block(iter); 5147 if (db) 5148 return db; 5149 } 5150 5151 for (;;) { 5152 /* 5153 * Find the next CTA Data Block Collection. First iterate all 5154 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 5155 * 5156 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 5157 * Extension, it's recommended that DisplayID extensions are 5158 * exposed after all of the CTA Extensions. 5159 */ 5160 iter->collection = __cea_db_iter_edid_next(iter); 5161 if (!iter->collection) 5162 iter->collection = __cea_db_iter_displayid_next(iter); 5163 5164 if (!iter->collection) 5165 return NULL; 5166 5167 db = __cea_db_iter_current_block(iter); 5168 if (db) 5169 return db; 5170 } 5171} 5172 5173#define cea_db_iter_for_each(__db, __iter) \ 5174 while (((__db) = __cea_db_iter_next(__iter))) 5175 5176static void cea_db_iter_end(struct cea_db_iter *iter) 5177{ 5178 displayid_iter_end(&iter->displayid_iter); 5179 drm_edid_iter_end(&iter->edid_iter); 5180 5181 memset(iter, 0, sizeof(*iter)); 5182} 5183 5184static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 5185{ 5186 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 5187 cea_db_payload_len(db) >= 5; 5188} 5189 5190static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 5191{ 5192 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 5193 cea_db_payload_len(db) >= 7; 5194} 5195 5196static bool cea_db_is_hdmi_forum_eeodb(const void *db) 5197{ 5198 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 5199 cea_db_payload_len(db) >= 2; 5200} 5201 5202static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 5203{ 5204 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 5205 cea_db_payload_len(db) == 21; 5206} 5207 5208static bool cea_db_is_vcdb(const struct cea_db *db) 5209{ 5210 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 5211 cea_db_payload_len(db) == 2; 5212} 5213 5214static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 5215{ 5216 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 5217 cea_db_payload_len(db) >= 7; 5218} 5219 5220static bool cea_db_is_y420cmdb(const struct cea_db *db) 5221{ 5222 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 5223} 5224 5225static bool cea_db_is_y420vdb(const struct cea_db *db) 5226{ 5227 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 5228} 5229 5230static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 5231{ 5232 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 5233 cea_db_payload_len(db) >= 3; 5234} 5235 5236/* 5237 * Get the HF-EEODB override extension block count from EDID. 5238 * 5239 * The passed in EDID may be partially read, as long as it has at least two 5240 * blocks (base block and one extension block) if EDID extension count is > 0. 5241 * 5242 * Note that this is *not* how you should parse CTA Data Blocks in general; this 5243 * is only to handle partially read EDIDs. Normally, use the CTA Data Block 5244 * iterators instead. 5245 * 5246 * References: 5247 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block 5248 */ 5249static int edid_hfeeodb_extension_block_count(const struct edid *edid) 5250{ 5251 const u8 *cta; 5252 5253 /* No extensions according to base block, no HF-EEODB. */ 5254 if (!edid_extension_block_count(edid)) 5255 return 0; 5256 5257 /* HF-EEODB is always in the first EDID extension block only */ 5258 cta = edid_extension_block_data(edid, 0); 5259 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3) 5260 return 0; 5261 5262 /* Need to have the data block collection, and at least 3 bytes. */ 5263 if (cea_db_collection_size(cta) < 3) 5264 return 0; 5265 5266 /* 5267 * Sinks that include the HF-EEODB in their E-EDID shall include one and 5268 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 5269 * through 6 of Block 1 of the E-EDID. 5270 */ 5271 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 5272 return 0; 5273 5274 return cta[4 + 2]; 5275} 5276 5277/* 5278 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB) 5279 * 5280 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB, 5281 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444 5282 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can 5283 * support YCBCR420 output too. 5284 */ 5285static void parse_cta_y420cmdb(struct drm_connector *connector, 5286 const struct cea_db *db, u64 *y420cmdb_map) 5287{ 5288 struct drm_display_info *info = &connector->display_info; 5289 int i, map_len = cea_db_payload_len(db) - 1; 5290 const u8 *data = cea_db_data(db) + 1; 5291 u64 map = 0; 5292 5293 if (map_len == 0) { 5294 /* All CEA modes support ycbcr420 sampling also.*/ 5295 map = U64_MAX; 5296 goto out; 5297 } 5298 5299 /* 5300 * This map indicates which of the existing CEA block modes 5301 * from VDB can support YCBCR420 output too. So if bit=0 is 5302 * set, first mode from VDB can support YCBCR420 output too. 5303 * We will parse and keep this map, before parsing VDB itself 5304 * to avoid going through the same block again and again. 5305 * 5306 * Spec is not clear about max possible size of this block. 5307 * Clamping max bitmap block size at 8 bytes. Every byte can 5308 * address 8 CEA modes, in this way this map can address 5309 * 8*8 = first 64 SVDs. 5310 */ 5311 if (WARN_ON_ONCE(map_len > 8)) 5312 map_len = 8; 5313 5314 for (i = 0; i < map_len; i++) 5315 map |= (u64)data[i] << (8 * i); 5316 5317out: 5318 if (map) 5319 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5320 5321 *y420cmdb_map = map; 5322} 5323 5324static int add_cea_modes(struct drm_connector *connector, 5325 const struct drm_edid *drm_edid) 5326{ 5327 const struct cea_db *db; 5328 struct cea_db_iter iter; 5329 int modes; 5330 5331 /* CTA VDB block VICs parsed earlier */ 5332 modes = add_cta_vdb_modes(connector); 5333 5334 cea_db_iter_edid_begin(drm_edid, &iter); 5335 cea_db_iter_for_each(db, &iter) { 5336 if (cea_db_is_hdmi_vsdb(db)) { 5337 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db, 5338 cea_db_payload_len(db)); 5339 } else if (cea_db_is_y420vdb(db)) { 5340 const u8 *vdb420 = cea_db_data(db) + 1; 5341 5342 /* Add 4:2:0(only) modes present in EDID */ 5343 modes += do_y420vdb_modes(connector, vdb420, 5344 cea_db_payload_len(db) - 1); 5345 } 5346 } 5347 cea_db_iter_end(&iter); 5348 5349 return modes; 5350} 5351 5352static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 5353 struct drm_display_mode *mode) 5354{ 5355 const struct drm_display_mode *cea_mode; 5356 int clock1, clock2, clock; 5357 u8 vic; 5358 const char *type; 5359 5360 /* 5361 * allow 5kHz clock difference either way to account for 5362 * the 10kHz clock resolution limit of detailed timings. 5363 */ 5364 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 5365 if (drm_valid_cea_vic(vic)) { 5366 type = "CEA"; 5367 cea_mode = cea_mode_for_vic(vic); 5368 clock1 = cea_mode->clock; 5369 clock2 = cea_mode_alternate_clock(cea_mode); 5370 } else { 5371 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 5372 if (drm_valid_hdmi_vic(vic)) { 5373 type = "HDMI"; 5374 cea_mode = &edid_4k_modes[vic]; 5375 clock1 = cea_mode->clock; 5376 clock2 = hdmi_mode_alternate_clock(cea_mode); 5377 } else { 5378 return; 5379 } 5380 } 5381 5382 /* pick whichever is closest */ 5383 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5384 clock = clock1; 5385 else 5386 clock = clock2; 5387 5388 if (mode->clock == clock) 5389 return; 5390 5391 drm_dbg_kms(connector->dev, 5392 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5393 connector->base.id, connector->name, 5394 type, vic, mode->clock, clock); 5395 mode->clock = clock; 5396} 5397 5398static void drm_calculate_luminance_range(struct drm_connector *connector) 5399{ 5400 const struct hdr_static_metadata *hdr_metadata = 5401 &connector->display_info.hdr_sink_metadata.hdmi_type1; 5402 struct drm_luminance_range_info *luminance_range = 5403 &connector->display_info.luminance_range; 5404 static const u8 pre_computed_values[] = { 5405 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 5406 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 5407 }; 5408 u32 max_avg, min_cll, max, min, q, r; 5409 5410 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) 5411 return; 5412 5413 max_avg = hdr_metadata->max_fall; 5414 min_cll = hdr_metadata->min_cll; 5415 5416 /* 5417 * From the specification (CTA-861-G), for calculating the maximum 5418 * luminance we need to use: 5419 * Luminance = 50*2**(CV/32) 5420 * Where CV is a one-byte value. 5421 * For calculating this expression we may need float point precision; 5422 * to avoid this complexity level, we take advantage that CV is divided 5423 * by a constant. From the Euclids division algorithm, we know that CV 5424 * can be written as: CV = 32*q + r. Next, we replace CV in the 5425 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 5426 * need to pre-compute the value of r/32. For pre-computing the values 5427 * We just used the following Ruby line: 5428 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 5429 * The results of the above expressions can be verified at 5430 * pre_computed_values. 5431 */ 5432 q = max_avg >> 5; 5433 r = max_avg % 32; 5434 max = (1 << q) * pre_computed_values[r]; 5435 5436 /* min luminance: maxLum * (CV/255)^2 / 100 */ 5437 q = DIV_ROUND_CLOSEST(min_cll, 255); 5438 min = max * DIV_ROUND_CLOSEST((q * q), 100); 5439 5440 luminance_range->min_luminance = min; 5441 luminance_range->max_luminance = max; 5442} 5443 5444static uint8_t eotf_supported(const u8 *edid_ext) 5445{ 5446 return edid_ext[2] & 5447 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5448 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5449 BIT(HDMI_EOTF_SMPTE_ST2084) | 5450 BIT(HDMI_EOTF_BT_2100_HLG)); 5451} 5452 5453static uint8_t hdr_metadata_type(const u8 *edid_ext) 5454{ 5455 return edid_ext[3] & 5456 BIT(HDMI_STATIC_METADATA_TYPE1); 5457} 5458 5459static void 5460drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5461{ 5462 struct hdr_static_metadata *hdr_metadata = 5463 &connector->display_info.hdr_sink_metadata.hdmi_type1; 5464 u16 len; 5465 5466 len = cea_db_payload_len(db); 5467 5468 hdr_metadata->eotf = eotf_supported(db); 5469 hdr_metadata->metadata_type = hdr_metadata_type(db); 5470 5471 if (len >= 4) 5472 hdr_metadata->max_cll = db[4]; 5473 if (len >= 5) 5474 hdr_metadata->max_fall = db[5]; 5475 if (len >= 6) { 5476 hdr_metadata->min_cll = db[6]; 5477 5478 /* Calculate only when all values are available */ 5479 drm_calculate_luminance_range(connector); 5480 } 5481} 5482 5483/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 5484static void 5485drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5486{ 5487 u8 len = cea_db_payload_len(db); 5488 5489 if (len >= 6 && (db[6] & (1 << 7))) 5490 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5491 5492 if (len >= 10 && hdmi_vsdb_latency_present(db)) { 5493 connector->latency_present[0] = true; 5494 connector->video_latency[0] = db[9]; 5495 connector->audio_latency[0] = db[10]; 5496 } 5497 5498 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) { 5499 connector->latency_present[1] = true; 5500 connector->video_latency[1] = db[11]; 5501 connector->audio_latency[1] = db[12]; 5502 } 5503 5504 drm_dbg_kms(connector->dev, 5505 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n", 5506 connector->base.id, connector->name, 5507 connector->latency_present[0], connector->latency_present[1], 5508 connector->video_latency[0], connector->video_latency[1], 5509 connector->audio_latency[0], connector->audio_latency[1]); 5510} 5511 5512static void 5513match_identity(const struct detailed_timing *timing, void *data) 5514{ 5515 struct drm_edid_match_closure *closure = data; 5516 unsigned int i; 5517 const char *name = closure->ident->name; 5518 unsigned int name_len = strlen(name); 5519 const char *desc = timing->data.other_data.data.str.str; 5520 unsigned int desc_len = ARRAY_SIZE(timing->data.other_data.data.str.str); 5521 5522 if (name_len > desc_len || 5523 !(is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME) || 5524 is_display_descriptor(timing, EDID_DETAIL_MONITOR_STRING))) 5525 return; 5526 5527 if (strncmp(name, desc, name_len)) 5528 return; 5529 5530 for (i = name_len; i < desc_len; i++) { 5531 if (desc[i] == '\n') 5532 break; 5533 /* Allow white space before EDID string terminator. */ 5534 if (!isspace(desc[i])) 5535 return; 5536 } 5537 5538 closure->matched = true; 5539} 5540 5541/** 5542 * drm_edid_match - match drm_edid with given identity 5543 * @drm_edid: EDID 5544 * @ident: the EDID identity to match with 5545 * 5546 * Check if the EDID matches with the given identity. 5547 * 5548 * Return: True if the given identity matched with EDID, false otherwise. 5549 */ 5550bool drm_edid_match(const struct drm_edid *drm_edid, 5551 const struct drm_edid_ident *ident) 5552{ 5553 if (!drm_edid || drm_edid_get_panel_id(drm_edid) != ident->panel_id) 5554 return false; 5555 5556 /* Match with name only if it's not NULL. */ 5557 if (ident->name) { 5558 struct drm_edid_match_closure closure = { 5559 .ident = ident, 5560 .matched = false, 5561 }; 5562 5563 drm_for_each_detailed_block(drm_edid, match_identity, &closure); 5564 5565 return closure.matched; 5566 } 5567 5568 return true; 5569} 5570EXPORT_SYMBOL(drm_edid_match); 5571 5572static void 5573monitor_name(const struct detailed_timing *timing, void *data) 5574{ 5575 const char **res = data; 5576 5577 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5578 return; 5579 5580 *res = timing->data.other_data.data.str.str; 5581} 5582 5583static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5584{ 5585 const char *edid_name = NULL; 5586 int mnl; 5587 5588 if (!drm_edid || !name) 5589 return 0; 5590 5591 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5592 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5593 if (edid_name[mnl] == 0x0a) 5594 break; 5595 5596 name[mnl] = edid_name[mnl]; 5597 } 5598 5599 return mnl; 5600} 5601 5602/** 5603 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5604 * @edid: monitor EDID information 5605 * @name: pointer to a character array to hold the name of the monitor 5606 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5607 * 5608 */ 5609void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5610{ 5611 int name_length = 0; 5612 5613 if (bufsize <= 0) 5614 return; 5615 5616 if (edid) { 5617 char buf[13]; 5618 struct drm_edid drm_edid = { 5619 .edid = edid, 5620 .size = edid_size(edid), 5621 }; 5622 5623 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5624 memcpy(name, buf, name_length); 5625 } 5626 5627 name[name_length] = '\0'; 5628} 5629EXPORT_SYMBOL(drm_edid_get_monitor_name); 5630 5631static void clear_eld(struct drm_connector *connector) 5632{ 5633 mutex_lock(&connector->eld_mutex); 5634 memset(connector->eld, 0, sizeof(connector->eld)); 5635 mutex_unlock(&connector->eld_mutex); 5636 5637 connector->latency_present[0] = false; 5638 connector->latency_present[1] = false; 5639 connector->video_latency[0] = 0; 5640 connector->audio_latency[0] = 0; 5641 connector->video_latency[1] = 0; 5642 connector->audio_latency[1] = 0; 5643} 5644 5645/* 5646 * Get 3-byte SAD buffer from struct cea_sad. 5647 */ 5648void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad) 5649{ 5650 sad[0] = cta_sad->format << 3 | cta_sad->channels; 5651 sad[1] = cta_sad->freq; 5652 sad[2] = cta_sad->byte2; 5653} 5654 5655/* 5656 * Set struct cea_sad from 3-byte SAD buffer. 5657 */ 5658void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad) 5659{ 5660 cta_sad->format = (sad[0] & 0x78) >> 3; 5661 cta_sad->channels = sad[0] & 0x07; 5662 cta_sad->freq = sad[1] & 0x7f; 5663 cta_sad->byte2 = sad[2]; 5664} 5665 5666/* 5667 * drm_edid_to_eld - build ELD from EDID 5668 * @connector: connector corresponding to the HDMI/DP sink 5669 * @drm_edid: EDID to parse 5670 * 5671 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5672 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5673 */ 5674static void drm_edid_to_eld(struct drm_connector *connector, 5675 const struct drm_edid *drm_edid) 5676{ 5677 const struct drm_display_info *info = &connector->display_info; 5678 const struct cea_db *db; 5679 struct cea_db_iter iter; 5680 uint8_t *eld = connector->eld; 5681 int total_sad_count = 0; 5682 int mnl; 5683 5684 if (!drm_edid) 5685 return; 5686 5687 mutex_lock(&connector->eld_mutex); 5688 5689 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5690 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n", 5691 connector->base.id, connector->name, 5692 &eld[DRM_ELD_MONITOR_NAME_STRING]); 5693 5694 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5695 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5696 5697 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5698 5699 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5700 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5701 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5702 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5703 5704 cea_db_iter_edid_begin(drm_edid, &iter); 5705 cea_db_iter_for_each(db, &iter) { 5706 const u8 *data = cea_db_data(db); 5707 int len = cea_db_payload_len(db); 5708 int sad_count; 5709 5710 switch (cea_db_tag(db)) { 5711 case CTA_DB_AUDIO: 5712 /* Audio Data Block, contains SADs */ 5713 sad_count = min(len / 3, 15 - total_sad_count); 5714 if (sad_count >= 1) 5715 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5716 data, sad_count * 3); 5717 total_sad_count += sad_count; 5718 break; 5719 case CTA_DB_SPEAKER: 5720 /* Speaker Allocation Data Block */ 5721 if (len >= 1) 5722 eld[DRM_ELD_SPEAKER] = data[0]; 5723 break; 5724 case CTA_DB_VENDOR: 5725 /* HDMI Vendor-Specific Data Block */ 5726 if (cea_db_is_hdmi_vsdb(db)) 5727 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5728 break; 5729 default: 5730 break; 5731 } 5732 } 5733 cea_db_iter_end(&iter); 5734 5735 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5736 5737 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5738 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5739 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5740 else 5741 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5742 5743 eld[DRM_ELD_BASELINE_ELD_LEN] = 5744 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5745 5746 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n", 5747 connector->base.id, connector->name, 5748 drm_eld_size(eld), total_sad_count); 5749 5750 mutex_unlock(&connector->eld_mutex); 5751} 5752 5753static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5754 struct cea_sad **psads) 5755{ 5756 const struct cea_db *db; 5757 struct cea_db_iter iter; 5758 int count = 0; 5759 5760 cea_db_iter_edid_begin(drm_edid, &iter); 5761 cea_db_iter_for_each(db, &iter) { 5762 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5763 struct cea_sad *sads; 5764 int i; 5765 5766 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5767 sads = kcalloc(count, sizeof(*sads), GFP_KERNEL); 5768 *psads = sads; 5769 if (!sads) 5770 return -ENOMEM; 5771 for (i = 0; i < count; i++) 5772 drm_edid_cta_sad_set(&sads[i], &db->data[i * 3]); 5773 break; 5774 } 5775 } 5776 cea_db_iter_end(&iter); 5777 5778 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5779 5780 return count; 5781} 5782 5783/** 5784 * drm_edid_to_sad - extracts SADs from EDID 5785 * @edid: EDID to parse 5786 * @sads: pointer that will be set to the extracted SADs 5787 * 5788 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5789 * 5790 * Note: The returned pointer needs to be freed using kfree(). 5791 * 5792 * Return: The number of found SADs or negative number on error. 5793 */ 5794int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5795{ 5796 struct drm_edid drm_edid; 5797 5798 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5799} 5800EXPORT_SYMBOL(drm_edid_to_sad); 5801 5802static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5803 u8 **sadb) 5804{ 5805 const struct cea_db *db; 5806 struct cea_db_iter iter; 5807 int count = 0; 5808 5809 cea_db_iter_edid_begin(drm_edid, &iter); 5810 cea_db_iter_for_each(db, &iter) { 5811 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5812 cea_db_payload_len(db) == 3) { 5813 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5814 GFP_KERNEL); 5815 if (!*sadb) 5816 return -ENOMEM; 5817 count = cea_db_payload_len(db); 5818 break; 5819 } 5820 } 5821 cea_db_iter_end(&iter); 5822 5823 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5824 5825 return count; 5826} 5827 5828/** 5829 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5830 * @edid: EDID to parse 5831 * @sadb: pointer to the speaker block 5832 * 5833 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5834 * 5835 * Note: The returned pointer needs to be freed using kfree(). 5836 * 5837 * Return: The number of found Speaker Allocation Blocks or negative number on 5838 * error. 5839 */ 5840int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5841{ 5842 struct drm_edid drm_edid; 5843 5844 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5845 sadb); 5846} 5847EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5848 5849/** 5850 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5851 * @connector: connector associated with the HDMI/DP sink 5852 * @mode: the display mode 5853 * 5854 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5855 * the sink doesn't support audio or video. 5856 */ 5857int drm_av_sync_delay(struct drm_connector *connector, 5858 const struct drm_display_mode *mode) 5859{ 5860 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5861 int a, v; 5862 5863 if (!connector->latency_present[0]) 5864 return 0; 5865 if (!connector->latency_present[1]) 5866 i = 0; 5867 5868 a = connector->audio_latency[i]; 5869 v = connector->video_latency[i]; 5870 5871 /* 5872 * HDMI/DP sink doesn't support audio or video? 5873 */ 5874 if (a == 255 || v == 255) 5875 return 0; 5876 5877 /* 5878 * Convert raw EDID values to millisecond. 5879 * Treat unknown latency as 0ms. 5880 */ 5881 if (a) 5882 a = min(2 * (a - 1), 500); 5883 if (v) 5884 v = min(2 * (v - 1), 500); 5885 5886 return max(v - a, 0); 5887} 5888EXPORT_SYMBOL(drm_av_sync_delay); 5889 5890static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5891{ 5892 const struct cea_db *db; 5893 struct cea_db_iter iter; 5894 bool hdmi = false; 5895 5896 /* 5897 * Because HDMI identifier is in Vendor Specific Block, 5898 * search it from all data blocks of CEA extension. 5899 */ 5900 cea_db_iter_edid_begin(drm_edid, &iter); 5901 cea_db_iter_for_each(db, &iter) { 5902 if (cea_db_is_hdmi_vsdb(db)) { 5903 hdmi = true; 5904 break; 5905 } 5906 } 5907 cea_db_iter_end(&iter); 5908 5909 return hdmi; 5910} 5911 5912/** 5913 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5914 * @edid: monitor EDID information 5915 * 5916 * Parse the CEA extension according to CEA-861-B. 5917 * 5918 * Drivers that have added the modes parsed from EDID to drm_display_info 5919 * should use &drm_display_info.is_hdmi instead of calling this function. 5920 * 5921 * Return: True if the monitor is HDMI, false if not or unknown. 5922 */ 5923bool drm_detect_hdmi_monitor(const struct edid *edid) 5924{ 5925 struct drm_edid drm_edid; 5926 5927 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5928} 5929EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5930 5931static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5932{ 5933 struct drm_edid_iter edid_iter; 5934 const struct cea_db *db; 5935 struct cea_db_iter iter; 5936 const u8 *edid_ext; 5937 bool has_audio = false; 5938 5939 drm_edid_iter_begin(drm_edid, &edid_iter); 5940 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5941 if (edid_ext[0] == CEA_EXT) { 5942 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5943 if (has_audio) 5944 break; 5945 } 5946 } 5947 drm_edid_iter_end(&edid_iter); 5948 5949 if (has_audio) { 5950 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5951 goto end; 5952 } 5953 5954 cea_db_iter_edid_begin(drm_edid, &iter); 5955 cea_db_iter_for_each(db, &iter) { 5956 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5957 const u8 *data = cea_db_data(db); 5958 int i; 5959 5960 for (i = 0; i < cea_db_payload_len(db); i += 3) 5961 DRM_DEBUG_KMS("CEA audio format %d\n", 5962 (data[i] >> 3) & 0xf); 5963 has_audio = true; 5964 break; 5965 } 5966 } 5967 cea_db_iter_end(&iter); 5968 5969end: 5970 return has_audio; 5971} 5972 5973/** 5974 * drm_detect_monitor_audio - check monitor audio capability 5975 * @edid: EDID block to scan 5976 * 5977 * Monitor should have CEA extension block. 5978 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5979 * audio' only. If there is any audio extension block and supported 5980 * audio format, assume at least 'basic audio' support, even if 'basic 5981 * audio' is not defined in EDID. 5982 * 5983 * Return: True if the monitor supports audio, false otherwise. 5984 */ 5985bool drm_detect_monitor_audio(const struct edid *edid) 5986{ 5987 struct drm_edid drm_edid; 5988 5989 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5990} 5991EXPORT_SYMBOL(drm_detect_monitor_audio); 5992 5993 5994/** 5995 * drm_default_rgb_quant_range - default RGB quantization range 5996 * @mode: display mode 5997 * 5998 * Determine the default RGB quantization range for the mode, 5999 * as specified in CEA-861. 6000 * 6001 * Return: The default RGB quantization range for the mode 6002 */ 6003enum hdmi_quantization_range 6004drm_default_rgb_quant_range(const struct drm_display_mode *mode) 6005{ 6006 /* All CEA modes other than VIC 1 use limited quantization range. */ 6007 return drm_match_cea_mode(mode) > 1 ? 6008 HDMI_QUANTIZATION_RANGE_LIMITED : 6009 HDMI_QUANTIZATION_RANGE_FULL; 6010} 6011EXPORT_SYMBOL(drm_default_rgb_quant_range); 6012 6013/* CTA-861 Video Data Block (CTA VDB) */ 6014static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db) 6015{ 6016 struct drm_display_info *info = &connector->display_info; 6017 int i, vic_index, len = cea_db_payload_len(db); 6018 const u8 *svds = cea_db_data(db); 6019 u8 *vics; 6020 6021 if (!len) 6022 return; 6023 6024 /* Gracefully handle multiple VDBs, however unlikely that is */ 6025 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL); 6026 if (!vics) 6027 return; 6028 6029 vic_index = info->vics_len; 6030 info->vics_len += len; 6031 info->vics = vics; 6032 6033 for (i = 0; i < len; i++) { 6034 u8 vic = svd_to_vic(svds[i]); 6035 6036 if (!drm_valid_cea_vic(vic)) 6037 vic = 0; 6038 6039 info->vics[vic_index++] = vic; 6040 } 6041} 6042 6043/* 6044 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB. 6045 * 6046 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed 6047 * using the VICs themselves. 6048 */ 6049static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map) 6050{ 6051 struct drm_display_info *info = &connector->display_info; 6052 struct drm_hdmi_info *hdmi = &info->hdmi; 6053 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map)); 6054 6055 for (i = 0; i < len; i++) { 6056 u8 vic = info->vics[i]; 6057 6058 if (vic && y420cmdb_map & BIT_ULL(i)) 6059 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 6060 } 6061} 6062 6063static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic) 6064{ 6065 const struct drm_display_info *info = &connector->display_info; 6066 int i; 6067 6068 if (!vic || !info->vics) 6069 return false; 6070 6071 for (i = 0; i < info->vics_len; i++) { 6072 if (info->vics[i] == vic) 6073 return true; 6074 } 6075 6076 return false; 6077} 6078 6079/* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */ 6080static void parse_cta_y420vdb(struct drm_connector *connector, 6081 const struct cea_db *db) 6082{ 6083 struct drm_display_info *info = &connector->display_info; 6084 struct drm_hdmi_info *hdmi = &info->hdmi; 6085 const u8 *svds = cea_db_data(db) + 1; 6086 int i; 6087 6088 for (i = 0; i < cea_db_payload_len(db) - 1; i++) { 6089 u8 vic = svd_to_vic(svds[i]); 6090 6091 if (!drm_valid_cea_vic(vic)) 6092 continue; 6093 6094 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 6095 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 6096 } 6097} 6098 6099static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 6100{ 6101 struct drm_display_info *info = &connector->display_info; 6102 6103 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n", 6104 connector->base.id, connector->name, db[2]); 6105 6106 if (db[2] & EDID_CEA_VCDB_QS) 6107 info->rgb_quant_range_selectable = true; 6108} 6109 6110static 6111void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 6112{ 6113 switch (max_frl_rate) { 6114 case 1: 6115 *max_lanes = 3; 6116 *max_rate_per_lane = 3; 6117 break; 6118 case 2: 6119 *max_lanes = 3; 6120 *max_rate_per_lane = 6; 6121 break; 6122 case 3: 6123 *max_lanes = 4; 6124 *max_rate_per_lane = 6; 6125 break; 6126 case 4: 6127 *max_lanes = 4; 6128 *max_rate_per_lane = 8; 6129 break; 6130 case 5: 6131 *max_lanes = 4; 6132 *max_rate_per_lane = 10; 6133 break; 6134 case 6: 6135 *max_lanes = 4; 6136 *max_rate_per_lane = 12; 6137 break; 6138 case 0: 6139 default: 6140 *max_lanes = 0; 6141 *max_rate_per_lane = 0; 6142 } 6143} 6144 6145static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 6146 const u8 *db) 6147{ 6148 u8 dc_mask; 6149 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 6150 6151 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 6152 hdmi->y420_dc_modes = dc_mask; 6153} 6154 6155static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, 6156 const u8 *hf_scds) 6157{ 6158 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 6159 6160 if (!hdmi_dsc->v_1p2) 6161 return; 6162 6163 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 6164 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 6165 6166 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 6167 hdmi_dsc->bpc_supported = 16; 6168 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 6169 hdmi_dsc->bpc_supported = 12; 6170 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 6171 hdmi_dsc->bpc_supported = 10; 6172 else 6173 /* Supports min 8 BPC if DSC 1.2 is supported*/ 6174 hdmi_dsc->bpc_supported = 8; 6175 6176 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) { 6177 u8 dsc_max_slices; 6178 u8 dsc_max_frl_rate; 6179 6180 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 6181 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 6182 &hdmi_dsc->max_frl_rate_per_lane); 6183 6184 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 6185 6186 switch (dsc_max_slices) { 6187 case 1: 6188 hdmi_dsc->max_slices = 1; 6189 hdmi_dsc->clk_per_slice = 340; 6190 break; 6191 case 2: 6192 hdmi_dsc->max_slices = 2; 6193 hdmi_dsc->clk_per_slice = 340; 6194 break; 6195 case 3: 6196 hdmi_dsc->max_slices = 4; 6197 hdmi_dsc->clk_per_slice = 340; 6198 break; 6199 case 4: 6200 hdmi_dsc->max_slices = 8; 6201 hdmi_dsc->clk_per_slice = 340; 6202 break; 6203 case 5: 6204 hdmi_dsc->max_slices = 8; 6205 hdmi_dsc->clk_per_slice = 400; 6206 break; 6207 case 6: 6208 hdmi_dsc->max_slices = 12; 6209 hdmi_dsc->clk_per_slice = 400; 6210 break; 6211 case 7: 6212 hdmi_dsc->max_slices = 16; 6213 hdmi_dsc->clk_per_slice = 400; 6214 break; 6215 case 0: 6216 default: 6217 hdmi_dsc->max_slices = 0; 6218 hdmi_dsc->clk_per_slice = 0; 6219 } 6220 } 6221 6222 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13]) 6223 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 6224} 6225 6226/* Sink Capability Data Structure */ 6227static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 6228 const u8 *hf_scds) 6229{ 6230 struct drm_display_info *info = &connector->display_info; 6231 struct drm_hdmi_info *hdmi = &info->hdmi; 6232 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 6233 int max_tmds_clock = 0; 6234 u8 max_frl_rate = 0; 6235 bool dsc_support = false; 6236 6237 info->has_hdmi_infoframe = true; 6238 6239 if (hf_scds[6] & 0x80) { 6240 hdmi->scdc.supported = true; 6241 if (hf_scds[6] & 0x40) 6242 hdmi->scdc.read_request = true; 6243 } 6244 6245 /* 6246 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 6247 * And as per the spec, three factors confirm this: 6248 * * Availability of a HF-VSDB block in EDID (check) 6249 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 6250 * * SCDC support available (let's check) 6251 * Lets check it out. 6252 */ 6253 6254 if (hf_scds[5]) { 6255 struct drm_scdc *scdc = &hdmi->scdc; 6256 6257 /* max clock is 5000 KHz times block value */ 6258 max_tmds_clock = hf_scds[5] * 5000; 6259 6260 if (max_tmds_clock > 340000) { 6261 info->max_tmds_clock = max_tmds_clock; 6262 } 6263 6264 if (scdc->supported) { 6265 scdc->scrambling.supported = true; 6266 6267 /* Few sinks support scrambling for clocks < 340M */ 6268 if ((hf_scds[6] & 0x8)) 6269 scdc->scrambling.low_rates = true; 6270 } 6271 } 6272 6273 if (hf_scds[7]) { 6274 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 6275 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 6276 &hdmi->max_frl_rate_per_lane); 6277 } 6278 6279 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 6280 6281 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) { 6282 drm_parse_dsc_info(hdmi_dsc, hf_scds); 6283 dsc_support = true; 6284 } 6285 6286 drm_dbg_kms(connector->dev, 6287 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n", 6288 connector->base.id, connector->name, 6289 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support)); 6290} 6291 6292static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 6293 const u8 *hdmi) 6294{ 6295 struct drm_display_info *info = &connector->display_info; 6296 unsigned int dc_bpc = 0; 6297 6298 /* HDMI supports at least 8 bpc */ 6299 info->bpc = 8; 6300 6301 if (cea_db_payload_len(hdmi) < 6) 6302 return; 6303 6304 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 6305 dc_bpc = 10; 6306 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 6307 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n", 6308 connector->base.id, connector->name); 6309 } 6310 6311 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 6312 dc_bpc = 12; 6313 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 6314 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n", 6315 connector->base.id, connector->name); 6316 } 6317 6318 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 6319 dc_bpc = 16; 6320 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 6321 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n", 6322 connector->base.id, connector->name); 6323 } 6324 6325 if (dc_bpc == 0) { 6326 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n", 6327 connector->base.id, connector->name); 6328 return; 6329 } 6330 6331 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n", 6332 connector->base.id, connector->name, dc_bpc); 6333 info->bpc = dc_bpc; 6334 6335 /* YCRCB444 is optional according to spec. */ 6336 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 6337 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 6338 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n", 6339 connector->base.id, connector->name); 6340 } 6341 6342 /* 6343 * Spec says that if any deep color mode is supported at all, 6344 * then deep color 36 bit must be supported. 6345 */ 6346 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 6347 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n", 6348 connector->base.id, connector->name); 6349 } 6350} 6351 6352/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 6353static void 6354drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 6355{ 6356 struct drm_display_info *info = &connector->display_info; 6357 u8 len = cea_db_payload_len(db); 6358 6359 info->is_hdmi = true; 6360 6361 info->source_physical_address = (db[4] << 8) | db[5]; 6362 6363 if (len >= 6) 6364 info->dvi_dual = db[6] & 1; 6365 if (len >= 7) 6366 info->max_tmds_clock = db[7] * 5000; 6367 6368 /* 6369 * Try to infer whether the sink supports HDMI infoframes. 6370 * 6371 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink 6372 * supports infoframes if HDMI_Video_present is set. 6373 */ 6374 if (len >= 8 && db[8] & BIT(5)) 6375 info->has_hdmi_infoframe = true; 6376 6377 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n", 6378 connector->base.id, connector->name, 6379 info->dvi_dual, info->max_tmds_clock); 6380 6381 drm_parse_hdmi_deep_color_info(connector, db); 6382} 6383 6384/* 6385 * See EDID extension for head-mounted and specialized monitors, specified at: 6386 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 6387 */ 6388static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 6389 const u8 *db) 6390{ 6391 struct drm_display_info *info = &connector->display_info; 6392 u8 version = db[4]; 6393 bool desktop_usage = db[5] & BIT(6); 6394 6395 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 6396 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 6397 info->non_desktop = true; 6398 6399 drm_dbg_kms(connector->dev, 6400 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n", 6401 connector->base.id, connector->name, version, db[5]); 6402} 6403 6404static void drm_parse_cea_ext(struct drm_connector *connector, 6405 const struct drm_edid *drm_edid) 6406{ 6407 struct drm_display_info *info = &connector->display_info; 6408 struct drm_edid_iter edid_iter; 6409 const struct cea_db *db; 6410 struct cea_db_iter iter; 6411 const u8 *edid_ext; 6412 u64 y420cmdb_map = 0; 6413 6414 drm_edid_iter_begin(drm_edid, &edid_iter); 6415 drm_edid_iter_for_each(edid_ext, &edid_iter) { 6416 if (edid_ext[0] != CEA_EXT) 6417 continue; 6418 6419 if (!info->cea_rev) 6420 info->cea_rev = edid_ext[1]; 6421 6422 if (info->cea_rev != edid_ext[1]) 6423 drm_dbg_kms(connector->dev, 6424 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n", 6425 connector->base.id, connector->name, 6426 info->cea_rev, edid_ext[1]); 6427 6428 /* The existence of a CTA extension should imply RGB support */ 6429 info->color_formats = DRM_COLOR_FORMAT_RGB444; 6430 if (edid_ext[3] & EDID_CEA_YCRCB444) 6431 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6432 if (edid_ext[3] & EDID_CEA_YCRCB422) 6433 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6434 if (edid_ext[3] & EDID_BASIC_AUDIO) 6435 info->has_audio = true; 6436 6437 } 6438 drm_edid_iter_end(&edid_iter); 6439 6440 cea_db_iter_edid_begin(drm_edid, &iter); 6441 cea_db_iter_for_each(db, &iter) { 6442 /* FIXME: convert parsers to use struct cea_db */ 6443 const u8 *data = (const u8 *)db; 6444 6445 if (cea_db_is_hdmi_vsdb(db)) 6446 drm_parse_hdmi_vsdb_video(connector, data); 6447 else if (cea_db_is_hdmi_forum_vsdb(db) || 6448 cea_db_is_hdmi_forum_scdb(db)) 6449 drm_parse_hdmi_forum_scds(connector, data); 6450 else if (cea_db_is_microsoft_vsdb(db)) 6451 drm_parse_microsoft_vsdb(connector, data); 6452 else if (cea_db_is_y420cmdb(db)) 6453 parse_cta_y420cmdb(connector, db, &y420cmdb_map); 6454 else if (cea_db_is_y420vdb(db)) 6455 parse_cta_y420vdb(connector, db); 6456 else if (cea_db_is_vcdb(db)) 6457 drm_parse_vcdb(connector, data); 6458 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 6459 drm_parse_hdr_metadata_block(connector, data); 6460 else if (cea_db_tag(db) == CTA_DB_VIDEO) 6461 parse_cta_vdb(connector, db); 6462 else if (cea_db_tag(db) == CTA_DB_AUDIO) 6463 info->has_audio = true; 6464 } 6465 cea_db_iter_end(&iter); 6466 6467 if (y420cmdb_map) 6468 update_cta_y420cmdb(connector, y420cmdb_map); 6469} 6470 6471static 6472void get_monitor_range(const struct detailed_timing *timing, void *c) 6473{ 6474 struct detailed_mode_closure *closure = c; 6475 struct drm_display_info *info = &closure->connector->display_info; 6476 struct drm_monitor_range_info *monitor_range = &info->monitor_range; 6477 const struct detailed_non_pixel *data = &timing->data.other_data; 6478 const struct detailed_data_monitor_range *range = &data->data.range; 6479 const struct edid *edid = closure->drm_edid->edid; 6480 6481 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 6482 return; 6483 6484 /* 6485 * These limits are used to determine the VRR refresh 6486 * rate range. Only the "range limits only" variant 6487 * of the range descriptor seems to guarantee that 6488 * any and all timings are accepted by the sink, as 6489 * opposed to just timings conforming to the indicated 6490 * formula (GTF/GTF2/CVT). Thus other variants of the 6491 * range descriptor are not accepted here. 6492 */ 6493 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 6494 return; 6495 6496 monitor_range->min_vfreq = range->min_vfreq; 6497 monitor_range->max_vfreq = range->max_vfreq; 6498 6499 if (edid->revision >= 4) { 6500 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 6501 monitor_range->min_vfreq += 255; 6502 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 6503 monitor_range->max_vfreq += 255; 6504 } 6505} 6506 6507static void drm_get_monitor_range(struct drm_connector *connector, 6508 const struct drm_edid *drm_edid) 6509{ 6510 const struct drm_display_info *info = &connector->display_info; 6511 struct detailed_mode_closure closure = { 6512 .connector = connector, 6513 .drm_edid = drm_edid, 6514 }; 6515 6516 if (drm_edid->edid->revision < 4) 6517 return; 6518 6519 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)) 6520 return; 6521 6522 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); 6523 6524 drm_dbg_kms(connector->dev, 6525 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 6526 connector->base.id, connector->name, 6527 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq); 6528} 6529 6530static void drm_parse_vesa_mso_data(struct drm_connector *connector, 6531 const struct displayid_block *block) 6532{ 6533 struct displayid_vesa_vendor_specific_block *vesa = 6534 (struct displayid_vesa_vendor_specific_block *)block; 6535 struct drm_display_info *info = &connector->display_info; 6536 6537 if (block->num_bytes < 3) { 6538 drm_dbg_kms(connector->dev, 6539 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n", 6540 connector->base.id, connector->name, block->num_bytes); 6541 return; 6542 } 6543 6544 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 6545 return; 6546 6547 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 6548 drm_dbg_kms(connector->dev, 6549 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", 6550 connector->base.id, connector->name); 6551 return; 6552 } 6553 6554 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 6555 default: 6556 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n", 6557 connector->base.id, connector->name); 6558 fallthrough; 6559 case 0: 6560 info->mso_stream_count = 0; 6561 break; 6562 case 1: 6563 info->mso_stream_count = 2; /* 2 or 4 links */ 6564 break; 6565 case 2: 6566 info->mso_stream_count = 4; /* 4 links */ 6567 break; 6568 } 6569 6570 if (!info->mso_stream_count) { 6571 info->mso_pixel_overlap = 0; 6572 return; 6573 } 6574 6575 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 6576 if (info->mso_pixel_overlap > 8) { 6577 drm_dbg_kms(connector->dev, 6578 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", 6579 connector->base.id, connector->name, 6580 info->mso_pixel_overlap); 6581 info->mso_pixel_overlap = 8; 6582 } 6583 6584 drm_dbg_kms(connector->dev, 6585 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", 6586 connector->base.id, connector->name, 6587 info->mso_stream_count, info->mso_pixel_overlap); 6588} 6589 6590static void drm_update_mso(struct drm_connector *connector, 6591 const struct drm_edid *drm_edid) 6592{ 6593 const struct displayid_block *block; 6594 struct displayid_iter iter; 6595 6596 displayid_iter_edid_begin(drm_edid, &iter); 6597 displayid_iter_for_each(block, &iter) { 6598 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 6599 drm_parse_vesa_mso_data(connector, block); 6600 } 6601 displayid_iter_end(&iter); 6602} 6603 6604/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 6605 * all of the values which would have been set from EDID 6606 */ 6607static void drm_reset_display_info(struct drm_connector *connector) 6608{ 6609 struct drm_display_info *info = &connector->display_info; 6610 6611 info->width_mm = 0; 6612 info->height_mm = 0; 6613 6614 info->bpc = 0; 6615 info->color_formats = 0; 6616 info->cea_rev = 0; 6617 info->max_tmds_clock = 0; 6618 info->dvi_dual = false; 6619 info->is_hdmi = false; 6620 info->has_audio = false; 6621 info->has_hdmi_infoframe = false; 6622 info->rgb_quant_range_selectable = false; 6623 memset(&info->hdmi, 0, sizeof(info->hdmi)); 6624 memset(&info->hdr_sink_metadata, 0, sizeof(info->hdr_sink_metadata)); 6625 6626 info->edid_hdmi_rgb444_dc_modes = 0; 6627 info->edid_hdmi_ycbcr444_dc_modes = 0; 6628 6629 info->non_desktop = 0; 6630 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 6631 memset(&info->luminance_range, 0, sizeof(info->luminance_range)); 6632 6633 info->mso_stream_count = 0; 6634 info->mso_pixel_overlap = 0; 6635 info->max_dsc_bpp = 0; 6636 6637 kfree(info->vics); 6638 info->vics = NULL; 6639 info->vics_len = 0; 6640 6641 info->quirks = 0; 6642 6643 info->source_physical_address = CEC_PHYS_ADDR_INVALID; 6644} 6645 6646static void update_displayid_info(struct drm_connector *connector, 6647 const struct drm_edid *drm_edid) 6648{ 6649 struct drm_display_info *info = &connector->display_info; 6650 const struct displayid_block *block; 6651 struct displayid_iter iter; 6652 6653 displayid_iter_edid_begin(drm_edid, &iter); 6654 displayid_iter_for_each(block, &iter) { 6655 drm_dbg_kms(connector->dev, 6656 "[CONNECTOR:%d:%s] DisplayID extension version 0x%02x, primary use 0x%02x\n", 6657 connector->base.id, connector->name, 6658 displayid_version(&iter), 6659 displayid_primary_use(&iter)); 6660 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 && 6661 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR || 6662 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR)) 6663 info->non_desktop = true; 6664 6665 /* 6666 * We're only interested in the base section here, no need to 6667 * iterate further. 6668 */ 6669 break; 6670 } 6671 displayid_iter_end(&iter); 6672} 6673 6674static void update_display_info(struct drm_connector *connector, 6675 const struct drm_edid *drm_edid) 6676{ 6677 struct drm_display_info *info = &connector->display_info; 6678 const struct edid *edid; 6679 6680 drm_reset_display_info(connector); 6681 clear_eld(connector); 6682 6683 if (!drm_edid) 6684 return; 6685 6686 edid = drm_edid->edid; 6687 6688 info->quirks = edid_get_quirks(drm_edid); 6689 6690 info->width_mm = edid->width_cm * 10; 6691 info->height_mm = edid->height_cm * 10; 6692 6693 drm_get_monitor_range(connector, drm_edid); 6694 6695 if (edid->revision < 3) 6696 goto out; 6697 6698 if (!drm_edid_is_digital(drm_edid)) 6699 goto out; 6700 6701 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 6702 drm_parse_cea_ext(connector, drm_edid); 6703 6704 update_displayid_info(connector, drm_edid); 6705 6706 /* 6707 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 6708 * 6709 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 6710 * tells us to assume 8 bpc color depth if the EDID doesn't have 6711 * extensions which tell otherwise. 6712 */ 6713 if (info->bpc == 0 && edid->revision == 3 && 6714 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 6715 info->bpc = 8; 6716 drm_dbg_kms(connector->dev, 6717 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n", 6718 connector->base.id, connector->name, info->bpc); 6719 } 6720 6721 /* Only defined for 1.4 with digital displays */ 6722 if (edid->revision < 4) 6723 goto out; 6724 6725 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6726 case DRM_EDID_DIGITAL_DEPTH_6: 6727 info->bpc = 6; 6728 break; 6729 case DRM_EDID_DIGITAL_DEPTH_8: 6730 info->bpc = 8; 6731 break; 6732 case DRM_EDID_DIGITAL_DEPTH_10: 6733 info->bpc = 10; 6734 break; 6735 case DRM_EDID_DIGITAL_DEPTH_12: 6736 info->bpc = 12; 6737 break; 6738 case DRM_EDID_DIGITAL_DEPTH_14: 6739 info->bpc = 14; 6740 break; 6741 case DRM_EDID_DIGITAL_DEPTH_16: 6742 info->bpc = 16; 6743 break; 6744 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6745 default: 6746 info->bpc = 0; 6747 break; 6748 } 6749 6750 drm_dbg_kms(connector->dev, 6751 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6752 connector->base.id, connector->name, info->bpc); 6753 6754 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6755 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6756 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6757 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6758 6759 drm_update_mso(connector, drm_edid); 6760 6761out: 6762 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_NON_DESKTOP)) { 6763 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n", 6764 connector->base.id, connector->name, 6765 info->non_desktop ? " (redundant quirk)" : ""); 6766 info->non_desktop = true; 6767 } 6768 6769 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_CAP_DSC_15BPP)) 6770 info->max_dsc_bpp = 15; 6771 6772 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_6BPC)) 6773 info->bpc = 6; 6774 6775 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_8BPC)) 6776 info->bpc = 8; 6777 6778 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_10BPC)) 6779 info->bpc = 10; 6780 6781 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_FORCE_12BPC)) 6782 info->bpc = 12; 6783 6784 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */ 6785 drm_edid_to_eld(connector, drm_edid); 6786} 6787 6788static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6789 const struct displayid_detailed_timings_1 *timings, 6790 bool type_7) 6791{ 6792 struct drm_display_mode *mode; 6793 unsigned int pixel_clock = (timings->pixel_clock[0] | 6794 (timings->pixel_clock[1] << 8) | 6795 (timings->pixel_clock[2] << 16)) + 1; 6796 unsigned int hactive = le16_to_cpu(timings->hactive) + 1; 6797 unsigned int hblank = le16_to_cpu(timings->hblank) + 1; 6798 unsigned int hsync = (le16_to_cpu(timings->hsync) & 0x7fff) + 1; 6799 unsigned int hsync_width = le16_to_cpu(timings->hsw) + 1; 6800 unsigned int vactive = le16_to_cpu(timings->vactive) + 1; 6801 unsigned int vblank = le16_to_cpu(timings->vblank) + 1; 6802 unsigned int vsync = (le16_to_cpu(timings->vsync) & 0x7fff) + 1; 6803 unsigned int vsync_width = le16_to_cpu(timings->vsw) + 1; 6804 bool hsync_positive = le16_to_cpu(timings->hsync) & (1 << 15); 6805 bool vsync_positive = le16_to_cpu(timings->vsync) & (1 << 15); 6806 6807 mode = drm_mode_create(dev); 6808 if (!mode) 6809 return NULL; 6810 6811 /* resolution is kHz for type VII, and 10 kHz for type I */ 6812 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6813 mode->hdisplay = hactive; 6814 mode->hsync_start = mode->hdisplay + hsync; 6815 mode->hsync_end = mode->hsync_start + hsync_width; 6816 mode->htotal = mode->hdisplay + hblank; 6817 6818 mode->vdisplay = vactive; 6819 mode->vsync_start = mode->vdisplay + vsync; 6820 mode->vsync_end = mode->vsync_start + vsync_width; 6821 mode->vtotal = mode->vdisplay + vblank; 6822 6823 mode->flags = 0; 6824 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6825 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6826 mode->type = DRM_MODE_TYPE_DRIVER; 6827 6828 if (timings->flags & 0x80) 6829 mode->type |= DRM_MODE_TYPE_PREFERRED; 6830 drm_mode_set_name(mode); 6831 6832 return mode; 6833} 6834 6835static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6836 const struct displayid_block *block) 6837{ 6838 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6839 int i; 6840 int num_timings; 6841 struct drm_display_mode *newmode; 6842 int num_modes = 0; 6843 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6844 /* blocks must be multiple of 20 bytes length */ 6845 if (block->num_bytes % 20) 6846 return 0; 6847 6848 num_timings = block->num_bytes / 20; 6849 for (i = 0; i < num_timings; i++) { 6850 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6851 6852 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6853 if (!newmode) 6854 continue; 6855 6856 drm_mode_probed_add(connector, newmode); 6857 num_modes++; 6858 } 6859 return num_modes; 6860} 6861 6862static struct drm_display_mode *drm_mode_displayid_formula(struct drm_device *dev, 6863 const struct displayid_formula_timings_9 *timings, 6864 bool type_10) 6865{ 6866 struct drm_display_mode *mode; 6867 u16 hactive = le16_to_cpu(timings->hactive) + 1; 6868 u16 vactive = le16_to_cpu(timings->vactive) + 1; 6869 u8 timing_formula = timings->flags & 0x7; 6870 6871 /* TODO: support RB-v2 & RB-v3 */ 6872 if (timing_formula > 1) 6873 return NULL; 6874 6875 /* TODO: support video-optimized refresh rate */ 6876 if (timings->flags & (1 << 4)) 6877 drm_dbg_kms(dev, "Fractional vrefresh is not implemented, proceeding with non-video-optimized refresh rate"); 6878 6879 mode = drm_cvt_mode(dev, hactive, vactive, timings->vrefresh + 1, timing_formula == 1, false, false); 6880 if (!mode) 6881 return NULL; 6882 6883 /* TODO: interpret S3D flags */ 6884 6885 mode->type = DRM_MODE_TYPE_DRIVER; 6886 drm_mode_set_name(mode); 6887 6888 return mode; 6889} 6890 6891static int add_displayid_formula_modes(struct drm_connector *connector, 6892 const struct displayid_block *block) 6893{ 6894 const struct displayid_formula_timing_block *formula_block = (struct displayid_formula_timing_block *)block; 6895 int num_timings; 6896 struct drm_display_mode *newmode; 6897 int num_modes = 0; 6898 bool type_10 = block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING; 6899 int timing_size = 6 + ((formula_block->base.rev & 0x70) >> 4); 6900 6901 /* extended blocks are not supported yet */ 6902 if (timing_size != 6) 6903 return 0; 6904 6905 if (block->num_bytes % timing_size) 6906 return 0; 6907 6908 num_timings = block->num_bytes / timing_size; 6909 for (int i = 0; i < num_timings; i++) { 6910 const struct displayid_formula_timings_9 *timings = &formula_block->timings[i]; 6911 6912 newmode = drm_mode_displayid_formula(connector->dev, timings, type_10); 6913 if (!newmode) 6914 continue; 6915 6916 drm_mode_probed_add(connector, newmode); 6917 num_modes++; 6918 } 6919 return num_modes; 6920} 6921 6922static int add_displayid_detailed_modes(struct drm_connector *connector, 6923 const struct drm_edid *drm_edid) 6924{ 6925 const struct displayid_block *block; 6926 struct displayid_iter iter; 6927 int num_modes = 0; 6928 6929 displayid_iter_edid_begin(drm_edid, &iter); 6930 displayid_iter_for_each(block, &iter) { 6931 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 6932 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 6933 num_modes += add_displayid_detailed_1_modes(connector, block); 6934 else if (block->tag == DATA_BLOCK_2_TYPE_9_FORMULA_TIMING || 6935 block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING) 6936 num_modes += add_displayid_formula_modes(connector, block); 6937 } 6938 displayid_iter_end(&iter); 6939 6940 return num_modes; 6941} 6942 6943static int _drm_edid_connector_add_modes(struct drm_connector *connector, 6944 const struct drm_edid *drm_edid) 6945{ 6946 int num_modes = 0; 6947 6948 if (!drm_edid) 6949 return 0; 6950 6951 /* 6952 * EDID spec says modes should be preferred in this order: 6953 * - preferred detailed mode 6954 * - other detailed modes from base block 6955 * - detailed modes from extension blocks 6956 * - CVT 3-byte code modes 6957 * - standard timing codes 6958 * - established timing codes 6959 * - modes inferred from GTF or CVT range information 6960 * 6961 * We get this pretty much right. 6962 * 6963 * XXX order for additional mode types in extension blocks? 6964 */ 6965 num_modes += add_detailed_modes(connector, drm_edid); 6966 num_modes += add_cvt_modes(connector, drm_edid); 6967 num_modes += add_standard_modes(connector, drm_edid); 6968 num_modes += add_established_modes(connector, drm_edid); 6969 num_modes += add_cea_modes(connector, drm_edid); 6970 num_modes += add_alternate_cea_modes(connector, drm_edid); 6971 num_modes += add_displayid_detailed_modes(connector, drm_edid); 6972 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) 6973 num_modes += add_inferred_modes(connector, drm_edid); 6974 6975 if (drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_60) || 6976 drm_edid_has_internal_quirk(connector, EDID_QUIRK_PREFER_LARGE_75)) 6977 edid_fixup_preferred(connector); 6978 6979 return num_modes; 6980} 6981 6982static void _drm_update_tile_info(struct drm_connector *connector, 6983 const struct drm_edid *drm_edid); 6984 6985static int _drm_edid_connector_property_update(struct drm_connector *connector, 6986 const struct drm_edid *drm_edid) 6987{ 6988 struct drm_device *dev = connector->dev; 6989 int ret; 6990 6991 if (connector->edid_blob_ptr) { 6992 const void *old_edid = connector->edid_blob_ptr->data; 6993 size_t old_edid_size = connector->edid_blob_ptr->length; 6994 6995 if (old_edid && !drm_edid_eq(drm_edid, old_edid, old_edid_size)) { 6996 connector->epoch_counter++; 6997 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n", 6998 connector->base.id, connector->name, 6999 connector->epoch_counter); 7000 } 7001 } 7002 7003 ret = drm_property_replace_global_blob(dev, 7004 &connector->edid_blob_ptr, 7005 drm_edid ? drm_edid->size : 0, 7006 drm_edid ? drm_edid->edid : NULL, 7007 &connector->base, 7008 dev->mode_config.edid_property); 7009 if (ret) { 7010 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n", 7011 connector->base.id, connector->name, ret); 7012 goto out; 7013 } 7014 7015 ret = drm_object_property_set_value(&connector->base, 7016 dev->mode_config.non_desktop_property, 7017 connector->display_info.non_desktop); 7018 if (ret) { 7019 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n", 7020 connector->base.id, connector->name, ret); 7021 goto out; 7022 } 7023 7024 ret = drm_connector_set_tile_property(connector); 7025 if (ret) { 7026 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n", 7027 connector->base.id, connector->name, ret); 7028 goto out; 7029 } 7030 7031out: 7032 return ret; 7033} 7034 7035/* For sysfs edid show implementation */ 7036ssize_t drm_edid_connector_property_show(struct drm_connector *connector, 7037 char *buf, loff_t off, size_t count) 7038{ 7039 const void *edid; 7040 size_t size; 7041 ssize_t ret = 0; 7042 7043 mutex_lock(&connector->dev->mode_config.mutex); 7044 7045 if (!connector->edid_blob_ptr) 7046 goto unlock; 7047 7048 edid = connector->edid_blob_ptr->data; 7049 size = connector->edid_blob_ptr->length; 7050 if (!edid) 7051 goto unlock; 7052 7053 if (off >= size) 7054 goto unlock; 7055 7056 if (off + count > size) 7057 count = size - off; 7058 7059 memcpy(buf, edid + off, count); 7060 7061 ret = count; 7062unlock: 7063 mutex_unlock(&connector->dev->mode_config.mutex); 7064 7065 return ret; 7066} 7067 7068/** 7069 * drm_edid_connector_update - Update connector information from EDID 7070 * @connector: Connector 7071 * @drm_edid: EDID 7072 * 7073 * Update the connector display info, ELD, HDR metadata, relevant properties, 7074 * etc. from the passed in EDID. 7075 * 7076 * If EDID is NULL, reset the information. 7077 * 7078 * Must be called before calling drm_edid_connector_add_modes(). 7079 * 7080 * Return: 0 on success, negative error on errors. 7081 */ 7082int drm_edid_connector_update(struct drm_connector *connector, 7083 const struct drm_edid *drm_edid) 7084{ 7085 update_display_info(connector, drm_edid); 7086 7087 _drm_update_tile_info(connector, drm_edid); 7088 7089 return _drm_edid_connector_property_update(connector, drm_edid); 7090} 7091EXPORT_SYMBOL(drm_edid_connector_update); 7092 7093/** 7094 * drm_edid_connector_add_modes - Update probed modes from the EDID property 7095 * @connector: Connector 7096 * 7097 * Add the modes from the previously updated EDID property to the connector 7098 * probed modes list. 7099 * 7100 * drm_edid_connector_update() must have been called before this to update the 7101 * EDID property. 7102 * 7103 * Return: The number of modes added, or 0 if we couldn't find any. 7104 */ 7105int drm_edid_connector_add_modes(struct drm_connector *connector) 7106{ 7107 const struct drm_edid *drm_edid = NULL; 7108 int count; 7109 7110 if (connector->edid_blob_ptr) 7111 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data, 7112 connector->edid_blob_ptr->length); 7113 7114 count = _drm_edid_connector_add_modes(connector, drm_edid); 7115 7116 drm_edid_free(drm_edid); 7117 7118 return count; 7119} 7120EXPORT_SYMBOL(drm_edid_connector_add_modes); 7121 7122/** 7123 * drm_connector_update_edid_property - update the edid property of a connector 7124 * @connector: drm connector 7125 * @edid: new value of the edid property 7126 * 7127 * This function creates a new blob modeset object and assigns its id to the 7128 * connector's edid property. 7129 * Since we also parse tile information from EDID's displayID block, we also 7130 * set the connector's tile property here. See drm_connector_set_tile_property() 7131 * for more details. 7132 * 7133 * This function is deprecated. Use drm_edid_connector_update() instead. 7134 * 7135 * Returns: 7136 * Zero on success, negative errno on failure. 7137 */ 7138int drm_connector_update_edid_property(struct drm_connector *connector, 7139 const struct edid *edid) 7140{ 7141 struct drm_edid drm_edid; 7142 7143 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid)); 7144} 7145EXPORT_SYMBOL(drm_connector_update_edid_property); 7146 7147/** 7148 * drm_add_edid_modes - add modes from EDID data, if available 7149 * @connector: connector we're probing 7150 * @edid: EDID data 7151 * 7152 * Add the specified modes to the connector's mode list. Also fills out the 7153 * &drm_display_info structure and ELD in @connector with any information which 7154 * can be derived from the edid. 7155 * 7156 * This function is deprecated. Use drm_edid_connector_add_modes() instead. 7157 * 7158 * Return: The number of modes added or 0 if we couldn't find any. 7159 */ 7160int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 7161{ 7162 struct drm_edid _drm_edid; 7163 const struct drm_edid *drm_edid; 7164 7165 if (edid && !drm_edid_is_valid(edid)) { 7166 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n", 7167 connector->base.id, connector->name); 7168 edid = NULL; 7169 } 7170 7171 drm_edid = drm_edid_legacy_init(&_drm_edid, edid); 7172 7173 update_display_info(connector, drm_edid); 7174 7175 return _drm_edid_connector_add_modes(connector, drm_edid); 7176} 7177EXPORT_SYMBOL(drm_add_edid_modes); 7178 7179/** 7180 * drm_add_modes_noedid - add modes for the connectors without EDID 7181 * @connector: connector we're probing 7182 * @hdisplay: the horizontal display limit 7183 * @vdisplay: the vertical display limit 7184 * 7185 * Add the specified modes to the connector's mode list. Only when the 7186 * hdisplay/vdisplay is not beyond the given limit, it will be added. 7187 * 7188 * Return: The number of modes added or 0 if we couldn't find any. 7189 */ 7190int drm_add_modes_noedid(struct drm_connector *connector, 7191 unsigned int hdisplay, unsigned int vdisplay) 7192{ 7193 int i, count = ARRAY_SIZE(drm_dmt_modes), num_modes = 0; 7194 struct drm_display_mode *mode; 7195 struct drm_device *dev = connector->dev; 7196 7197 for (i = 0; i < count; i++) { 7198 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 7199 7200 if (hdisplay && vdisplay) { 7201 /* 7202 * Only when two are valid, they will be used to check 7203 * whether the mode should be added to the mode list of 7204 * the connector. 7205 */ 7206 if (ptr->hdisplay > hdisplay || 7207 ptr->vdisplay > vdisplay) 7208 continue; 7209 } 7210 if (drm_mode_vrefresh(ptr) > 61) 7211 continue; 7212 mode = drm_mode_duplicate(dev, ptr); 7213 if (mode) { 7214 drm_mode_probed_add(connector, mode); 7215 num_modes++; 7216 } 7217 } 7218 return num_modes; 7219} 7220EXPORT_SYMBOL(drm_add_modes_noedid); 7221 7222static bool is_hdmi2_sink(const struct drm_connector *connector) 7223{ 7224 /* 7225 * FIXME: sil-sii8620 doesn't have a connector around when 7226 * we need one, so we have to be prepared for a NULL connector. 7227 */ 7228 if (!connector) 7229 return true; 7230 7231 return connector->display_info.hdmi.scdc.supported || 7232 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 7233} 7234 7235static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 7236 const struct drm_display_mode *mode) 7237{ 7238 bool has_hdmi_infoframe = connector ? 7239 connector->display_info.has_hdmi_infoframe : false; 7240 7241 if (!has_hdmi_infoframe) 7242 return 0; 7243 7244 /* No HDMI VIC when signalling 3D video format */ 7245 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 7246 return 0; 7247 7248 return drm_match_hdmi_mode(mode); 7249} 7250 7251static u8 drm_mode_cea_vic(const struct drm_connector *connector, 7252 const struct drm_display_mode *mode) 7253{ 7254 /* 7255 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 7256 * we should send its VIC in vendor infoframes, else send the 7257 * VIC in AVI infoframes. Lets check if this mode is present in 7258 * HDMI 1.4b 4K modes 7259 */ 7260 if (drm_mode_hdmi_vic(connector, mode)) 7261 return 0; 7262 7263 return drm_match_cea_mode(mode); 7264} 7265 7266/* 7267 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that 7268 * conform to HDMI 1.4. 7269 * 7270 * HDMI 1.4 (CTA-861-D) VIC range: [1..64] 7271 * HDMI 2.0 (CTA-861-F) VIC range: [1..107] 7272 * 7273 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI 7274 * version. 7275 */ 7276static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic) 7277{ 7278 if (!is_hdmi2_sink(connector) && vic > 64 && 7279 !cta_vdb_has_vic(connector, vic)) 7280 return 0; 7281 7282 return vic; 7283} 7284 7285/** 7286 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 7287 * data from a DRM display mode 7288 * @frame: HDMI AVI infoframe 7289 * @connector: the connector 7290 * @mode: DRM display mode 7291 * 7292 * Return: 0 on success or a negative error code on failure. 7293 */ 7294int 7295drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 7296 const struct drm_connector *connector, 7297 const struct drm_display_mode *mode) 7298{ 7299 enum hdmi_picture_aspect picture_aspect; 7300 u8 vic, hdmi_vic; 7301 7302 if (!frame || !mode) 7303 return -EINVAL; 7304 7305 hdmi_avi_infoframe_init(frame); 7306 7307 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 7308 frame->pixel_repeat = 1; 7309 7310 vic = drm_mode_cea_vic(connector, mode); 7311 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 7312 7313 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7314 7315 /* 7316 * As some drivers don't support atomic, we can't use connector state. 7317 * So just initialize the frame with default values, just the same way 7318 * as it's done with other properties here. 7319 */ 7320 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 7321 frame->itc = 0; 7322 7323 /* 7324 * Populate picture aspect ratio from either 7325 * user input (if specified) or from the CEA/HDMI mode lists. 7326 */ 7327 picture_aspect = mode->picture_aspect_ratio; 7328 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 7329 if (vic) 7330 picture_aspect = drm_get_cea_aspect_ratio(vic); 7331 else if (hdmi_vic) 7332 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 7333 } 7334 7335 /* 7336 * The infoframe can't convey anything but none, 4:3 7337 * and 16:9, so if the user has asked for anything else 7338 * we can only satisfy it by specifying the right VIC. 7339 */ 7340 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 7341 if (vic) { 7342 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 7343 return -EINVAL; 7344 } else if (hdmi_vic) { 7345 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 7346 return -EINVAL; 7347 } else { 7348 return -EINVAL; 7349 } 7350 7351 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7352 } 7353 7354 frame->video_code = vic_for_avi_infoframe(connector, vic); 7355 frame->picture_aspect = picture_aspect; 7356 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 7357 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 7358 7359 return 0; 7360} 7361EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 7362 7363/** 7364 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 7365 * quantization range information 7366 * @frame: HDMI AVI infoframe 7367 * @connector: the connector 7368 * @mode: DRM display mode 7369 * @rgb_quant_range: RGB quantization range (Q) 7370 */ 7371void 7372drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 7373 const struct drm_connector *connector, 7374 const struct drm_display_mode *mode, 7375 enum hdmi_quantization_range rgb_quant_range) 7376{ 7377 const struct drm_display_info *info = &connector->display_info; 7378 7379 /* 7380 * CEA-861: 7381 * "A Source shall not send a non-zero Q value that does not correspond 7382 * to the default RGB Quantization Range for the transmitted Picture 7383 * unless the Sink indicates support for the Q bit in a Video 7384 * Capabilities Data Block." 7385 * 7386 * HDMI 2.0 recommends sending non-zero Q when it does match the 7387 * default RGB quantization range for the mode, even when QS=0. 7388 */ 7389 if (info->rgb_quant_range_selectable || 7390 rgb_quant_range == drm_default_rgb_quant_range(mode)) 7391 frame->quantization_range = rgb_quant_range; 7392 else 7393 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 7394 7395 /* 7396 * CEA-861-F: 7397 * "When transmitting any RGB colorimetry, the Source should set the 7398 * YQ-field to match the RGB Quantization Range being transmitted 7399 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 7400 * set YQ=1) and the Sink shall ignore the YQ-field." 7401 * 7402 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 7403 * by non-zero YQ when receiving RGB. There doesn't seem to be any 7404 * good way to tell which version of CEA-861 the sink supports, so 7405 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 7406 * on CEA-861-F. 7407 */ 7408 if (!is_hdmi2_sink(connector) || 7409 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 7410 frame->ycc_quantization_range = 7411 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 7412 else 7413 frame->ycc_quantization_range = 7414 HDMI_YCC_QUANTIZATION_RANGE_FULL; 7415} 7416EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 7417 7418static enum hdmi_3d_structure 7419s3d_structure_from_display_mode(const struct drm_display_mode *mode) 7420{ 7421 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 7422 7423 switch (layout) { 7424 case DRM_MODE_FLAG_3D_FRAME_PACKING: 7425 return HDMI_3D_STRUCTURE_FRAME_PACKING; 7426 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 7427 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 7428 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 7429 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 7430 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 7431 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 7432 case DRM_MODE_FLAG_3D_L_DEPTH: 7433 return HDMI_3D_STRUCTURE_L_DEPTH; 7434 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 7435 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 7436 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 7437 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 7438 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 7439 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 7440 default: 7441 return HDMI_3D_STRUCTURE_INVALID; 7442 } 7443} 7444 7445/** 7446 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 7447 * data from a DRM display mode 7448 * @frame: HDMI vendor infoframe 7449 * @connector: the connector 7450 * @mode: DRM display mode 7451 * 7452 * Note that there's is a need to send HDMI vendor infoframes only when using a 7453 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 7454 * function will return -EINVAL, error that can be safely ignored. 7455 * 7456 * Return: 0 on success or a negative error code on failure. 7457 */ 7458int 7459drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 7460 const struct drm_connector *connector, 7461 const struct drm_display_mode *mode) 7462{ 7463 /* 7464 * FIXME: sil-sii8620 doesn't have a connector around when 7465 * we need one, so we have to be prepared for a NULL connector. 7466 */ 7467 bool has_hdmi_infoframe = connector ? 7468 connector->display_info.has_hdmi_infoframe : false; 7469 int err; 7470 7471 if (!frame || !mode) 7472 return -EINVAL; 7473 7474 if (!has_hdmi_infoframe) 7475 return -EINVAL; 7476 7477 err = hdmi_vendor_infoframe_init(frame); 7478 if (err < 0) 7479 return err; 7480 7481 /* 7482 * Even if it's not absolutely necessary to send the infoframe 7483 * (ie.vic==0 and s3d_struct==0) we will still send it if we 7484 * know that the sink can handle it. This is based on a 7485 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 7486 * have trouble realizing that they should switch from 3D to 2D 7487 * mode if the source simply stops sending the infoframe when 7488 * it wants to switch from 3D to 2D. 7489 */ 7490 frame->vic = drm_mode_hdmi_vic(connector, mode); 7491 frame->s3d_struct = s3d_structure_from_display_mode(mode); 7492 7493 return 0; 7494} 7495EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 7496 7497static void drm_parse_tiled_block(struct drm_connector *connector, 7498 const struct displayid_block *block) 7499{ 7500 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 7501 u16 w, h; 7502 u8 tile_v_loc, tile_h_loc; 7503 u8 num_v_tile, num_h_tile; 7504 struct drm_tile_group *tg; 7505 7506 w = tile->tile_size[0] | tile->tile_size[1] << 8; 7507 h = tile->tile_size[2] | tile->tile_size[3] << 8; 7508 7509 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 7510 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 7511 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 7512 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 7513 7514 connector->has_tile = true; 7515 if (tile->tile_cap & 0x80) 7516 connector->tile_is_single_monitor = true; 7517 7518 connector->num_h_tile = num_h_tile + 1; 7519 connector->num_v_tile = num_v_tile + 1; 7520 connector->tile_h_loc = tile_h_loc; 7521 connector->tile_v_loc = tile_v_loc; 7522 connector->tile_h_size = w + 1; 7523 connector->tile_v_size = h + 1; 7524 7525 drm_dbg_kms(connector->dev, 7526 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c", 7527 connector->base.id, connector->name, 7528 tile->tile_cap, 7529 connector->tile_h_size, connector->tile_v_size, 7530 connector->num_h_tile, connector->num_v_tile, 7531 connector->tile_h_loc, connector->tile_v_loc, 7532 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 7533 7534 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 7535 if (!tg) 7536 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 7537 if (!tg) 7538 return; 7539 7540 if (connector->tile_group != tg) { 7541 /* if we haven't got a pointer, 7542 take the reference, drop ref to old tile group */ 7543 if (connector->tile_group) 7544 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7545 connector->tile_group = tg; 7546 } else { 7547 /* if same tile group, then release the ref we just took. */ 7548 drm_mode_put_tile_group(connector->dev, tg); 7549 } 7550} 7551 7552static bool displayid_is_tiled_block(const struct displayid_iter *iter, 7553 const struct displayid_block *block) 7554{ 7555 return (displayid_version(iter) < DISPLAY_ID_STRUCTURE_VER_20 && 7556 block->tag == DATA_BLOCK_TILED_DISPLAY) || 7557 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 && 7558 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY); 7559} 7560 7561static void _drm_update_tile_info(struct drm_connector *connector, 7562 const struct drm_edid *drm_edid) 7563{ 7564 const struct displayid_block *block; 7565 struct displayid_iter iter; 7566 7567 connector->has_tile = false; 7568 7569 displayid_iter_edid_begin(drm_edid, &iter); 7570 displayid_iter_for_each(block, &iter) { 7571 if (displayid_is_tiled_block(&iter, block)) 7572 drm_parse_tiled_block(connector, block); 7573 } 7574 displayid_iter_end(&iter); 7575 7576 if (!connector->has_tile && connector->tile_group) { 7577 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7578 connector->tile_group = NULL; 7579 } 7580} 7581 7582/** 7583 * drm_edid_is_digital - is digital? 7584 * @drm_edid: The EDID 7585 * 7586 * Return true if input is digital. 7587 */ 7588bool drm_edid_is_digital(const struct drm_edid *drm_edid) 7589{ 7590 return drm_edid && drm_edid->edid && 7591 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL; 7592} 7593EXPORT_SYMBOL(drm_edid_is_digital);
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