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ti-sn65dsi86.c
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linux-6.19.14/drivers/gpu/drm/bridge/ti-sn65dsi86.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf 5 */ 6 7#include <linux/atomic.h> 8#include <linux/auxiliary_bus.h> 9#include <linux/bitfield.h> 10#include <linux/bits.h> 11#include <linux/clk.h> 12#include <linux/debugfs.h> 13#include <linux/gpio/consumer.h> 14#include <linux/gpio/driver.h> 15#include <linux/i2c.h> 16#include <linux/iopoll.h> 17#include <linux/module.h> 18#include <linux/of_graph.h> 19#include <linux/pm_runtime.h> 20#include <linux/pwm.h> 21#include <linux/regmap.h> 22#include <linux/regulator/consumer.h> 23 24#include <linux/unaligned.h> 25 26#include <drm/display/drm_dp_aux_bus.h> 27#include <drm/display/drm_dp_helper.h> 28#include <drm/drm_atomic.h> 29#include <drm/drm_atomic_helper.h> 30#include <drm/drm_bridge.h> 31#include <drm/drm_bridge_connector.h> 32#include <drm/drm_edid.h> 33#include <drm/drm_mipi_dsi.h> 34#include <drm/drm_of.h> 35#include <drm/drm_print.h> 36#include <drm/drm_probe_helper.h> 37 38#define SN_DEVICE_ID_REGS 0x00 /* up to 0x07 */ 39#define SN_DEVICE_REV_REG 0x08 40#define SN_DPPLL_SRC_REG 0x0A 41#define DPPLL_CLK_SRC_DSICLK BIT(0) 42#define REFCLK_FREQ_MASK GENMASK(3, 1) 43#define REFCLK_FREQ(x) ((x) << 1) 44#define DPPLL_SRC_DP_PLL_LOCK BIT(7) 45#define SN_PLL_ENABLE_REG 0x0D 46#define SN_DSI_LANES_REG 0x10 47#define CHA_DSI_LANES_MASK GENMASK(4, 3) 48#define CHA_DSI_LANES(x) ((x) << 3) 49#define SN_DSIA_CLK_FREQ_REG 0x12 50#define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20 51#define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24 52#define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C 53#define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D 54#define CHA_HSYNC_POLARITY BIT(7) 55#define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30 56#define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31 57#define CHA_VSYNC_POLARITY BIT(7) 58#define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34 59#define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36 60#define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38 61#define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A 62#define SN_LN_ASSIGN_REG 0x59 63#define LN_ASSIGN_WIDTH 2 64#define SN_ENH_FRAME_REG 0x5A 65#define VSTREAM_ENABLE BIT(3) 66#define LN_POLRS_OFFSET 4 67#define LN_POLRS_MASK 0xf0 68#define SN_DATA_FORMAT_REG 0x5B 69#define BPP_18_RGB BIT(0) 70#define SN_HPD_DISABLE_REG 0x5C 71#define HPD_DISABLE BIT(0) 72#define HPD_DEBOUNCED_STATE BIT(4) 73#define SN_GPIO_IO_REG 0x5E 74#define SN_GPIO_INPUT_SHIFT 4 75#define SN_GPIO_OUTPUT_SHIFT 0 76#define SN_GPIO_CTRL_REG 0x5F 77#define SN_GPIO_MUX_INPUT 0 78#define SN_GPIO_MUX_OUTPUT 1 79#define SN_GPIO_MUX_SPECIAL 2 80#define SN_GPIO_MUX_MASK 0x3 81#define SN_AUX_WDATA_REG(x) (0x64 + (x)) 82#define SN_AUX_ADDR_19_16_REG 0x74 83#define SN_AUX_ADDR_15_8_REG 0x75 84#define SN_AUX_ADDR_7_0_REG 0x76 85#define SN_AUX_ADDR_MASK GENMASK(19, 0) 86#define SN_AUX_LENGTH_REG 0x77 87#define SN_AUX_CMD_REG 0x78 88#define AUX_CMD_SEND BIT(0) 89#define AUX_CMD_REQ(x) ((x) << 4) 90#define SN_AUX_RDATA_REG(x) (0x79 + (x)) 91#define SN_SSC_CONFIG_REG 0x93 92#define DP_NUM_LANES_MASK GENMASK(5, 4) 93#define DP_NUM_LANES(x) ((x) << 4) 94#define SN_DATARATE_CONFIG_REG 0x94 95#define DP_DATARATE_MASK GENMASK(7, 5) 96#define DP_DATARATE(x) ((x) << 5) 97#define SN_TRAINING_SETTING_REG 0x95 98#define SCRAMBLE_DISABLE BIT(4) 99#define SN_ML_TX_MODE_REG 0x96 100#define ML_TX_MAIN_LINK_OFF 0 101#define ML_TX_NORMAL_MODE BIT(0) 102#define SN_PWM_PRE_DIV_REG 0xA0 103#define SN_BACKLIGHT_SCALE_REG 0xA1 104#define BACKLIGHT_SCALE_MAX 0xFFFF 105#define SN_BACKLIGHT_REG 0xA3 106#define SN_PWM_EN_INV_REG 0xA5 107#define SN_PWM_INV_MASK BIT(0) 108#define SN_PWM_EN_MASK BIT(1) 109 110#define SN_IRQ_EN_REG 0xE0 111#define IRQ_EN BIT(0) 112 113#define SN_IRQ_EVENTS_EN_REG 0xE6 114#define HPD_INSERTION_EN BIT(1) 115#define HPD_REMOVAL_EN BIT(2) 116 117#define SN_AUX_CMD_STATUS_REG 0xF4 118#define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3) 119#define AUX_IRQ_STATUS_AUX_SHORT BIT(5) 120#define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6) 121#define SN_IRQ_STATUS_REG 0xF5 122#define HPD_REMOVAL_STATUS BIT(2) 123#define HPD_INSERTION_STATUS BIT(1) 124 125#define MIN_DSI_CLK_FREQ_MHZ 40 126 127/* fudge factor required to account for 8b/10b encoding */ 128#define DP_CLK_FUDGE_NUM 10 129#define DP_CLK_FUDGE_DEN 8 130 131/* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */ 132#define SN_AUX_MAX_PAYLOAD_BYTES 16 133 134#define SN_REGULATOR_SUPPLY_NUM 4 135 136#define SN_MAX_DP_LANES 4 137#define SN_NUM_GPIOS 4 138#define SN_GPIO_PHYSICAL_OFFSET 1 139 140#define SN_LINK_TRAINING_TRIES 10 141 142#define SN_PWM_GPIO_IDX 3 /* 4th GPIO */ 143 144/** 145 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver. 146 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality. 147 * @gpio_aux: AUX-bus sub device for GPIO controller functionality. 148 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality. 149 * @pwm_aux: AUX-bus sub device for PWM controller functionality. 150 * 151 * @dev: Pointer to the top level (i2c) device. 152 * @regmap: Regmap for accessing i2c. 153 * @aux: Our aux channel. 154 * @bridge: Our bridge. 155 * @connector: Our connector. 156 * @host_node: Remote DSI node. 157 * @dsi: Our MIPI DSI source. 158 * @refclk: Our reference clock. 159 * @next_bridge: The bridge on the eDP side. 160 * @enable_gpio: The GPIO we toggle to enable the bridge. 161 * @supplies: Data for bulk enabling/disabling our regulators. 162 * @dp_lanes: Count of dp_lanes we're using. 163 * @ln_assign: Value to program to the LN_ASSIGN register. 164 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG. 165 * @comms_enabled: If true then communication over the aux channel is enabled. 166 * @hpd_enabled: If true then HPD events are enabled. 167 * @comms_mutex: Protects modification of comms_enabled. 168 * @hpd_mutex: Protects modification of hpd_enabled. 169 * 170 * @gchip: If we expose our GPIOs, this is used. 171 * @gchip_output: A cache of whether we've set GPIOs to output. This 172 * serves double-duty of keeping track of the direction and 173 * also keeping track of whether we've incremented the 174 * pm_runtime reference count for this pin, which we do 175 * whenever a pin is configured as an output. This is a 176 * bitmap so we can do atomic ops on it without an extra 177 * lock so concurrent users of our 4 GPIOs don't stomp on 178 * each other's read-modify-write. 179 * 180 * @pchip: pwm_chip if the PWM is exposed. 181 * @pwm_enabled: Used to track if the PWM signal is currently enabled. 182 * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM. 183 * @pwm_refclk_freq: Cache for the reference clock input to the PWM. 184 */ 185struct ti_sn65dsi86 { 186 struct auxiliary_device *bridge_aux; 187 struct auxiliary_device *gpio_aux; 188 struct auxiliary_device *aux_aux; 189 struct auxiliary_device *pwm_aux; 190 191 struct device *dev; 192 struct regmap *regmap; 193 struct drm_dp_aux aux; 194 struct drm_bridge bridge; 195 struct drm_connector *connector; 196 struct device_node *host_node; 197 struct mipi_dsi_device *dsi; 198 struct clk *refclk; 199 struct drm_bridge *next_bridge; 200 struct gpio_desc *enable_gpio; 201 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM]; 202 int dp_lanes; 203 u8 ln_assign; 204 u8 ln_polrs; 205 bool comms_enabled; 206 bool hpd_enabled; 207 struct mutex comms_mutex; 208 struct mutex hpd_mutex; 209 210#if defined(CONFIG_OF_GPIO) 211 struct gpio_chip gchip; 212 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS); 213#endif 214#if IS_REACHABLE(CONFIG_PWM) 215 struct pwm_chip *pchip; 216 bool pwm_enabled; 217 atomic_t pwm_pin_busy; 218#endif 219 unsigned int pwm_refclk_freq; 220}; 221 222static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = { 223 { .range_min = 0, .range_max = 0xFF }, 224}; 225 226static const struct regmap_access_table ti_sn_bridge_volatile_table = { 227 .yes_ranges = ti_sn65dsi86_volatile_ranges, 228 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges), 229}; 230 231static const struct regmap_config ti_sn65dsi86_regmap_config = { 232 .reg_bits = 8, 233 .val_bits = 8, 234 .volatile_table = &ti_sn_bridge_volatile_table, 235 .cache_type = REGCACHE_NONE, 236 .max_register = 0xFF, 237}; 238 239static int ti_sn65dsi86_read_u8(struct ti_sn65dsi86 *pdata, unsigned int reg, 240 u8 *val) 241{ 242 int ret; 243 unsigned int reg_val; 244 245 ret = regmap_read(pdata->regmap, reg, ®_val); 246 if (ret) { 247 dev_err(pdata->dev, "fail to read raw reg %#x: %d\n", 248 reg, ret); 249 return ret; 250 } 251 *val = (u8)reg_val; 252 253 return 0; 254} 255 256static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata, 257 unsigned int reg, u16 *val) 258{ 259 u8 buf[2]; 260 int ret; 261 262 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 263 if (ret) 264 return ret; 265 266 *val = buf[0] | (buf[1] << 8); 267 268 return 0; 269} 270 271static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata, 272 unsigned int reg, u16 val) 273{ 274 u8 buf[2] = { val & 0xff, val >> 8 }; 275 276 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 277} 278 279static struct drm_display_mode * 280get_new_adjusted_display_mode(struct drm_bridge *bridge, 281 struct drm_atomic_state *state) 282{ 283 struct drm_connector *connector = 284 drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 285 struct drm_connector_state *conn_state = 286 drm_atomic_get_new_connector_state(state, connector); 287 struct drm_crtc_state *crtc_state = 288 drm_atomic_get_new_crtc_state(state, conn_state->crtc); 289 290 return &crtc_state->adjusted_mode; 291} 292 293static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata, 294 struct drm_atomic_state *state) 295{ 296 u32 bit_rate_khz, clk_freq_khz; 297 struct drm_display_mode *mode = 298 get_new_adjusted_display_mode(&pdata->bridge, state); 299 300 bit_rate_khz = mode->clock * 301 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 302 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2); 303 304 return clk_freq_khz; 305} 306 307/* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */ 308static const u32 ti_sn_bridge_refclk_lut[] = { 309 12000000, 310 19200000, 311 26000000, 312 27000000, 313 38400000, 314}; 315 316/* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */ 317static const u32 ti_sn_bridge_dsiclk_lut[] = { 318 468000000, 319 384000000, 320 416000000, 321 486000000, 322 460800000, 323}; 324 325static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata, 326 struct drm_atomic_state *state) 327{ 328 int i; 329 u32 refclk_rate; 330 const u32 *refclk_lut; 331 size_t refclk_lut_size; 332 333 if (pdata->refclk) { 334 refclk_rate = clk_get_rate(pdata->refclk); 335 refclk_lut = ti_sn_bridge_refclk_lut; 336 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut); 337 clk_prepare_enable(pdata->refclk); 338 } else { 339 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata, state) * 1000; 340 refclk_lut = ti_sn_bridge_dsiclk_lut; 341 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut); 342 } 343 344 /* for i equals to refclk_lut_size means default frequency */ 345 for (i = 0; i < refclk_lut_size; i++) 346 if (refclk_lut[i] == refclk_rate) 347 break; 348 349 /* avoid buffer overflow and "1" is the default rate in the datasheet. */ 350 if (i >= refclk_lut_size) 351 i = 1; 352 353 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK, 354 REFCLK_FREQ(i)); 355 356 /* 357 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG, 358 * regardless of its actual sourcing. 359 */ 360 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i]; 361} 362 363static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata, 364 struct drm_atomic_state *state) 365{ 366 mutex_lock(&pdata->comms_mutex); 367 368 /* configure bridge ref_clk */ 369 ti_sn_bridge_set_refclk_freq(pdata, state); 370 371 /* 372 * HPD on this bridge chip is a bit useless. This is an eDP bridge 373 * so the HPD is an internal signal that's only there to signal that 374 * the panel is done powering up. ...but the bridge chip debounces 375 * this signal by between 100 ms and 400 ms (depending on process, 376 * voltage, and temperate--I measured it at about 200 ms). One 377 * particular panel asserted HPD 84 ms after it was powered on meaning 378 * that we saw HPD 284 ms after power on. ...but the same panel said 379 * that instead of looking at HPD you could just hardcode a delay of 380 * 200 ms. We'll assume that the panel driver will have the hardcoded 381 * delay in its prepare and always disable HPD. 382 * 383 * For DisplayPort bridge type, we need HPD. So we use the bridge type 384 * to conditionally disable HPD. 385 * NOTE: The bridge type is set in ti_sn_bridge_probe() but enable_comms() 386 * can be called before. So for DisplayPort, HPD will be enabled once 387 * bridge type is set. We are using bridge type instead of "no-hpd" 388 * property because it is not used properly in devicetree description 389 * and hence is unreliable. 390 */ 391 392 if (pdata->bridge.type != DRM_MODE_CONNECTOR_DisplayPort) 393 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE, 394 HPD_DISABLE); 395 396 pdata->comms_enabled = true; 397 398 mutex_unlock(&pdata->comms_mutex); 399} 400 401static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata) 402{ 403 mutex_lock(&pdata->comms_mutex); 404 405 pdata->comms_enabled = false; 406 clk_disable_unprepare(pdata->refclk); 407 408 mutex_unlock(&pdata->comms_mutex); 409} 410 411static int __maybe_unused ti_sn65dsi86_resume(struct device *dev) 412{ 413 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 414 const struct i2c_client *client = to_i2c_client(pdata->dev); 415 int ret; 416 417 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 418 if (ret) { 419 DRM_ERROR("failed to enable supplies %d\n", ret); 420 return ret; 421 } 422 423 /* td2: min 100 us after regulators before enabling the GPIO */ 424 usleep_range(100, 110); 425 426 gpiod_set_value_cansleep(pdata->enable_gpio, 1); 427 428 /* 429 * After EN is deasserted and an external clock is detected, the bridge 430 * will sample GPIO3:1 to determine its frequency. The driver will 431 * overwrite this setting in ti_sn_bridge_set_refclk_freq(). But this is 432 * racy. Thus we have to wait a couple of us. According to the datasheet 433 * the GPIO lines has to be stable at least 5 us (td5) but it seems that 434 * is not enough and the refclk frequency value is still lost or 435 * overwritten by the bridge itself. Waiting for 20us seems to work. 436 */ 437 usleep_range(20, 30); 438 439 /* 440 * If we have a reference clock we can enable communication w/ the 441 * panel (including the aux channel) w/out any need for an input clock 442 * so we can do it in resume which lets us read the EDID before 443 * pre_enable(). Without a reference clock we need the MIPI reference 444 * clock so reading early doesn't work. 445 */ 446 if (pdata->refclk) 447 ti_sn65dsi86_enable_comms(pdata, NULL); 448 449 if (client->irq) { 450 ret = regmap_update_bits(pdata->regmap, SN_IRQ_EN_REG, IRQ_EN, 451 IRQ_EN); 452 if (ret) 453 dev_err(pdata->dev, "Failed to enable IRQ events: %d\n", ret); 454 } 455 456 return ret; 457} 458 459static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev) 460{ 461 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 462 int ret; 463 464 if (pdata->refclk) 465 ti_sn65dsi86_disable_comms(pdata); 466 467 gpiod_set_value_cansleep(pdata->enable_gpio, 0); 468 469 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 470 if (ret) 471 DRM_ERROR("failed to disable supplies %d\n", ret); 472 473 return ret; 474} 475 476static const struct dev_pm_ops ti_sn65dsi86_pm_ops = { 477 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL) 478 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 479 pm_runtime_force_resume) 480}; 481 482static int status_show(struct seq_file *s, void *data) 483{ 484 struct ti_sn65dsi86 *pdata = s->private; 485 unsigned int reg, val; 486 487 seq_puts(s, "STATUS REGISTERS:\n"); 488 489 pm_runtime_get_sync(pdata->dev); 490 491 /* IRQ Status Registers, see Table 31 in datasheet */ 492 for (reg = 0xf0; reg <= 0xf8; reg++) { 493 regmap_read(pdata->regmap, reg, &val); 494 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val); 495 } 496 497 pm_runtime_put_autosuspend(pdata->dev); 498 499 return 0; 500} 501DEFINE_SHOW_ATTRIBUTE(status); 502 503/* ----------------------------------------------------------------------------- 504 * Auxiliary Devices (*not* AUX) 505 */ 506 507static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata, 508 struct auxiliary_device **aux_out, 509 const char *name) 510{ 511 struct device *dev = pdata->dev; 512 const struct i2c_client *client = to_i2c_client(dev); 513 struct auxiliary_device *aux; 514 int id; 515 516 id = (client->adapter->nr << 10) | client->addr; 517 aux = __devm_auxiliary_device_create(dev, KBUILD_MODNAME, name, 518 NULL, id); 519 if (!aux) 520 return -ENODEV; 521 522 *aux_out = aux; 523 return 0; 524} 525 526/* ----------------------------------------------------------------------------- 527 * AUX Adapter 528 */ 529 530static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux) 531{ 532 return container_of(aux, struct ti_sn65dsi86, aux); 533} 534 535static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux, 536 struct drm_dp_aux_msg *msg) 537{ 538 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux); 539 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); 540 u32 request_val = AUX_CMD_REQ(msg->request); 541 u8 *buf = msg->buffer; 542 unsigned int len = msg->size; 543 unsigned int short_len; 544 unsigned int val; 545 int ret; 546 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG]; 547 548 if (len > SN_AUX_MAX_PAYLOAD_BYTES) 549 return -EINVAL; 550 551 pm_runtime_get_sync(pdata->dev); 552 mutex_lock(&pdata->comms_mutex); 553 554 /* 555 * If someone tries to do a DDC over AUX transaction before pre_enable() 556 * on a device without a dedicated reference clock then we just can't 557 * do it. Fail right away. This prevents non-refclk users from reading 558 * the EDID before enabling the panel but such is life. 559 */ 560 if (!pdata->comms_enabled) { 561 ret = -EIO; 562 goto exit; 563 } 564 565 switch (request) { 566 case DP_AUX_NATIVE_WRITE: 567 case DP_AUX_I2C_WRITE: 568 case DP_AUX_NATIVE_READ: 569 case DP_AUX_I2C_READ: 570 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val); 571 /* Assume it's good */ 572 msg->reply = 0; 573 break; 574 default: 575 ret = -EINVAL; 576 goto exit; 577 } 578 579 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32)); 580 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len, 581 addr_len); 582 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len, 583 ARRAY_SIZE(addr_len)); 584 585 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) 586 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len); 587 588 /* Clear old status bits before start so we don't get confused */ 589 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG, 590 AUX_IRQ_STATUS_NAT_I2C_FAIL | 591 AUX_IRQ_STATUS_AUX_RPLY_TOUT | 592 AUX_IRQ_STATUS_AUX_SHORT); 593 594 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND); 595 596 /* Zero delay loop because i2c transactions are slow already */ 597 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val, 598 !(val & AUX_CMD_SEND), 0, 50 * 1000); 599 if (ret) 600 goto exit; 601 602 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val); 603 if (ret) 604 goto exit; 605 606 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) { 607 /* 608 * The hardware tried the message seven times per the DP spec 609 * but it hit a timeout. We ignore defers here because they're 610 * handled in hardware. 611 */ 612 ret = -ETIMEDOUT; 613 goto exit; 614 } 615 616 if (val & AUX_IRQ_STATUS_AUX_SHORT) { 617 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &short_len); 618 len = min(len, short_len); 619 if (ret) 620 goto exit; 621 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) { 622 switch (request) { 623 case DP_AUX_I2C_WRITE: 624 case DP_AUX_I2C_READ: 625 msg->reply |= DP_AUX_I2C_REPLY_NACK; 626 break; 627 case DP_AUX_NATIVE_READ: 628 case DP_AUX_NATIVE_WRITE: 629 msg->reply |= DP_AUX_NATIVE_REPLY_NACK; 630 break; 631 } 632 len = 0; 633 goto exit; 634 } 635 636 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0) 637 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len); 638 639exit: 640 mutex_unlock(&pdata->comms_mutex); 641 pm_runtime_mark_last_busy(pdata->dev); 642 pm_runtime_put_autosuspend(pdata->dev); 643 644 if (ret) 645 return ret; 646 return len; 647} 648 649static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us) 650{ 651 /* 652 * The HPD in this chip is a bit useless (See comment in 653 * ti_sn65dsi86_enable_comms) so if our driver is expected to wait 654 * for HPD, we just assume it's asserted after the wait_us delay. 655 * 656 * In case we are asked to wait forever (wait_us=0) take conservative 657 * 500ms delay. 658 */ 659 if (wait_us == 0) 660 wait_us = 500000; 661 662 usleep_range(wait_us, wait_us + 1000); 663 664 return 0; 665} 666 667static int ti_sn_aux_probe(struct auxiliary_device *adev, 668 const struct auxiliary_device_id *id) 669{ 670 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 671 int ret; 672 673 pdata->aux.name = "ti-sn65dsi86-aux"; 674 pdata->aux.dev = &adev->dev; 675 pdata->aux.transfer = ti_sn_aux_transfer; 676 pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted; 677 drm_dp_aux_init(&pdata->aux); 678 679 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux); 680 if (ret) 681 return ret; 682 683 /* 684 * The eDP to MIPI bridge parts don't work until the AUX channel is 685 * setup so we don't add it in the main driver probe, we add it now. 686 */ 687 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge"); 688} 689 690static const struct auxiliary_device_id ti_sn_aux_id_table[] = { 691 { .name = "ti_sn65dsi86.aux", }, 692 {}, 693}; 694 695static struct auxiliary_driver ti_sn_aux_driver = { 696 .name = "aux", 697 .probe = ti_sn_aux_probe, 698 .id_table = ti_sn_aux_id_table, 699}; 700 701/*------------------------------------------------------------------------------ 702 * DRM Bridge 703 */ 704 705static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge) 706{ 707 return container_of(bridge, struct ti_sn65dsi86, bridge); 708} 709 710static int ti_sn_attach_host(struct auxiliary_device *adev, struct ti_sn65dsi86 *pdata) 711{ 712 int val; 713 struct mipi_dsi_host *host; 714 struct mipi_dsi_device *dsi; 715 struct device *dev = pdata->dev; 716 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge", 717 .channel = 0, 718 .node = NULL, 719 }; 720 721 host = of_find_mipi_dsi_host_by_node(pdata->host_node); 722 if (!host) 723 return -EPROBE_DEFER; 724 725 dsi = devm_mipi_dsi_device_register_full(&adev->dev, host, &info); 726 if (IS_ERR(dsi)) 727 return PTR_ERR(dsi); 728 729 /* TODO: setting to 4 MIPI lanes always for now */ 730 dsi->lanes = 4; 731 dsi->format = MIPI_DSI_FMT_RGB888; 732 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; 733 734 /* check if continuous dsi clock is required or not */ 735 pm_runtime_get_sync(dev); 736 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val); 737 pm_runtime_put_autosuspend(dev); 738 if (!(val & DPPLL_CLK_SRC_DSICLK)) 739 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; 740 741 pdata->dsi = dsi; 742 743 return devm_mipi_dsi_attach(&adev->dev, dsi); 744} 745 746static int ti_sn_bridge_attach(struct drm_bridge *bridge, 747 struct drm_encoder *encoder, 748 enum drm_bridge_attach_flags flags) 749{ 750 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 751 int ret; 752 753 pdata->aux.drm_dev = bridge->dev; 754 ret = drm_dp_aux_register(&pdata->aux); 755 if (ret < 0) { 756 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret); 757 return ret; 758 } 759 760 /* 761 * Attach the next bridge. 762 * We never want the next bridge to *also* create a connector. 763 */ 764 ret = drm_bridge_attach(encoder, pdata->next_bridge, 765 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); 766 if (ret < 0) 767 goto err_initted_aux; 768 769 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 770 return 0; 771 772 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev, 773 pdata->bridge.encoder); 774 if (IS_ERR(pdata->connector)) { 775 ret = PTR_ERR(pdata->connector); 776 goto err_initted_aux; 777 } 778 779 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder); 780 781 return 0; 782 783err_initted_aux: 784 drm_dp_aux_unregister(&pdata->aux); 785 return ret; 786} 787 788static void ti_sn_bridge_detach(struct drm_bridge *bridge) 789{ 790 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux); 791} 792 793static enum drm_mode_status 794ti_sn_bridge_mode_valid(struct drm_bridge *bridge, 795 const struct drm_display_info *info, 796 const struct drm_display_mode *mode) 797{ 798 /* maximum supported resolution is 4K at 60 fps */ 799 if (mode->clock > 594000) 800 return MODE_CLOCK_HIGH; 801 802 /* 803 * The front and back porch registers are 8 bits, and pulse width 804 * registers are 15 bits, so reject any modes with larger periods. 805 */ 806 807 if ((mode->hsync_start - mode->hdisplay) > 0xff) 808 return MODE_HBLANK_WIDE; 809 810 if ((mode->vsync_start - mode->vdisplay) > 0xff) 811 return MODE_VBLANK_WIDE; 812 813 if ((mode->hsync_end - mode->hsync_start) > 0x7fff) 814 return MODE_HSYNC_WIDE; 815 816 if ((mode->vsync_end - mode->vsync_start) > 0x7fff) 817 return MODE_VSYNC_WIDE; 818 819 if ((mode->htotal - mode->hsync_end) > 0xff) 820 return MODE_HBLANK_WIDE; 821 822 if ((mode->vtotal - mode->vsync_end) > 0xff) 823 return MODE_VBLANK_WIDE; 824 825 return MODE_OK; 826} 827 828static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge, 829 struct drm_atomic_state *state) 830{ 831 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 832 833 /* disable video stream */ 834 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0); 835} 836 837static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata, 838 struct drm_atomic_state *state) 839{ 840 unsigned int bit_rate_mhz, clk_freq_mhz; 841 unsigned int val; 842 struct drm_display_mode *mode = 843 get_new_adjusted_display_mode(&pdata->bridge, state); 844 845 /* set DSIA clk frequency */ 846 bit_rate_mhz = (mode->clock / 1000) * 847 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 848 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); 849 850 /* for each increment in val, frequency increases by 5MHz */ 851 val = (MIN_DSI_CLK_FREQ_MHZ / 5) + 852 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); 853 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); 854} 855 856static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector) 857{ 858 if (connector->display_info.bpc <= 6) 859 return 18; 860 else 861 return 24; 862} 863 864/* 865 * LUT index corresponds to register value and 866 * LUT values corresponds to dp data rate supported 867 * by the bridge in Mbps unit. 868 */ 869static const unsigned int ti_sn_bridge_dp_rate_lut[] = { 870 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 871}; 872 873static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata, 874 struct drm_atomic_state *state, 875 unsigned int bpp) 876{ 877 unsigned int bit_rate_khz, dp_rate_mhz; 878 unsigned int i; 879 struct drm_display_mode *mode = 880 get_new_adjusted_display_mode(&pdata->bridge, state); 881 882 /* Calculate minimum bit rate based on our pixel clock. */ 883 bit_rate_khz = mode->clock * bpp; 884 885 /* Calculate minimum DP data rate, taking 80% as per DP spec */ 886 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM, 887 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN); 888 889 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) 890 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz) 891 break; 892 893 return i; 894} 895 896static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata) 897{ 898 unsigned int valid_rates = 0; 899 unsigned int rate_per_200khz; 900 unsigned int rate_mhz; 901 u8 dpcd_val; 902 int ret; 903 int i, j; 904 905 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val); 906 if (ret != 1) { 907 DRM_DEV_ERROR(pdata->dev, 908 "Can't read eDP rev (%d), assuming 1.1\n", ret); 909 dpcd_val = DP_EDP_11; 910 } 911 912 if (dpcd_val >= DP_EDP_14) { 913 /* eDP 1.4 devices must provide a custom table */ 914 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 915 916 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES, 917 sink_rates, sizeof(sink_rates)); 918 919 if (ret != sizeof(sink_rates)) { 920 DRM_DEV_ERROR(pdata->dev, 921 "Can't read supported rate table (%d)\n", ret); 922 923 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */ 924 memset(sink_rates, 0, sizeof(sink_rates)); 925 } 926 927 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 928 rate_per_200khz = le16_to_cpu(sink_rates[i]); 929 930 if (!rate_per_200khz) 931 break; 932 933 rate_mhz = rate_per_200khz * 200 / 1000; 934 for (j = 0; 935 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 936 j++) { 937 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz) 938 valid_rates |= BIT(j); 939 } 940 } 941 942 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) { 943 if (valid_rates & BIT(i)) 944 return valid_rates; 945 } 946 DRM_DEV_ERROR(pdata->dev, 947 "No matching eDP rates in table; falling back\n"); 948 } 949 950 /* On older versions best we can do is use DP_MAX_LINK_RATE */ 951 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val); 952 if (ret != 1) { 953 DRM_DEV_ERROR(pdata->dev, 954 "Can't read max rate (%d); assuming 5.4 GHz\n", 955 ret); 956 dpcd_val = DP_LINK_BW_5_4; 957 } 958 959 switch (dpcd_val) { 960 default: 961 DRM_DEV_ERROR(pdata->dev, 962 "Unexpected max rate (%#x); assuming 5.4 GHz\n", 963 (int)dpcd_val); 964 fallthrough; 965 case DP_LINK_BW_5_4: 966 valid_rates |= BIT(7); 967 fallthrough; 968 case DP_LINK_BW_2_7: 969 valid_rates |= BIT(4); 970 fallthrough; 971 case DP_LINK_BW_1_62: 972 valid_rates |= BIT(1); 973 break; 974 } 975 976 return valid_rates; 977} 978 979static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata, 980 struct drm_atomic_state *state) 981{ 982 struct drm_display_mode *mode = 983 get_new_adjusted_display_mode(&pdata->bridge, state); 984 u8 hsync_polarity = 0, vsync_polarity = 0; 985 986 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 987 hsync_polarity = CHA_HSYNC_POLARITY; 988 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 989 vsync_polarity = CHA_VSYNC_POLARITY; 990 991 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG, 992 mode->hdisplay); 993 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG, 994 mode->vdisplay); 995 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, 996 (mode->hsync_end - mode->hsync_start) & 0xFF); 997 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, 998 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) | 999 hsync_polarity); 1000 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, 1001 (mode->vsync_end - mode->vsync_start) & 0xFF); 1002 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, 1003 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) | 1004 vsync_polarity); 1005 1006 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG, 1007 (mode->htotal - mode->hsync_end) & 0xFF); 1008 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG, 1009 (mode->vtotal - mode->vsync_end) & 0xFF); 1010 1011 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, 1012 (mode->hsync_start - mode->hdisplay) & 0xFF); 1013 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG, 1014 (mode->vsync_start - mode->vdisplay) & 0xFF); 1015 1016 usleep_range(10000, 10500); /* 10ms delay recommended by spec */ 1017} 1018 1019static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata) 1020{ 1021 u8 data; 1022 int ret; 1023 1024 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); 1025 if (ret != 1) { 1026 DRM_DEV_ERROR(pdata->dev, 1027 "Can't read lane count (%d); assuming 4\n", ret); 1028 return 4; 1029 } 1030 1031 return data & DP_LANE_COUNT_MASK; 1032} 1033 1034static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx, 1035 const char **last_err_str) 1036{ 1037 unsigned int val; 1038 int ret; 1039 int i; 1040 1041 /* set dp clk frequency value */ 1042 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, 1043 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx)); 1044 1045 /* enable DP PLL */ 1046 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); 1047 1048 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, 1049 val & DPPLL_SRC_DP_PLL_LOCK, 1000, 1050 50 * 1000); 1051 if (ret) { 1052 *last_err_str = "DP_PLL_LOCK polling failed"; 1053 goto exit; 1054 } 1055 1056 /* 1057 * We'll try to link train several times. As part of link training 1058 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If 1059 * the panel isn't ready quite it might respond NAK here which means 1060 * we need to try again. 1061 */ 1062 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) { 1063 /* Semi auto link training mode */ 1064 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); 1065 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, 1066 val == ML_TX_MAIN_LINK_OFF || 1067 val == ML_TX_NORMAL_MODE, 1000, 1068 500 * 1000); 1069 if (ret) { 1070 *last_err_str = "Training complete polling failed"; 1071 } else if (val == ML_TX_MAIN_LINK_OFF) { 1072 *last_err_str = "Link training failed, link is off"; 1073 ret = -EIO; 1074 continue; 1075 } 1076 1077 break; 1078 } 1079 1080 /* If we saw quite a few retries, add a note about it */ 1081 if (!ret && i > SN_LINK_TRAINING_TRIES / 2) 1082 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i); 1083 1084exit: 1085 /* Disable the PLL if we failed */ 1086 if (ret) 1087 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1088 1089 return ret; 1090} 1091 1092static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge, 1093 struct drm_atomic_state *state) 1094{ 1095 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1096 struct drm_connector *connector; 1097 const char *last_err_str = "No supported DP rate"; 1098 unsigned int valid_rates; 1099 int dp_rate_idx; 1100 unsigned int val; 1101 int ret = -EINVAL; 1102 int max_dp_lanes; 1103 unsigned int bpp; 1104 1105 connector = drm_atomic_get_new_connector_for_encoder(state, 1106 bridge->encoder); 1107 if (!connector) { 1108 dev_err_ratelimited(pdata->dev, "Could not get the connector\n"); 1109 return; 1110 } 1111 1112 max_dp_lanes = ti_sn_get_max_lanes(pdata); 1113 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes); 1114 1115 /* DSI_A lane config */ 1116 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes); 1117 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, 1118 CHA_DSI_LANES_MASK, val); 1119 1120 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign); 1121 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK, 1122 pdata->ln_polrs << LN_POLRS_OFFSET); 1123 1124 /* set dsi clk frequency value */ 1125 ti_sn_bridge_set_dsi_rate(pdata, state); 1126 1127 /* 1128 * The SN65DSI86 only supports ASSR Display Authentication method and 1129 * this method is enabled for eDP panels. An eDP panel must support this 1130 * authentication method. We need to enable this method in the eDP panel 1131 * at DisplayPort address 0x0010A prior to link training. 1132 * 1133 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays 1134 * we need to disable the scrambler. 1135 */ 1136 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) { 1137 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, 1138 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); 1139 1140 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1141 SCRAMBLE_DISABLE, 0); 1142 } else { 1143 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1144 SCRAMBLE_DISABLE, SCRAMBLE_DISABLE); 1145 } 1146 1147 bpp = ti_sn_bridge_get_bpp(connector); 1148 /* Set the DP output format (18 bpp or 24 bpp) */ 1149 val = bpp == 18 ? BPP_18_RGB : 0; 1150 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); 1151 1152 /* DP lane config */ 1153 val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); 1154 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 1155 val); 1156 1157 valid_rates = ti_sn_bridge_read_valid_rates(pdata); 1158 1159 /* Train until we run out of rates */ 1160 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, state, bpp); 1161 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 1162 dp_rate_idx++) { 1163 if (!(valid_rates & BIT(dp_rate_idx))) 1164 continue; 1165 1166 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str); 1167 if (!ret) 1168 break; 1169 } 1170 if (ret) { 1171 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret); 1172 return; 1173 } 1174 1175 /* config video parameters */ 1176 ti_sn_bridge_set_video_timings(pdata, state); 1177 1178 /* enable video stream */ 1179 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 1180 VSTREAM_ENABLE); 1181} 1182 1183static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge, 1184 struct drm_atomic_state *state) 1185{ 1186 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1187 1188 pm_runtime_get_sync(pdata->dev); 1189 1190 if (!pdata->refclk) 1191 ti_sn65dsi86_enable_comms(pdata, state); 1192 1193 /* td7: min 100 us after enable before DSI data */ 1194 usleep_range(100, 110); 1195} 1196 1197static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge, 1198 struct drm_atomic_state *state) 1199{ 1200 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1201 1202 /* semi auto link training mode OFF */ 1203 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); 1204 /* Num lanes to 0 as per power sequencing in data sheet */ 1205 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0); 1206 /* disable DP PLL */ 1207 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1208 1209 if (!pdata->refclk) 1210 ti_sn65dsi86_disable_comms(pdata); 1211 1212 pm_runtime_put_sync(pdata->dev); 1213} 1214 1215static enum drm_connector_status 1216ti_sn_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 1217{ 1218 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1219 int val = 0; 1220 1221 /* 1222 * Runtime reference is grabbed in ti_sn_bridge_hpd_enable() 1223 * as the chip won't report HPD just after being powered on. 1224 * HPD_DEBOUNCED_STATE reflects correct state only after the 1225 * debounce time (~100-400 ms). 1226 */ 1227 1228 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val); 1229 1230 return val & HPD_DEBOUNCED_STATE ? connector_status_connected 1231 : connector_status_disconnected; 1232} 1233 1234static const struct drm_edid *ti_sn_bridge_edid_read(struct drm_bridge *bridge, 1235 struct drm_connector *connector) 1236{ 1237 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1238 1239 return drm_edid_read_ddc(connector, &pdata->aux.ddc); 1240} 1241 1242static void ti_sn65dsi86_debugfs_init(struct drm_bridge *bridge, struct dentry *root) 1243{ 1244 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1245 struct dentry *debugfs; 1246 1247 debugfs = debugfs_create_dir(dev_name(pdata->dev), root); 1248 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops); 1249} 1250 1251static void ti_sn_bridge_hpd_enable(struct drm_bridge *bridge) 1252{ 1253 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1254 const struct i2c_client *client = to_i2c_client(pdata->dev); 1255 int ret; 1256 1257 /* 1258 * Device needs to be powered on before reading the HPD state 1259 * for reliable hpd detection in ti_sn_bridge_detect() due to 1260 * the high debounce time. 1261 */ 1262 1263 pm_runtime_get_sync(pdata->dev); 1264 1265 mutex_lock(&pdata->hpd_mutex); 1266 pdata->hpd_enabled = true; 1267 mutex_unlock(&pdata->hpd_mutex); 1268 1269 if (client->irq) { 1270 ret = regmap_set_bits(pdata->regmap, SN_IRQ_EVENTS_EN_REG, 1271 HPD_REMOVAL_EN | HPD_INSERTION_EN); 1272 if (ret) 1273 dev_err(pdata->dev, "Failed to enable HPD events: %d\n", ret); 1274 } 1275} 1276 1277static void ti_sn_bridge_hpd_disable(struct drm_bridge *bridge) 1278{ 1279 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1280 const struct i2c_client *client = to_i2c_client(pdata->dev); 1281 int ret; 1282 1283 if (client->irq) { 1284 ret = regmap_clear_bits(pdata->regmap, SN_IRQ_EVENTS_EN_REG, 1285 HPD_REMOVAL_EN | HPD_INSERTION_EN); 1286 if (ret) 1287 dev_err(pdata->dev, "Failed to disable HPD events: %d\n", ret); 1288 } 1289 1290 mutex_lock(&pdata->hpd_mutex); 1291 pdata->hpd_enabled = false; 1292 mutex_unlock(&pdata->hpd_mutex); 1293 1294 pm_runtime_put_autosuspend(pdata->dev); 1295} 1296 1297static const struct drm_bridge_funcs ti_sn_bridge_funcs = { 1298 .attach = ti_sn_bridge_attach, 1299 .detach = ti_sn_bridge_detach, 1300 .mode_valid = ti_sn_bridge_mode_valid, 1301 .edid_read = ti_sn_bridge_edid_read, 1302 .detect = ti_sn_bridge_detect, 1303 .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable, 1304 .atomic_enable = ti_sn_bridge_atomic_enable, 1305 .atomic_disable = ti_sn_bridge_atomic_disable, 1306 .atomic_post_disable = ti_sn_bridge_atomic_post_disable, 1307 .atomic_reset = drm_atomic_helper_bridge_reset, 1308 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1309 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1310 .debugfs_init = ti_sn65dsi86_debugfs_init, 1311 .hpd_enable = ti_sn_bridge_hpd_enable, 1312 .hpd_disable = ti_sn_bridge_hpd_disable, 1313}; 1314 1315static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata, 1316 struct device_node *np) 1317{ 1318 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 }; 1319 u32 lane_polarities[SN_MAX_DP_LANES] = { }; 1320 struct device_node *endpoint; 1321 u8 ln_assign = 0; 1322 u8 ln_polrs = 0; 1323 int dp_lanes; 1324 int i; 1325 1326 /* 1327 * Read config from the device tree about lane remapping and lane 1328 * polarities. These are optional and we assume identity map and 1329 * normal polarity if nothing is specified. It's OK to specify just 1330 * data-lanes but not lane-polarities but not vice versa. 1331 * 1332 * Error checking is light (we just make sure we don't crash or 1333 * buffer overrun) and we assume dts is well formed and specifying 1334 * mappings that the hardware supports. 1335 */ 1336 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1337 dp_lanes = drm_of_get_data_lanes_count(endpoint, 1, SN_MAX_DP_LANES); 1338 if (dp_lanes > 0) { 1339 of_property_read_u32_array(endpoint, "data-lanes", 1340 lane_assignments, dp_lanes); 1341 of_property_read_u32_array(endpoint, "lane-polarities", 1342 lane_polarities, dp_lanes); 1343 } else { 1344 dp_lanes = SN_MAX_DP_LANES; 1345 } 1346 of_node_put(endpoint); 1347 1348 /* 1349 * Convert into register format. Loop over all lanes even if 1350 * data-lanes had fewer elements so that we nicely initialize 1351 * the LN_ASSIGN register. 1352 */ 1353 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) { 1354 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i]; 1355 ln_polrs = ln_polrs << 1 | lane_polarities[i]; 1356 } 1357 1358 /* Stash in our struct for when we power on */ 1359 pdata->dp_lanes = dp_lanes; 1360 pdata->ln_assign = ln_assign; 1361 pdata->ln_polrs = ln_polrs; 1362} 1363 1364static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata) 1365{ 1366 struct device_node *np = pdata->dev->of_node; 1367 1368 pdata->host_node = of_graph_get_remote_node(np, 0, 0); 1369 1370 if (!pdata->host_node) { 1371 DRM_ERROR("remote dsi host node not found\n"); 1372 return -ENODEV; 1373 } 1374 1375 return 0; 1376} 1377 1378static irqreturn_t ti_sn_bridge_interrupt(int irq, void *private) 1379{ 1380 struct ti_sn65dsi86 *pdata = private; 1381 struct drm_device *dev = pdata->bridge.dev; 1382 u8 status; 1383 int ret; 1384 bool hpd_event; 1385 1386 ret = ti_sn65dsi86_read_u8(pdata, SN_IRQ_STATUS_REG, &status); 1387 if (ret) { 1388 dev_err(pdata->dev, "Failed to read IRQ status: %d\n", ret); 1389 return IRQ_NONE; 1390 } 1391 1392 hpd_event = status & (HPD_REMOVAL_STATUS | HPD_INSERTION_STATUS); 1393 1394 dev_dbg(pdata->dev, "(SN_IRQ_STATUS_REG = %#x)\n", status); 1395 if (!status) 1396 return IRQ_NONE; 1397 1398 ret = regmap_write(pdata->regmap, SN_IRQ_STATUS_REG, status); 1399 if (ret) { 1400 dev_err(pdata->dev, "Failed to clear IRQ status: %d\n", ret); 1401 return IRQ_NONE; 1402 } 1403 1404 /* Only send the HPD event if we are bound with a device. */ 1405 mutex_lock(&pdata->hpd_mutex); 1406 if (pdata->hpd_enabled && hpd_event) 1407 drm_kms_helper_hotplug_event(dev); 1408 mutex_unlock(&pdata->hpd_mutex); 1409 1410 return IRQ_HANDLED; 1411} 1412 1413static int ti_sn_bridge_probe(struct auxiliary_device *adev, 1414 const struct auxiliary_device_id *id) 1415{ 1416 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1417 struct device_node *np = pdata->dev->of_node; 1418 const struct i2c_client *client = to_i2c_client(pdata->dev); 1419 int ret; 1420 1421 pdata->next_bridge = devm_drm_of_get_bridge(&adev->dev, np, 1, 0); 1422 if (IS_ERR(pdata->next_bridge)) 1423 return dev_err_probe(&adev->dev, PTR_ERR(pdata->next_bridge), 1424 "failed to create panel bridge\n"); 1425 1426 ti_sn_bridge_parse_lanes(pdata, np); 1427 1428 ret = ti_sn_bridge_parse_dsi_host(pdata); 1429 if (ret) 1430 return ret; 1431 1432 pdata->bridge.of_node = np; 1433 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort 1434 ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP; 1435 1436 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) { 1437 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT; 1438 if (client->irq) 1439 pdata->bridge.ops |= DRM_BRIDGE_OP_HPD; 1440 /* 1441 * If comms were already enabled they would have been enabled 1442 * with the wrong value of HPD_DISABLE. Update it now. Comms 1443 * could be enabled if anyone is holding a pm_runtime reference 1444 * (like if a GPIO is in use). Note that in most cases nobody 1445 * is doing AUX channel xfers before the bridge is added so 1446 * HPD doesn't _really_ matter then. The only exception is in 1447 * the eDP case where the panel wants to read the EDID before 1448 * the bridge is added. We always consistently have HPD disabled 1449 * for eDP. 1450 */ 1451 mutex_lock(&pdata->comms_mutex); 1452 if (pdata->comms_enabled) 1453 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, 1454 HPD_DISABLE, 0); 1455 mutex_unlock(&pdata->comms_mutex); 1456 } 1457 1458 drm_bridge_add(&pdata->bridge); 1459 1460 ret = ti_sn_attach_host(adev, pdata); 1461 if (ret) { 1462 dev_err_probe(&adev->dev, ret, "failed to attach dsi host\n"); 1463 goto err_remove_bridge; 1464 } 1465 1466 return 0; 1467 1468err_remove_bridge: 1469 drm_bridge_remove(&pdata->bridge); 1470 return ret; 1471} 1472 1473static void ti_sn_bridge_remove(struct auxiliary_device *adev) 1474{ 1475 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1476 1477 if (!pdata) 1478 return; 1479 1480 drm_bridge_remove(&pdata->bridge); 1481 1482 of_node_put(pdata->host_node); 1483} 1484 1485static const struct auxiliary_device_id ti_sn_bridge_id_table[] = { 1486 { .name = "ti_sn65dsi86.bridge", }, 1487 {}, 1488}; 1489 1490static struct auxiliary_driver ti_sn_bridge_driver = { 1491 .name = "bridge", 1492 .probe = ti_sn_bridge_probe, 1493 .remove = ti_sn_bridge_remove, 1494 .id_table = ti_sn_bridge_id_table, 1495}; 1496 1497/* ----------------------------------------------------------------------------- 1498 * PWM Controller 1499 */ 1500#if IS_REACHABLE(CONFIG_PWM) 1501static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) 1502{ 1503 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0; 1504} 1505 1506static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) 1507{ 1508 atomic_set(&pdata->pwm_pin_busy, 0); 1509} 1510 1511static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip) 1512{ 1513 return pwmchip_get_drvdata(chip); 1514} 1515 1516static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 1517{ 1518 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1519 1520 return ti_sn_pwm_pin_request(pdata); 1521} 1522 1523static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 1524{ 1525 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1526 1527 ti_sn_pwm_pin_release(pdata); 1528} 1529 1530/* 1531 * Limitations: 1532 * - The PWM signal is not driven when the chip is powered down, or in its 1533 * reset state and the driver does not implement the "suspend state" 1534 * described in the documentation. In order to save power, state->enabled is 1535 * interpreted as denoting if the signal is expected to be valid, and is used 1536 * to determine if the chip needs to be kept powered. 1537 * - Changing both period and duty_cycle is not done atomically, neither is the 1538 * multi-byte register updates, so the output might briefly be undefined 1539 * during update. 1540 */ 1541static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 1542 const struct pwm_state *state) 1543{ 1544 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1545 unsigned int pwm_en_inv; 1546 unsigned int backlight; 1547 unsigned int pre_div; 1548 unsigned int scale; 1549 u64 period_max; 1550 u64 period; 1551 int ret; 1552 1553 if (!pdata->pwm_enabled) { 1554 ret = pm_runtime_resume_and_get(pwmchip_parent(chip)); 1555 if (ret < 0) 1556 return ret; 1557 } 1558 1559 if (state->enabled) { 1560 if (!pdata->pwm_enabled) { 1561 /* 1562 * The chip might have been powered down while we 1563 * didn't hold a PM runtime reference, so mux in the 1564 * PWM function on the GPIO pin again. 1565 */ 1566 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1567 SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX), 1568 SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX)); 1569 if (ret) { 1570 dev_err(pwmchip_parent(chip), "failed to mux in PWM function\n"); 1571 goto out; 1572 } 1573 } 1574 1575 /* 1576 * Per the datasheet the PWM frequency is given by: 1577 * 1578 * REFCLK_FREQ 1579 * PWM_FREQ = ----------------------------------- 1580 * PWM_PRE_DIV * BACKLIGHT_SCALE + 1 1581 * 1582 * However, after careful review the author is convinced that 1583 * the documentation has lost some parenthesis around 1584 * "BACKLIGHT_SCALE + 1". 1585 * 1586 * With the period T_pwm = 1/PWM_FREQ this can be written: 1587 * 1588 * T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1) 1589 * 1590 * In order to keep BACKLIGHT_SCALE within its 16 bits, 1591 * PWM_PRE_DIV must be: 1592 * 1593 * T_pwm * REFCLK_FREQ 1594 * PWM_PRE_DIV >= ------------------------- 1595 * BACKLIGHT_SCALE_MAX + 1 1596 * 1597 * To simplify the search and to favour higher resolution of 1598 * the duty cycle over accuracy of the period, the lowest 1599 * possible PWM_PRE_DIV is used. Finally the scale is 1600 * calculated as: 1601 * 1602 * T_pwm * REFCLK_FREQ 1603 * BACKLIGHT_SCALE = ---------------------- - 1 1604 * PWM_PRE_DIV 1605 * 1606 * Here T_pwm is represented in seconds, so appropriate scaling 1607 * to nanoseconds is necessary. 1608 */ 1609 1610 /* Minimum T_pwm is 1 / REFCLK_FREQ */ 1611 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) { 1612 ret = -EINVAL; 1613 goto out; 1614 } 1615 1616 /* 1617 * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ 1618 * Limit period to this to avoid overflows 1619 */ 1620 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1), 1621 pdata->pwm_refclk_freq); 1622 period = min(state->period, period_max); 1623 1624 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq, 1625 (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1)); 1626 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1; 1627 1628 /* 1629 * The documentation has the duty ratio given as: 1630 * 1631 * duty BACKLIGHT 1632 * ------- = --------------------- 1633 * period BACKLIGHT_SCALE + 1 1634 * 1635 * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according 1636 * to definition above and adjusting for nanosecond 1637 * representation of duty cycle gives us: 1638 */ 1639 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq, 1640 (u64)NSEC_PER_SEC * pre_div); 1641 if (backlight > scale) 1642 backlight = scale; 1643 1644 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div); 1645 if (ret) { 1646 dev_err(pwmchip_parent(chip), "failed to update PWM_PRE_DIV\n"); 1647 goto out; 1648 } 1649 1650 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale); 1651 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight); 1652 } 1653 1654 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) | 1655 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED); 1656 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv); 1657 if (ret) { 1658 dev_err(pwmchip_parent(chip), "failed to update PWM_EN/PWM_INV\n"); 1659 goto out; 1660 } 1661 1662 pdata->pwm_enabled = state->enabled; 1663out: 1664 1665 if (!pdata->pwm_enabled) 1666 pm_runtime_put_sync(pwmchip_parent(chip)); 1667 1668 return ret; 1669} 1670 1671static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 1672 struct pwm_state *state) 1673{ 1674 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1675 unsigned int pwm_en_inv; 1676 unsigned int pre_div; 1677 u16 backlight; 1678 u16 scale; 1679 int ret; 1680 1681 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv); 1682 if (ret) 1683 return ret; 1684 1685 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale); 1686 if (ret) 1687 return ret; 1688 1689 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight); 1690 if (ret) 1691 return ret; 1692 1693 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div); 1694 if (ret) 1695 return ret; 1696 1697 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv); 1698 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv)) 1699 state->polarity = PWM_POLARITY_INVERSED; 1700 else 1701 state->polarity = PWM_POLARITY_NORMAL; 1702 1703 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1), 1704 pdata->pwm_refclk_freq); 1705 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight, 1706 pdata->pwm_refclk_freq); 1707 1708 if (state->duty_cycle > state->period) 1709 state->duty_cycle = state->period; 1710 1711 return 0; 1712} 1713 1714static const struct pwm_ops ti_sn_pwm_ops = { 1715 .request = ti_sn_pwm_request, 1716 .free = ti_sn_pwm_free, 1717 .apply = ti_sn_pwm_apply, 1718 .get_state = ti_sn_pwm_get_state, 1719}; 1720 1721static int ti_sn_pwm_probe(struct auxiliary_device *adev, 1722 const struct auxiliary_device_id *id) 1723{ 1724 struct pwm_chip *chip; 1725 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1726 1727 pdata->pchip = chip = devm_pwmchip_alloc(&adev->dev, 1, 0); 1728 if (IS_ERR(chip)) 1729 return PTR_ERR(chip); 1730 1731 pwmchip_set_drvdata(chip, pdata); 1732 1733 chip->ops = &ti_sn_pwm_ops; 1734 chip->of_xlate = of_pwm_single_xlate; 1735 1736 devm_pm_runtime_enable(&adev->dev); 1737 1738 return pwmchip_add(chip); 1739} 1740 1741static void ti_sn_pwm_remove(struct auxiliary_device *adev) 1742{ 1743 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1744 1745 pwmchip_remove(pdata->pchip); 1746 1747 if (pdata->pwm_enabled) 1748 pm_runtime_put_sync(&adev->dev); 1749} 1750 1751static const struct auxiliary_device_id ti_sn_pwm_id_table[] = { 1752 { .name = "ti_sn65dsi86.pwm", }, 1753 {}, 1754}; 1755 1756static struct auxiliary_driver ti_sn_pwm_driver = { 1757 .name = "pwm", 1758 .probe = ti_sn_pwm_probe, 1759 .remove = ti_sn_pwm_remove, 1760 .id_table = ti_sn_pwm_id_table, 1761}; 1762 1763static int __init ti_sn_pwm_register(void) 1764{ 1765 return auxiliary_driver_register(&ti_sn_pwm_driver); 1766} 1767 1768static void ti_sn_pwm_unregister(void) 1769{ 1770 auxiliary_driver_unregister(&ti_sn_pwm_driver); 1771} 1772 1773#else 1774static inline int __maybe_unused ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; } 1775static inline void __maybe_unused ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {} 1776 1777static inline int ti_sn_pwm_register(void) { return 0; } 1778static inline void ti_sn_pwm_unregister(void) {} 1779#endif 1780 1781/* ----------------------------------------------------------------------------- 1782 * GPIO Controller 1783 */ 1784#if defined(CONFIG_OF_GPIO) 1785 1786static int tn_sn_bridge_of_xlate(struct gpio_chip *chip, 1787 const struct of_phandle_args *gpiospec, 1788 u32 *flags) 1789{ 1790 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells)) 1791 return -EINVAL; 1792 1793 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1) 1794 return -EINVAL; 1795 1796 if (flags) 1797 *flags = gpiospec->args[1]; 1798 1799 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET; 1800} 1801 1802static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip, 1803 unsigned int offset) 1804{ 1805 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1806 1807 /* 1808 * We already have to keep track of the direction because we use 1809 * that to figure out whether we've powered the device. We can 1810 * just return that rather than (maybe) powering up the device 1811 * to ask its direction. 1812 */ 1813 return test_bit(offset, pdata->gchip_output) ? 1814 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1815} 1816 1817static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset) 1818{ 1819 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1820 unsigned int val; 1821 int ret; 1822 1823 /* 1824 * When the pin is an input we don't forcibly keep the bridge 1825 * powered--we just power it on to read the pin. NOTE: part of 1826 * the reason this works is that the bridge defaults (when 1827 * powered back on) to all 4 GPIOs being configured as GPIO input. 1828 * Also note that if something else is keeping the chip powered the 1829 * pm_runtime functions are lightweight increments of a refcount. 1830 */ 1831 pm_runtime_get_sync(pdata->dev); 1832 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val); 1833 pm_runtime_put_autosuspend(pdata->dev); 1834 1835 if (ret) 1836 return ret; 1837 1838 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset)); 1839} 1840 1841static int ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, 1842 int val) 1843{ 1844 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1845 1846 val &= 1; 1847 return regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, 1848 BIT(SN_GPIO_OUTPUT_SHIFT + offset), 1849 val << (SN_GPIO_OUTPUT_SHIFT + offset)); 1850} 1851 1852static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip, 1853 unsigned int offset) 1854{ 1855 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1856 int shift = offset * 2; 1857 int ret; 1858 1859 if (!test_and_clear_bit(offset, pdata->gchip_output)) 1860 return 0; 1861 1862 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1863 SN_GPIO_MUX_MASK << shift, 1864 SN_GPIO_MUX_INPUT << shift); 1865 if (ret) { 1866 set_bit(offset, pdata->gchip_output); 1867 return ret; 1868 } 1869 1870 /* 1871 * NOTE: if nobody else is powering the device this may fully power 1872 * it off and when it comes back it will have lost all state, but 1873 * that's OK because the default is input and we're now an input. 1874 */ 1875 pm_runtime_put_autosuspend(pdata->dev); 1876 1877 return 0; 1878} 1879 1880static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, 1881 unsigned int offset, int val) 1882{ 1883 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1884 int shift = offset * 2; 1885 int ret; 1886 1887 if (test_and_set_bit(offset, pdata->gchip_output)) 1888 return 0; 1889 1890 pm_runtime_get_sync(pdata->dev); 1891 1892 /* Set value first to avoid glitching */ 1893 ti_sn_bridge_gpio_set(chip, offset, val); 1894 1895 /* Set direction */ 1896 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1897 SN_GPIO_MUX_MASK << shift, 1898 SN_GPIO_MUX_OUTPUT << shift); 1899 if (ret) { 1900 clear_bit(offset, pdata->gchip_output); 1901 pm_runtime_put_autosuspend(pdata->dev); 1902 } 1903 1904 return ret; 1905} 1906 1907static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset) 1908{ 1909 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1910 1911 if (offset == SN_PWM_GPIO_IDX) 1912 return ti_sn_pwm_pin_request(pdata); 1913 1914 return 0; 1915} 1916 1917static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset) 1918{ 1919 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1920 1921 /* We won't keep pm_runtime if we're input, so switch there on free */ 1922 ti_sn_bridge_gpio_direction_input(chip, offset); 1923 1924 if (offset == SN_PWM_GPIO_IDX) 1925 ti_sn_pwm_pin_release(pdata); 1926} 1927 1928static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = { 1929 "GPIO1", "GPIO2", "GPIO3", "GPIO4" 1930}; 1931 1932static int ti_sn_gpio_probe(struct auxiliary_device *adev, 1933 const struct auxiliary_device_id *id) 1934{ 1935 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1936 int ret; 1937 1938 /* Only init if someone is going to use us as a GPIO controller */ 1939 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller")) 1940 return 0; 1941 1942 pdata->gchip.label = dev_name(pdata->dev); 1943 pdata->gchip.parent = pdata->dev; 1944 pdata->gchip.owner = THIS_MODULE; 1945 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate; 1946 pdata->gchip.of_gpio_n_cells = 2; 1947 pdata->gchip.request = ti_sn_bridge_gpio_request; 1948 pdata->gchip.free = ti_sn_bridge_gpio_free; 1949 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction; 1950 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input; 1951 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output; 1952 pdata->gchip.get = ti_sn_bridge_gpio_get; 1953 pdata->gchip.set = ti_sn_bridge_gpio_set; 1954 pdata->gchip.can_sleep = true; 1955 pdata->gchip.names = ti_sn_bridge_gpio_names; 1956 pdata->gchip.ngpio = SN_NUM_GPIOS; 1957 pdata->gchip.base = -1; 1958 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata); 1959 if (ret) 1960 dev_err(pdata->dev, "can't add gpio chip\n"); 1961 1962 return ret; 1963} 1964 1965static const struct auxiliary_device_id ti_sn_gpio_id_table[] = { 1966 { .name = "ti_sn65dsi86.gpio", }, 1967 {}, 1968}; 1969 1970MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table); 1971 1972static struct auxiliary_driver ti_sn_gpio_driver = { 1973 .name = "gpio", 1974 .probe = ti_sn_gpio_probe, 1975 .id_table = ti_sn_gpio_id_table, 1976}; 1977 1978static int __init ti_sn_gpio_register(void) 1979{ 1980 return auxiliary_driver_register(&ti_sn_gpio_driver); 1981} 1982 1983static void ti_sn_gpio_unregister(void) 1984{ 1985 auxiliary_driver_unregister(&ti_sn_gpio_driver); 1986} 1987 1988#else 1989 1990static inline int ti_sn_gpio_register(void) { return 0; } 1991static inline void ti_sn_gpio_unregister(void) {} 1992 1993#endif 1994 1995/* ----------------------------------------------------------------------------- 1996 * Probe & Remove 1997 */ 1998 1999static void ti_sn65dsi86_runtime_disable(void *data) 2000{ 2001 pm_runtime_dont_use_autosuspend(data); 2002 pm_runtime_disable(data); 2003} 2004 2005static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata) 2006{ 2007 unsigned int i; 2008 const char * const ti_sn_bridge_supply_names[] = { 2009 "vcca", "vcc", "vccio", "vpll", 2010 }; 2011 2012 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++) 2013 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i]; 2014 2015 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM, 2016 pdata->supplies); 2017} 2018 2019static int ti_sn65dsi86_probe(struct i2c_client *client) 2020{ 2021 struct device *dev = &client->dev; 2022 struct ti_sn65dsi86 *pdata; 2023 u8 id_buf[8]; 2024 int ret; 2025 2026 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 2027 DRM_ERROR("device doesn't support I2C\n"); 2028 return -ENODEV; 2029 } 2030 2031 pdata = devm_drm_bridge_alloc(dev, struct ti_sn65dsi86, bridge, &ti_sn_bridge_funcs); 2032 if (IS_ERR(pdata)) 2033 return PTR_ERR(pdata); 2034 dev_set_drvdata(dev, pdata); 2035 pdata->dev = dev; 2036 2037 mutex_init(&pdata->hpd_mutex); 2038 mutex_init(&pdata->comms_mutex); 2039 2040 pdata->regmap = devm_regmap_init_i2c(client, 2041 &ti_sn65dsi86_regmap_config); 2042 if (IS_ERR(pdata->regmap)) 2043 return dev_err_probe(dev, PTR_ERR(pdata->regmap), 2044 "regmap i2c init failed\n"); 2045 2046 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable", 2047 GPIOD_OUT_LOW); 2048 if (IS_ERR(pdata->enable_gpio)) 2049 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio), 2050 "failed to get enable gpio from DT\n"); 2051 2052 ret = ti_sn65dsi86_parse_regulators(pdata); 2053 if (ret) 2054 return dev_err_probe(dev, ret, "failed to parse regulators\n"); 2055 2056 pdata->refclk = devm_clk_get_optional(dev, "refclk"); 2057 if (IS_ERR(pdata->refclk)) 2058 return dev_err_probe(dev, PTR_ERR(pdata->refclk), 2059 "failed to get reference clock\n"); 2060 2061 pm_runtime_enable(dev); 2062 pm_runtime_set_autosuspend_delay(pdata->dev, 500); 2063 pm_runtime_use_autosuspend(pdata->dev); 2064 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev); 2065 if (ret) 2066 return ret; 2067 2068 pm_runtime_get_sync(dev); 2069 ret = regmap_bulk_read(pdata->regmap, SN_DEVICE_ID_REGS, id_buf, ARRAY_SIZE(id_buf)); 2070 pm_runtime_put_autosuspend(dev); 2071 if (ret) 2072 return dev_err_probe(dev, ret, "failed to read device id\n"); 2073 2074 /* The ID string is stored backwards */ 2075 if (strncmp(id_buf, "68ISD ", ARRAY_SIZE(id_buf))) 2076 return dev_err_probe(dev, -EOPNOTSUPP, "unsupported device id\n"); 2077 2078 if (client->irq) { 2079 ret = devm_request_threaded_irq(pdata->dev, client->irq, NULL, 2080 ti_sn_bridge_interrupt, 2081 IRQF_ONESHOT, 2082 dev_name(pdata->dev), pdata); 2083 2084 if (ret) 2085 return dev_err_probe(dev, ret, "failed to request interrupt\n"); 2086 } 2087 2088 /* 2089 * Break ourselves up into a collection of aux devices. The only real 2090 * motiviation here is to solve the chicken-and-egg problem of probe 2091 * ordering. The bridge wants the panel to be there when it probes. 2092 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards) 2093 * when it probes. The panel and maybe backlight might want the DDC 2094 * bus or the pwm_chip. Having sub-devices allows the some sub devices 2095 * to finish probing even if others return -EPROBE_DEFER and gets us 2096 * around the problems. 2097 */ 2098 2099 if (IS_ENABLED(CONFIG_OF_GPIO)) { 2100 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio"); 2101 if (ret) 2102 return ret; 2103 } 2104 2105 if (IS_REACHABLE(CONFIG_PWM)) { 2106 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm"); 2107 if (ret) 2108 return ret; 2109 } 2110 2111 /* 2112 * NOTE: At the end of the AUX channel probe we'll add the aux device 2113 * for the bridge. This is because the bridge can't be used until the 2114 * AUX channel is there and this is a very simple solution to the 2115 * dependency problem. 2116 */ 2117 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux"); 2118} 2119 2120static const struct i2c_device_id ti_sn65dsi86_id[] = { 2121 { "ti,sn65dsi86" }, 2122 {} 2123}; 2124MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id); 2125 2126static const struct of_device_id ti_sn65dsi86_match_table[] = { 2127 {.compatible = "ti,sn65dsi86"}, 2128 {}, 2129}; 2130MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table); 2131 2132static struct i2c_driver ti_sn65dsi86_driver = { 2133 .driver = { 2134 .name = "ti_sn65dsi86", 2135 .of_match_table = ti_sn65dsi86_match_table, 2136 .pm = &ti_sn65dsi86_pm_ops, 2137 }, 2138 .probe = ti_sn65dsi86_probe, 2139 .id_table = ti_sn65dsi86_id, 2140}; 2141 2142static int __init ti_sn65dsi86_init(void) 2143{ 2144 int ret; 2145 2146 ret = i2c_add_driver(&ti_sn65dsi86_driver); 2147 if (ret) 2148 return ret; 2149 2150 ret = ti_sn_gpio_register(); 2151 if (ret) 2152 goto err_main_was_registered; 2153 2154 ret = ti_sn_pwm_register(); 2155 if (ret) 2156 goto err_gpio_was_registered; 2157 2158 ret = auxiliary_driver_register(&ti_sn_aux_driver); 2159 if (ret) 2160 goto err_pwm_was_registered; 2161 2162 ret = auxiliary_driver_register(&ti_sn_bridge_driver); 2163 if (ret) 2164 goto err_aux_was_registered; 2165 2166 return 0; 2167 2168err_aux_was_registered: 2169 auxiliary_driver_unregister(&ti_sn_aux_driver); 2170err_pwm_was_registered: 2171 ti_sn_pwm_unregister(); 2172err_gpio_was_registered: 2173 ti_sn_gpio_unregister(); 2174err_main_was_registered: 2175 i2c_del_driver(&ti_sn65dsi86_driver); 2176 2177 return ret; 2178} 2179module_init(ti_sn65dsi86_init); 2180 2181static void __exit ti_sn65dsi86_exit(void) 2182{ 2183 auxiliary_driver_unregister(&ti_sn_bridge_driver); 2184 auxiliary_driver_unregister(&ti_sn_aux_driver); 2185 ti_sn_pwm_unregister(); 2186 ti_sn_gpio_unregister(); 2187 i2c_del_driver(&ti_sn65dsi86_driver); 2188} 2189module_exit(ti_sn65dsi86_exit); 2190 2191MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>"); 2192MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver"); 2193MODULE_LICENSE("GPL v2");
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