FILE
ti-sn65dsi83.c
File preview with syntax highlighting.
linux-6.19.14/drivers/gpu/drm/bridge/ti-sn65dsi83.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * TI SN65DSI83,84,85 driver 4 * 5 * Currently supported: 6 * - SN65DSI83 7 * = 1x Single-link DSI ~ 1x Single-link LVDS 8 * - Supported 9 * - Single-link LVDS mode tested 10 * - SN65DSI84 11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS 12 * - Supported 13 * - Dual-link LVDS mode tested 14 * - 2x Single-link LVDS mode unsupported 15 * (should be easy to add by someone who has the HW) 16 * - SN65DSI85 17 * = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS 18 * - Unsupported 19 * (should be easy to add by someone who has the HW) 20 * 21 * Copyright (C) 2021 Marek Vasut <marex@denx.de> 22 * 23 * Based on previous work of: 24 * Valentin Raevsky <valentin@compulab.co.il> 25 * Philippe Schenker <philippe.schenker@toradex.com> 26 */ 27 28#include <linux/bits.h> 29#include <linux/clk.h> 30#include <linux/gpio/consumer.h> 31#include <linux/i2c.h> 32#include <linux/media-bus-format.h> 33#include <linux/module.h> 34#include <linux/of.h> 35#include <linux/of_graph.h> 36#include <linux/regmap.h> 37#include <linux/regulator/consumer.h> 38#include <linux/timer.h> 39#include <linux/workqueue.h> 40 41#include <drm/drm_atomic_helper.h> 42#include <drm/drm_bridge.h> 43#include <drm/drm_bridge_helper.h> 44#include <drm/drm_mipi_dsi.h> 45#include <drm/drm_of.h> 46#include <drm/drm_print.h> 47#include <drm/drm_probe_helper.h> 48 49/* ID registers */ 50#define REG_ID(n) (0x00 + (n)) 51/* Reset and clock registers */ 52#define REG_RC_RESET 0x09 53#define REG_RC_RESET_SOFT_RESET BIT(0) 54#define REG_RC_LVDS_PLL 0x0a 55#define REG_RC_LVDS_PLL_PLL_EN_STAT BIT(7) 56#define REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n) (((n) & 0x7) << 1) 57#define REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY BIT(0) 58#define REG_RC_DSI_CLK 0x0b 59#define REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n) (((n) & 0x1f) << 3) 60#define REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n) ((n) & 0x3) 61#define REG_RC_PLL_EN 0x0d 62#define REG_RC_PLL_EN_PLL_EN BIT(0) 63/* DSI registers */ 64#define REG_DSI_LANE 0x10 65#define REG_DSI_LANE_LEFT_RIGHT_PIXELS BIT(7) /* DSI85-only */ 66#define REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0 /* DSI85-only */ 67#define REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE BIT(6) /* DSI85-only */ 68#define REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE BIT(5) 69#define REG_DSI_LANE_CHA_DSI_LANES(n) (((n) & 0x3) << 3) 70#define REG_DSI_LANE_CHB_DSI_LANES(n) (((n) & 0x3) << 1) 71#define REG_DSI_LANE_SOT_ERR_TOL_DIS BIT(0) 72#define REG_DSI_EQ 0x11 73#define REG_DSI_EQ_CHA_DSI_DATA_EQ(n) (((n) & 0x3) << 6) 74#define REG_DSI_EQ_CHA_DSI_CLK_EQ(n) (((n) & 0x3) << 2) 75#define REG_DSI_CLK 0x12 76#define REG_DSI_CLK_CHA_DSI_CLK_RANGE(n) ((n) & 0xff) 77/* LVDS registers */ 78#define REG_LVDS_FMT 0x18 79#define REG_LVDS_FMT_DE_NEG_POLARITY BIT(7) 80#define REG_LVDS_FMT_HS_NEG_POLARITY BIT(6) 81#define REG_LVDS_FMT_VS_NEG_POLARITY BIT(5) 82#define REG_LVDS_FMT_LVDS_LINK_CFG BIT(4) /* 0:AB 1:A-only */ 83#define REG_LVDS_FMT_CHA_24BPP_MODE BIT(3) 84#define REG_LVDS_FMT_CHB_24BPP_MODE BIT(2) 85#define REG_LVDS_FMT_CHA_24BPP_FORMAT1 BIT(1) 86#define REG_LVDS_FMT_CHB_24BPP_FORMAT1 BIT(0) 87#define REG_LVDS_VCOM 0x19 88#define REG_LVDS_VCOM_CHA_LVDS_VOCM BIT(6) 89#define REG_LVDS_VCOM_CHB_LVDS_VOCM BIT(4) 90#define REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n) (((n) & 0x3) << 2) 91#define REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n) ((n) & 0x3) 92#define REG_LVDS_LANE 0x1a 93#define REG_LVDS_LANE_EVEN_ODD_SWAP BIT(6) 94#define REG_LVDS_LANE_CHA_REVERSE_LVDS BIT(5) 95#define REG_LVDS_LANE_CHB_REVERSE_LVDS BIT(4) 96#define REG_LVDS_LANE_CHA_LVDS_TERM BIT(1) 97#define REG_LVDS_LANE_CHB_LVDS_TERM BIT(0) 98#define REG_LVDS_CM 0x1b 99#define REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n) (((n) & 0x3) << 4) 100#define REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n) ((n) & 0x3) 101/* Video registers */ 102#define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW 0x20 103#define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21 104#define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW 0x24 105#define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x25 106#define REG_VID_CHA_SYNC_DELAY_LOW 0x28 107#define REG_VID_CHA_SYNC_DELAY_HIGH 0x29 108#define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW 0x2c 109#define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2d 110#define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30 111#define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31 112#define REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34 113#define REG_VID_CHA_VERTICAL_BACK_PORCH 0x36 114#define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38 115#define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a 116#define REG_VID_CHA_TEST_PATTERN 0x3c 117/* IRQ registers */ 118#define REG_IRQ_GLOBAL 0xe0 119#define REG_IRQ_GLOBAL_IRQ_EN BIT(0) 120#define REG_IRQ_EN 0xe1 121#define REG_IRQ_EN_CHA_SYNCH_ERR_EN BIT(7) 122#define REG_IRQ_EN_CHA_CRC_ERR_EN BIT(6) 123#define REG_IRQ_EN_CHA_UNC_ECC_ERR_EN BIT(5) 124#define REG_IRQ_EN_CHA_COR_ECC_ERR_EN BIT(4) 125#define REG_IRQ_EN_CHA_LLP_ERR_EN BIT(3) 126#define REG_IRQ_EN_CHA_SOT_BIT_ERR_EN BIT(2) 127#define REG_IRQ_EN_CHA_PLL_UNLOCK_EN BIT(0) 128#define REG_IRQ_STAT 0xe5 129#define REG_IRQ_STAT_CHA_SYNCH_ERR BIT(7) 130#define REG_IRQ_STAT_CHA_CRC_ERR BIT(6) 131#define REG_IRQ_STAT_CHA_UNC_ECC_ERR BIT(5) 132#define REG_IRQ_STAT_CHA_COR_ECC_ERR BIT(4) 133#define REG_IRQ_STAT_CHA_LLP_ERR BIT(3) 134#define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2) 135#define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0) 136 137enum sn65dsi83_channel { 138 CHANNEL_A, 139 CHANNEL_B 140}; 141 142enum sn65dsi83_lvds_term { 143 OHM_100, 144 OHM_200 145}; 146 147enum sn65dsi83_model { 148 MODEL_SN65DSI83, 149 MODEL_SN65DSI84, 150}; 151 152struct sn65dsi83 { 153 struct drm_bridge bridge; 154 struct device *dev; 155 struct regmap *regmap; 156 struct mipi_dsi_device *dsi; 157 struct drm_bridge *panel_bridge; 158 struct gpio_desc *enable_gpio; 159 struct regulator *vcc; 160 bool lvds_dual_link; 161 bool lvds_dual_link_even_odd_swap; 162 int lvds_vod_swing_conf[2]; 163 int lvds_term_conf[2]; 164 int irq; 165 struct delayed_work monitor_work; 166 struct work_struct reset_work; 167}; 168 169static const struct regmap_range sn65dsi83_readable_ranges[] = { 170 regmap_reg_range(REG_ID(0), REG_ID(8)), 171 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK), 172 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 173 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 174 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 175 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 176 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 177 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 178 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 179 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 180 REG_VID_CHA_SYNC_DELAY_HIGH), 181 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 182 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 183 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 184 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 185 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 186 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 187 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 188 REG_VID_CHA_VERTICAL_BACK_PORCH), 189 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 190 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 191 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 192 REG_VID_CHA_VERTICAL_FRONT_PORCH), 193 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 194 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 195 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 196}; 197 198static const struct regmap_access_table sn65dsi83_readable_table = { 199 .yes_ranges = sn65dsi83_readable_ranges, 200 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges), 201}; 202 203static const struct regmap_range sn65dsi83_writeable_ranges[] = { 204 regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK), 205 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 206 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 207 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 208 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 209 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 210 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 211 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 212 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 213 REG_VID_CHA_SYNC_DELAY_HIGH), 214 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 215 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 216 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 217 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 218 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 219 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 220 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 221 REG_VID_CHA_VERTICAL_BACK_PORCH), 222 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 223 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 224 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 225 REG_VID_CHA_VERTICAL_FRONT_PORCH), 226 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 227 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 228 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 229}; 230 231static const struct regmap_access_table sn65dsi83_writeable_table = { 232 .yes_ranges = sn65dsi83_writeable_ranges, 233 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges), 234}; 235 236static const struct regmap_range sn65dsi83_volatile_ranges[] = { 237 regmap_reg_range(REG_RC_RESET, REG_RC_RESET), 238 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL), 239 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 240}; 241 242static const struct regmap_access_table sn65dsi83_volatile_table = { 243 .yes_ranges = sn65dsi83_volatile_ranges, 244 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges), 245}; 246 247static const struct regmap_config sn65dsi83_regmap_config = { 248 .reg_bits = 8, 249 .val_bits = 8, 250 .rd_table = &sn65dsi83_readable_table, 251 .wr_table = &sn65dsi83_writeable_table, 252 .volatile_table = &sn65dsi83_volatile_table, 253 .cache_type = REGCACHE_MAPLE, 254 .max_register = REG_IRQ_STAT, 255}; 256 257static const int lvds_vod_swing_data_table[2][4][2] = { 258 { /* 100 Ohm */ 259 { 180000, 313000 }, 260 { 215000, 372000 }, 261 { 250000, 430000 }, 262 { 290000, 488000 }, 263 }, 264 { /* 200 Ohm */ 265 { 150000, 261000 }, 266 { 200000, 346000 }, 267 { 250000, 428000 }, 268 { 300000, 511000 }, 269 }, 270}; 271 272static const int lvds_vod_swing_clock_table[2][4][2] = { 273 { /* 100 Ohm */ 274 { 140000, 244000 }, 275 { 168000, 290000 }, 276 { 195000, 335000 }, 277 { 226000, 381000 }, 278 }, 279 { /* 200 Ohm */ 280 { 117000, 204000 }, 281 { 156000, 270000 }, 282 { 195000, 334000 }, 283 { 234000, 399000 }, 284 }, 285}; 286 287static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge) 288{ 289 return container_of(bridge, struct sn65dsi83, bridge); 290} 291 292static int sn65dsi83_attach(struct drm_bridge *bridge, 293 struct drm_encoder *encoder, 294 enum drm_bridge_attach_flags flags) 295{ 296 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 297 298 return drm_bridge_attach(encoder, ctx->panel_bridge, 299 &ctx->bridge, flags); 300} 301 302static void sn65dsi83_detach(struct drm_bridge *bridge) 303{ 304 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 305 306 if (!ctx->dsi) 307 return; 308 309 ctx->dsi = NULL; 310} 311 312static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx, 313 const struct drm_display_mode *mode) 314{ 315 /* 316 * The encoding of the LVDS_CLK_RANGE is as follows: 317 * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz 318 * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz 319 * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz 320 * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz 321 * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz 322 * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz 323 * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that 324 * the ends of the ranges are clamped to the supported range. Since 325 * sn65dsi83_mode_valid() already filters the valid modes and limits 326 * the clock to 25..154 MHz, the range calculation can be simplified 327 * as follows: 328 */ 329 int mode_clock = mode->clock; 330 331 if (ctx->lvds_dual_link) 332 mode_clock /= 2; 333 334 return (mode_clock - 12500) / 25000; 335} 336 337static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx, 338 const struct drm_display_mode *mode) 339{ 340 /* 341 * The encoding of the CHA_DSI_CLK_RANGE is as follows: 342 * 0x00 through 0x07 - Reserved 343 * 0x08 - 40 <= DSI_CLK < 45 MHz 344 * 0x09 - 45 <= DSI_CLK < 50 MHz 345 * ... 346 * 0x63 - 495 <= DSI_CLK < 500 MHz 347 * 0x64 - 500 MHz 348 * 0x65 through 0xFF - Reserved 349 * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz. 350 * The DSI clock are calculated as: 351 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2 352 * the 2 is there because the bus is DDR. 353 */ 354 return clamp((unsigned int)mode->clock * 355 mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) / 356 ctx->dsi->lanes / 2, 40000U, 500000U) / 5000U; 357} 358 359static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx) 360{ 361 /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */ 362 unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format); 363 364 dsi_div /= ctx->dsi->lanes; 365 366 if (!ctx->lvds_dual_link) 367 dsi_div /= 2; 368 369 return dsi_div - 1; 370} 371 372static int sn65dsi83_reset_pipe(struct sn65dsi83 *sn65dsi83) 373{ 374 struct drm_modeset_acquire_ctx ctx; 375 int err; 376 377 /* 378 * Reset active outputs of the related CRTC. 379 * 380 * This way, drm core will reconfigure each components in the CRTC 381 * outputs path. In our case, this will force the previous component to 382 * go back in LP11 mode and so allow the reconfiguration of SN65DSI83 383 * bridge. 384 * 385 * Keep the lock during the whole operation to be atomic. 386 */ 387 388 drm_modeset_acquire_init(&ctx, 0); 389 390 dev_warn(sn65dsi83->dev, "reset the pipe\n"); 391 392retry: 393 err = drm_bridge_helper_reset_crtc(&sn65dsi83->bridge, &ctx); 394 if (err == -EDEADLK) { 395 drm_modeset_backoff(&ctx); 396 goto retry; 397 } 398 399 drm_modeset_drop_locks(&ctx); 400 drm_modeset_acquire_fini(&ctx); 401 402 return 0; 403} 404 405static void sn65dsi83_reset_work(struct work_struct *ws) 406{ 407 struct sn65dsi83 *ctx = container_of(ws, struct sn65dsi83, reset_work); 408 int ret; 409 410 /* Reset the pipe */ 411 ret = sn65dsi83_reset_pipe(ctx); 412 if (ret) { 413 dev_err(ctx->dev, "reset pipe failed %pe\n", ERR_PTR(ret)); 414 return; 415 } 416 if (ctx->irq) 417 enable_irq(ctx->irq); 418} 419 420static void sn65dsi83_handle_errors(struct sn65dsi83 *ctx) 421{ 422 unsigned int irq_stat; 423 int ret; 424 425 /* 426 * Schedule a reset in case of: 427 * - the bridge doesn't answer 428 * - the bridge signals an error 429 */ 430 431 ret = regmap_read(ctx->regmap, REG_IRQ_STAT, &irq_stat); 432 433 /* 434 * Some hardware (Toradex Verdin AM62) is known to report the 435 * PLL_UNLOCK error interrupt while working without visible 436 * problems. In lack of a reliable way to discriminate such cases 437 * from user-visible PLL_UNLOCK cases, ignore that bit entirely. 438 */ 439 if (ret || irq_stat & ~REG_IRQ_STAT_CHA_PLL_UNLOCK) { 440 /* 441 * IRQ acknowledged is not always possible (the bridge can be in 442 * a state where it doesn't answer anymore). To prevent an 443 * interrupt storm, disable interrupt. The interrupt will be 444 * after the reset. 445 */ 446 if (ctx->irq) 447 disable_irq_nosync(ctx->irq); 448 449 schedule_work(&ctx->reset_work); 450 } 451} 452 453static void sn65dsi83_monitor_work(struct work_struct *work) 454{ 455 struct sn65dsi83 *ctx = container_of(to_delayed_work(work), 456 struct sn65dsi83, monitor_work); 457 458 sn65dsi83_handle_errors(ctx); 459 460 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000)); 461} 462 463static void sn65dsi83_monitor_start(struct sn65dsi83 *ctx) 464{ 465 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000)); 466} 467 468static void sn65dsi83_monitor_stop(struct sn65dsi83 *ctx) 469{ 470 cancel_delayed_work_sync(&ctx->monitor_work); 471} 472 473static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, 474 struct drm_atomic_state *state) 475{ 476 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 477 const unsigned int dual_factor = ctx->lvds_dual_link ? 2 : 1; 478 const struct drm_bridge_state *bridge_state; 479 const struct drm_crtc_state *crtc_state; 480 const struct drm_display_mode *mode; 481 struct drm_connector *connector; 482 struct drm_crtc *crtc; 483 bool lvds_format_24bpp; 484 bool lvds_format_jeida; 485 unsigned int pval; 486 __le16 le16val; 487 u16 val; 488 int ret; 489 490 ret = regulator_enable(ctx->vcc); 491 if (ret) { 492 dev_err(ctx->dev, "Failed to enable vcc: %d\n", ret); 493 return; 494 } 495 496 /* Deassert reset */ 497 gpiod_set_value_cansleep(ctx->enable_gpio, 1); 498 usleep_range(10000, 11000); 499 500 /* Get the LVDS format from the bridge state. */ 501 bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 502 503 switch (bridge_state->output_bus_cfg.format) { 504 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 505 lvds_format_24bpp = false; 506 lvds_format_jeida = true; 507 break; 508 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 509 lvds_format_24bpp = true; 510 lvds_format_jeida = true; 511 break; 512 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 513 lvds_format_24bpp = true; 514 lvds_format_jeida = false; 515 break; 516 default: 517 /* 518 * Some bridges still don't set the correct 519 * LVDS bus pixel format, use SPWG24 default 520 * format until those are fixed. 521 */ 522 lvds_format_24bpp = true; 523 lvds_format_jeida = false; 524 dev_warn(ctx->dev, 525 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", 526 bridge_state->output_bus_cfg.format); 527 break; 528 } 529 530 /* 531 * Retrieve the CRTC adjusted mode. This requires a little dance to go 532 * from the bridge to the encoder, to the connector and to the CRTC. 533 */ 534 connector = drm_atomic_get_new_connector_for_encoder(state, 535 bridge->encoder); 536 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 537 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 538 mode = &crtc_state->adjusted_mode; 539 540 /* Clear reset, disable PLL */ 541 regmap_write(ctx->regmap, REG_RC_RESET, 0x00); 542 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 543 544 /* Reference clock derived from DSI link clock. */ 545 regmap_write(ctx->regmap, REG_RC_LVDS_PLL, 546 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) | 547 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY); 548 regmap_write(ctx->regmap, REG_DSI_CLK, 549 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx, mode))); 550 regmap_write(ctx->regmap, REG_RC_DSI_CLK, 551 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx))); 552 553 /* Set number of DSI lanes and LVDS link config. */ 554 regmap_write(ctx->regmap, REG_DSI_LANE, 555 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE | 556 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi->lanes - 1)) | 557 /* CHB is DSI85-only, set to default on DSI83/DSI84 */ 558 REG_DSI_LANE_CHB_DSI_LANES(3)); 559 /* No equalization. */ 560 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00); 561 562 /* Set up sync signal polarity. */ 563 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 564 REG_LVDS_FMT_HS_NEG_POLARITY : 0) | 565 (mode->flags & DRM_MODE_FLAG_NVSYNC ? 566 REG_LVDS_FMT_VS_NEG_POLARITY : 0); 567 val |= bridge_state->output_bus_cfg.flags & DRM_BUS_FLAG_DE_LOW ? 568 REG_LVDS_FMT_DE_NEG_POLARITY : 0; 569 570 /* Set up bits-per-pixel, 18bpp or 24bpp. */ 571 if (lvds_format_24bpp) { 572 val |= REG_LVDS_FMT_CHA_24BPP_MODE; 573 if (ctx->lvds_dual_link) 574 val |= REG_LVDS_FMT_CHB_24BPP_MODE; 575 } 576 577 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */ 578 if (lvds_format_jeida) { 579 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1; 580 if (ctx->lvds_dual_link) 581 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1; 582 } 583 584 /* Set up LVDS output config (DSI84,DSI85) */ 585 if (!ctx->lvds_dual_link) 586 val |= REG_LVDS_FMT_LVDS_LINK_CFG; 587 588 regmap_write(ctx->regmap, REG_LVDS_FMT, val); 589 regmap_write(ctx->regmap, REG_LVDS_VCOM, 590 REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_A]) | 591 REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_B])); 592 regmap_write(ctx->regmap, REG_LVDS_LANE, 593 (ctx->lvds_dual_link_even_odd_swap ? 594 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) | 595 (ctx->lvds_term_conf[CHANNEL_A] ? 596 REG_LVDS_LANE_CHA_LVDS_TERM : 0) | 597 (ctx->lvds_term_conf[CHANNEL_B] ? 598 REG_LVDS_LANE_CHB_LVDS_TERM : 0)); 599 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); 600 601 le16val = cpu_to_le16(mode->hdisplay); 602 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 603 &le16val, 2); 604 le16val = cpu_to_le16(mode->vdisplay); 605 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 606 &le16val, 2); 607 /* 32 + 1 pixel clock to ensure proper operation */ 608 le16val = cpu_to_le16(32 + 1); 609 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2); 610 le16val = cpu_to_le16((mode->hsync_end - mode->hsync_start) / dual_factor); 611 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 612 &le16val, 2); 613 le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start); 614 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 615 &le16val, 2); 616 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH, 617 (mode->htotal - mode->hsync_end) / dual_factor); 618 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH, 619 mode->vtotal - mode->vsync_end); 620 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 621 (mode->hsync_start - mode->hdisplay) / dual_factor); 622 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, 623 mode->vsync_start - mode->vdisplay); 624 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); 625 626 /* Enable PLL */ 627 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); 628 usleep_range(3000, 4000); 629 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval, 630 pval & REG_RC_LVDS_PLL_PLL_EN_STAT, 631 1000, 100000); 632 if (ret) { 633 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret); 634 /* On failure, disable PLL again and exit. */ 635 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 636 return; 637 } 638 639 /* Trigger reset after CSR register update. */ 640 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET); 641 642 /* Wait for 10ms after soft reset as specified in datasheet */ 643 usleep_range(10000, 12000); 644} 645 646static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, 647 struct drm_atomic_state *state) 648{ 649 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 650 unsigned int pval; 651 652 /* Clear all errors that got asserted during initialization. */ 653 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); 654 regmap_write(ctx->regmap, REG_IRQ_STAT, pval); 655 656 /* Wait for 1ms and check for errors in status register */ 657 usleep_range(1000, 1100); 658 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); 659 if (pval) 660 dev_err(ctx->dev, "Unexpected link status 0x%02x\n", pval); 661 662 if (ctx->irq) { 663 /* Enable irq to detect errors */ 664 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, REG_IRQ_GLOBAL_IRQ_EN); 665 regmap_write(ctx->regmap, REG_IRQ_EN, 0xff & ~REG_IRQ_EN_CHA_PLL_UNLOCK_EN); 666 } else { 667 /* Use the polling task */ 668 sn65dsi83_monitor_start(ctx); 669 } 670} 671 672static void sn65dsi83_atomic_disable(struct drm_bridge *bridge, 673 struct drm_atomic_state *state) 674{ 675 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 676 int ret; 677 678 if (ctx->irq) { 679 /* Disable irq */ 680 regmap_write(ctx->regmap, REG_IRQ_EN, 0x0); 681 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, 0x0); 682 } else { 683 /* Stop the polling task */ 684 sn65dsi83_monitor_stop(ctx); 685 } 686 687 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ 688 gpiod_set_value_cansleep(ctx->enable_gpio, 0); 689 usleep_range(10000, 11000); 690 691 ret = regulator_disable(ctx->vcc); 692 if (ret) 693 dev_err(ctx->dev, "Failed to disable vcc: %d\n", ret); 694 695 regcache_mark_dirty(ctx->regmap); 696} 697 698static enum drm_mode_status 699sn65dsi83_mode_valid(struct drm_bridge *bridge, 700 const struct drm_display_info *info, 701 const struct drm_display_mode *mode) 702{ 703 /* LVDS output clock range 25..154 MHz */ 704 if (mode->clock < 25000) 705 return MODE_CLOCK_LOW; 706 if (mode->clock > 154000) 707 return MODE_CLOCK_HIGH; 708 709 return MODE_OK; 710} 711 712#define MAX_INPUT_SEL_FORMATS 1 713 714static u32 * 715sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 716 struct drm_bridge_state *bridge_state, 717 struct drm_crtc_state *crtc_state, 718 struct drm_connector_state *conn_state, 719 u32 output_fmt, 720 unsigned int *num_input_fmts) 721{ 722 u32 *input_fmts; 723 724 *num_input_fmts = 0; 725 726 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 727 GFP_KERNEL); 728 if (!input_fmts) 729 return NULL; 730 731 /* This is the DSI-end bus format */ 732 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 733 *num_input_fmts = 1; 734 735 return input_fmts; 736} 737 738static const struct drm_bridge_funcs sn65dsi83_funcs = { 739 .attach = sn65dsi83_attach, 740 .detach = sn65dsi83_detach, 741 .atomic_enable = sn65dsi83_atomic_enable, 742 .atomic_pre_enable = sn65dsi83_atomic_pre_enable, 743 .atomic_disable = sn65dsi83_atomic_disable, 744 .mode_valid = sn65dsi83_mode_valid, 745 746 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 747 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 748 .atomic_reset = drm_atomic_helper_bridge_reset, 749 .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts, 750}; 751 752static int sn65dsi83_select_lvds_vod_swing(struct device *dev, 753 u32 lvds_vod_swing_data[2], u32 lvds_vod_swing_clk[2], u8 lvds_term) 754{ 755 int i; 756 757 for (i = 0; i <= 3; i++) { 758 if (lvds_vod_swing_data_table[lvds_term][i][0] >= lvds_vod_swing_data[0] && 759 lvds_vod_swing_data_table[lvds_term][i][1] <= lvds_vod_swing_data[1] && 760 lvds_vod_swing_clock_table[lvds_term][i][0] >= lvds_vod_swing_clk[0] && 761 lvds_vod_swing_clock_table[lvds_term][i][1] <= lvds_vod_swing_clk[1]) 762 return i; 763 } 764 765 dev_err(dev, "failed to find appropriate LVDS_VOD_SWING configuration\n"); 766 return -EINVAL; 767} 768 769static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel) 770{ 771 struct device *dev = ctx->dev; 772 struct device_node *endpoint; 773 int endpoint_reg; 774 /* Set so the property can be freely selected if not defined */ 775 u32 lvds_vod_swing_data[2] = { 0, 1000000 }; 776 u32 lvds_vod_swing_clk[2] = { 0, 1000000 }; 777 /* Set default near end terminataion to 200 Ohm */ 778 u32 lvds_term = 200; 779 int lvds_vod_swing_conf; 780 int ret = 0; 781 int ret_data; 782 int ret_clock; 783 784 if (channel == CHANNEL_A) 785 endpoint_reg = 2; 786 else 787 endpoint_reg = 3; 788 789 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, endpoint_reg, -1); 790 791 of_property_read_u32(endpoint, "ti,lvds-termination-ohms", &lvds_term); 792 if (lvds_term == 100) 793 ctx->lvds_term_conf[channel] = OHM_100; 794 else if (lvds_term == 200) 795 ctx->lvds_term_conf[channel] = OHM_200; 796 else { 797 ret = -EINVAL; 798 goto exit; 799 } 800 801 ret_data = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-data-microvolt", 802 lvds_vod_swing_data, ARRAY_SIZE(lvds_vod_swing_data)); 803 if (ret_data != 0 && ret_data != -EINVAL) { 804 ret = ret_data; 805 goto exit; 806 } 807 808 ret_clock = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-clock-microvolt", 809 lvds_vod_swing_clk, ARRAY_SIZE(lvds_vod_swing_clk)); 810 if (ret_clock != 0 && ret_clock != -EINVAL) { 811 ret = ret_clock; 812 goto exit; 813 } 814 815 /* Use default value if both properties are NOT defined. */ 816 if (ret_data == -EINVAL && ret_clock == -EINVAL) 817 lvds_vod_swing_conf = 0x1; 818 819 /* Use lookup table if any of the two properties is defined. */ 820 if (!ret_data || !ret_clock) { 821 lvds_vod_swing_conf = sn65dsi83_select_lvds_vod_swing(dev, lvds_vod_swing_data, 822 lvds_vod_swing_clk, ctx->lvds_term_conf[channel]); 823 if (lvds_vod_swing_conf < 0) { 824 ret = lvds_vod_swing_conf; 825 goto exit; 826 } 827 } 828 829 ctx->lvds_vod_swing_conf[channel] = lvds_vod_swing_conf; 830 ret = 0; 831exit: 832 of_node_put(endpoint); 833 return ret; 834} 835 836static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model) 837{ 838 struct drm_bridge *panel_bridge; 839 struct device *dev = ctx->dev; 840 int ret; 841 842 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_A); 843 if (ret < 0) 844 return ret; 845 846 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_B); 847 if (ret < 0) 848 return ret; 849 850 ctx->lvds_dual_link = false; 851 ctx->lvds_dual_link_even_odd_swap = false; 852 if (model != MODEL_SN65DSI83) { 853 struct device_node *port2, *port3; 854 int dual_link; 855 856 port2 = of_graph_get_port_by_id(dev->of_node, 2); 857 port3 = of_graph_get_port_by_id(dev->of_node, 3); 858 dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3); 859 of_node_put(port2); 860 of_node_put(port3); 861 862 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) { 863 ctx->lvds_dual_link = true; 864 /* Odd pixels to LVDS Channel A, even pixels to B */ 865 ctx->lvds_dual_link_even_odd_swap = false; 866 } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { 867 ctx->lvds_dual_link = true; 868 /* Even pixels to LVDS Channel A, odd pixels to B */ 869 ctx->lvds_dual_link_even_odd_swap = true; 870 } 871 } 872 873 panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0); 874 if (IS_ERR(panel_bridge)) 875 return dev_err_probe(dev, PTR_ERR(panel_bridge), "Failed to get panel bridge\n"); 876 877 ctx->panel_bridge = panel_bridge; 878 879 ctx->vcc = devm_regulator_get(dev, "vcc"); 880 if (IS_ERR(ctx->vcc)) 881 return dev_err_probe(dev, PTR_ERR(ctx->vcc), 882 "Failed to get supply 'vcc'\n"); 883 884 return 0; 885} 886 887static int sn65dsi83_host_attach(struct sn65dsi83 *ctx) 888{ 889 struct device *dev = ctx->dev; 890 struct device_node *host_node; 891 struct device_node *endpoint; 892 struct mipi_dsi_device *dsi; 893 struct mipi_dsi_host *host; 894 const struct mipi_dsi_device_info info = { 895 .type = "sn65dsi83", 896 .channel = 0, 897 .node = NULL, 898 }; 899 int dsi_lanes, ret; 900 901 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); 902 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4); 903 host_node = of_graph_get_remote_port_parent(endpoint); 904 host = of_find_mipi_dsi_host_by_node(host_node); 905 of_node_put(host_node); 906 of_node_put(endpoint); 907 908 if (!host) 909 return -EPROBE_DEFER; 910 911 if (dsi_lanes < 0) 912 return dsi_lanes; 913 914 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 915 if (IS_ERR(dsi)) 916 return dev_err_probe(dev, PTR_ERR(dsi), 917 "failed to create dsi device\n"); 918 919 ctx->dsi = dsi; 920 921 dsi->lanes = dsi_lanes; 922 dsi->format = MIPI_DSI_FMT_RGB888; 923 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 924 MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP | 925 MIPI_DSI_MODE_VIDEO_NO_HSA | MIPI_DSI_MODE_NO_EOT_PACKET; 926 927 ret = devm_mipi_dsi_attach(dev, dsi); 928 if (ret < 0) { 929 dev_err(dev, "failed to attach dsi to host: %d\n", ret); 930 return ret; 931 } 932 933 return 0; 934} 935 936static irqreturn_t sn65dsi83_irq(int irq, void *data) 937{ 938 struct sn65dsi83 *ctx = data; 939 940 sn65dsi83_handle_errors(ctx); 941 return IRQ_HANDLED; 942} 943 944static int sn65dsi83_probe(struct i2c_client *client) 945{ 946 const struct i2c_device_id *id = i2c_client_get_device_id(client); 947 struct device *dev = &client->dev; 948 enum sn65dsi83_model model; 949 struct sn65dsi83 *ctx; 950 int ret; 951 952 ctx = devm_drm_bridge_alloc(dev, struct sn65dsi83, bridge, &sn65dsi83_funcs); 953 if (IS_ERR(ctx)) 954 return PTR_ERR(ctx); 955 956 ctx->dev = dev; 957 INIT_WORK(&ctx->reset_work, sn65dsi83_reset_work); 958 INIT_DELAYED_WORK(&ctx->monitor_work, sn65dsi83_monitor_work); 959 960 if (dev->of_node) { 961 model = (enum sn65dsi83_model)(uintptr_t) 962 of_device_get_match_data(dev); 963 } else { 964 model = id->driver_data; 965 } 966 967 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ 968 ctx->enable_gpio = devm_gpiod_get_optional(ctx->dev, "enable", 969 GPIOD_OUT_LOW); 970 if (IS_ERR(ctx->enable_gpio)) 971 return dev_err_probe(dev, PTR_ERR(ctx->enable_gpio), "failed to get enable GPIO\n"); 972 973 usleep_range(10000, 11000); 974 975 ret = sn65dsi83_parse_dt(ctx, model); 976 if (ret) 977 return ret; 978 979 ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config); 980 if (IS_ERR(ctx->regmap)) 981 return dev_err_probe(dev, PTR_ERR(ctx->regmap), "failed to get regmap\n"); 982 983 if (client->irq) { 984 ctx->irq = client->irq; 985 ret = devm_request_threaded_irq(ctx->dev, ctx->irq, NULL, sn65dsi83_irq, 986 IRQF_ONESHOT, dev_name(ctx->dev), ctx); 987 if (ret) 988 return dev_err_probe(dev, ret, "failed to request irq\n"); 989 } 990 991 dev_set_drvdata(dev, ctx); 992 i2c_set_clientdata(client, ctx); 993 994 ctx->bridge.of_node = dev->of_node; 995 ctx->bridge.pre_enable_prev_first = true; 996 ctx->bridge.type = DRM_MODE_CONNECTOR_LVDS; 997 drm_bridge_add(&ctx->bridge); 998 999 ret = sn65dsi83_host_attach(ctx); 1000 if (ret) { 1001 dev_err_probe(dev, ret, "failed to attach DSI host\n"); 1002 goto err_remove_bridge; 1003 } 1004 1005 return 0; 1006 1007err_remove_bridge: 1008 drm_bridge_remove(&ctx->bridge); 1009 return ret; 1010} 1011 1012static void sn65dsi83_remove(struct i2c_client *client) 1013{ 1014 struct sn65dsi83 *ctx = i2c_get_clientdata(client); 1015 1016 drm_bridge_remove(&ctx->bridge); 1017} 1018 1019static const struct i2c_device_id sn65dsi83_id[] = { 1020 { "ti,sn65dsi83", MODEL_SN65DSI83 }, 1021 { "ti,sn65dsi84", MODEL_SN65DSI84 }, 1022 {}, 1023}; 1024MODULE_DEVICE_TABLE(i2c, sn65dsi83_id); 1025 1026static const struct of_device_id sn65dsi83_match_table[] = { 1027 { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 }, 1028 { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 }, 1029 {}, 1030}; 1031MODULE_DEVICE_TABLE(of, sn65dsi83_match_table); 1032 1033static struct i2c_driver sn65dsi83_driver = { 1034 .probe = sn65dsi83_probe, 1035 .remove = sn65dsi83_remove, 1036 .id_table = sn65dsi83_id, 1037 .driver = { 1038 .name = "sn65dsi83", 1039 .of_match_table = sn65dsi83_match_table, 1040 }, 1041}; 1042module_i2c_driver(sn65dsi83_driver); 1043 1044MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 1045MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver"); 1046MODULE_LICENSE("GPL v2");
~/
Read-only file preview.