tda998x_drv.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2012 Texas Instruments
   4 * Author: Rob Clark <robdclark@gmail.com>
   5 */
   6
   7#include <linux/component.h>
   8#include <linux/gpio/consumer.h>
   9#include <linux/hdmi.h>
  10#include <linux/i2c.h>
  11#include <linux/module.h>
  12#include <linux/platform_data/tda9950.h>
  13#include <linux/irq.h>
  14#include <sound/asoundef.h>
  15#include <sound/hdmi-codec.h>
  16
  17#include <drm/drm_atomic_helper.h>
  18#include <drm/drm_bridge.h>
  19#include <drm/drm_edid.h>
  20#include <drm/drm_of.h>
  21#include <drm/drm_print.h>
  22#include <drm/drm_probe_helper.h>
  23#include <drm/drm_simple_kms_helper.h>
  24
  25#include <media/cec-notifier.h>
  26
  27#include <dt-bindings/display/tda998x.h>
  28
  29#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  30
  31enum {
  32	AUDIO_ROUTE_I2S,
  33	AUDIO_ROUTE_SPDIF,
  34	AUDIO_ROUTE_NUM
  35};
  36
  37struct tda998x_audio_route {
  38	u8 ena_aclk;
  39	u8 mux_ap;
  40	u8 aip_clksel;
  41};
  42
  43struct tda998x_audio_settings {
  44	const struct tda998x_audio_route *route;
  45	struct hdmi_audio_infoframe cea;
  46	unsigned int sample_rate;
  47	u8 status[5];
  48	u8 ena_ap;
  49	u8 i2s_format;
  50	u8 cts_n;
  51};
  52
  53struct tda998x_priv {
  54	struct i2c_client *cec;
  55	struct i2c_client *hdmi;
  56	struct mutex mutex;
  57	u16 rev;
  58	u8 cec_addr;
  59	u8 current_page;
  60	bool is_on;
  61	bool supports_infoframes;
  62	bool sink_has_audio;
  63	enum hdmi_quantization_range rgb_quant_range;
  64	u8 vip_cntrl_0;
  65	u8 vip_cntrl_1;
  66	u8 vip_cntrl_2;
  67	unsigned long tmds_clock;
  68	struct tda998x_audio_settings audio;
  69
  70	struct platform_device *audio_pdev;
  71	struct mutex audio_mutex;
  72
  73	struct mutex edid_mutex;
  74	wait_queue_head_t wq_edid;
  75	volatile int wq_edid_wait;
  76
  77	struct work_struct detect_work;
  78	struct timer_list edid_delay_timer;
  79	wait_queue_head_t edid_delay_waitq;
  80	bool edid_delay_active;
  81
  82	struct drm_encoder encoder;
  83	struct drm_bridge bridge;
  84	struct drm_connector connector;
  85
  86	u8 audio_port_enable[AUDIO_ROUTE_NUM];
  87	struct tda9950_glue cec_glue;
  88	struct gpio_desc *calib;
  89	struct cec_notifier *cec_notify;
  90};
  91
  92#define conn_to_tda998x_priv(x) \
  93	container_of(x, struct tda998x_priv, connector)
  94#define enc_to_tda998x_priv(x) \
  95	container_of(x, struct tda998x_priv, encoder)
  96#define bridge_to_tda998x_priv(x) \
  97	container_of(x, struct tda998x_priv, bridge)
  98
  99/* The TDA9988 series of devices use a paged register scheme.. to simplify
 100 * things we encode the page # in upper bits of the register #.  To read/
 101 * write a given register, we need to make sure CURPAGE register is set
 102 * appropriately.  Which implies reads/writes are not atomic.  Fun!
 103 */
 104
 105#define REG(page, addr) (((page) << 8) | (addr))
 106#define REG2ADDR(reg)   ((reg) & 0xff)
 107#define REG2PAGE(reg)   (((reg) >> 8) & 0xff)
 108
 109#define REG_CURPAGE               0xff                /* write */
 110
 111
 112/* Page 00h: General Control */
 113#define REG_VERSION_LSB           REG(0x00, 0x00)     /* read */
 114#define REG_MAIN_CNTRL0           REG(0x00, 0x01)     /* read/write */
 115# define MAIN_CNTRL0_SR           (1 << 0)
 116# define MAIN_CNTRL0_DECS         (1 << 1)
 117# define MAIN_CNTRL0_DEHS         (1 << 2)
 118# define MAIN_CNTRL0_CECS         (1 << 3)
 119# define MAIN_CNTRL0_CEHS         (1 << 4)
 120# define MAIN_CNTRL0_SCALER       (1 << 7)
 121#define REG_VERSION_MSB           REG(0x00, 0x02)     /* read */
 122#define REG_SOFTRESET             REG(0x00, 0x0a)     /* write */
 123# define SOFTRESET_AUDIO          (1 << 0)
 124# define SOFTRESET_I2C_MASTER     (1 << 1)
 125#define REG_DDC_DISABLE           REG(0x00, 0x0b)     /* read/write */
 126#define REG_CCLK_ON               REG(0x00, 0x0c)     /* read/write */
 127#define REG_I2C_MASTER            REG(0x00, 0x0d)     /* read/write */
 128# define I2C_MASTER_DIS_MM        (1 << 0)
 129# define I2C_MASTER_DIS_FILT      (1 << 1)
 130# define I2C_MASTER_APP_STRT_LAT  (1 << 2)
 131#define REG_FEAT_POWERDOWN        REG(0x00, 0x0e)     /* read/write */
 132# define FEAT_POWERDOWN_PREFILT   BIT(0)
 133# define FEAT_POWERDOWN_CSC       BIT(1)
 134# define FEAT_POWERDOWN_SPDIF     (1 << 3)
 135#define REG_INT_FLAGS_0           REG(0x00, 0x0f)     /* read/write */
 136#define REG_INT_FLAGS_1           REG(0x00, 0x10)     /* read/write */
 137#define REG_INT_FLAGS_2           REG(0x00, 0x11)     /* read/write */
 138# define INT_FLAGS_2_EDID_BLK_RD  (1 << 1)
 139#define REG_ENA_ACLK              REG(0x00, 0x16)     /* read/write */
 140#define REG_ENA_VP_0              REG(0x00, 0x18)     /* read/write */
 141#define REG_ENA_VP_1              REG(0x00, 0x19)     /* read/write */
 142#define REG_ENA_VP_2              REG(0x00, 0x1a)     /* read/write */
 143#define REG_ENA_AP                REG(0x00, 0x1e)     /* read/write */
 144#define REG_VIP_CNTRL_0           REG(0x00, 0x20)     /* write */
 145# define VIP_CNTRL_0_MIRR_A       (1 << 7)
 146# define VIP_CNTRL_0_SWAP_A(x)    (((x) & 7) << 4)
 147# define VIP_CNTRL_0_MIRR_B       (1 << 3)
 148# define VIP_CNTRL_0_SWAP_B(x)    (((x) & 7) << 0)
 149#define REG_VIP_CNTRL_1           REG(0x00, 0x21)     /* write */
 150# define VIP_CNTRL_1_MIRR_C       (1 << 7)
 151# define VIP_CNTRL_1_SWAP_C(x)    (((x) & 7) << 4)
 152# define VIP_CNTRL_1_MIRR_D       (1 << 3)
 153# define VIP_CNTRL_1_SWAP_D(x)    (((x) & 7) << 0)
 154#define REG_VIP_CNTRL_2           REG(0x00, 0x22)     /* write */
 155# define VIP_CNTRL_2_MIRR_E       (1 << 7)
 156# define VIP_CNTRL_2_SWAP_E(x)    (((x) & 7) << 4)
 157# define VIP_CNTRL_2_MIRR_F       (1 << 3)
 158# define VIP_CNTRL_2_SWAP_F(x)    (((x) & 7) << 0)
 159#define REG_VIP_CNTRL_3           REG(0x00, 0x23)     /* write */
 160# define VIP_CNTRL_3_X_TGL        (1 << 0)
 161# define VIP_CNTRL_3_H_TGL        (1 << 1)
 162# define VIP_CNTRL_3_V_TGL        (1 << 2)
 163# define VIP_CNTRL_3_EMB          (1 << 3)
 164# define VIP_CNTRL_3_SYNC_DE      (1 << 4)
 165# define VIP_CNTRL_3_SYNC_HS      (1 << 5)
 166# define VIP_CNTRL_3_DE_INT       (1 << 6)
 167# define VIP_CNTRL_3_EDGE         (1 << 7)
 168#define REG_VIP_CNTRL_4           REG(0x00, 0x24)     /* write */
 169# define VIP_CNTRL_4_BLC(x)       (((x) & 3) << 0)
 170# define VIP_CNTRL_4_BLANKIT(x)   (((x) & 3) << 2)
 171# define VIP_CNTRL_4_CCIR656      (1 << 4)
 172# define VIP_CNTRL_4_656_ALT      (1 << 5)
 173# define VIP_CNTRL_4_TST_656      (1 << 6)
 174# define VIP_CNTRL_4_TST_PAT      (1 << 7)
 175#define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
 176# define VIP_CNTRL_5_CKCASE       (1 << 0)
 177# define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
 178#define REG_MUX_AP                REG(0x00, 0x26)     /* read/write */
 179# define MUX_AP_SELECT_I2S	  0x64
 180# define MUX_AP_SELECT_SPDIF	  0x40
 181#define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
 182#define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
 183# define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
 184# define MAT_CONTRL_MAT_BP        (1 << 2)
 185#define REG_VIDFORMAT             REG(0x00, 0xa0)     /* write */
 186#define REG_REFPIX_MSB            REG(0x00, 0xa1)     /* write */
 187#define REG_REFPIX_LSB            REG(0x00, 0xa2)     /* write */
 188#define REG_REFLINE_MSB           REG(0x00, 0xa3)     /* write */
 189#define REG_REFLINE_LSB           REG(0x00, 0xa4)     /* write */
 190#define REG_NPIX_MSB              REG(0x00, 0xa5)     /* write */
 191#define REG_NPIX_LSB              REG(0x00, 0xa6)     /* write */
 192#define REG_NLINE_MSB             REG(0x00, 0xa7)     /* write */
 193#define REG_NLINE_LSB             REG(0x00, 0xa8)     /* write */
 194#define REG_VS_LINE_STRT_1_MSB    REG(0x00, 0xa9)     /* write */
 195#define REG_VS_LINE_STRT_1_LSB    REG(0x00, 0xaa)     /* write */
 196#define REG_VS_PIX_STRT_1_MSB     REG(0x00, 0xab)     /* write */
 197#define REG_VS_PIX_STRT_1_LSB     REG(0x00, 0xac)     /* write */
 198#define REG_VS_LINE_END_1_MSB     REG(0x00, 0xad)     /* write */
 199#define REG_VS_LINE_END_1_LSB     REG(0x00, 0xae)     /* write */
 200#define REG_VS_PIX_END_1_MSB      REG(0x00, 0xaf)     /* write */
 201#define REG_VS_PIX_END_1_LSB      REG(0x00, 0xb0)     /* write */
 202#define REG_VS_LINE_STRT_2_MSB    REG(0x00, 0xb1)     /* write */
 203#define REG_VS_LINE_STRT_2_LSB    REG(0x00, 0xb2)     /* write */
 204#define REG_VS_PIX_STRT_2_MSB     REG(0x00, 0xb3)     /* write */
 205#define REG_VS_PIX_STRT_2_LSB     REG(0x00, 0xb4)     /* write */
 206#define REG_VS_LINE_END_2_MSB     REG(0x00, 0xb5)     /* write */
 207#define REG_VS_LINE_END_2_LSB     REG(0x00, 0xb6)     /* write */
 208#define REG_VS_PIX_END_2_MSB      REG(0x00, 0xb7)     /* write */
 209#define REG_VS_PIX_END_2_LSB      REG(0x00, 0xb8)     /* write */
 210#define REG_HS_PIX_START_MSB      REG(0x00, 0xb9)     /* write */
 211#define REG_HS_PIX_START_LSB      REG(0x00, 0xba)     /* write */
 212#define REG_HS_PIX_STOP_MSB       REG(0x00, 0xbb)     /* write */
 213#define REG_HS_PIX_STOP_LSB       REG(0x00, 0xbc)     /* write */
 214#define REG_VWIN_START_1_MSB      REG(0x00, 0xbd)     /* write */
 215#define REG_VWIN_START_1_LSB      REG(0x00, 0xbe)     /* write */
 216#define REG_VWIN_END_1_MSB        REG(0x00, 0xbf)     /* write */
 217#define REG_VWIN_END_1_LSB        REG(0x00, 0xc0)     /* write */
 218#define REG_VWIN_START_2_MSB      REG(0x00, 0xc1)     /* write */
 219#define REG_VWIN_START_2_LSB      REG(0x00, 0xc2)     /* write */
 220#define REG_VWIN_END_2_MSB        REG(0x00, 0xc3)     /* write */
 221#define REG_VWIN_END_2_LSB        REG(0x00, 0xc4)     /* write */
 222#define REG_DE_START_MSB          REG(0x00, 0xc5)     /* write */
 223#define REG_DE_START_LSB          REG(0x00, 0xc6)     /* write */
 224#define REG_DE_STOP_MSB           REG(0x00, 0xc7)     /* write */
 225#define REG_DE_STOP_LSB           REG(0x00, 0xc8)     /* write */
 226#define REG_TBG_CNTRL_0           REG(0x00, 0xca)     /* write */
 227# define TBG_CNTRL_0_TOP_TGL      (1 << 0)
 228# define TBG_CNTRL_0_TOP_SEL      (1 << 1)
 229# define TBG_CNTRL_0_DE_EXT       (1 << 2)
 230# define TBG_CNTRL_0_TOP_EXT      (1 << 3)
 231# define TBG_CNTRL_0_FRAME_DIS    (1 << 5)
 232# define TBG_CNTRL_0_SYNC_MTHD    (1 << 6)
 233# define TBG_CNTRL_0_SYNC_ONCE    (1 << 7)
 234#define REG_TBG_CNTRL_1           REG(0x00, 0xcb)     /* write */
 235# define TBG_CNTRL_1_H_TGL        (1 << 0)
 236# define TBG_CNTRL_1_V_TGL        (1 << 1)
 237# define TBG_CNTRL_1_TGL_EN       (1 << 2)
 238# define TBG_CNTRL_1_X_EXT        (1 << 3)
 239# define TBG_CNTRL_1_H_EXT        (1 << 4)
 240# define TBG_CNTRL_1_V_EXT        (1 << 5)
 241# define TBG_CNTRL_1_DWIN_DIS     (1 << 6)
 242#define REG_ENABLE_SPACE          REG(0x00, 0xd6)     /* write */
 243#define REG_HVF_CNTRL_0           REG(0x00, 0xe4)     /* write */
 244# define HVF_CNTRL_0_SM           (1 << 7)
 245# define HVF_CNTRL_0_RWB          (1 << 6)
 246# define HVF_CNTRL_0_PREFIL(x)    (((x) & 3) << 2)
 247# define HVF_CNTRL_0_INTPOL(x)    (((x) & 3) << 0)
 248#define REG_HVF_CNTRL_1           REG(0x00, 0xe5)     /* write */
 249# define HVF_CNTRL_1_FOR          (1 << 0)
 250# define HVF_CNTRL_1_YUVBLK       (1 << 1)
 251# define HVF_CNTRL_1_VQR(x)       (((x) & 3) << 2)
 252# define HVF_CNTRL_1_PAD(x)       (((x) & 3) << 4)
 253# define HVF_CNTRL_1_SEMI_PLANAR  (1 << 6)
 254#define REG_RPT_CNTRL             REG(0x00, 0xf0)     /* write */
 255# define RPT_CNTRL_REPEAT(x)      ((x) & 15)
 256#define REG_I2S_FORMAT            REG(0x00, 0xfc)     /* read/write */
 257# define I2S_FORMAT_PHILIPS       (0 << 0)
 258# define I2S_FORMAT_LEFT_J        (2 << 0)
 259# define I2S_FORMAT_RIGHT_J       (3 << 0)
 260#define REG_AIP_CLKSEL            REG(0x00, 0xfd)     /* write */
 261# define AIP_CLKSEL_AIP_SPDIF	  (0 << 3)
 262# define AIP_CLKSEL_AIP_I2S	  (1 << 3)
 263# define AIP_CLKSEL_FS_ACLK	  (0 << 0)
 264# define AIP_CLKSEL_FS_MCLK	  (1 << 0)
 265# define AIP_CLKSEL_FS_FS64SPDIF  (2 << 0)
 266
 267/* Page 02h: PLL settings */
 268#define REG_PLL_SERIAL_1          REG(0x02, 0x00)     /* read/write */
 269# define PLL_SERIAL_1_SRL_FDN     (1 << 0)
 270# define PLL_SERIAL_1_SRL_IZ(x)   (((x) & 3) << 1)
 271# define PLL_SERIAL_1_SRL_MAN_IZ  (1 << 6)
 272#define REG_PLL_SERIAL_2          REG(0x02, 0x01)     /* read/write */
 273# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
 274# define PLL_SERIAL_2_SRL_PR(x)   (((x) & 0xf) << 4)
 275#define REG_PLL_SERIAL_3          REG(0x02, 0x02)     /* read/write */
 276# define PLL_SERIAL_3_SRL_CCIR    (1 << 0)
 277# define PLL_SERIAL_3_SRL_DE      (1 << 2)
 278# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
 279#define REG_SERIALIZER            REG(0x02, 0x03)     /* read/write */
 280#define REG_BUFFER_OUT            REG(0x02, 0x04)     /* read/write */
 281#define REG_PLL_SCG1              REG(0x02, 0x05)     /* read/write */
 282#define REG_PLL_SCG2              REG(0x02, 0x06)     /* read/write */
 283#define REG_PLL_SCGN1             REG(0x02, 0x07)     /* read/write */
 284#define REG_PLL_SCGN2             REG(0x02, 0x08)     /* read/write */
 285#define REG_PLL_SCGR1             REG(0x02, 0x09)     /* read/write */
 286#define REG_PLL_SCGR2             REG(0x02, 0x0a)     /* read/write */
 287#define REG_AUDIO_DIV             REG(0x02, 0x0e)     /* read/write */
 288# define AUDIO_DIV_SERCLK_1       0
 289# define AUDIO_DIV_SERCLK_2       1
 290# define AUDIO_DIV_SERCLK_4       2
 291# define AUDIO_DIV_SERCLK_8       3
 292# define AUDIO_DIV_SERCLK_16      4
 293# define AUDIO_DIV_SERCLK_32      5
 294#define REG_SEL_CLK               REG(0x02, 0x11)     /* read/write */
 295# define SEL_CLK_SEL_CLK1         (1 << 0)
 296# define SEL_CLK_SEL_VRF_CLK(x)   (((x) & 3) << 1)
 297# define SEL_CLK_ENA_SC_CLK       (1 << 3)
 298#define REG_ANA_GENERAL           REG(0x02, 0x12)     /* read/write */
 299
 300
 301/* Page 09h: EDID Control */
 302#define REG_EDID_DATA_0           REG(0x09, 0x00)     /* read */
 303/* next 127 successive registers are the EDID block */
 304#define REG_EDID_CTRL             REG(0x09, 0xfa)     /* read/write */
 305#define REG_DDC_ADDR              REG(0x09, 0xfb)     /* read/write */
 306#define REG_DDC_OFFS              REG(0x09, 0xfc)     /* read/write */
 307#define REG_DDC_SEGM_ADDR         REG(0x09, 0xfd)     /* read/write */
 308#define REG_DDC_SEGM              REG(0x09, 0xfe)     /* read/write */
 309
 310
 311/* Page 10h: information frames and packets */
 312#define REG_IF1_HB0               REG(0x10, 0x20)     /* read/write */
 313#define REG_IF2_HB0               REG(0x10, 0x40)     /* read/write */
 314#define REG_IF3_HB0               REG(0x10, 0x60)     /* read/write */
 315#define REG_IF4_HB0               REG(0x10, 0x80)     /* read/write */
 316#define REG_IF5_HB0               REG(0x10, 0xa0)     /* read/write */
 317
 318
 319/* Page 11h: audio settings and content info packets */
 320#define REG_AIP_CNTRL_0           REG(0x11, 0x00)     /* read/write */
 321# define AIP_CNTRL_0_RST_FIFO     (1 << 0)
 322# define AIP_CNTRL_0_SWAP         (1 << 1)
 323# define AIP_CNTRL_0_LAYOUT       (1 << 2)
 324# define AIP_CNTRL_0_ACR_MAN      (1 << 5)
 325# define AIP_CNTRL_0_RST_CTS      (1 << 6)
 326#define REG_CA_I2S                REG(0x11, 0x01)     /* read/write */
 327# define CA_I2S_CA_I2S(x)         (((x) & 31) << 0)
 328# define CA_I2S_HBR_CHSTAT        (1 << 6)
 329#define REG_LATENCY_RD            REG(0x11, 0x04)     /* read/write */
 330#define REG_ACR_CTS_0             REG(0x11, 0x05)     /* read/write */
 331#define REG_ACR_CTS_1             REG(0x11, 0x06)     /* read/write */
 332#define REG_ACR_CTS_2             REG(0x11, 0x07)     /* read/write */
 333#define REG_ACR_N_0               REG(0x11, 0x08)     /* read/write */
 334#define REG_ACR_N_1               REG(0x11, 0x09)     /* read/write */
 335#define REG_ACR_N_2               REG(0x11, 0x0a)     /* read/write */
 336#define REG_CTS_N                 REG(0x11, 0x0c)     /* read/write */
 337# define CTS_N_K(x)               (((x) & 7) << 0)
 338# define CTS_N_M(x)               (((x) & 3) << 4)
 339#define REG_ENC_CNTRL             REG(0x11, 0x0d)     /* read/write */
 340# define ENC_CNTRL_RST_ENC        (1 << 0)
 341# define ENC_CNTRL_RST_SEL        (1 << 1)
 342# define ENC_CNTRL_CTL_CODE(x)    (((x) & 3) << 2)
 343#define REG_DIP_FLAGS             REG(0x11, 0x0e)     /* read/write */
 344# define DIP_FLAGS_ACR            (1 << 0)
 345# define DIP_FLAGS_GC             (1 << 1)
 346#define REG_DIP_IF_FLAGS          REG(0x11, 0x0f)     /* read/write */
 347# define DIP_IF_FLAGS_IF1         (1 << 1)
 348# define DIP_IF_FLAGS_IF2         (1 << 2)
 349# define DIP_IF_FLAGS_IF3         (1 << 3)
 350# define DIP_IF_FLAGS_IF4         (1 << 4)
 351# define DIP_IF_FLAGS_IF5         (1 << 5)
 352#define REG_CH_STAT_B(x)          REG(0x11, 0x14 + (x)) /* read/write */
 353
 354
 355/* Page 12h: HDCP and OTP */
 356#define REG_TX3                   REG(0x12, 0x9a)     /* read/write */
 357#define REG_TX4                   REG(0x12, 0x9b)     /* read/write */
 358# define TX4_PD_RAM               (1 << 1)
 359#define REG_TX33                  REG(0x12, 0xb8)     /* read/write */
 360# define TX33_HDMI                (1 << 1)
 361
 362
 363/* Page 13h: Gamut related metadata packets */
 364
 365
 366
 367/* CEC registers: (not paged)
 368 */
 369#define REG_CEC_INTSTATUS	  0xee		      /* read */
 370# define CEC_INTSTATUS_CEC	  (1 << 0)
 371# define CEC_INTSTATUS_HDMI	  (1 << 1)
 372#define REG_CEC_CAL_XOSC_CTRL1    0xf2
 373# define CEC_CAL_XOSC_CTRL1_ENA_CAL	BIT(0)
 374#define REG_CEC_DES_FREQ2         0xf5
 375# define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7)
 376#define REG_CEC_CLK               0xf6
 377# define CEC_CLK_FRO              0x11
 378#define REG_CEC_FRO_IM_CLK_CTRL   0xfb                /* read/write */
 379# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
 380# define CEC_FRO_IM_CLK_CTRL_ENA_OTP   (1 << 6)
 381# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
 382# define CEC_FRO_IM_CLK_CTRL_FRO_DIV   (1 << 0)
 383#define REG_CEC_RXSHPDINTENA	  0xfc		      /* read/write */
 384#define REG_CEC_RXSHPDINT	  0xfd		      /* read */
 385# define CEC_RXSHPDINT_RXSENS     BIT(0)
 386# define CEC_RXSHPDINT_HPD        BIT(1)
 387#define REG_CEC_RXSHPDLEV         0xfe                /* read */
 388# define CEC_RXSHPDLEV_RXSENS     (1 << 0)
 389# define CEC_RXSHPDLEV_HPD        (1 << 1)
 390
 391#define REG_CEC_ENAMODS           0xff                /* read/write */
 392# define CEC_ENAMODS_EN_CEC_CLK   (1 << 7)
 393# define CEC_ENAMODS_DIS_FRO      (1 << 6)
 394# define CEC_ENAMODS_DIS_CCLK     (1 << 5)
 395# define CEC_ENAMODS_EN_RXSENS    (1 << 2)
 396# define CEC_ENAMODS_EN_HDMI      (1 << 1)
 397# define CEC_ENAMODS_EN_CEC       (1 << 0)
 398
 399
 400/* Device versions: */
 401#define TDA9989N2                 0x0101
 402#define TDA19989                  0x0201
 403#define TDA19989N2                0x0202
 404#define TDA19988                  0x0301
 405
 406static void
 407cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
 408{
 409	u8 buf[] = {addr, val};
 410	struct i2c_msg msg = {
 411		.addr = priv->cec_addr,
 412		.len = 2,
 413		.buf = buf,
 414	};
 415	int ret;
 416
 417	ret = i2c_transfer(priv->hdmi->adapter, &msg, 1);
 418	if (ret < 0)
 419		dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n",
 420			ret, addr);
 421}
 422
 423static u8
 424cec_read(struct tda998x_priv *priv, u8 addr)
 425{
 426	u8 val;
 427	struct i2c_msg msg[2] = {
 428		{
 429			.addr = priv->cec_addr,
 430			.len = 1,
 431			.buf = &addr,
 432		}, {
 433			.addr = priv->cec_addr,
 434			.flags = I2C_M_RD,
 435			.len = 1,
 436			.buf = &val,
 437		},
 438	};
 439	int ret;
 440
 441	ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg));
 442	if (ret < 0) {
 443		dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n",
 444			ret, addr);
 445		val = 0;
 446	}
 447
 448	return val;
 449}
 450
 451static void cec_enamods(struct tda998x_priv *priv, u8 mods, bool enable)
 452{
 453	int val = cec_read(priv, REG_CEC_ENAMODS);
 454
 455	if (val < 0)
 456		return;
 457
 458	if (enable)
 459		val |= mods;
 460	else
 461		val &= ~mods;
 462
 463	cec_write(priv, REG_CEC_ENAMODS, val);
 464}
 465
 466static void tda998x_cec_set_calibration(struct tda998x_priv *priv, bool enable)
 467{
 468	if (enable) {
 469		u8 val;
 470
 471		cec_write(priv, 0xf3, 0xc0);
 472		cec_write(priv, 0xf4, 0xd4);
 473
 474		/* Enable automatic calibration mode */
 475		val = cec_read(priv, REG_CEC_DES_FREQ2);
 476		val &= ~CEC_DES_FREQ2_DIS_AUTOCAL;
 477		cec_write(priv, REG_CEC_DES_FREQ2, val);
 478
 479		/* Enable free running oscillator */
 480		cec_write(priv, REG_CEC_CLK, CEC_CLK_FRO);
 481		cec_enamods(priv, CEC_ENAMODS_DIS_FRO, false);
 482
 483		cec_write(priv, REG_CEC_CAL_XOSC_CTRL1,
 484			  CEC_CAL_XOSC_CTRL1_ENA_CAL);
 485	} else {
 486		cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0);
 487	}
 488}
 489
 490/*
 491 * Calibration for the internal oscillator: we need to set calibration mode,
 492 * and then pulse the IRQ line low for a 10ms ± 1% period.
 493 */
 494static void tda998x_cec_calibration(struct tda998x_priv *priv)
 495{
 496	struct gpio_desc *calib = priv->calib;
 497
 498	mutex_lock(&priv->edid_mutex);
 499	if (priv->hdmi->irq > 0)
 500		disable_irq(priv->hdmi->irq);
 501	gpiod_direction_output(calib, 1);
 502	tda998x_cec_set_calibration(priv, true);
 503
 504	local_irq_disable();
 505	gpiod_set_value(calib, 0);
 506	mdelay(10);
 507	gpiod_set_value(calib, 1);
 508	local_irq_enable();
 509
 510	tda998x_cec_set_calibration(priv, false);
 511	gpiod_direction_input(calib);
 512	if (priv->hdmi->irq > 0)
 513		enable_irq(priv->hdmi->irq);
 514	mutex_unlock(&priv->edid_mutex);
 515}
 516
 517static int tda998x_cec_hook_init(void *data)
 518{
 519	struct tda998x_priv *priv = data;
 520	struct gpio_desc *calib;
 521
 522	calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS);
 523	if (IS_ERR(calib)) {
 524		dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n",
 525			 PTR_ERR(calib));
 526		return PTR_ERR(calib);
 527	}
 528
 529	priv->calib = calib;
 530
 531	return 0;
 532}
 533
 534static void tda998x_cec_hook_exit(void *data)
 535{
 536	struct tda998x_priv *priv = data;
 537
 538	gpiod_put(priv->calib);
 539	priv->calib = NULL;
 540}
 541
 542static int tda998x_cec_hook_open(void *data)
 543{
 544	struct tda998x_priv *priv = data;
 545
 546	cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, true);
 547	tda998x_cec_calibration(priv);
 548
 549	return 0;
 550}
 551
 552static void tda998x_cec_hook_release(void *data)
 553{
 554	struct tda998x_priv *priv = data;
 555
 556	cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, false);
 557}
 558
 559static int
 560set_page(struct tda998x_priv *priv, u16 reg)
 561{
 562	if (REG2PAGE(reg) != priv->current_page) {
 563		struct i2c_client *client = priv->hdmi;
 564		u8 buf[] = {
 565				REG_CURPAGE, REG2PAGE(reg)
 566		};
 567		int ret = i2c_master_send(client, buf, sizeof(buf));
 568		if (ret < 0) {
 569			dev_err(&client->dev, "%s %04x err %d\n", __func__,
 570					reg, ret);
 571			return ret;
 572		}
 573
 574		priv->current_page = REG2PAGE(reg);
 575	}
 576	return 0;
 577}
 578
 579static int
 580reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
 581{
 582	struct i2c_client *client = priv->hdmi;
 583	u8 addr = REG2ADDR(reg);
 584	int ret;
 585
 586	mutex_lock(&priv->mutex);
 587	ret = set_page(priv, reg);
 588	if (ret < 0)
 589		goto out;
 590
 591	ret = i2c_master_send(client, &addr, sizeof(addr));
 592	if (ret < 0)
 593		goto fail;
 594
 595	ret = i2c_master_recv(client, buf, cnt);
 596	if (ret < 0)
 597		goto fail;
 598
 599	goto out;
 600
 601fail:
 602	dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
 603out:
 604	mutex_unlock(&priv->mutex);
 605	return ret;
 606}
 607
 608#define MAX_WRITE_RANGE_BUF 32
 609
 610static void
 611reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
 612{
 613	struct i2c_client *client = priv->hdmi;
 614	/* This is the maximum size of the buffer passed in */
 615	u8 buf[MAX_WRITE_RANGE_BUF + 1];
 616	int ret;
 617
 618	if (cnt > MAX_WRITE_RANGE_BUF) {
 619		dev_err(&client->dev, "Fixed write buffer too small (%d)\n",
 620				MAX_WRITE_RANGE_BUF);
 621		return;
 622	}
 623
 624	buf[0] = REG2ADDR(reg);
 625	memcpy(&buf[1], p, cnt);
 626
 627	mutex_lock(&priv->mutex);
 628	ret = set_page(priv, reg);
 629	if (ret < 0)
 630		goto out;
 631
 632	ret = i2c_master_send(client, buf, cnt + 1);
 633	if (ret < 0)
 634		dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 635out:
 636	mutex_unlock(&priv->mutex);
 637}
 638
 639static int
 640reg_read(struct tda998x_priv *priv, u16 reg)
 641{
 642	u8 val = 0;
 643	int ret;
 644
 645	ret = reg_read_range(priv, reg, &val, sizeof(val));
 646	if (ret < 0)
 647		return ret;
 648	return val;
 649}
 650
 651static void
 652reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
 653{
 654	struct i2c_client *client = priv->hdmi;
 655	u8 buf[] = {REG2ADDR(reg), val};
 656	int ret;
 657
 658	mutex_lock(&priv->mutex);
 659	ret = set_page(priv, reg);
 660	if (ret < 0)
 661		goto out;
 662
 663	ret = i2c_master_send(client, buf, sizeof(buf));
 664	if (ret < 0)
 665		dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 666out:
 667	mutex_unlock(&priv->mutex);
 668}
 669
 670static void
 671reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
 672{
 673	struct i2c_client *client = priv->hdmi;
 674	u8 buf[] = {REG2ADDR(reg), val >> 8, val};
 675	int ret;
 676
 677	mutex_lock(&priv->mutex);
 678	ret = set_page(priv, reg);
 679	if (ret < 0)
 680		goto out;
 681
 682	ret = i2c_master_send(client, buf, sizeof(buf));
 683	if (ret < 0)
 684		dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 685out:
 686	mutex_unlock(&priv->mutex);
 687}
 688
 689static void
 690reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
 691{
 692	int old_val;
 693
 694	old_val = reg_read(priv, reg);
 695	if (old_val >= 0)
 696		reg_write(priv, reg, old_val | val);
 697}
 698
 699static void
 700reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
 701{
 702	int old_val;
 703
 704	old_val = reg_read(priv, reg);
 705	if (old_val >= 0)
 706		reg_write(priv, reg, old_val & ~val);
 707}
 708
 709static void
 710tda998x_reset(struct tda998x_priv *priv)
 711{
 712	/* reset audio and i2c master: */
 713	reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
 714	msleep(50);
 715	reg_write(priv, REG_SOFTRESET, 0);
 716	msleep(50);
 717
 718	/* reset transmitter: */
 719	reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 720	reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 721
 722	/* PLL registers common configuration */
 723	reg_write(priv, REG_PLL_SERIAL_1, 0x00);
 724	reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
 725	reg_write(priv, REG_PLL_SERIAL_3, 0x00);
 726	reg_write(priv, REG_SERIALIZER,   0x00);
 727	reg_write(priv, REG_BUFFER_OUT,   0x00);
 728	reg_write(priv, REG_PLL_SCG1,     0x00);
 729	reg_write(priv, REG_AUDIO_DIV,    AUDIO_DIV_SERCLK_8);
 730	reg_write(priv, REG_SEL_CLK,      SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 731	reg_write(priv, REG_PLL_SCGN1,    0xfa);
 732	reg_write(priv, REG_PLL_SCGN2,    0x00);
 733	reg_write(priv, REG_PLL_SCGR1,    0x5b);
 734	reg_write(priv, REG_PLL_SCGR2,    0x00);
 735	reg_write(priv, REG_PLL_SCG2,     0x10);
 736
 737	/* Write the default value MUX register */
 738	reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
 739}
 740
 741/*
 742 * The TDA998x has a problem when trying to read the EDID close to a
 743 * HPD assertion: it needs a delay of 100ms to avoid timing out while
 744 * trying to read EDID data.
 745 *
 746 * However, tda998x_connector_get_modes() may be called at any moment
 747 * after tda998x_connector_detect() indicates that we are connected, so
 748 * we need to delay probing modes in tda998x_connector_get_modes() after
 749 * we have seen a HPD inactive->active transition.  This code implements
 750 * that delay.
 751 */
 752static void tda998x_edid_delay_done(struct timer_list *t)
 753{
 754	struct tda998x_priv *priv = timer_container_of(priv, t,
 755						       edid_delay_timer);
 756
 757	priv->edid_delay_active = false;
 758	wake_up(&priv->edid_delay_waitq);
 759	schedule_work(&priv->detect_work);
 760}
 761
 762static void tda998x_edid_delay_start(struct tda998x_priv *priv)
 763{
 764	priv->edid_delay_active = true;
 765	mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
 766}
 767
 768static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
 769{
 770	return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
 771}
 772
 773/*
 774 * We need to run the KMS hotplug event helper outside of our threaded
 775 * interrupt routine as this can call back into our get_modes method,
 776 * which will want to make use of interrupts.
 777 */
 778static void tda998x_detect_work(struct work_struct *work)
 779{
 780	struct tda998x_priv *priv =
 781		container_of(work, struct tda998x_priv, detect_work);
 782	struct drm_device *dev = priv->connector.dev;
 783
 784	if (dev)
 785		drm_kms_helper_hotplug_event(dev);
 786}
 787
 788/*
 789 * only 2 interrupts may occur: screen plug/unplug and EDID read
 790 */
 791static irqreturn_t tda998x_irq_thread(int irq, void *data)
 792{
 793	struct tda998x_priv *priv = data;
 794	u8 sta, cec, lvl, flag0, flag1, flag2;
 795	bool handled = false;
 796
 797	sta = cec_read(priv, REG_CEC_INTSTATUS);
 798	if (sta & CEC_INTSTATUS_HDMI) {
 799		cec = cec_read(priv, REG_CEC_RXSHPDINT);
 800		lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
 801		flag0 = reg_read(priv, REG_INT_FLAGS_0);
 802		flag1 = reg_read(priv, REG_INT_FLAGS_1);
 803		flag2 = reg_read(priv, REG_INT_FLAGS_2);
 804		DRM_DEBUG_DRIVER(
 805			"tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
 806			sta, cec, lvl, flag0, flag1, flag2);
 807
 808		if (cec & CEC_RXSHPDINT_HPD) {
 809			if (lvl & CEC_RXSHPDLEV_HPD) {
 810				tda998x_edid_delay_start(priv);
 811			} else {
 812				schedule_work(&priv->detect_work);
 813				cec_notifier_phys_addr_invalidate(
 814						priv->cec_notify);
 815			}
 816
 817			handled = true;
 818		}
 819
 820		if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
 821			priv->wq_edid_wait = 0;
 822			wake_up(&priv->wq_edid);
 823			handled = true;
 824		}
 825	}
 826
 827	return IRQ_RETVAL(handled);
 828}
 829
 830static void
 831tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
 832		 union hdmi_infoframe *frame)
 833{
 834	u8 buf[MAX_WRITE_RANGE_BUF];
 835	ssize_t len;
 836
 837	len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
 838	if (len < 0) {
 839		dev_err(&priv->hdmi->dev,
 840			"hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
 841			frame->any.type, len);
 842		return;
 843	}
 844
 845	reg_clear(priv, REG_DIP_IF_FLAGS, bit);
 846	reg_write_range(priv, addr, buf, len);
 847	reg_set(priv, REG_DIP_IF_FLAGS, bit);
 848}
 849
 850static void tda998x_write_aif(struct tda998x_priv *priv,
 851			      const struct hdmi_audio_infoframe *cea)
 852{
 853	union hdmi_infoframe frame;
 854
 855	frame.audio = *cea;
 856
 857	tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
 858}
 859
 860static void
 861tda998x_write_avi(struct tda998x_priv *priv, const struct drm_display_mode *mode)
 862{
 863	union hdmi_infoframe frame;
 864
 865	drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 866						 &priv->connector, mode);
 867	frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
 868	drm_hdmi_avi_infoframe_quant_range(&frame.avi, &priv->connector, mode,
 869					   priv->rgb_quant_range);
 870
 871	tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
 872}
 873
 874static void tda998x_write_vsi(struct tda998x_priv *priv,
 875			      const struct drm_display_mode *mode)
 876{
 877	union hdmi_infoframe frame;
 878
 879	if (drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 880							&priv->connector,
 881							mode))
 882		reg_clear(priv, REG_DIP_IF_FLAGS, DIP_IF_FLAGS_IF1);
 883	else
 884		tda998x_write_if(priv, DIP_IF_FLAGS_IF1, REG_IF1_HB0, &frame);
 885}
 886
 887/* Audio support */
 888
 889static const struct tda998x_audio_route tda998x_audio_route[AUDIO_ROUTE_NUM] = {
 890	[AUDIO_ROUTE_I2S] = {
 891		.ena_aclk = 1,
 892		.mux_ap = MUX_AP_SELECT_I2S,
 893		.aip_clksel = AIP_CLKSEL_AIP_I2S | AIP_CLKSEL_FS_ACLK,
 894	},
 895	[AUDIO_ROUTE_SPDIF] = {
 896		.ena_aclk = 0,
 897		.mux_ap = MUX_AP_SELECT_SPDIF,
 898		.aip_clksel = AIP_CLKSEL_AIP_SPDIF | AIP_CLKSEL_FS_FS64SPDIF,
 899	},
 900};
 901
 902/* Configure the TDA998x audio data and clock routing. */
 903static int tda998x_derive_routing(struct tda998x_priv *priv,
 904				  struct tda998x_audio_settings *s,
 905				  unsigned int route)
 906{
 907	s->route = &tda998x_audio_route[route];
 908	s->ena_ap = priv->audio_port_enable[route];
 909	if (s->ena_ap == 0) {
 910		dev_err(&priv->hdmi->dev, "no audio configuration found\n");
 911		return -EINVAL;
 912	}
 913
 914	return 0;
 915}
 916
 917/*
 918 * The audio clock divisor register controls a divider producing Audio_Clk_Out
 919 * from SERclk by dividing it by 2^n where 0 <= n <= 5.  We don't know what
 920 * Audio_Clk_Out or SERclk are. We guess SERclk is the same as TMDS clock.
 921 *
 922 * It seems that Audio_Clk_Out must be the smallest value that is greater
 923 * than 128*fs, otherwise audio does not function. There is some suggestion
 924 * that 126*fs is a better value.
 925 */
 926static u8 tda998x_get_adiv(struct tda998x_priv *priv, unsigned int fs)
 927{
 928	unsigned long min_audio_clk = fs * 128;
 929	unsigned long ser_clk = priv->tmds_clock * 1000;
 930	u8 adiv;
 931
 932	for (adiv = AUDIO_DIV_SERCLK_32; adiv != AUDIO_DIV_SERCLK_1; adiv--)
 933		if (ser_clk > min_audio_clk << adiv)
 934			break;
 935
 936	dev_dbg(&priv->hdmi->dev,
 937		"ser_clk=%luHz fs=%uHz min_aclk=%luHz adiv=%d\n",
 938		ser_clk, fs, min_audio_clk, adiv);
 939
 940	return adiv;
 941}
 942
 943/*
 944 * In auto-CTS mode, the TDA998x uses a "measured time stamp" counter to
 945 * generate the CTS value.  It appears that the "measured time stamp" is
 946 * the number of TDMS clock cycles within a number of audio input clock
 947 * cycles defined by the k and N parameters defined below, in a similar
 948 * way to that which is set out in the CTS generation in the HDMI spec.
 949 *
 950 *  tmdsclk ----> mts -> /m ---> CTS
 951 *                 ^
 952 *  sclk -> /k -> /N
 953 *
 954 * CTS = mts / m, where m is 2^M.
 955 * /k is a divider based on the K value below, K+1 for K < 4, or 8 for K >= 4
 956 * /N is a divider based on the HDMI specified N value.
 957 *
 958 * This produces the following equation:
 959 *  CTS = tmds_clock * k * N / (sclk * m)
 960 *
 961 * When combined with the sink-side equation, and realising that sclk is
 962 * bclk_ratio * fs, we end up with:
 963 *  k = m * bclk_ratio / 128.
 964 *
 965 * Note: S/PDIF always uses a bclk_ratio of 64.
 966 */
 967static int tda998x_derive_cts_n(struct tda998x_priv *priv,
 968				struct tda998x_audio_settings *settings,
 969				unsigned int ratio)
 970{
 971	switch (ratio) {
 972	case 16:
 973		settings->cts_n = CTS_N_M(3) | CTS_N_K(0);
 974		break;
 975	case 32:
 976		settings->cts_n = CTS_N_M(3) | CTS_N_K(1);
 977		break;
 978	case 48:
 979		settings->cts_n = CTS_N_M(3) | CTS_N_K(2);
 980		break;
 981	case 64:
 982		settings->cts_n = CTS_N_M(3) | CTS_N_K(3);
 983		break;
 984	case 128:
 985		settings->cts_n = CTS_N_M(0) | CTS_N_K(0);
 986		break;
 987	default:
 988		dev_err(&priv->hdmi->dev, "unsupported bclk ratio %ufs\n",
 989			ratio);
 990		return -EINVAL;
 991	}
 992	return 0;
 993}
 994
 995static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
 996{
 997	if (on) {
 998		reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 999		reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
1000		reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1001	} else {
1002		reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1003	}
1004}
1005
1006static void tda998x_configure_audio(struct tda998x_priv *priv)
1007{
1008	const struct tda998x_audio_settings *settings = &priv->audio;
1009	u8 buf[6], adiv;
1010	u32 n;
1011
1012	/* If audio is not configured, there is nothing to do. */
1013	if (settings->ena_ap == 0)
1014		return;
1015
1016	adiv = tda998x_get_adiv(priv, settings->sample_rate);
1017
1018	/* Enable audio ports */
1019	reg_write(priv, REG_ENA_AP, settings->ena_ap);
1020	reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk);
1021	reg_write(priv, REG_MUX_AP, settings->route->mux_ap);
1022	reg_write(priv, REG_I2S_FORMAT, settings->i2s_format);
1023	reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel);
1024	reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
1025					AIP_CNTRL_0_ACR_MAN);	/* auto CTS */
1026	reg_write(priv, REG_CTS_N, settings->cts_n);
1027	reg_write(priv, REG_AUDIO_DIV, adiv);
1028
1029	/*
1030	 * This is the approximate value of N, which happens to be
1031	 * the recommended values for non-coherent clocks.
1032	 */
1033	n = 128 * settings->sample_rate / 1000;
1034
1035	/* Write the CTS and N values */
1036	buf[0] = 0x44;
1037	buf[1] = 0x42;
1038	buf[2] = 0x01;
1039	buf[3] = n;
1040	buf[4] = n >> 8;
1041	buf[5] = n >> 16;
1042	reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
1043
1044	/* Reset CTS generator */
1045	reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1046	reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1047
1048	/* Write the channel status
1049	 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
1050	 * there is a separate register for each I2S wire.
1051	 */
1052	buf[0] = settings->status[0];
1053	buf[1] = settings->status[1];
1054	buf[2] = settings->status[3];
1055	buf[3] = settings->status[4];
1056	reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
1057
1058	tda998x_audio_mute(priv, true);
1059	msleep(20);
1060	tda998x_audio_mute(priv, false);
1061
1062	tda998x_write_aif(priv, &settings->cea);
1063}
1064
1065static int tda998x_audio_hw_params(struct device *dev, void *data,
1066				   struct hdmi_codec_daifmt *daifmt,
1067				   struct hdmi_codec_params *params)
1068{
1069	struct tda998x_priv *priv = dev_get_drvdata(dev);
1070	unsigned int bclk_ratio;
1071	bool spdif = daifmt->fmt == HDMI_SPDIF;
1072	int ret;
1073	struct tda998x_audio_settings audio = {
1074		.sample_rate = params->sample_rate,
1075		.cea = params->cea,
1076	};
1077
1078	memcpy(audio.status, params->iec.status,
1079	       min(sizeof(audio.status), sizeof(params->iec.status)));
1080
1081	switch (daifmt->fmt) {
1082	case HDMI_I2S:
1083		audio.i2s_format = I2S_FORMAT_PHILIPS;
1084		break;
1085	case HDMI_LEFT_J:
1086		audio.i2s_format = I2S_FORMAT_LEFT_J;
1087		break;
1088	case HDMI_RIGHT_J:
1089		audio.i2s_format = I2S_FORMAT_RIGHT_J;
1090		break;
1091	case HDMI_SPDIF:
1092		audio.i2s_format = 0;
1093		break;
1094	default:
1095		dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
1096		return -EINVAL;
1097	}
1098
1099	if (!spdif &&
1100	    (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
1101	     daifmt->bit_clk_provider || daifmt->frame_clk_provider)) {
1102		dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1103			daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1104			daifmt->bit_clk_provider,
1105			daifmt->frame_clk_provider);
1106		return -EINVAL;
1107	}
1108
1109	ret = tda998x_derive_routing(priv, &audio, AUDIO_ROUTE_I2S + spdif);
1110	if (ret < 0)
1111		return ret;
1112
1113	bclk_ratio = spdif ? 64 : params->sample_width * 2;
1114	ret = tda998x_derive_cts_n(priv, &audio, bclk_ratio);
1115	if (ret < 0)
1116		return ret;
1117
1118	mutex_lock(&priv->audio_mutex);
1119	priv->audio = audio;
1120	if (priv->supports_infoframes && priv->sink_has_audio)
1121		tda998x_configure_audio(priv);
1122	mutex_unlock(&priv->audio_mutex);
1123
1124	return 0;
1125}
1126
1127static void tda998x_audio_shutdown(struct device *dev, void *data)
1128{
1129	struct tda998x_priv *priv = dev_get_drvdata(dev);
1130
1131	mutex_lock(&priv->audio_mutex);
1132
1133	reg_write(priv, REG_ENA_AP, 0);
1134	priv->audio.ena_ap = 0;
1135
1136	mutex_unlock(&priv->audio_mutex);
1137}
1138
1139static int tda998x_audio_mute_stream(struct device *dev, void *data,
1140				     bool enable, int direction)
1141{
1142	struct tda998x_priv *priv = dev_get_drvdata(dev);
1143
1144	mutex_lock(&priv->audio_mutex);
1145
1146	tda998x_audio_mute(priv, enable);
1147
1148	mutex_unlock(&priv->audio_mutex);
1149	return 0;
1150}
1151
1152static int tda998x_audio_get_eld(struct device *dev, void *data,
1153				 uint8_t *buf, size_t len)
1154{
1155	struct tda998x_priv *priv = dev_get_drvdata(dev);
1156
1157	mutex_lock(&priv->audio_mutex);
1158	memcpy(buf, priv->connector.eld,
1159	       min(sizeof(priv->connector.eld), len));
1160	mutex_unlock(&priv->audio_mutex);
1161
1162	return 0;
1163}
1164
1165static const struct hdmi_codec_ops audio_codec_ops = {
1166	.hw_params = tda998x_audio_hw_params,
1167	.audio_shutdown = tda998x_audio_shutdown,
1168	.mute_stream = tda998x_audio_mute_stream,
1169	.get_eld = tda998x_audio_get_eld,
1170};
1171
1172static int tda998x_audio_codec_init(struct tda998x_priv *priv,
1173				    struct device *dev)
1174{
1175	struct hdmi_codec_pdata codec_data = {
1176		.ops = &audio_codec_ops,
1177		.max_i2s_channels = 2,
1178		.no_i2s_capture = 1,
1179		.no_spdif_capture = 1,
1180		.no_capture_mute = 1,
1181	};
1182
1183	if (priv->audio_port_enable[AUDIO_ROUTE_I2S])
1184		codec_data.i2s = 1;
1185	if (priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1186		codec_data.spdif = 1;
1187
1188	priv->audio_pdev = platform_device_register_data(
1189		dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1190		&codec_data, sizeof(codec_data));
1191
1192	return PTR_ERR_OR_ZERO(priv->audio_pdev);
1193}
1194
1195/* DRM connector functions */
1196
1197static enum drm_connector_status
1198tda998x_connector_detect(struct drm_connector *connector, bool force)
1199{
1200	struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1201	u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1202
1203	return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1204			connector_status_disconnected;
1205}
1206
1207static void tda998x_connector_destroy(struct drm_connector *connector)
1208{
1209	drm_connector_cleanup(connector);
1210}
1211
1212static const struct drm_connector_funcs tda998x_connector_funcs = {
1213	.reset = drm_atomic_helper_connector_reset,
1214	.fill_modes = drm_helper_probe_single_connector_modes,
1215	.detect = tda998x_connector_detect,
1216	.destroy = tda998x_connector_destroy,
1217	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1218	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1219};
1220
1221static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1222{
1223	struct tda998x_priv *priv = data;
1224	u8 offset, segptr;
1225	int ret, i;
1226
1227	offset = (blk & 1) ? 128 : 0;
1228	segptr = blk / 2;
1229
1230	mutex_lock(&priv->edid_mutex);
1231
1232	reg_write(priv, REG_DDC_ADDR, 0xa0);
1233	reg_write(priv, REG_DDC_OFFS, offset);
1234	reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1235	reg_write(priv, REG_DDC_SEGM, segptr);
1236
1237	/* enable reading EDID: */
1238	priv->wq_edid_wait = 1;
1239	reg_write(priv, REG_EDID_CTRL, 0x1);
1240
1241	/* flag must be cleared by sw: */
1242	reg_write(priv, REG_EDID_CTRL, 0x0);
1243
1244	/* wait for block read to complete: */
1245	if (priv->hdmi->irq) {
1246		i = wait_event_timeout(priv->wq_edid,
1247					!priv->wq_edid_wait,
1248					msecs_to_jiffies(100));
1249		if (i < 0) {
1250			dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1251			ret = i;
1252			goto failed;
1253		}
1254	} else {
1255		for (i = 100; i > 0; i--) {
1256			msleep(1);
1257			ret = reg_read(priv, REG_INT_FLAGS_2);
1258			if (ret < 0)
1259				goto failed;
1260			if (ret & INT_FLAGS_2_EDID_BLK_RD)
1261				break;
1262		}
1263	}
1264
1265	if (i == 0) {
1266		dev_err(&priv->hdmi->dev, "read edid timeout\n");
1267		ret = -ETIMEDOUT;
1268		goto failed;
1269	}
1270
1271	ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1272	if (ret != length) {
1273		dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1274			blk, ret);
1275		goto failed;
1276	}
1277
1278	ret = 0;
1279
1280 failed:
1281	mutex_unlock(&priv->edid_mutex);
1282	return ret;
1283}
1284
1285static int tda998x_connector_get_modes(struct drm_connector *connector)
1286{
1287	struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1288	const struct drm_edid *drm_edid;
1289	int n;
1290
1291	/*
1292	 * If we get killed while waiting for the HPD timeout, return
1293	 * no modes found: we are not in a restartable path, so we
1294	 * can't handle signals gracefully.
1295	 */
1296	if (tda998x_edid_delay_wait(priv))
1297		return 0;
1298
1299	if (priv->rev == TDA19988)
1300		reg_clear(priv, REG_TX4, TX4_PD_RAM);
1301
1302	drm_edid = drm_edid_read_custom(connector, read_edid_block, priv);
1303
1304	if (priv->rev == TDA19988)
1305		reg_set(priv, REG_TX4, TX4_PD_RAM);
1306
1307	drm_edid_connector_update(connector, drm_edid);
1308	cec_notifier_set_phys_addr(priv->cec_notify,
1309				   connector->display_info.source_physical_address);
1310
1311	if (!drm_edid) {
1312		dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1313		return 0;
1314	}
1315
1316	mutex_lock(&priv->audio_mutex);
1317	n = drm_edid_connector_add_modes(connector);
1318	priv->sink_has_audio = connector->display_info.has_audio;
1319	mutex_unlock(&priv->audio_mutex);
1320
1321	drm_edid_free(drm_edid);
1322
1323	return n;
1324}
1325
1326static struct drm_encoder *
1327tda998x_connector_best_encoder(struct drm_connector *connector)
1328{
1329	struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1330
1331	return priv->bridge.encoder;
1332}
1333
1334static
1335const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1336	.get_modes = tda998x_connector_get_modes,
1337	.best_encoder = tda998x_connector_best_encoder,
1338};
1339
1340static int tda998x_connector_init(struct tda998x_priv *priv,
1341				  struct drm_device *drm)
1342{
1343	struct drm_connector *connector = &priv->connector;
1344	int ret;
1345
1346	connector->interlace_allowed = 1;
1347
1348	if (priv->hdmi->irq)
1349		connector->polled = DRM_CONNECTOR_POLL_HPD;
1350	else
1351		connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1352			DRM_CONNECTOR_POLL_DISCONNECT;
1353
1354	drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1355	ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1356				 DRM_MODE_CONNECTOR_HDMIA);
1357	if (ret)
1358		return ret;
1359
1360	drm_connector_attach_encoder(&priv->connector,
1361				     priv->bridge.encoder);
1362
1363	return 0;
1364}
1365
1366/* DRM bridge functions */
1367
1368static int tda998x_bridge_attach(struct drm_bridge *bridge,
1369				 struct drm_encoder *encoder,
1370				 enum drm_bridge_attach_flags flags)
1371{
1372	struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1373
1374	if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
1375		DRM_ERROR("Fix bridge driver to make connector optional!");
1376		return -EINVAL;
1377	}
1378
1379	return tda998x_connector_init(priv, bridge->dev);
1380}
1381
1382static void tda998x_bridge_detach(struct drm_bridge *bridge)
1383{
1384	struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1385
1386	drm_connector_cleanup(&priv->connector);
1387}
1388
1389static enum drm_mode_status tda998x_bridge_mode_valid(struct drm_bridge *bridge,
1390				     const struct drm_display_info *info,
1391				     const struct drm_display_mode *mode)
1392{
1393	/* TDA19988 dotclock can go up to 165MHz */
1394	struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1395
1396	if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1397		return MODE_CLOCK_HIGH;
1398	if (mode->htotal >= BIT(13))
1399		return MODE_BAD_HVALUE;
1400	if (mode->vtotal >= BIT(11))
1401		return MODE_BAD_VVALUE;
1402	return MODE_OK;
1403}
1404
1405static void tda998x_bridge_enable(struct drm_bridge *bridge)
1406{
1407	struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1408
1409	if (!priv->is_on) {
1410		/* enable video ports, audio will be enabled later */
1411		reg_write(priv, REG_ENA_VP_0, 0xff);
1412		reg_write(priv, REG_ENA_VP_1, 0xff);
1413		reg_write(priv, REG_ENA_VP_2, 0xff);
1414		/* set muxing after enabling ports: */
1415		reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1416		reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1417		reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
1418
1419		priv->is_on = true;
1420	}
1421}
1422
1423static void tda998x_bridge_disable(struct drm_bridge *bridge)
1424{
1425	struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1426
1427	if (priv->is_on) {
1428		/* disable video ports */
1429		reg_write(priv, REG_ENA_VP_0, 0x00);
1430		reg_write(priv, REG_ENA_VP_1, 0x00);
1431		reg_write(priv, REG_ENA_VP_2, 0x00);
1432
1433		priv->is_on = false;
1434	}
1435}
1436
1437static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
1438				    const struct drm_display_mode *mode,
1439				    const struct drm_display_mode *adjusted_mode)
1440{
1441	struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1442	unsigned long tmds_clock;
1443	u16 ref_pix, ref_line, n_pix, n_line;
1444	u16 hs_pix_s, hs_pix_e;
1445	u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1446	u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1447	u16 vwin1_line_s, vwin1_line_e;
1448	u16 vwin2_line_s, vwin2_line_e;
1449	u16 de_pix_s, de_pix_e;
1450	u8 reg, div, rep, sel_clk;
1451
1452	/*
1453	 * Since we are "computer" like, our source invariably produces
1454	 * full-range RGB.  If the monitor supports full-range, then use
1455	 * it, otherwise reduce to limited-range.
1456	 */
1457	priv->rgb_quant_range =
1458		priv->connector.display_info.rgb_quant_range_selectable ?
1459		HDMI_QUANTIZATION_RANGE_FULL :
1460		drm_default_rgb_quant_range(adjusted_mode);
1461
1462	/*
1463	 * Internally TDA998x is using ITU-R BT.656 style sync but
1464	 * we get VESA style sync. TDA998x is using a reference pixel
1465	 * relative to ITU to sync to the input frame and for output
1466	 * sync generation. Currently, we are using reference detection
1467	 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1468	 * which is position of rising VS with coincident rising HS.
1469	 *
1470	 * Now there is some issues to take care of:
1471	 * - HDMI data islands require sync-before-active
1472	 * - TDA998x register values must be > 0 to be enabled
1473	 * - REFLINE needs an additional offset of +1
1474	 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1475	 *
1476	 * So we add +1 to all horizontal and vertical register values,
1477	 * plus an additional +3 for REFPIX as we are using RGB input only.
1478	 */
1479	n_pix        = mode->htotal;
1480	n_line       = mode->vtotal;
1481
1482	hs_pix_e     = mode->hsync_end - mode->hdisplay;
1483	hs_pix_s     = mode->hsync_start - mode->hdisplay;
1484	de_pix_e     = mode->htotal;
1485	de_pix_s     = mode->htotal - mode->hdisplay;
1486	ref_pix      = 3 + hs_pix_s;
1487
1488	/*
1489	 * Attached LCD controllers may generate broken sync. Allow
1490	 * those to adjust the position of the rising VS edge by adding
1491	 * HSKEW to ref_pix.
1492	 */
1493	if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1494		ref_pix += adjusted_mode->hskew;
1495
1496	if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1497		ref_line     = 1 + mode->vsync_start - mode->vdisplay;
1498		vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1499		vwin1_line_e = vwin1_line_s + mode->vdisplay;
1500		vs1_pix_s    = vs1_pix_e = hs_pix_s;
1501		vs1_line_s   = mode->vsync_start - mode->vdisplay;
1502		vs1_line_e   = vs1_line_s +
1503			       mode->vsync_end - mode->vsync_start;
1504		vwin2_line_s = vwin2_line_e = 0;
1505		vs2_pix_s    = vs2_pix_e  = 0;
1506		vs2_line_s   = vs2_line_e = 0;
1507	} else {
1508		ref_line     = 1 + (mode->vsync_start - mode->vdisplay)/2;
1509		vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1510		vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1511		vs1_pix_s    = vs1_pix_e = hs_pix_s;
1512		vs1_line_s   = (mode->vsync_start - mode->vdisplay)/2;
1513		vs1_line_e   = vs1_line_s +
1514			       (mode->vsync_end - mode->vsync_start)/2;
1515		vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1516		vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1517		vs2_pix_s    = vs2_pix_e = hs_pix_s + mode->htotal/2;
1518		vs2_line_s   = vs1_line_s + mode->vtotal/2 ;
1519		vs2_line_e   = vs2_line_s +
1520			       (mode->vsync_end - mode->vsync_start)/2;
1521	}
1522
1523	/*
1524	 * Select pixel repeat depending on the double-clock flag
1525	 * (which means we have to repeat each pixel once.)
1526	 */
1527	rep = mode->flags & DRM_MODE_FLAG_DBLCLK ? 1 : 0;
1528	sel_clk = SEL_CLK_ENA_SC_CLK | SEL_CLK_SEL_CLK1 |
1529		  SEL_CLK_SEL_VRF_CLK(rep ? 2 : 0);
1530
1531	/* the TMDS clock is scaled up by the pixel repeat */
1532	tmds_clock = mode->clock * (1 + rep);
1533
1534	/*
1535	 * The divisor is power-of-2. The TDA9983B datasheet gives
1536	 * this as ranges of Msample/s, which is 10x the TMDS clock:
1537	 *   0 - 800 to 1500 Msample/s
1538	 *   1 - 400 to 800 Msample/s
1539	 *   2 - 200 to 400 Msample/s
1540	 *   3 - as 2 above
1541	 */
1542	for (div = 0; div < 3; div++)
1543		if (80000 >> div <= tmds_clock)
1544			break;
1545
1546	mutex_lock(&priv->audio_mutex);
1547
1548	priv->tmds_clock = tmds_clock;
1549
1550	/* mute the audio FIFO: */
1551	reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1552
1553	/* set HDMI HDCP mode off: */
1554	reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
1555	reg_clear(priv, REG_TX33, TX33_HDMI);
1556	reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
1557
1558	/* no pre-filter or interpolator: */
1559	reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
1560			HVF_CNTRL_0_INTPOL(0));
1561	reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT);
1562	reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1563	reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
1564			VIP_CNTRL_4_BLC(0));
1565
1566	reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
1567	reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1568					  PLL_SERIAL_3_SRL_DE);
1569	reg_write(priv, REG_SERIALIZER, 0);
1570	reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
1571
1572	reg_write(priv, REG_RPT_CNTRL, RPT_CNTRL_REPEAT(rep));
1573	reg_write(priv, REG_SEL_CLK, sel_clk);
1574	reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
1575			PLL_SERIAL_2_SRL_PR(rep));
1576
1577	/* set color matrix according to output rgb quant range */
1578	if (priv->rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) {
1579		static u8 tda998x_full_to_limited_range[] = {
1580			MAT_CONTRL_MAT_SC(2),
1581			0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1582			0x03, 0x6f, 0x00, 0x00, 0x00, 0x00,
1583			0x00, 0x00, 0x03, 0x6f, 0x00, 0x00,
1584			0x00, 0x00, 0x00, 0x00, 0x03, 0x6f,
1585			0x00, 0x40, 0x00, 0x40, 0x00, 0x40
1586		};
1587		reg_clear(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1588		reg_write_range(priv, REG_MAT_CONTRL,
1589				tda998x_full_to_limited_range,
1590				sizeof(tda998x_full_to_limited_range));
1591	} else {
1592		reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1593					MAT_CONTRL_MAT_SC(1));
1594		reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1595	}
1596
1597	/* set BIAS tmds value: */
1598	reg_write(priv, REG_ANA_GENERAL, 0x09);
1599
1600	/*
1601	 * Sync on rising HSYNC/VSYNC
1602	 */
1603	reg = VIP_CNTRL_3_SYNC_HS;
1604
1605	/*
1606	 * TDA19988 requires high-active sync at input stage,
1607	 * so invert low-active sync provided by master encoder here
1608	 */
1609	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1610		reg |= VIP_CNTRL_3_H_TGL;
1611	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1612		reg |= VIP_CNTRL_3_V_TGL;
1613	reg_write(priv, REG_VIP_CNTRL_3, reg);
1614
1615	reg_write(priv, REG_VIDFORMAT, 0x00);
1616	reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1617	reg_write16(priv, REG_REFLINE_MSB, ref_line);
1618	reg_write16(priv, REG_NPIX_MSB, n_pix);
1619	reg_write16(priv, REG_NLINE_MSB, n_line);
1620	reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1621	reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1622	reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1623	reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1624	reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1625	reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1626	reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1627	reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1628	reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1629	reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1630	reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1631	reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1632	reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1633	reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1634	reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1635	reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1636
1637	if (priv->rev == TDA19988) {
1638		/* let incoming pixels fill the active space (if any) */
1639		reg_write(priv, REG_ENABLE_SPACE, 0x00);
1640	}
1641
1642	/*
1643	 * Always generate sync polarity relative to input sync and
1644	 * revert input stage toggled sync at output stage
1645	 */
1646	reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1647	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1648		reg |= TBG_CNTRL_1_H_TGL;
1649	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1650		reg |= TBG_CNTRL_1_V_TGL;
1651	reg_write(priv, REG_TBG_CNTRL_1, reg);
1652
1653	/* must be last register set: */
1654	reg_write(priv, REG_TBG_CNTRL_0, 0);
1655
1656	/* CEA-861B section 6 says that:
1657	 * CEA version 1 (CEA-861) has no support for infoframes.
1658	 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1659	 * and optional basic audio.
1660	 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1661	 * and optional digital audio, with audio infoframes.
1662	 *
1663	 * Since we only support generation of version 2 AVI infoframes,
1664	 * ignore CEA version 2 and below (iow, behave as if we're a
1665	 * CEA-861 source.)
1666	 */
1667	priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1668
1669	if (priv->supports_infoframes) {
1670		/* We need to turn HDMI HDCP stuff on to get audio through */
1671		reg &= ~TBG_CNTRL_1_DWIN_DIS;
1672		reg_write(priv, REG_TBG_CNTRL_1, reg);
1673		reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1674		reg_set(priv, REG_TX33, TX33_HDMI);
1675
1676		tda998x_write_avi(priv, adjusted_mode);
1677		tda998x_write_vsi(priv, adjusted_mode);
1678
1679		if (priv->sink_has_audio)
1680			tda998x_configure_audio(priv);
1681	}
1682
1683	mutex_unlock(&priv->audio_mutex);
1684}
1685
1686static const struct drm_bridge_funcs tda998x_bridge_funcs = {
1687	.attach = tda998x_bridge_attach,
1688	.detach = tda998x_bridge_detach,
1689	.mode_valid = tda998x_bridge_mode_valid,
1690	.disable = tda998x_bridge_disable,
1691	.mode_set = tda998x_bridge_mode_set,
1692	.enable = tda998x_bridge_enable,
1693};
1694
1695/* I2C driver functions */
1696
1697static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1698				   struct device_node *np)
1699{
1700	const u32 *port_data;
1701	u32 size;
1702	int i;
1703
1704	port_data = of_get_property(np, "audio-ports", &size);
1705	if (!port_data)
1706		return 0;
1707
1708	size /= sizeof(u32);
1709	if (size > 2 * ARRAY_SIZE(priv->audio_port_enable) || size % 2 != 0) {
1710		dev_err(&priv->hdmi->dev,
1711			"Bad number of elements in audio-ports dt-property\n");
1712		return -EINVAL;
1713	}
1714
1715	size /= 2;
1716
1717	for (i = 0; i < size; i++) {
1718		unsigned int route;
1719		u8 afmt = be32_to_cpup(&port_data[2*i]);
1720		u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1721
1722		switch (afmt) {
1723		case TDA998x_I2S:
1724			route = AUDIO_ROUTE_I2S;
1725			break;
1726		case TDA998x_SPDIF:
1727			route = AUDIO_ROUTE_SPDIF;
1728			break;
1729		default:
1730			dev_err(&priv->hdmi->dev,
1731				"Bad audio format %u\n", afmt);
1732			return -EINVAL;
1733		}
1734
1735		if (!ena_ap) {
1736			dev_err(&priv->hdmi->dev, "invalid zero port config\n");
1737			continue;
1738		}
1739
1740		if (priv->audio_port_enable[route]) {
1741			dev_err(&priv->hdmi->dev,
1742				"%s format already configured\n",
1743				route == AUDIO_ROUTE_SPDIF ? "SPDIF" : "I2S");
1744			return -EINVAL;
1745		}
1746
1747		priv->audio_port_enable[route] = ena_ap;
1748	}
1749	return 0;
1750}
1751
1752static void tda998x_destroy(struct device *dev)
1753{
1754	struct tda998x_priv *priv = dev_get_drvdata(dev);
1755
1756	drm_bridge_remove(&priv->bridge);
1757
1758	/* disable all IRQs and free the IRQ handler */
1759	cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1760	reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1761
1762	if (priv->audio_pdev)
1763		platform_device_unregister(priv->audio_pdev);
1764
1765	if (priv->hdmi->irq)
1766		free_irq(priv->hdmi->irq, priv);
1767
1768	timer_delete_sync(&priv->edid_delay_timer);
1769	cancel_work_sync(&priv->detect_work);
1770
1771	i2c_unregister_device(priv->cec);
1772
1773	cec_notifier_conn_unregister(priv->cec_notify);
1774}
1775
1776static int tda998x_create(struct device *dev)
1777{
1778	struct i2c_client *client = to_i2c_client(dev);
1779	struct device_node *np = client->dev.of_node;
1780	struct i2c_board_info cec_info;
1781	struct tda998x_priv *priv;
1782	u32 video;
1783	int rev_lo, rev_hi, ret;
1784
1785	priv = devm_drm_bridge_alloc(dev, struct tda998x_priv, bridge, &tda998x_bridge_funcs);
1786	if (IS_ERR(priv))
1787		return PTR_ERR(priv);
1788
1789	dev_set_drvdata(dev, priv);
1790
1791	mutex_init(&priv->mutex);	/* protect the page access */
1792	mutex_init(&priv->audio_mutex); /* protect access from audio thread */
1793	mutex_init(&priv->edid_mutex);
1794	INIT_LIST_HEAD(&priv->bridge.list);
1795	init_waitqueue_head(&priv->edid_delay_waitq);
1796	timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0);
1797	INIT_WORK(&priv->detect_work, tda998x_detect_work);
1798
1799	priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1800	priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1801	priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1802
1803	/* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1804	priv->cec_addr = 0x34 + (client->addr & 0x03);
1805	priv->current_page = 0xff;
1806	priv->hdmi = client;
1807
1808	/* wake up the device: */
1809	cec_write(priv, REG_CEC_ENAMODS,
1810			CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1811
1812	tda998x_reset(priv);
1813
1814	/* read version: */
1815	rev_lo = reg_read(priv, REG_VERSION_LSB);
1816	if (rev_lo < 0) {
1817		dev_err(dev, "failed to read version: %d\n", rev_lo);
1818		return rev_lo;
1819	}
1820
1821	rev_hi = reg_read(priv, REG_VERSION_MSB);
1822	if (rev_hi < 0) {
1823		dev_err(dev, "failed to read version: %d\n", rev_hi);
1824		return rev_hi;
1825	}
1826
1827	priv->rev = rev_lo | rev_hi << 8;
1828
1829	/* mask off feature bits: */
1830	priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1831
1832	switch (priv->rev) {
1833	case TDA9989N2:
1834		dev_info(dev, "found TDA9989 n2");
1835		break;
1836	case TDA19989:
1837		dev_info(dev, "found TDA19989");
1838		break;
1839	case TDA19989N2:
1840		dev_info(dev, "found TDA19989 n2");
1841		break;
1842	case TDA19988:
1843		dev_info(dev, "found TDA19988");
1844		break;
1845	default:
1846		dev_err(dev, "found unsupported device: %04x\n", priv->rev);
1847		return -ENXIO;
1848	}
1849
1850	/* after reset, enable DDC: */
1851	reg_write(priv, REG_DDC_DISABLE, 0x00);
1852
1853	/* set clock on DDC channel: */
1854	reg_write(priv, REG_TX3, 39);
1855
1856	/* if necessary, disable multi-master: */
1857	if (priv->rev == TDA19989)
1858		reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1859
1860	cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1861			CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1862
1863	/* ensure interrupts are disabled */
1864	cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1865
1866	/* clear pending interrupts */
1867	cec_read(priv, REG_CEC_RXSHPDINT);
1868	reg_read(priv, REG_INT_FLAGS_0);
1869	reg_read(priv, REG_INT_FLAGS_1);
1870	reg_read(priv, REG_INT_FLAGS_2);
1871
1872	/* initialize the optional IRQ */
1873	if (client->irq) {
1874		unsigned long irq_flags;
1875
1876		/* init read EDID waitqueue and HDP work */
1877		init_waitqueue_head(&priv->wq_edid);
1878
1879		irq_flags =
1880			irqd_get_trigger_type(irq_get_irq_data(client->irq));
1881
1882		priv->cec_glue.irq_flags = irq_flags;
1883
1884		irq_flags |= IRQF_SHARED | IRQF_ONESHOT;
1885		ret = request_threaded_irq(client->irq, NULL,
1886					   tda998x_irq_thread, irq_flags,
1887					   "tda998x", priv);
1888		if (ret) {
1889			dev_err(dev, "failed to request IRQ#%u: %d\n",
1890				client->irq, ret);
1891			goto err_irq;
1892		}
1893
1894		/* enable HPD irq */
1895		cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1896	}
1897
1898	priv->cec_notify = cec_notifier_conn_register(dev, NULL, NULL);
1899	if (!priv->cec_notify) {
1900		ret = -ENOMEM;
1901		goto fail;
1902	}
1903
1904	priv->cec_glue.parent = dev;
1905	priv->cec_glue.data = priv;
1906	priv->cec_glue.init = tda998x_cec_hook_init;
1907	priv->cec_glue.exit = tda998x_cec_hook_exit;
1908	priv->cec_glue.open = tda998x_cec_hook_open;
1909	priv->cec_glue.release = tda998x_cec_hook_release;
1910
1911	/*
1912	 * Some TDA998x are actually two I2C devices merged onto one piece
1913	 * of silicon: TDA9989 and TDA19989 combine the HDMI transmitter
1914	 * with a slightly modified TDA9950 CEC device.  The CEC device
1915	 * is at the TDA9950 address, with the address pins strapped across
1916	 * to the TDA998x address pins.  Hence, it always has the same
1917	 * offset.
1918	 */
1919	memset(&cec_info, 0, sizeof(cec_info));
1920	strscpy(cec_info.type, "tda9950", sizeof(cec_info.type));
1921	cec_info.addr = priv->cec_addr;
1922	cec_info.platform_data = &priv->cec_glue;
1923	cec_info.irq = client->irq;
1924
1925	priv->cec = i2c_new_client_device(client->adapter, &cec_info);
1926	if (IS_ERR(priv->cec)) {
1927		ret = PTR_ERR(priv->cec);
1928		goto fail;
1929	}
1930
1931	/* enable EDID read irq: */
1932	reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1933
1934	if (np) {
1935		/* get the device tree parameters */
1936		ret = of_property_read_u32(np, "video-ports", &video);
1937		if (ret == 0) {
1938			priv->vip_cntrl_0 = video >> 16;
1939			priv->vip_cntrl_1 = video >> 8;
1940			priv->vip_cntrl_2 = video;
1941		}
1942
1943		ret = tda998x_get_audio_ports(priv, np);
1944		if (ret)
1945			goto fail;
1946
1947		if (priv->audio_port_enable[AUDIO_ROUTE_I2S] ||
1948		    priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1949			tda998x_audio_codec_init(priv, &client->dev);
1950	}
1951
1952#ifdef CONFIG_OF
1953	priv->bridge.of_node = dev->of_node;
1954#endif
1955
1956	drm_bridge_add(&priv->bridge);
1957
1958	return 0;
1959
1960fail:
1961	tda998x_destroy(dev);
1962err_irq:
1963	return ret;
1964}
1965
1966/* DRM encoder functions */
1967
1968static int tda998x_encoder_init(struct device *dev, struct drm_device *drm)
1969{
1970	struct tda998x_priv *priv = dev_get_drvdata(dev);
1971	u32 crtcs = 0;
1972	int ret;
1973
1974	if (dev->of_node)
1975		crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1976
1977	/* If no CRTCs were found, fall back to our old behaviour */
1978	if (crtcs == 0) {
1979		dev_warn(dev, "Falling back to first CRTC\n");
1980		crtcs = 1 << 0;
1981	}
1982
1983	priv->encoder.possible_crtcs = crtcs;
1984
1985	ret = drm_simple_encoder_init(drm, &priv->encoder,
1986				      DRM_MODE_ENCODER_TMDS);
1987	if (ret)
1988		goto err_encoder;
1989
1990	ret = drm_bridge_attach(&priv->encoder, &priv->bridge, NULL, 0);
1991	if (ret)
1992		goto err_bridge;
1993
1994	return 0;
1995
1996err_bridge:
1997	drm_encoder_cleanup(&priv->encoder);
1998err_encoder:
1999	return ret;
2000}
2001
2002static int tda998x_bind(struct device *dev, struct device *master, void *data)
2003{
2004	struct drm_device *drm = data;
2005
2006	return tda998x_encoder_init(dev, drm);
2007}
2008
2009static void tda998x_unbind(struct device *dev, struct device *master,
2010			   void *data)
2011{
2012	struct tda998x_priv *priv = dev_get_drvdata(dev);
2013
2014	drm_encoder_cleanup(&priv->encoder);
2015}
2016
2017static const struct component_ops tda998x_ops = {
2018	.bind = tda998x_bind,
2019	.unbind = tda998x_unbind,
2020};
2021
2022static int
2023tda998x_probe(struct i2c_client *client)
2024{
2025	int ret;
2026
2027	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
2028		dev_warn(&client->dev, "adapter does not support I2C\n");
2029		return -EIO;
2030	}
2031
2032	ret = tda998x_create(&client->dev);
2033	if (ret)
2034		return ret;
2035
2036	ret = component_add(&client->dev, &tda998x_ops);
2037	if (ret)
2038		tda998x_destroy(&client->dev);
2039	return ret;
2040}
2041
2042static void tda998x_remove(struct i2c_client *client)
2043{
2044	component_del(&client->dev, &tda998x_ops);
2045	tda998x_destroy(&client->dev);
2046}
2047
2048#ifdef CONFIG_OF
2049static const struct of_device_id tda998x_dt_ids[] = {
2050	{ .compatible = "nxp,tda998x", },
2051	{ }
2052};
2053MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
2054#endif
2055
2056static const struct i2c_device_id tda998x_ids[] = {
2057	{ "tda998x" },
2058	{ }
2059};
2060MODULE_DEVICE_TABLE(i2c, tda998x_ids);
2061
2062static struct i2c_driver tda998x_driver = {
2063	.probe = tda998x_probe,
2064	.remove = tda998x_remove,
2065	.driver = {
2066		.name = "tda998x",
2067		.of_match_table = of_match_ptr(tda998x_dt_ids),
2068	},
2069	.id_table = tda998x_ids,
2070};
2071
2072module_i2c_driver(tda998x_driver);
2073
2074MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
2075MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
2076MODULE_LICENSE("GPL");