tc358775.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * TC358775 DSI to LVDS bridge driver
  4 *
  5 * Copyright (C) 2020 SMART Wireless Computing
  6 * Author: Vinay Simha BN <simhavcs@gmail.com>
  7 *
  8 */
  9/* #define DEBUG */
 10#include <linux/bitfield.h>
 11#include <linux/clk.h>
 12#include <linux/device.h>
 13#include <linux/gpio/consumer.h>
 14#include <linux/i2c.h>
 15#include <linux/kernel.h>
 16#include <linux/media-bus-format.h>
 17#include <linux/module.h>
 18#include <linux/of_device.h>
 19#include <linux/regulator/consumer.h>
 20#include <linux/slab.h>
 21
 22#include <linux/unaligned.h>
 23
 24#include <drm/display/drm_dp_helper.h>
 25#include <drm/drm_atomic_helper.h>
 26#include <drm/drm_bridge.h>
 27#include <drm/drm_mipi_dsi.h>
 28#include <drm/drm_of.h>
 29#include <drm/drm_probe_helper.h>
 30
 31#define FLD_VAL(val, start, end) FIELD_PREP(GENMASK(start, end), val)
 32
 33/* Registers */
 34
 35/* DSI D-PHY Layer Registers */
 36#define D0W_DPHYCONTTX  0x0004  /* Data Lane 0 DPHY Tx Control */
 37#define CLW_DPHYCONTRX  0x0020  /* Clock Lane DPHY Rx Control */
 38#define D0W_DPHYCONTRX  0x0024  /* Data Lane 0 DPHY Rx Control */
 39#define D1W_DPHYCONTRX  0x0028  /* Data Lane 1 DPHY Rx Control */
 40#define D2W_DPHYCONTRX  0x002C  /* Data Lane 2 DPHY Rx Control */
 41#define D3W_DPHYCONTRX  0x0030  /* Data Lane 3 DPHY Rx Control */
 42#define COM_DPHYCONTRX  0x0038  /* DPHY Rx Common Control */
 43#define CLW_CNTRL       0x0040  /* Clock Lane Control */
 44#define D0W_CNTRL       0x0044  /* Data Lane 0 Control */
 45#define D1W_CNTRL       0x0048  /* Data Lane 1 Control */
 46#define D2W_CNTRL       0x004C  /* Data Lane 2 Control */
 47#define D3W_CNTRL       0x0050  /* Data Lane 3 Control */
 48#define DFTMODE_CNTRL   0x0054  /* DFT Mode Control */
 49
 50/* DSI PPI Layer Registers */
 51#define PPI_STARTPPI    0x0104  /* START control bit of PPI-TX function. */
 52#define PPI_START_FUNCTION      1
 53
 54#define PPI_BUSYPPI     0x0108
 55#define PPI_LINEINITCNT 0x0110  /* Line Initialization Wait Counter  */
 56#define PPI_LPTXTIMECNT 0x0114
 57#define PPI_LANEENABLE  0x0134  /* Enables each lane at the PPI layer. */
 58#define PPI_TX_RX_TA    0x013C  /* DSI Bus Turn Around timing parameters */
 59
 60/* Analog timer function enable */
 61#define PPI_CLS_ATMR    0x0140  /* Delay for Clock Lane in LPRX  */
 62#define PPI_D0S_ATMR    0x0144  /* Delay for Data Lane 0 in LPRX */
 63#define PPI_D1S_ATMR    0x0148  /* Delay for Data Lane 1 in LPRX */
 64#define PPI_D2S_ATMR    0x014C  /* Delay for Data Lane 2 in LPRX */
 65#define PPI_D3S_ATMR    0x0150  /* Delay for Data Lane 3 in LPRX */
 66
 67#define PPI_D0S_CLRSIPOCOUNT    0x0164  /* For lane 0 */
 68#define PPI_D1S_CLRSIPOCOUNT    0x0168  /* For lane 1 */
 69#define PPI_D2S_CLRSIPOCOUNT    0x016C  /* For lane 2 */
 70#define PPI_D3S_CLRSIPOCOUNT    0x0170  /* For lane 3 */
 71
 72#define CLS_PRE         0x0180  /* Digital Counter inside of PHY IO */
 73#define D0S_PRE         0x0184  /* Digital Counter inside of PHY IO */
 74#define D1S_PRE         0x0188  /* Digital Counter inside of PHY IO */
 75#define D2S_PRE         0x018C  /* Digital Counter inside of PHY IO */
 76#define D3S_PRE         0x0190  /* Digital Counter inside of PHY IO */
 77#define CLS_PREP        0x01A0  /* Digital Counter inside of PHY IO */
 78#define D0S_PREP        0x01A4  /* Digital Counter inside of PHY IO */
 79#define D1S_PREP        0x01A8  /* Digital Counter inside of PHY IO */
 80#define D2S_PREP        0x01AC  /* Digital Counter inside of PHY IO */
 81#define D3S_PREP        0x01B0  /* Digital Counter inside of PHY IO */
 82#define CLS_ZERO        0x01C0  /* Digital Counter inside of PHY IO */
 83#define D0S_ZERO        0x01C4  /* Digital Counter inside of PHY IO */
 84#define D1S_ZERO        0x01C8  /* Digital Counter inside of PHY IO */
 85#define D2S_ZERO        0x01CC  /* Digital Counter inside of PHY IO */
 86#define D3S_ZERO        0x01D0  /* Digital Counter inside of PHY IO */
 87
 88#define PPI_CLRFLG      0x01E0  /* PRE Counters has reached set values */
 89#define PPI_CLRSIPO     0x01E4  /* Clear SIPO values, Slave mode use only. */
 90#define HSTIMEOUT       0x01F0  /* HS Rx Time Out Counter */
 91#define HSTIMEOUTENABLE 0x01F4  /* Enable HS Rx Time Out Counter */
 92#define DSI_STARTDSI    0x0204  /* START control bit of DSI-TX function */
 93#define DSI_RX_START	1
 94
 95#define DSI_BUSYDSI     0x0208
 96#define DSI_LANEENABLE  0x0210  /* Enables each lane at the Protocol layer. */
 97#define DSI_LANESTATUS0 0x0214  /* Displays lane is in HS RX mode. */
 98#define DSI_LANESTATUS1 0x0218  /* Displays lane is in ULPS or STOP state */
 99
100#define DSI_INTSTATUS   0x0220  /* Interrupt Status */
101#define DSI_INTMASK     0x0224  /* Interrupt Mask */
102#define DSI_INTCLR      0x0228  /* Interrupt Clear */
103#define DSI_LPTXTO      0x0230  /* Low Power Tx Time Out Counter */
104
105#define DSIERRCNT       0x0300  /* DSI Error Count */
106#define APLCTRL         0x0400  /* Application Layer Control */
107#define RDPKTLN         0x0404  /* Command Read Packet Length */
108
109#define VPCTRL          0x0450  /* Video Path Control */
110#define EVTMODE		BIT(5)  /* Video event mode enable, tc35876x only */
111#define HTIM1           0x0454  /* Horizontal Timing Control 1 */
112#define HTIM2           0x0458  /* Horizontal Timing Control 2 */
113#define VTIM1           0x045C  /* Vertical Timing Control 1 */
114#define VTIM2           0x0460  /* Vertical Timing Control 2 */
115#define VFUEN           0x0464  /* Video Frame Timing Update Enable */
116#define VFUEN_EN	BIT(0)  /* Upload Enable */
117
118/* Mux Input Select for LVDS LINK Input */
119#define LV_MX0003        0x0480  /* Bit 0 to 3 */
120#define LV_MX0407        0x0484  /* Bit 4 to 7 */
121#define LV_MX0811        0x0488  /* Bit 8 to 11 */
122#define LV_MX1215        0x048C  /* Bit 12 to 15 */
123#define LV_MX1619        0x0490  /* Bit 16 to 19 */
124#define LV_MX2023        0x0494  /* Bit 20 to 23 */
125#define LV_MX2427        0x0498  /* Bit 24 to 27 */
126#define LV_MX(b0, b1, b2, b3)	(FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
127				FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24))
128
129/* Input bit numbers used in mux registers */
130enum {
131	LVI_R0,
132	LVI_R1,
133	LVI_R2,
134	LVI_R3,
135	LVI_R4,
136	LVI_R5,
137	LVI_R6,
138	LVI_R7,
139	LVI_G0,
140	LVI_G1,
141	LVI_G2,
142	LVI_G3,
143	LVI_G4,
144	LVI_G5,
145	LVI_G6,
146	LVI_G7,
147	LVI_B0,
148	LVI_B1,
149	LVI_B2,
150	LVI_B3,
151	LVI_B4,
152	LVI_B5,
153	LVI_B6,
154	LVI_B7,
155	LVI_HS,
156	LVI_VS,
157	LVI_DE,
158	LVI_L0
159};
160
161#define LVCFG           0x049C  /* LVDS Configuration  */
162#define LVPHY0          0x04A0  /* LVDS PHY 0 */
163#define LV_PHY0_RST(v)          FLD_VAL(v, 22, 22) /* PHY reset */
164#define LV_PHY0_IS(v)           FLD_VAL(v, 15, 14)
165#define LV_PHY0_ND(v)           FLD_VAL(v, 4, 0) /* Frequency range select */
166#define LV_PHY0_PRBS_ON(v)      FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */
167
168#define LVPHY1          0x04A4  /* LVDS PHY 1 */
169#define SYSSTAT         0x0500  /* System Status  */
170#define SYSRST          0x0504  /* System Reset  */
171
172#define SYS_RST_I2CS	BIT(0) /* Reset I2C-Slave controller */
173#define SYS_RST_I2CM	BIT(1) /* Reset I2C-Master controller */
174#define SYS_RST_LCD	BIT(2) /* Reset LCD controller */
175#define SYS_RST_BM	BIT(3) /* Reset Bus Management controller */
176#define SYS_RST_DSIRX	BIT(4) /* Reset DSI-RX and App controller */
177#define SYS_RST_REG	BIT(5) /* Reset Register module */
178
179/* GPIO Registers */
180#define GPIOC           0x0520  /* GPIO Control  */
181#define GPIOO           0x0524  /* GPIO Output  */
182#define GPIOI           0x0528  /* GPIO Input  */
183
184/* I2C Registers */
185#define I2CTIMCTRL      0x0540  /* I2C IF Timing and Enable Control */
186#define I2CMADDR        0x0544  /* I2C Master Addressing */
187#define WDATAQ          0x0548  /* Write Data Queue */
188#define RDATAQ          0x054C  /* Read Data Queue */
189
190/* Chip ID and Revision ID Register */
191#define IDREG           0x0580
192
193#define LPX_PERIOD		4
194#define TTA_GET			0x40000
195#define TTA_SURE		6
196#define SINGLE_LINK		1
197#define DUAL_LINK		2
198
199#define TC358775XBG_ID  0x00007500
200
201/* Debug Registers */
202#define DEBUG00         0x05A0  /* Debug */
203#define DEBUG01         0x05A4  /* LVDS Data */
204
205#define DSI_CLEN_BIT		BIT(0)
206#define DIVIDE_BY_3		3 /* PCLK=DCLK/3 */
207#define DIVIDE_BY_6		6 /* PCLK=DCLK/6 */
208#define LVCFG_LVEN_BIT		BIT(0)
209
210#define L0EN BIT(1)
211
212#define TC358775_VPCTRL_VSDELAY__MASK	0x3FF00000
213#define TC358775_VPCTRL_VSDELAY__SHIFT	20
214static inline u32 TC358775_VPCTRL_VSDELAY(uint32_t val)
215{
216	return ((val) << TC358775_VPCTRL_VSDELAY__SHIFT) &
217			TC358775_VPCTRL_VSDELAY__MASK;
218}
219
220#define TC358775_VPCTRL_OPXLFMT__MASK	0x00000100
221#define TC358775_VPCTRL_OPXLFMT__SHIFT	8
222static inline u32 TC358775_VPCTRL_OPXLFMT(uint32_t val)
223{
224	return ((val) << TC358775_VPCTRL_OPXLFMT__SHIFT) &
225			TC358775_VPCTRL_OPXLFMT__MASK;
226}
227
228#define TC358775_VPCTRL_MSF__MASK	0x00000001
229#define TC358775_VPCTRL_MSF__SHIFT	0
230static inline u32 TC358775_VPCTRL_MSF(uint32_t val)
231{
232	return ((val) << TC358775_VPCTRL_MSF__SHIFT) &
233			TC358775_VPCTRL_MSF__MASK;
234}
235
236#define TC358775_LVCFG_PCLKDIV__MASK	0x000000f0
237#define TC358775_LVCFG_PCLKDIV__SHIFT	4
238static inline u32 TC358775_LVCFG_PCLKDIV(uint32_t val)
239{
240	return ((val) << TC358775_LVCFG_PCLKDIV__SHIFT) &
241			TC358775_LVCFG_PCLKDIV__MASK;
242}
243
244#define TC358775_LVCFG_LVDLINK__MASK                         0x00000002
245#define TC358775_LVCFG_LVDLINK__SHIFT                        1
246static inline u32 TC358775_LVCFG_LVDLINK(uint32_t val)
247{
248	return ((val) << TC358775_LVCFG_LVDLINK__SHIFT) &
249			TC358775_LVCFG_LVDLINK__MASK;
250}
251
252enum tc358775_ports {
253	TC358775_DSI_IN,
254	TC358775_LVDS_OUT0,
255	TC358775_LVDS_OUT1,
256};
257
258enum tc3587x5_type {
259	TC358765 = 0x65,
260	TC358775 = 0x75,
261};
262
263struct tc_data {
264	struct i2c_client	*i2c;
265	struct device		*dev;
266
267	struct drm_bridge	bridge;
268	struct drm_bridge	*panel_bridge;
269
270	struct device_node *host_node;
271	struct mipi_dsi_device *dsi;
272	u8 num_dsi_lanes;
273
274	struct regulator	*vdd;
275	struct regulator	*vddio;
276	struct gpio_desc	*reset_gpio;
277	struct gpio_desc	*stby_gpio;
278	u8			lvds_link; /* single-link or dual-link */
279	u8			bpc;
280
281	enum tc3587x5_type	type;
282};
283
284static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
285{
286	return container_of(b, struct tc_data, bridge);
287}
288
289static void tc_bridge_atomic_pre_enable(struct drm_bridge *bridge,
290					struct drm_atomic_state *state)
291{
292	struct tc_data *tc = bridge_to_tc(bridge);
293	struct device *dev = &tc->dsi->dev;
294	int ret;
295
296	ret = regulator_enable(tc->vddio);
297	if (ret < 0)
298		dev_err(dev, "regulator vddio enable failed, %d\n", ret);
299	usleep_range(10000, 11000);
300
301	ret = regulator_enable(tc->vdd);
302	if (ret < 0)
303		dev_err(dev, "regulator vdd enable failed, %d\n", ret);
304	usleep_range(10000, 11000);
305
306	gpiod_set_value(tc->stby_gpio, 0);
307	usleep_range(10000, 11000);
308
309	gpiod_set_value(tc->reset_gpio, 0);
310	usleep_range(10, 20);
311}
312
313static void tc_bridge_atomic_post_disable(struct drm_bridge *bridge,
314					  struct drm_atomic_state *state)
315{
316	struct tc_data *tc = bridge_to_tc(bridge);
317	struct device *dev = &tc->dsi->dev;
318	int ret;
319
320	gpiod_set_value(tc->reset_gpio, 1);
321	usleep_range(10, 20);
322
323	gpiod_set_value(tc->stby_gpio, 1);
324	usleep_range(10000, 11000);
325
326	ret = regulator_disable(tc->vdd);
327	if (ret < 0)
328		dev_err(dev, "regulator vdd disable failed, %d\n", ret);
329	usleep_range(10000, 11000);
330
331	ret = regulator_disable(tc->vddio);
332	if (ret < 0)
333		dev_err(dev, "regulator vddio disable failed, %d\n", ret);
334	usleep_range(10000, 11000);
335}
336
337static void d2l_read(struct i2c_client *i2c, u16 addr, u32 *val)
338{
339	int ret;
340	u8 buf_addr[2];
341
342	put_unaligned_be16(addr, buf_addr);
343	ret = i2c_master_send(i2c, buf_addr, sizeof(buf_addr));
344	if (ret < 0)
345		goto fail;
346
347	ret = i2c_master_recv(i2c, (u8 *)val, sizeof(*val));
348	if (ret < 0)
349		goto fail;
350
351	pr_debug("d2l: I2C : addr:%04x value:%08x\n", addr, *val);
352	return;
353
354fail:
355	dev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n",
356		ret, addr);
357}
358
359static void d2l_write(struct i2c_client *i2c, u16 addr, u32 val)
360{
361	u8 data[6];
362	int ret;
363
364	put_unaligned_be16(addr, data);
365	put_unaligned_le32(val, data + 2);
366
367	ret = i2c_master_send(i2c, data, ARRAY_SIZE(data));
368	if (ret < 0)
369		dev_err(&i2c->dev, "Error %d writing to subaddress 0x%x\n",
370			ret, addr);
371}
372
373static void tc_bridge_atomic_enable(struct drm_bridge *bridge,
374				    struct drm_atomic_state *state)
375{
376	struct tc_data *tc = bridge_to_tc(bridge);
377	u32 hback_porch, hsync_len, hfront_porch, hactive, htime1, htime2;
378	u32 vback_porch, vsync_len, vfront_porch, vactive, vtime1, vtime2;
379	u32 val = 0;
380	u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay;
381	struct drm_connector *connector =
382		drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
383	struct drm_connector_state *conn_state =
384		drm_atomic_get_new_connector_state(state, connector);
385	struct drm_crtc_state *crtc_state =
386		drm_atomic_get_new_crtc_state(state, conn_state->crtc);
387	struct drm_display_mode *mode = &crtc_state->adjusted_mode;
388
389	hback_porch = mode->htotal - mode->hsync_end;
390	hsync_len  = mode->hsync_end - mode->hsync_start;
391	vback_porch = mode->vtotal - mode->vsync_end;
392	vsync_len  = mode->vsync_end - mode->vsync_start;
393
394	htime1 = (hback_porch << 16) + hsync_len;
395	vtime1 = (vback_porch << 16) + vsync_len;
396
397	hfront_porch = mode->hsync_start - mode->hdisplay;
398	hactive = mode->hdisplay;
399	vfront_porch = mode->vsync_start - mode->vdisplay;
400	vactive = mode->vdisplay;
401
402	htime2 = (hfront_porch << 16) + hactive;
403	vtime2 = (vfront_porch << 16) + vactive;
404
405	d2l_read(tc->i2c, IDREG, &val);
406
407	dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n",
408		 (val >> 8) & 0xFF, val & 0xFF);
409
410	d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM |
411		  SYS_RST_LCD | SYS_RST_I2CM);
412	usleep_range(30000, 40000);
413
414	d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
415	d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD);
416	d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3);
417	d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3);
418	d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3);
419	d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3);
420
421	val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT;
422	d2l_write(tc->i2c, PPI_LANEENABLE, val);
423	d2l_write(tc->i2c, DSI_LANEENABLE, val);
424
425	d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION);
426	d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START);
427
428	/* Video event mode vs pulse mode bit, does not exist for tc358775 */
429	if (tc->type == TC358765)
430		val = EVTMODE;
431	else
432		val = 0;
433
434	if (tc->bpc == 8)
435		val |= TC358775_VPCTRL_OPXLFMT(1);
436	else /* bpc = 6; */
437		val |= TC358775_VPCTRL_MSF(1);
438
439	dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000;
440	clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : DIVIDE_BY_3);
441	byteclk = dsiclk / 4;
442	t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes;
443	t2 = ((100000 / clkdiv)) * (hactive + hback_porch + hsync_len + hfront_porch) / 1000;
444	t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) /
445		tc->num_dsi_lanes);
446
447	vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive;
448
449	val |= TC358775_VPCTRL_VSDELAY(vsdelay);
450	d2l_write(tc->i2c, VPCTRL, val);
451
452	d2l_write(tc->i2c, HTIM1, htime1);
453	d2l_write(tc->i2c, VTIM1, vtime1);
454	d2l_write(tc->i2c, HTIM2, htime2);
455	d2l_write(tc->i2c, VTIM2, vtime2);
456
457	d2l_write(tc->i2c, VFUEN, VFUEN_EN);
458	d2l_write(tc->i2c, SYSRST, SYS_RST_LCD);
459	d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6));
460
461	dev_dbg(tc->dev, "bus_formats %04x bpc %d\n",
462		connector->display_info.bus_formats[0],
463		tc->bpc);
464	if (connector->display_info.bus_formats[0] ==
465		MEDIA_BUS_FMT_RGB888_1X7X4_SPWG) {
466		/* VESA-24 */
467		d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
468		d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0));
469		d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7));
470		d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
471		d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2));
472		d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
473		d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6));
474	} else {
475		/* JEIDA-18 and JEIDA-24 */
476		d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R2, LVI_R3, LVI_R4, LVI_R5));
477		d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R6, LVI_R1, LVI_R7, LVI_G2));
478		d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G3, LVI_G4, LVI_G0, LVI_G1));
479		d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G5, LVI_G6, LVI_G7, LVI_B2));
480		d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B0, LVI_B1, LVI_B3, LVI_B4));
481		d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B5, LVI_B6, LVI_B7, LVI_L0));
482		d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R0));
483	}
484
485	d2l_write(tc->i2c, VFUEN, VFUEN_EN);
486
487	val = LVCFG_LVEN_BIT;
488	if (tc->lvds_link == DUAL_LINK) {
489		val |= TC358775_LVCFG_LVDLINK(1);
490		val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_6);
491	} else {
492		val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_3);
493	}
494	d2l_write(tc->i2c, LVCFG, val);
495}
496
497static enum drm_mode_status
498tc_mode_valid(struct drm_bridge *bridge,
499	      const struct drm_display_info *info,
500	      const struct drm_display_mode *mode)
501{
502	struct tc_data *tc = bridge_to_tc(bridge);
503
504	/*
505	 * Maximum pixel clock speed 135MHz for single-link
506	 * 270MHz for dual-link
507	 */
508	if ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) ||
509	    (mode->clock > 270000 && tc->lvds_link == DUAL_LINK))
510		return MODE_CLOCK_HIGH;
511
512	switch (info->bus_formats[0]) {
513	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
514	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
515		/* RGB888 */
516		tc->bpc = 8;
517		break;
518	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
519		/* RGB666 */
520		tc->bpc = 6;
521		break;
522	default:
523		dev_warn(tc->dev,
524			 "unsupported LVDS bus format 0x%04x\n",
525			 info->bus_formats[0]);
526		return MODE_NOMODE;
527	}
528
529	return MODE_OK;
530}
531
532static int tc358775_parse_dt(struct device_node *np, struct tc_data *tc)
533{
534	struct device_node *endpoint;
535	struct device_node *remote;
536	int dsi_lanes = -1;
537
538	endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
539						 TC358775_DSI_IN, -1);
540	dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4);
541
542	/* Quirk old dtb: Use data lanes from the DSI host side instead of bridge */
543	if (dsi_lanes == -EINVAL || dsi_lanes == -ENODEV) {
544		remote = of_graph_get_remote_endpoint(endpoint);
545		dsi_lanes = drm_of_get_data_lanes_count(remote, 1, 4);
546		of_node_put(remote);
547		if (dsi_lanes >= 1)
548			dev_warn(tc->dev, "no dsi-lanes for the bridge, using host lanes\n");
549	}
550
551	of_node_put(endpoint);
552
553	if (dsi_lanes < 0)
554		return dsi_lanes;
555
556	tc->num_dsi_lanes = dsi_lanes;
557
558	tc->host_node = of_graph_get_remote_node(np, 0, 0);
559	if (!tc->host_node)
560		return -ENODEV;
561
562	of_node_put(tc->host_node);
563
564	tc->lvds_link = SINGLE_LINK;
565	endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
566						 TC358775_LVDS_OUT1, -1);
567	if (endpoint) {
568		remote = of_graph_get_remote_port_parent(endpoint);
569		of_node_put(endpoint);
570
571		if (remote) {
572			if (of_device_is_available(remote))
573				tc->lvds_link = DUAL_LINK;
574			of_node_put(remote);
575		}
576	}
577
578	dev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes);
579	dev_dbg(tc->dev, "operating in %d-link mode\n",	tc->lvds_link);
580
581	return 0;
582}
583
584static int tc_bridge_attach(struct drm_bridge *bridge,
585			    struct drm_encoder *encoder,
586			    enum drm_bridge_attach_flags flags)
587{
588	struct tc_data *tc = bridge_to_tc(bridge);
589
590	/* Attach the panel-bridge to the dsi bridge */
591	return drm_bridge_attach(encoder, tc->panel_bridge,
592				 &tc->bridge, flags);
593}
594
595static const struct drm_bridge_funcs tc_bridge_funcs = {
596	.attach = tc_bridge_attach,
597	.atomic_pre_enable = tc_bridge_atomic_pre_enable,
598	.atomic_enable = tc_bridge_atomic_enable,
599	.mode_valid = tc_mode_valid,
600	.atomic_post_disable = tc_bridge_atomic_post_disable,
601	.atomic_reset = drm_atomic_helper_bridge_reset,
602	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
603	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
604};
605
606static int tc_attach_host(struct tc_data *tc)
607{
608	struct device *dev = &tc->i2c->dev;
609	struct mipi_dsi_host *host;
610	struct mipi_dsi_device *dsi;
611	int ret;
612	const struct mipi_dsi_device_info info = { .type = "tc358775",
613							.channel = 0,
614							.node = NULL,
615						};
616
617	host = of_find_mipi_dsi_host_by_node(tc->host_node);
618	if (!host)
619		return dev_err_probe(dev, -EPROBE_DEFER, "failed to find dsi host\n");
620
621	dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
622	if (IS_ERR(dsi)) {
623		dev_err(dev, "failed to create dsi device\n");
624		return PTR_ERR(dsi);
625	}
626
627	tc->dsi = dsi;
628
629	dsi->lanes = tc->num_dsi_lanes;
630	dsi->format = MIPI_DSI_FMT_RGB888;
631	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
632			  MIPI_DSI_MODE_LPM;
633
634	/*
635	 * The hs_rate and lp_rate are data rate values. The HS mode is
636	 * differential, while the LP mode is single ended. As the HS mode
637	 * uses DDR, the DSI clock frequency is half the hs_rate. The 10 Mbs
638	 * data rate for LP mode is not specified in the bridge data sheet,
639	 * but seems to be part of the MIPI DSI spec.
640	 */
641	if (tc->type == TC358765)
642		dsi->hs_rate = 800000000;
643	else
644		dsi->hs_rate = 1000000000;
645	dsi->lp_rate = 10000000;
646
647	ret = devm_mipi_dsi_attach(dev, dsi);
648	if (ret < 0) {
649		dev_err(dev, "failed to attach dsi to host\n");
650		return ret;
651	}
652
653	return 0;
654}
655
656static int tc_probe(struct i2c_client *client)
657{
658	struct device *dev = &client->dev;
659	struct tc_data *tc;
660	int ret;
661
662	tc = devm_drm_bridge_alloc(dev, struct tc_data, bridge,
663				   &tc_bridge_funcs);
664	if (IS_ERR(tc))
665		return PTR_ERR(tc);
666
667	tc->dev = dev;
668	tc->i2c = client;
669	tc->type = (enum tc3587x5_type)(unsigned long)of_device_get_match_data(dev);
670
671	tc->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node,
672						  TC358775_LVDS_OUT0, 0);
673	if (IS_ERR(tc->panel_bridge))
674		return PTR_ERR(tc->panel_bridge);
675
676	ret = tc358775_parse_dt(dev->of_node, tc);
677	if (ret)
678		return ret;
679
680	tc->vddio = devm_regulator_get(dev, "vddio-supply");
681	if (IS_ERR(tc->vddio)) {
682		ret = PTR_ERR(tc->vddio);
683		dev_err(dev, "vddio-supply not found\n");
684		return ret;
685	}
686
687	tc->vdd = devm_regulator_get(dev, "vdd-supply");
688	if (IS_ERR(tc->vdd)) {
689		ret = PTR_ERR(tc->vdd);
690		dev_err(dev, "vdd-supply not found\n");
691		return ret;
692	}
693
694	tc->stby_gpio = devm_gpiod_get_optional(dev, "stby", GPIOD_OUT_HIGH);
695	if (IS_ERR(tc->stby_gpio))
696		return PTR_ERR(tc->stby_gpio);
697
698	tc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
699	if (IS_ERR(tc->reset_gpio)) {
700		ret = PTR_ERR(tc->reset_gpio);
701		dev_err(dev, "cannot get reset-gpios %d\n", ret);
702		return ret;
703	}
704
705	tc->bridge.of_node = dev->of_node;
706	tc->bridge.pre_enable_prev_first = true;
707	drm_bridge_add(&tc->bridge);
708
709	i2c_set_clientdata(client, tc);
710
711	ret = tc_attach_host(tc);
712	if (ret)
713		goto err_bridge_remove;
714
715	return 0;
716
717err_bridge_remove:
718	drm_bridge_remove(&tc->bridge);
719	return ret;
720}
721
722static void tc_remove(struct i2c_client *client)
723{
724	struct tc_data *tc = i2c_get_clientdata(client);
725
726	drm_bridge_remove(&tc->bridge);
727}
728
729static const struct i2c_device_id tc358775_i2c_ids[] = {
730	{ "tc358765", TC358765, },
731	{ "tc358775", TC358775, },
732	{ }
733};
734MODULE_DEVICE_TABLE(i2c, tc358775_i2c_ids);
735
736static const struct of_device_id tc358775_of_ids[] = {
737	{ .compatible = "toshiba,tc358765", .data = (void *)TC358765, },
738	{ .compatible = "toshiba,tc358775", .data = (void *)TC358775, },
739	{ }
740};
741MODULE_DEVICE_TABLE(of, tc358775_of_ids);
742
743static struct i2c_driver tc358775_driver = {
744	.driver = {
745		.name = "tc358775",
746		.of_match_table = tc358775_of_ids,
747	},
748	.id_table = tc358775_i2c_ids,
749	.probe = tc_probe,
750	.remove	= tc_remove,
751};
752module_i2c_driver(tc358775_driver);
753
754MODULE_AUTHOR("Vinay Simha BN <simhavcs@gmail.com>");
755MODULE_DESCRIPTION("TC358775 DSI/LVDS bridge driver");
756MODULE_LICENSE("GPL v2");