tc358762.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
  4 *
  5 * Based on tc358764.c by
  6 *  Andrzej Hajda <a.hajda@samsung.com>
  7 *  Maciej Purski <m.purski@samsung.com>
  8 *
  9 * Based on rpi_touchscreen.c by
 10 *  Eric Anholt <eric@anholt.net>
 11 */
 12
 13#include <linux/delay.h>
 14#include <linux/gpio/consumer.h>
 15#include <linux/mod_devicetable.h>
 16#include <linux/module.h>
 17#include <linux/of_graph.h>
 18#include <linux/regulator/consumer.h>
 19
 20#include <video/mipi_display.h>
 21
 22#include <drm/drm_atomic_helper.h>
 23#include <drm/drm_bridge.h>
 24#include <drm/drm_crtc.h>
 25#include <drm/drm_mipi_dsi.h>
 26#include <drm/drm_of.h>
 27#include <drm/drm_print.h>
 28#include <drm/drm_probe_helper.h>
 29
 30/* PPI layer registers */
 31#define PPI_STARTPPI		0x0104 /* START control bit */
 32#define PPI_LPTXTIMECNT		0x0114 /* LPTX timing signal */
 33#define PPI_D0S_ATMR		0x0144
 34#define PPI_D1S_ATMR		0x0148
 35#define PPI_D0S_CLRSIPOCOUNT	0x0164 /* Assertion timer for Lane 0 */
 36#define PPI_D1S_CLRSIPOCOUNT	0x0168 /* Assertion timer for Lane 1 */
 37#define PPI_START_FUNCTION	1
 38
 39/* DSI layer registers */
 40#define DSI_STARTDSI		0x0204 /* START control bit of DSI-TX */
 41#define DSI_LANEENABLE		0x0210 /* Enables each lane */
 42#define DSI_RX_START		1
 43
 44/* LCDC/DPI Host Registers, based on guesswork that this matches TC358764 */
 45#define LCDCTRL			0x0420 /* Video Path Control */
 46#define LCDCTRL_MSF		BIT(0) /* Magic square in RGB666 */
 47#define LCDCTRL_VTGEN		BIT(4)/* Use chip clock for timing */
 48#define LCDCTRL_UNK6		BIT(6) /* Unknown */
 49#define LCDCTRL_EVTMODE		BIT(5) /* Event mode */
 50#define LCDCTRL_RGB888		BIT(8) /* RGB888 mode */
 51#define LCDCTRL_HSPOL		BIT(17) /* Polarity of HSYNC signal */
 52#define LCDCTRL_DEPOL		BIT(18) /* Polarity of DE signal */
 53#define LCDCTRL_VSPOL		BIT(19) /* Polarity of VSYNC signal */
 54#define LCDCTRL_VSDELAY(v)	(((v) & 0xfff) << 20) /* VSYNC delay */
 55
 56/* SPI Master Registers */
 57#define SPICMR			0x0450
 58#define SPITCR			0x0454
 59
 60/* System Controller Registers */
 61#define SYSCTRL			0x0464
 62
 63/* System registers */
 64#define LPX_PERIOD		3
 65
 66/* Lane enable PPI and DSI register bits */
 67#define LANEENABLE_CLEN		BIT(0)
 68#define LANEENABLE_L0EN		BIT(1)
 69#define LANEENABLE_L1EN		BIT(2)
 70
 71struct tc358762 {
 72	struct device *dev;
 73	struct drm_bridge bridge;
 74	struct regulator *regulator;
 75	struct drm_bridge *panel_bridge;
 76	struct gpio_desc *reset_gpio;
 77	struct drm_display_mode mode;
 78	bool pre_enabled;
 79	int error;
 80};
 81
 82static int tc358762_clear_error(struct tc358762 *ctx)
 83{
 84	int ret = ctx->error;
 85
 86	ctx->error = 0;
 87	return ret;
 88}
 89
 90static void tc358762_write(struct tc358762 *ctx, u16 addr, u32 val)
 91{
 92	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 93	ssize_t ret;
 94	u8 data[6];
 95
 96	if (ctx->error)
 97		return;
 98
 99	data[0] = addr;
100	data[1] = addr >> 8;
101	data[2] = val;
102	data[3] = val >> 8;
103	data[4] = val >> 16;
104	data[5] = val >> 24;
105
106	ret = mipi_dsi_generic_write(dsi, data, sizeof(data));
107	if (ret < 0)
108		ctx->error = ret;
109}
110
111static inline struct tc358762 *bridge_to_tc358762(struct drm_bridge *bridge)
112{
113	return container_of(bridge, struct tc358762, bridge);
114}
115
116static int tc358762_init(struct tc358762 *ctx)
117{
118	u32 lcdctrl;
119
120	tc358762_write(ctx, DSI_LANEENABLE,
121		       LANEENABLE_L0EN | LANEENABLE_CLEN);
122	tc358762_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5);
123	tc358762_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5);
124	tc358762_write(ctx, PPI_D0S_ATMR, 0);
125	tc358762_write(ctx, PPI_D1S_ATMR, 0);
126	tc358762_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD);
127
128	tc358762_write(ctx, SPICMR, 0x00);
129
130	lcdctrl = LCDCTRL_VSDELAY(1) | LCDCTRL_RGB888 |
131		  LCDCTRL_UNK6 | LCDCTRL_VTGEN;
132
133	if (ctx->mode.flags & DRM_MODE_FLAG_NHSYNC)
134		lcdctrl |= LCDCTRL_HSPOL;
135
136	if (ctx->mode.flags & DRM_MODE_FLAG_NVSYNC)
137		lcdctrl |= LCDCTRL_VSPOL;
138
139	tc358762_write(ctx, LCDCTRL, lcdctrl);
140
141	tc358762_write(ctx, SYSCTRL, 0x040f);
142	msleep(100);
143
144	tc358762_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION);
145	tc358762_write(ctx, DSI_STARTDSI, DSI_RX_START);
146
147	msleep(100);
148
149	return tc358762_clear_error(ctx);
150}
151
152static void tc358762_post_disable(struct drm_bridge *bridge,
153				  struct drm_atomic_state *state)
154{
155	struct tc358762 *ctx = bridge_to_tc358762(bridge);
156	int ret;
157
158	/*
159	 * The post_disable hook might be called multiple times.
160	 * We want to avoid regulator imbalance below.
161	 */
162	if (!ctx->pre_enabled)
163		return;
164
165	ctx->pre_enabled = false;
166
167	if (ctx->reset_gpio)
168		gpiod_set_value_cansleep(ctx->reset_gpio, 0);
169
170	ret = regulator_disable(ctx->regulator);
171	if (ret < 0)
172		dev_err(ctx->dev, "error disabling regulators (%d)\n", ret);
173}
174
175static void tc358762_pre_enable(struct drm_bridge *bridge,
176				struct drm_atomic_state *state)
177{
178	struct tc358762 *ctx = bridge_to_tc358762(bridge);
179	int ret;
180
181	ret = regulator_enable(ctx->regulator);
182	if (ret < 0)
183		dev_err(ctx->dev, "error enabling regulators (%d)\n", ret);
184
185	if (ctx->reset_gpio) {
186		gpiod_set_value_cansleep(ctx->reset_gpio, 1);
187		usleep_range(5000, 10000);
188	}
189
190	ctx->pre_enabled = true;
191}
192
193static void tc358762_enable(struct drm_bridge *bridge,
194			    struct drm_atomic_state *state)
195{
196	struct tc358762 *ctx = bridge_to_tc358762(bridge);
197	int ret;
198
199	ret = tc358762_init(ctx);
200	if (ret < 0)
201		dev_err(ctx->dev, "error initializing bridge (%d)\n", ret);
202}
203
204static int tc358762_attach(struct drm_bridge *bridge,
205			   struct drm_encoder *encoder,
206			   enum drm_bridge_attach_flags flags)
207{
208	struct tc358762 *ctx = bridge_to_tc358762(bridge);
209
210	return drm_bridge_attach(encoder, ctx->panel_bridge,
211				 bridge, flags);
212}
213
214static void tc358762_bridge_mode_set(struct drm_bridge *bridge,
215				     const struct drm_display_mode *mode,
216				     const struct drm_display_mode *adj)
217{
218	struct tc358762 *ctx = bridge_to_tc358762(bridge);
219
220	drm_mode_copy(&ctx->mode, mode);
221}
222
223static const struct drm_bridge_funcs tc358762_bridge_funcs = {
224	.atomic_post_disable = tc358762_post_disable,
225	.atomic_pre_enable = tc358762_pre_enable,
226	.atomic_enable = tc358762_enable,
227	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
228	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
229	.atomic_reset = drm_atomic_helper_bridge_reset,
230	.attach = tc358762_attach,
231	.mode_set = tc358762_bridge_mode_set,
232};
233
234static int tc358762_parse_dt(struct tc358762 *ctx)
235{
236	struct drm_bridge *panel_bridge;
237	struct device *dev = ctx->dev;
238
239	panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
240	if (IS_ERR(panel_bridge))
241		return PTR_ERR(panel_bridge);
242
243	ctx->panel_bridge = panel_bridge;
244
245	/* Reset GPIO is optional */
246	ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
247	if (IS_ERR(ctx->reset_gpio))
248		return PTR_ERR(ctx->reset_gpio);
249
250	return 0;
251}
252
253static int tc358762_configure_regulators(struct tc358762 *ctx)
254{
255	ctx->regulator = devm_regulator_get(ctx->dev, "vddc");
256	if (IS_ERR(ctx->regulator))
257		return PTR_ERR(ctx->regulator);
258
259	return 0;
260}
261
262static int tc358762_probe(struct mipi_dsi_device *dsi)
263{
264	struct device *dev = &dsi->dev;
265	struct tc358762 *ctx;
266	int ret;
267
268	ctx = devm_drm_bridge_alloc(dev, struct tc358762, bridge,
269				    &tc358762_bridge_funcs);
270	if (IS_ERR(ctx))
271		return PTR_ERR(ctx);
272
273	mipi_dsi_set_drvdata(dsi, ctx);
274
275	ctx->dev = dev;
276	ctx->pre_enabled = false;
277
278	/* TODO: Find out how to get dual-lane mode working */
279	dsi->lanes = 1;
280	dsi->format = MIPI_DSI_FMT_RGB888;
281	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
282			  MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO_HSE;
283
284	ret = tc358762_parse_dt(ctx);
285	if (ret < 0)
286		return ret;
287
288	ret = tc358762_configure_regulators(ctx);
289	if (ret < 0)
290		return ret;
291
292	ctx->bridge.type = DRM_MODE_CONNECTOR_DPI;
293	ctx->bridge.of_node = dev->of_node;
294	ctx->bridge.pre_enable_prev_first = true;
295
296	drm_bridge_add(&ctx->bridge);
297
298	ret = mipi_dsi_attach(dsi);
299	if (ret < 0) {
300		drm_bridge_remove(&ctx->bridge);
301		dev_err(dev, "failed to attach dsi\n");
302	}
303
304	return ret;
305}
306
307static void tc358762_remove(struct mipi_dsi_device *dsi)
308{
309	struct tc358762 *ctx = mipi_dsi_get_drvdata(dsi);
310
311	mipi_dsi_detach(dsi);
312	drm_bridge_remove(&ctx->bridge);
313}
314
315static const struct of_device_id tc358762_of_match[] = {
316	{ .compatible = "toshiba,tc358762" },
317	{ }
318};
319MODULE_DEVICE_TABLE(of, tc358762_of_match);
320
321static struct mipi_dsi_driver tc358762_driver = {
322	.probe = tc358762_probe,
323	.remove = tc358762_remove,
324	.driver = {
325		.name = "tc358762",
326		.of_match_table = tc358762_of_match,
327	},
328};
329module_mipi_dsi_driver(tc358762_driver);
330
331MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
332MODULE_DESCRIPTION("MIPI-DSI based Driver for TC358762 DSI/DPI Bridge");
333MODULE_LICENSE("GPL v2");